Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

50117

1

T1

412

T10

268

T13

274

auto[1]

17375

1

T2

103

T8

3

T10

65

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49274

1

T1

285

T2

103

T8

3

auto[1]

18218

1

T1

127

T10

101

T13

120

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	34733	1			T1	227		T2	49		T8	3
others[1]	5639	1			T1	39		T2	8		T10	32
others[2]	5655	1			T1	31		T2	7		T10	25
others[3]	6538	1			T1	40		T2	8		T10	34
interest[1]	3787	1			T1	19		T2	2		T10	22
interest[4]	22867	1			T1	153		T2	26		T8	3
interest[64]	11140	1			T1	56		T2	29		T10	51

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	16346	1			T1	158		T10	81		T13	70
auto[0]	auto[0]	others[1]	2666	1			T1	24		T10	19		T13	18
auto[0]	auto[0]	others[2]	2706	1			T1	21		T10	13		T13	11
auto[0]	auto[0]	others[3]	3123	1			T1	30		T10	15		T13	16
auto[0]	auto[0]	interest[1]	1864	1			T1	13		T10	15		T13	8
auto[0]	auto[0]	interest[4]	10680	1			T1	108		T10	54		T13	50
auto[0]	auto[0]	interest[64]	5194	1			T1	39		T10	24		T13	31
auto[0]	auto[1]	others[0]	9002	1			T2	49		T8	3		T10	38
auto[0]	auto[1]	others[1]	1449	1			T2	8		T10	5		T13	7
auto[0]	auto[1]	others[2]	1422	1			T2	7		T10	5		T13	10
auto[0]	auto[1]	others[3]	1671	1			T2	8		T10	6		T13	4
auto[0]	auto[1]	interest[1]	907	1			T2	2		T10	1		T13	8
auto[0]	auto[1]	interest[4]	5992	1			T2	26		T8	3		T10	26
auto[0]	auto[1]	interest[64]	2924	1			T2	29		T10	10		T13	15
auto[1]	auto[0]	others[0]	9385	1			T1	69		T10	50		T13	54
auto[1]	auto[0]	others[1]	1524	1			T1	15		T10	8		T13	11
auto[1]	auto[0]	others[2]	1527	1			T1	10		T10	7		T13	10
auto[1]	auto[0]	others[3]	1744	1			T1	10		T10	13		T13	12
auto[1]	auto[0]	interest[1]	1016	1			T1	6		T10	6		T13	13
auto[1]	auto[0]	interest[4]	6195	1			T1	45		T10	37		T13	31
auto[1]	auto[0]	interest[64]	3022	1			T1	17		T10	17		T13	20

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal