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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.03 98.38 93.99 98.62 89.36 97.19 95.45 99.21


Total test records in report: 1130
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T156 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.2201070045 Jul 09 05:36:02 PM PDT 24 Jul 09 05:36:11 PM PDT 24 705986034 ps
T1030 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.1218975217 Jul 09 05:35:46 PM PDT 24 Jul 09 05:35:47 PM PDT 24 13283905 ps
T259 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2533750767 Jul 09 05:35:43 PM PDT 24 Jul 09 05:36:00 PM PDT 24 1000347868 ps
T123 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3577925813 Jul 09 05:35:50 PM PDT 24 Jul 09 05:35:53 PM PDT 24 51568729 ps
T1031 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2294361016 Jul 09 05:36:02 PM PDT 24 Jul 09 05:36:04 PM PDT 24 20661681 ps
T1032 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2313103058 Jul 09 05:35:59 PM PDT 24 Jul 09 05:36:04 PM PDT 24 322020956 ps
T157 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1049722678 Jul 09 05:36:10 PM PDT 24 Jul 09 05:36:12 PM PDT 24 278513280 ps
T261 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2303140183 Jul 09 05:36:15 PM PDT 24 Jul 09 05:36:23 PM PDT 24 213454001 ps
T1033 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1525525997 Jul 09 05:36:15 PM PDT 24 Jul 09 05:36:17 PM PDT 24 184145038 ps
T1034 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1566804986 Jul 09 05:35:54 PM PDT 24 Jul 09 05:35:57 PM PDT 24 258178474 ps
T1035 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.834576333 Jul 09 05:36:22 PM PDT 24 Jul 09 05:36:23 PM PDT 24 47282981 ps
T124 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3641732181 Jul 09 05:36:07 PM PDT 24 Jul 09 05:36:10 PM PDT 24 154366646 ps
T1036 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.2064115830 Jul 09 05:36:17 PM PDT 24 Jul 09 05:36:18 PM PDT 24 43127056 ps
T1037 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.992590355 Jul 09 05:36:14 PM PDT 24 Jul 09 05:36:15 PM PDT 24 44157214 ps
T1038 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.2586852521 Jul 09 05:36:14 PM PDT 24 Jul 09 05:36:16 PM PDT 24 36480404 ps
T1039 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.1640155757 Jul 09 05:36:26 PM PDT 24 Jul 09 05:36:27 PM PDT 24 64109581 ps
T1040 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1194726314 Jul 09 05:35:58 PM PDT 24 Jul 09 05:36:01 PM PDT 24 258036231 ps
T262 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2454067856 Jul 09 05:36:14 PM PDT 24 Jul 09 05:36:36 PM PDT 24 4232616396 ps
T125 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.2550426200 Jul 09 05:36:17 PM PDT 24 Jul 09 05:36:20 PM PDT 24 91896815 ps
T1041 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3222139757 Jul 09 05:35:52 PM PDT 24 Jul 09 05:35:53 PM PDT 24 25790969 ps
T108 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.898244627 Jul 09 05:35:45 PM PDT 24 Jul 09 05:35:48 PM PDT 24 127403747 ps
T253 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2852210680 Jul 09 05:35:54 PM PDT 24 Jul 09 05:36:13 PM PDT 24 1207001064 ps
T1042 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3202832610 Jul 09 05:35:49 PM PDT 24 Jul 09 05:35:52 PM PDT 24 139578906 ps
T1043 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.281386890 Jul 09 05:36:21 PM PDT 24 Jul 09 05:36:22 PM PDT 24 12716930 ps
T105 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3719862646 Jul 09 05:35:49 PM PDT 24 Jul 09 05:35:52 PM PDT 24 72048274 ps
T1044 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2546937578 Jul 09 05:35:45 PM PDT 24 Jul 09 05:35:47 PM PDT 24 10269532 ps
T126 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.4058714047 Jul 09 05:36:09 PM PDT 24 Jul 09 05:36:12 PM PDT 24 360310018 ps
T127 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1140051063 Jul 09 05:35:55 PM PDT 24 Jul 09 05:35:58 PM PDT 24 131330618 ps
T104 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3963962809 Jul 09 05:36:15 PM PDT 24 Jul 09 05:36:19 PM PDT 24 107897645 ps
T128 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.3225295645 Jul 09 05:36:04 PM PDT 24 Jul 09 05:36:06 PM PDT 24 39524010 ps
T1045 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3844164454 Jul 09 05:36:13 PM PDT 24 Jul 09 05:36:17 PM PDT 24 66693120 ps
T129 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3073492316 Jul 09 05:35:57 PM PDT 24 Jul 09 05:36:38 PM PDT 24 2795711710 ps
T1046 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2704516862 Jul 09 05:35:54 PM PDT 24 Jul 09 05:35:56 PM PDT 24 18469335 ps
T256 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.2262517881 Jul 09 05:36:02 PM PDT 24 Jul 09 05:36:16 PM PDT 24 205511604 ps
T1047 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.2035773289 Jul 09 05:36:21 PM PDT 24 Jul 09 05:36:23 PM PDT 24 71276710 ps
T1048 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.1392250418 Jul 09 05:35:40 PM PDT 24 Jul 09 05:35:42 PM PDT 24 121584459 ps
T1049 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.3482284745 Jul 09 05:36:20 PM PDT 24 Jul 09 05:36:21 PM PDT 24 13638033 ps
T106 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.921432760 Jul 09 05:36:01 PM PDT 24 Jul 09 05:36:05 PM PDT 24 74436133 ps
T1050 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.225566822 Jul 09 05:36:10 PM PDT 24 Jul 09 05:36:14 PM PDT 24 145396105 ps
T1051 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1207499543 Jul 09 05:35:58 PM PDT 24 Jul 09 05:36:01 PM PDT 24 36735506 ps
T86 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3517105589 Jul 09 05:35:50 PM PDT 24 Jul 09 05:35:52 PM PDT 24 65690408 ps
T113 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1531671059 Jul 09 05:36:13 PM PDT 24 Jul 09 05:36:18 PM PDT 24 162837433 ps
T1052 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.3934932685 Jul 09 05:35:41 PM PDT 24 Jul 09 05:35:43 PM PDT 24 11245548 ps
T1053 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1473793488 Jul 09 05:36:16 PM PDT 24 Jul 09 05:36:21 PM PDT 24 187603249 ps
T1054 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2578265462 Jul 09 05:36:09 PM PDT 24 Jul 09 05:36:10 PM PDT 24 31585565 ps
T254 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1213671936 Jul 09 05:36:10 PM PDT 24 Jul 09 05:36:26 PM PDT 24 2639367844 ps
T252 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.3816833463 Jul 09 05:35:45 PM PDT 24 Jul 09 05:35:49 PM PDT 24 581551723 ps
T1055 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.4095323283 Jul 09 05:36:18 PM PDT 24 Jul 09 05:36:20 PM PDT 24 45889672 ps
T1056 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.3251971552 Jul 09 05:36:14 PM PDT 24 Jul 09 05:36:21 PM PDT 24 1137157817 ps
T1057 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1611761494 Jul 09 05:36:21 PM PDT 24 Jul 09 05:36:23 PM PDT 24 24570371 ps
T1058 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2052390130 Jul 09 05:35:46 PM PDT 24 Jul 09 05:35:48 PM PDT 24 199504765 ps
T1059 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3457880141 Jul 09 05:36:10 PM PDT 24 Jul 09 05:36:12 PM PDT 24 49694054 ps
T1060 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1982284582 Jul 09 05:35:43 PM PDT 24 Jul 09 05:35:47 PM PDT 24 1058132386 ps
T1061 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.78557026 Jul 09 05:36:27 PM PDT 24 Jul 09 05:36:28 PM PDT 24 44454034 ps
T1062 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3423531708 Jul 09 05:36:04 PM PDT 24 Jul 09 05:36:06 PM PDT 24 17209985 ps
T1063 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.2106078616 Jul 09 05:36:24 PM PDT 24 Jul 09 05:36:25 PM PDT 24 50811895 ps
T1064 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3306681367 Jul 09 05:36:21 PM PDT 24 Jul 09 05:36:22 PM PDT 24 22990690 ps
T1065 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.984544139 Jul 09 05:35:54 PM PDT 24 Jul 09 05:35:58 PM PDT 24 336681329 ps
T1066 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1236047250 Jul 09 05:36:04 PM PDT 24 Jul 09 05:36:06 PM PDT 24 181012306 ps
T1067 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3151391805 Jul 09 05:36:02 PM PDT 24 Jul 09 05:36:06 PM PDT 24 50476721 ps
T1068 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2503854168 Jul 09 05:36:15 PM PDT 24 Jul 09 05:36:19 PM PDT 24 110017564 ps
T1069 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3650639685 Jul 09 05:36:10 PM PDT 24 Jul 09 05:36:15 PM PDT 24 132532047 ps
T260 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3298065412 Jul 09 05:35:57 PM PDT 24 Jul 09 05:36:10 PM PDT 24 194878969 ps
T111 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.3264883525 Jul 09 05:35:59 PM PDT 24 Jul 09 05:36:04 PM PDT 24 235907382 ps
T1070 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.1705497925 Jul 09 05:36:19 PM PDT 24 Jul 09 05:36:21 PM PDT 24 15179166 ps
T1071 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.2897624551 Jul 09 05:36:16 PM PDT 24 Jul 09 05:36:25 PM PDT 24 297613639 ps
T1072 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.262079063 Jul 09 05:35:46 PM PDT 24 Jul 09 05:35:49 PM PDT 24 863427224 ps
T1073 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.173600745 Jul 09 05:35:54 PM PDT 24 Jul 09 05:36:17 PM PDT 24 313366397 ps
T1074 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.2481005551 Jul 09 05:36:13 PM PDT 24 Jul 09 05:36:18 PM PDT 24 792094781 ps
T1075 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.4062061103 Jul 09 05:35:58 PM PDT 24 Jul 09 05:36:01 PM PDT 24 135720947 ps
T1076 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2601073422 Jul 09 05:36:06 PM PDT 24 Jul 09 05:36:10 PM PDT 24 562081599 ps
T87 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2522554414 Jul 09 05:35:53 PM PDT 24 Jul 09 05:35:55 PM PDT 24 36204982 ps
T1077 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1663952035 Jul 09 05:35:54 PM PDT 24 Jul 09 05:35:59 PM PDT 24 54144789 ps
T1078 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.1240563887 Jul 09 05:36:22 PM PDT 24 Jul 09 05:36:24 PM PDT 24 13652007 ps
T1079 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.578044712 Jul 09 05:36:11 PM PDT 24 Jul 09 05:36:19 PM PDT 24 214637994 ps
T1080 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2542116406 Jul 09 05:36:03 PM PDT 24 Jul 09 05:36:05 PM PDT 24 58240248 ps
T1081 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2308672774 Jul 09 05:36:05 PM PDT 24 Jul 09 05:36:06 PM PDT 24 14667362 ps
T1082 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.822981464 Jul 09 05:36:24 PM PDT 24 Jul 09 05:36:26 PM PDT 24 22469212 ps
T1083 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3568193821 Jul 09 05:36:13 PM PDT 24 Jul 09 05:36:29 PM PDT 24 2692511957 ps
T1084 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2082021786 Jul 09 05:35:53 PM PDT 24 Jul 09 05:36:21 PM PDT 24 7522806990 ps
T1085 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.1734901987 Jul 09 05:36:04 PM PDT 24 Jul 09 05:36:06 PM PDT 24 51309922 ps
T1086 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.498855961 Jul 09 05:36:10 PM PDT 24 Jul 09 05:36:19 PM PDT 24 321747756 ps
T112 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.868622627 Jul 09 05:36:19 PM PDT 24 Jul 09 05:36:24 PM PDT 24 64659677 ps
T1087 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.2165328019 Jul 09 05:36:19 PM PDT 24 Jul 09 05:36:20 PM PDT 24 36002738 ps
T1088 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3431994531 Jul 09 05:35:55 PM PDT 24 Jul 09 05:35:57 PM PDT 24 15776866 ps
T109 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2074976568 Jul 09 05:36:11 PM PDT 24 Jul 09 05:36:15 PM PDT 24 694698585 ps
T1089 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3160810468 Jul 09 05:35:50 PM PDT 24 Jul 09 05:35:51 PM PDT 24 39308417 ps
T1090 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.483545503 Jul 09 05:36:22 PM PDT 24 Jul 09 05:36:23 PM PDT 24 14272823 ps
T1091 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.319584108 Jul 09 05:36:11 PM PDT 24 Jul 09 05:36:15 PM PDT 24 467199936 ps
T1092 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.387088488 Jul 09 05:36:21 PM PDT 24 Jul 09 05:36:23 PM PDT 24 68445499 ps
T1093 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.2325855524 Jul 09 05:35:54 PM PDT 24 Jul 09 05:35:56 PM PDT 24 37195257 ps
T257 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3434910465 Jul 09 05:35:41 PM PDT 24 Jul 09 05:35:49 PM PDT 24 410975972 ps
T1094 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.4081925960 Jul 09 05:36:07 PM PDT 24 Jul 09 05:36:09 PM PDT 24 55907657 ps
T1095 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3188387638 Jul 09 05:36:05 PM PDT 24 Jul 09 05:36:07 PM PDT 24 15162797 ps
T1096 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2491112171 Jul 09 05:35:49 PM PDT 24 Jul 09 05:35:52 PM PDT 24 41707366 ps
T1097 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1366169265 Jul 09 05:36:03 PM PDT 24 Jul 09 05:36:04 PM PDT 24 14488133 ps
T1098 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1367296262 Jul 09 05:35:51 PM PDT 24 Jul 09 05:35:56 PM PDT 24 2136888331 ps
T1099 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.4249563994 Jul 09 05:35:40 PM PDT 24 Jul 09 05:35:55 PM PDT 24 963593491 ps
T1100 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1052148905 Jul 09 05:36:13 PM PDT 24 Jul 09 05:36:16 PM PDT 24 232148550 ps
T1101 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3501219081 Jul 09 05:36:22 PM PDT 24 Jul 09 05:36:23 PM PDT 24 13325556 ps
T1102 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3335163716 Jul 09 05:35:56 PM PDT 24 Jul 09 05:35:58 PM PDT 24 23541817 ps
T1103 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.3445026026 Jul 09 05:36:06 PM PDT 24 Jul 09 05:36:09 PM PDT 24 44272423 ps
T1104 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.305724501 Jul 09 05:35:52 PM PDT 24 Jul 09 05:35:55 PM PDT 24 110851759 ps
T1105 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2232345693 Jul 09 05:36:15 PM PDT 24 Jul 09 05:36:20 PM PDT 24 591654338 ps
T258 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.581323760 Jul 09 05:36:13 PM PDT 24 Jul 09 05:36:34 PM PDT 24 2691259977 ps
T1106 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3243078590 Jul 09 05:35:41 PM PDT 24 Jul 09 05:35:44 PM PDT 24 117459363 ps
T1107 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2110855706 Jul 09 05:36:03 PM PDT 24 Jul 09 05:36:08 PM PDT 24 974225774 ps
T1108 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.2094049733 Jul 09 05:35:48 PM PDT 24 Jul 09 05:35:49 PM PDT 24 34790921 ps
T1109 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2019371062 Jul 09 05:36:25 PM PDT 24 Jul 09 05:36:27 PM PDT 24 166882296 ps
T1110 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1451094445 Jul 09 05:36:00 PM PDT 24 Jul 09 05:36:03 PM PDT 24 159520678 ps
T1111 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.1191100365 Jul 09 05:35:44 PM PDT 24 Jul 09 05:35:46 PM PDT 24 102458093 ps
T1112 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1267709591 Jul 09 05:36:19 PM PDT 24 Jul 09 05:36:23 PM PDT 24 661591117 ps
T1113 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.3593441456 Jul 09 05:36:00 PM PDT 24 Jul 09 05:36:06 PM PDT 24 526741709 ps
T1114 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1802552330 Jul 09 05:36:22 PM PDT 24 Jul 09 05:36:23 PM PDT 24 10815824 ps
T1115 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3855986999 Jul 09 05:36:06 PM PDT 24 Jul 09 05:36:29 PM PDT 24 3225309260 ps
T1116 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1244326022 Jul 09 05:36:12 PM PDT 24 Jul 09 05:36:15 PM PDT 24 381482804 ps
T1117 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.2830989962 Jul 09 05:36:03 PM PDT 24 Jul 09 05:36:05 PM PDT 24 31257268 ps
T1118 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1196883594 Jul 09 05:36:18 PM PDT 24 Jul 09 05:36:22 PM PDT 24 206425048 ps
T1119 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.150013281 Jul 09 05:36:04 PM PDT 24 Jul 09 05:36:09 PM PDT 24 773083508 ps
T1120 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3527995307 Jul 09 05:36:07 PM PDT 24 Jul 09 05:36:11 PM PDT 24 127523353 ps
T1121 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.189152183 Jul 09 05:35:56 PM PDT 24 Jul 09 05:35:59 PM PDT 24 519248131 ps
T1122 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1007136769 Jul 09 05:35:48 PM PDT 24 Jul 09 05:36:25 PM PDT 24 1092436069 ps
T1123 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2016646545 Jul 09 05:35:53 PM PDT 24 Jul 09 05:35:56 PM PDT 24 44568095 ps
T1124 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.1770609082 Jul 09 05:35:52 PM PDT 24 Jul 09 05:36:01 PM PDT 24 324786942 ps
T1125 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2521423011 Jul 09 05:36:10 PM PDT 24 Jul 09 05:36:13 PM PDT 24 96459648 ps
T1126 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.4098749278 Jul 09 05:35:55 PM PDT 24 Jul 09 05:35:57 PM PDT 24 68691983 ps
T1127 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2212381036 Jul 09 05:36:24 PM PDT 24 Jul 09 05:36:26 PM PDT 24 55328266 ps
T1128 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.1554095859 Jul 09 05:35:55 PM PDT 24 Jul 09 05:35:57 PM PDT 24 31973136 ps
T1129 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.306869819 Jul 09 05:35:48 PM PDT 24 Jul 09 05:35:52 PM PDT 24 312025738 ps
T1130 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3924622881 Jul 09 05:36:16 PM PDT 24 Jul 09 05:36:18 PM PDT 24 79327217 ps

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.222769064
Short name T10
Test name
Test status
Simulation time 69793271487 ps
CPU time 689.52 seconds
Started Jul 09 05:40:46 PM PDT 24
Finished Jul 09 05:52:16 PM PDT 24
Peak memory 268148 kb
Host smart-e716611c-415a-4e5a-a21f-643d15aa368c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222769064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.222769064
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.1880413303
Short name T16
Test name
Test status
Simulation time 178265254606 ps
CPU time 461.11 seconds
Started Jul 09 05:39:23 PM PDT 24
Finished Jul 09 05:47:05 PM PDT 24
Peak memory 265252 kb
Host smart-df45e1a8-9ea1-4d6b-9731-85ba297bf40c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880413303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.1880413303
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3285034022
Short name T96
Test name
Test status
Simulation time 3033400087 ps
CPU time 15.39 seconds
Started Jul 09 05:36:03 PM PDT 24
Finished Jul 09 05:36:19 PM PDT 24
Peak memory 216496 kb
Host smart-03cdb2da-b1a8-4a8d-b700-299b3daa3dda
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285034022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.3285034022
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.1789324148
Short name T18
Test name
Test status
Simulation time 211872502186 ps
CPU time 547.05 seconds
Started Jul 09 05:38:31 PM PDT 24
Finished Jul 09 05:47:39 PM PDT 24
Peak memory 273856 kb
Host smart-87eb74b7-3b0d-4216-a858-1a1cd9cb27e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789324148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.1789324148
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.1051167220
Short name T22
Test name
Test status
Simulation time 29584578801 ps
CPU time 284.78 seconds
Started Jul 09 05:40:23 PM PDT 24
Finished Jul 09 05:45:08 PM PDT 24
Peak memory 265680 kb
Host smart-b893ced1-7b52-4a02-b93a-0d6d6d4ea203
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051167220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.1051167220
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.295542326
Short name T68
Test name
Test status
Simulation time 17071155 ps
CPU time 0.76 seconds
Started Jul 09 05:38:28 PM PDT 24
Finished Jul 09 05:38:29 PM PDT 24
Peak memory 216060 kb
Host smart-fda7fa17-4087-48bd-a79e-f994a042a8fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295542326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.295542326
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.2970798138
Short name T91
Test name
Test status
Simulation time 8178535424 ps
CPU time 89.89 seconds
Started Jul 09 05:38:48 PM PDT 24
Finished Jul 09 05:40:20 PM PDT 24
Peak memory 252732 kb
Host smart-8db777e5-71e7-43ad-a5cd-026c711b0eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970798138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds
.2970798138
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.458926359
Short name T159
Test name
Test status
Simulation time 45269232617 ps
CPU time 477.43 seconds
Started Jul 09 05:38:38 PM PDT 24
Finished Jul 09 05:46:36 PM PDT 24
Peak memory 265656 kb
Host smart-3837e0bd-eeb5-469c-be60-3d072c13915e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458926359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stress
_all.458926359
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.1324111149
Short name T13
Test name
Test status
Simulation time 68553456900 ps
CPU time 342.33 seconds
Started Jul 09 05:39:26 PM PDT 24
Finished Jul 09 05:45:09 PM PDT 24
Peak memory 249296 kb
Host smart-f1b7fd81-7708-4873-87dd-d7e0a1e55b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324111149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.1324111149
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.914808396
Short name T95
Test name
Test status
Simulation time 75281029 ps
CPU time 2.63 seconds
Started Jul 09 05:36:03 PM PDT 24
Finished Jul 09 05:36:06 PM PDT 24
Peak memory 216108 kb
Host smart-c6744560-3338-46dd-b324-708584fceebb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914808396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.914808396
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.2569645432
Short name T33
Test name
Test status
Simulation time 108454662545 ps
CPU time 538.8 seconds
Started Jul 09 05:40:03 PM PDT 24
Finished Jul 09 05:49:04 PM PDT 24
Peak memory 265484 kb
Host smart-f39e17e1-71b2-45ad-8eca-965d74f6e004
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569645432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.2569645432
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.3496497384
Short name T147
Test name
Test status
Simulation time 11755971118 ps
CPU time 84.24 seconds
Started Jul 09 05:40:28 PM PDT 24
Finished Jul 09 05:41:53 PM PDT 24
Peak memory 249112 kb
Host smart-418ff0a5-bb93-4b7c-8472-5901520eca83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496497384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.3496497384
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.3363580834
Short name T322
Test name
Test status
Simulation time 17126910 ps
CPU time 0.7 seconds
Started Jul 09 05:39:26 PM PDT 24
Finished Jul 09 05:39:27 PM PDT 24
Peak memory 205488 kb
Host smart-1f53a4a2-1851-41d5-a379-3a075cf396fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363580834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
3363580834
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.278395561
Short name T55
Test name
Test status
Simulation time 126272332977 ps
CPU time 1272.68 seconds
Started Jul 09 05:39:29 PM PDT 24
Finished Jul 09 06:00:43 PM PDT 24
Peak memory 290124 kb
Host smart-dd5458fa-6643-43d1-9fed-2f56dcaab25f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278395561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stres
s_all.278395561
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.3712929866
Short name T46
Test name
Test status
Simulation time 25360334306 ps
CPU time 266.6 seconds
Started Jul 09 05:40:02 PM PDT 24
Finished Jul 09 05:44:31 PM PDT 24
Peak memory 250284 kb
Host smart-4cbfbb5b-98e3-4517-b048-c6e6c73b41e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712929866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.3712929866
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2998977355
Short name T84
Test name
Test status
Simulation time 19345836 ps
CPU time 1.12 seconds
Started Jul 09 05:35:43 PM PDT 24
Finished Jul 09 05:35:45 PM PDT 24
Peak memory 207356 kb
Host smart-052fc904-f975-4ee6-9623-9a2a2ce6f364
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998977355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.2998977355
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.1622661299
Short name T175
Test name
Test status
Simulation time 150235485475 ps
CPU time 692.83 seconds
Started Jul 09 05:39:31 PM PDT 24
Finished Jul 09 05:51:05 PM PDT 24
Peak memory 265640 kb
Host smart-d31c58ff-8327-4fe6-93d8-e3fe3d3475e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622661299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.1622661299
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.2301293684
Short name T32
Test name
Test status
Simulation time 169189133321 ps
CPU time 391.38 seconds
Started Jul 09 05:40:34 PM PDT 24
Finished Jul 09 05:47:06 PM PDT 24
Peak memory 257488 kb
Host smart-e13b2cf9-3615-4713-b5ee-79569344baa9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301293684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.2301293684
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.15748447
Short name T70
Test name
Test status
Simulation time 251660384 ps
CPU time 1.3 seconds
Started Jul 09 05:38:34 PM PDT 24
Finished Jul 09 05:38:37 PM PDT 24
Peak memory 237148 kb
Host smart-9cf1d1d2-f4e2-4d5d-ba85-9a094ca8914e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15748447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.15748447
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.3756340858
Short name T189
Test name
Test status
Simulation time 244000798647 ps
CPU time 429.07 seconds
Started Jul 09 05:40:04 PM PDT 24
Finished Jul 09 05:47:15 PM PDT 24
Peak memory 253812 kb
Host smart-282d96b4-d5f9-4c4e-9d56-ee1c6b9c1f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756340858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmd
s.3756340858
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.3350616937
Short name T224
Test name
Test status
Simulation time 328024726343 ps
CPU time 682.22 seconds
Started Jul 09 05:38:55 PM PDT 24
Finished Jul 09 05:50:18 PM PDT 24
Peak memory 273216 kb
Host smart-aa813a00-b3f4-4429-b930-b4d413b917a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350616937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.3350616937
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.325922107
Short name T188
Test name
Test status
Simulation time 108553424433 ps
CPU time 221.45 seconds
Started Jul 09 05:40:44 PM PDT 24
Finished Jul 09 05:44:26 PM PDT 24
Peak memory 265532 kb
Host smart-81b3c4dd-1342-454a-9ff6-d8ecc45a982f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325922107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmds
.325922107
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.3109332658
Short name T19
Test name
Test status
Simulation time 20249180607 ps
CPU time 113.94 seconds
Started Jul 09 05:39:44 PM PDT 24
Finished Jul 09 05:41:39 PM PDT 24
Peak memory 249272 kb
Host smart-ce78f706-4cd8-4d28-8633-3fd141378807
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109332658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.3109332658
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2074976568
Short name T109
Test name
Test status
Simulation time 694698585 ps
CPU time 3.84 seconds
Started Jul 09 05:36:11 PM PDT 24
Finished Jul 09 05:36:15 PM PDT 24
Peak memory 216092 kb
Host smart-627dd4f0-4d61-4db9-bd21-79d80d77464f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074976568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
2074976568
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.581323760
Short name T258
Test name
Test status
Simulation time 2691259977 ps
CPU time 20.66 seconds
Started Jul 09 05:36:13 PM PDT 24
Finished Jul 09 05:36:34 PM PDT 24
Peak memory 217204 kb
Host smart-7ee110f1-5fec-4cd5-94c4-baaf1205cceb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581323760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device
_tl_intg_err.581323760
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.4099302663
Short name T54
Test name
Test status
Simulation time 8474538574 ps
CPU time 158.14 seconds
Started Jul 09 05:40:08 PM PDT 24
Finished Jul 09 05:42:48 PM PDT 24
Peak memory 281860 kb
Host smart-c35cadf1-0b1e-4f1a-a070-5936fdd8d6a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099302663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.4099302663
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.4198818279
Short name T93
Test name
Test status
Simulation time 127658124986 ps
CPU time 64.18 seconds
Started Jul 09 05:39:15 PM PDT 24
Finished Jul 09 05:40:20 PM PDT 24
Peak memory 236128 kb
Host smart-c7c63b1c-0830-4689-9ccc-0da2ef1c8782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198818279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.4198818279
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.2440648845
Short name T241
Test name
Test status
Simulation time 4768462790 ps
CPU time 68.31 seconds
Started Jul 09 05:40:35 PM PDT 24
Finished Jul 09 05:41:44 PM PDT 24
Peak memory 254852 kb
Host smart-717c855a-0bdf-47a9-bbc5-afeb1d5d0a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440648845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmd
s.2440648845
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.518065190
Short name T170
Test name
Test status
Simulation time 31119214977 ps
CPU time 85.9 seconds
Started Jul 09 05:39:50 PM PDT 24
Finished Jul 09 05:41:17 PM PDT 24
Peak memory 251732 kb
Host smart-d15af21d-0316-4c19-a61e-54f76a4f6d4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518065190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmds
.518065190
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.1070518675
Short name T219
Test name
Test status
Simulation time 47973190338 ps
CPU time 225.18 seconds
Started Jul 09 05:39:14 PM PDT 24
Finished Jul 09 05:43:00 PM PDT 24
Peak memory 256276 kb
Host smart-12d9ef15-46e5-45cd-be76-f23a5246674e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070518675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.1070518675
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.2031299369
Short name T178
Test name
Test status
Simulation time 10888649948 ps
CPU time 71.09 seconds
Started Jul 09 05:39:16 PM PDT 24
Finished Jul 09 05:40:29 PM PDT 24
Peak memory 253540 kb
Host smart-6c6fc7eb-409b-4973-85ba-9fedbf453fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031299369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.2031299369
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.3781417181
Short name T60
Test name
Test status
Simulation time 276241179909 ps
CPU time 472.19 seconds
Started Jul 09 05:39:22 PM PDT 24
Finished Jul 09 05:47:15 PM PDT 24
Peak memory 263472 kb
Host smart-f594fc5d-2fb9-4840-b6bf-e50f9d0c4b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781417181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.3781417181
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.1836466207
Short name T83
Test name
Test status
Simulation time 37514721506 ps
CPU time 359.35 seconds
Started Jul 09 05:39:34 PM PDT 24
Finished Jul 09 05:45:35 PM PDT 24
Peak memory 257020 kb
Host smart-450af558-b4ab-4796-b8e2-7b8dab0584f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836466207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.1836466207
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.3702462785
Short name T226
Test name
Test status
Simulation time 4954860149 ps
CPU time 71.04 seconds
Started Jul 09 05:39:49 PM PDT 24
Finished Jul 09 05:41:01 PM PDT 24
Peak memory 255952 kb
Host smart-4e4afabd-c4d5-48d4-a37c-0310d64964dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702462785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmd
s.3702462785
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3162263742
Short name T107
Test name
Test status
Simulation time 545426633 ps
CPU time 4.58 seconds
Started Jul 09 05:35:56 PM PDT 24
Finished Jul 09 05:36:01 PM PDT 24
Peak memory 215960 kb
Host smart-0a73b72e-3aef-4ae1-95d4-020e3b9c44de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162263742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.3
162263742
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.1013264728
Short name T301
Test name
Test status
Simulation time 1752331690 ps
CPU time 22.88 seconds
Started Jul 09 05:39:48 PM PDT 24
Finished Jul 09 05:40:11 PM PDT 24
Peak memory 233416 kb
Host smart-bc82f61b-9e79-4a17-80c0-135edd6ccd53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013264728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.1013264728
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3855986999
Short name T1115
Test name
Test status
Simulation time 3225309260 ps
CPU time 23.09 seconds
Started Jul 09 05:36:06 PM PDT 24
Finished Jul 09 05:36:29 PM PDT 24
Peak memory 216408 kb
Host smart-907c4d74-5f76-4252-ade6-a5d6d48fa563
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855986999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.3855986999
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.4282733827
Short name T161
Test name
Test status
Simulation time 45319644168 ps
CPU time 492.48 seconds
Started Jul 09 05:39:11 PM PDT 24
Finished Jul 09 05:47:25 PM PDT 24
Peak memory 271692 kb
Host smart-d14c2d76-aa99-4006-8875-9bc1c38d127a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282733827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.4282733827
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_upload.3642029704
Short name T204
Test name
Test status
Simulation time 9236331649 ps
CPU time 13.66 seconds
Started Jul 09 05:39:06 PM PDT 24
Finished Jul 09 05:39:20 PM PDT 24
Peak memory 232772 kb
Host smart-a1f40ec3-56f5-452f-8c63-91bcd55f25e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642029704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.3642029704
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.151175370
Short name T51
Test name
Test status
Simulation time 30990436922 ps
CPU time 354.9 seconds
Started Jul 09 05:39:17 PM PDT 24
Finished Jul 09 05:45:13 PM PDT 24
Peak memory 268192 kb
Host smart-67cdf0f4-504a-4c25-8599-219f1a7c96fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151175370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idle
.151175370
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.3617152226
Short name T214
Test name
Test status
Simulation time 21698510390 ps
CPU time 108.52 seconds
Started Jul 09 05:39:17 PM PDT 24
Finished Jul 09 05:41:07 PM PDT 24
Peak memory 255488 kb
Host smart-228ab6af-dafe-4381-aa4f-30058bb02a7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617152226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.3617152226
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.3403913203
Short name T64
Test name
Test status
Simulation time 272865420 ps
CPU time 10.77 seconds
Started Jul 09 05:39:29 PM PDT 24
Finished Jul 09 05:39:41 PM PDT 24
Peak memory 239908 kb
Host smart-d6af8b9f-a152-41c6-98ef-362480264be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403913203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.3403913203
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.2531796980
Short name T297
Test name
Test status
Simulation time 1719755366 ps
CPU time 8.02 seconds
Started Jul 09 05:40:32 PM PDT 24
Finished Jul 09 05:40:41 PM PDT 24
Peak memory 224440 kb
Host smart-63300046-dcb3-4e57-8f10-3df9af00a235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531796980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.2531796980
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.921432760
Short name T106
Test name
Test status
Simulation time 74436133 ps
CPU time 2.53 seconds
Started Jul 09 05:36:01 PM PDT 24
Finished Jul 09 05:36:05 PM PDT 24
Peak memory 216128 kb
Host smart-62ea826e-120d-4b5f-9812-1c46ef9ff59c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921432760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.921432760
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.578044712
Short name T1079
Test name
Test status
Simulation time 214637994 ps
CPU time 7.58 seconds
Started Jul 09 05:36:11 PM PDT 24
Finished Jul 09 05:36:19 PM PDT 24
Peak memory 207452 kb
Host smart-0799212b-3dac-445e-b534-61fab6a15d69
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578044712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_aliasing.578044712
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.4249563994
Short name T1099
Test name
Test status
Simulation time 963593491 ps
CPU time 13.97 seconds
Started Jul 09 05:35:40 PM PDT 24
Finished Jul 09 05:35:55 PM PDT 24
Peak memory 207708 kb
Host smart-addf7135-cab7-407a-b5a9-17f7061c73eb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249563994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.4249563994
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2052390130
Short name T1058
Test name
Test status
Simulation time 199504765 ps
CPU time 1.64 seconds
Started Jul 09 05:35:46 PM PDT 24
Finished Jul 09 05:35:48 PM PDT 24
Peak memory 215752 kb
Host smart-4f3cc1c8-16c4-48e5-833c-83d72d92817e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052390130 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.2052390130
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2471407714
Short name T118
Test name
Test status
Simulation time 146148030 ps
CPU time 2.4 seconds
Started Jul 09 05:35:42 PM PDT 24
Finished Jul 09 05:35:45 PM PDT 24
Peak memory 215824 kb
Host smart-00fd8fc5-53bd-41c4-9901-5c83332ff1fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471407714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.2
471407714
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.1392250418
Short name T1048
Test name
Test status
Simulation time 121584459 ps
CPU time 0.7 seconds
Started Jul 09 05:35:40 PM PDT 24
Finished Jul 09 05:35:42 PM PDT 24
Peak memory 204312 kb
Host smart-51df9b16-7a28-42f6-82cc-0b362440255a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392250418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.1
392250418
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3243078590
Short name T1106
Test name
Test status
Simulation time 117459363 ps
CPU time 2.16 seconds
Started Jul 09 05:35:41 PM PDT 24
Finished Jul 09 05:35:44 PM PDT 24
Peak memory 215764 kb
Host smart-d46a05cd-0278-4e0a-abf1-22c45160a425
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243078590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.3243078590
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.3934932685
Short name T1052
Test name
Test status
Simulation time 11245548 ps
CPU time 0.63 seconds
Started Jul 09 05:35:41 PM PDT 24
Finished Jul 09 05:35:43 PM PDT 24
Peak memory 204308 kb
Host smart-0f124a63-5072-4259-bfe8-87aa61a701d6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934932685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.3934932685
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.262079063
Short name T1072
Test name
Test status
Simulation time 863427224 ps
CPU time 3.17 seconds
Started Jul 09 05:35:46 PM PDT 24
Finished Jul 09 05:35:49 PM PDT 24
Peak memory 215744 kb
Host smart-3081fd72-6825-4433-bed1-449cd5a8652d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262079063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sp
i_device_same_csr_outstanding.262079063
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.898244627
Short name T108
Test name
Test status
Simulation time 127403747 ps
CPU time 2.15 seconds
Started Jul 09 05:35:45 PM PDT 24
Finished Jul 09 05:35:48 PM PDT 24
Peak memory 215984 kb
Host smart-3682ec83-2d4f-4d5e-9ce4-ccb96c266aa8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898244627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.898244627
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3434910465
Short name T257
Test name
Test status
Simulation time 410975972 ps
CPU time 6.98 seconds
Started Jul 09 05:35:41 PM PDT 24
Finished Jul 09 05:35:49 PM PDT 24
Peak memory 222900 kb
Host smart-3393667f-90f3-4686-bdf3-4169e8571346
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434910465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.3434910465
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1847563368
Short name T1027
Test name
Test status
Simulation time 3628447731 ps
CPU time 24.15 seconds
Started Jul 09 05:35:49 PM PDT 24
Finished Jul 09 05:36:14 PM PDT 24
Peak memory 207552 kb
Host smart-839027bf-7d0e-4995-8c04-a2551f7d35c7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847563368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.1847563368
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1007136769
Short name T1122
Test name
Test status
Simulation time 1092436069 ps
CPU time 36.36 seconds
Started Jul 09 05:35:48 PM PDT 24
Finished Jul 09 05:36:25 PM PDT 24
Peak memory 207528 kb
Host smart-e86b03fc-2949-4165-b26e-4e1306f50168
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007136769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.1007136769
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2456372465
Short name T85
Test name
Test status
Simulation time 26451536 ps
CPU time 0.99 seconds
Started Jul 09 05:35:45 PM PDT 24
Finished Jul 09 05:35:46 PM PDT 24
Peak memory 207184 kb
Host smart-cea5fe19-3006-4ca4-89e6-87d15d6608c5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456372465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.2456372465
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3202832610
Short name T1042
Test name
Test status
Simulation time 139578906 ps
CPU time 2.83 seconds
Started Jul 09 05:35:49 PM PDT 24
Finished Jul 09 05:35:52 PM PDT 24
Peak memory 217364 kb
Host smart-152b04de-3487-4796-bc0a-c9a8fc024808
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202832610 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.3202832610
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1982284582
Short name T1060
Test name
Test status
Simulation time 1058132386 ps
CPU time 2.75 seconds
Started Jul 09 05:35:43 PM PDT 24
Finished Jul 09 05:35:47 PM PDT 24
Peak memory 215636 kb
Host smart-305f2146-0960-4c02-ac50-907e6bdf9789
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982284582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.1
982284582
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.1218975217
Short name T1030
Test name
Test status
Simulation time 13283905 ps
CPU time 0.7 seconds
Started Jul 09 05:35:46 PM PDT 24
Finished Jul 09 05:35:47 PM PDT 24
Peak memory 204304 kb
Host smart-17d9b000-5202-4f9b-9809-a5c21327cb6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218975217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.1
218975217
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.1191100365
Short name T1111
Test name
Test status
Simulation time 102458093 ps
CPU time 1.78 seconds
Started Jul 09 05:35:44 PM PDT 24
Finished Jul 09 05:35:46 PM PDT 24
Peak memory 215732 kb
Host smart-4853353e-14ab-45fc-9a97-e070af0a7979
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191100365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.1191100365
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2546937578
Short name T1044
Test name
Test status
Simulation time 10269532 ps
CPU time 0.64 seconds
Started Jul 09 05:35:45 PM PDT 24
Finished Jul 09 05:35:47 PM PDT 24
Peak memory 204080 kb
Host smart-537dda7b-3d12-4544-bc52-7ac87ac71bc4
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546937578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.2546937578
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.306869819
Short name T1129
Test name
Test status
Simulation time 312025738 ps
CPU time 2.86 seconds
Started Jul 09 05:35:48 PM PDT 24
Finished Jul 09 05:35:52 PM PDT 24
Peak memory 215696 kb
Host smart-ba76da44-6b12-45c5-98f4-867e8179dff2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306869819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sp
i_device_same_csr_outstanding.306869819
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.3816833463
Short name T252
Test name
Test status
Simulation time 581551723 ps
CPU time 3.56 seconds
Started Jul 09 05:35:45 PM PDT 24
Finished Jul 09 05:35:49 PM PDT 24
Peak memory 216016 kb
Host smart-38b5f95a-8f78-48f2-904f-a650f15e437b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816833463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.3
816833463
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2533750767
Short name T259
Test name
Test status
Simulation time 1000347868 ps
CPU time 16.87 seconds
Started Jul 09 05:35:43 PM PDT 24
Finished Jul 09 05:36:00 PM PDT 24
Peak memory 215736 kb
Host smart-f735baff-67d7-4a56-abc5-a18fcfa599d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533750767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.2533750767
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.728110790
Short name T158
Test name
Test status
Simulation time 97831415 ps
CPU time 1.96 seconds
Started Jul 09 05:36:01 PM PDT 24
Finished Jul 09 05:36:04 PM PDT 24
Peak memory 216960 kb
Host smart-eb064b7d-27ba-4aed-8607-0814cb4bcebd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728110790 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.728110790
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3641732181
Short name T124
Test name
Test status
Simulation time 154366646 ps
CPU time 1.32 seconds
Started Jul 09 05:36:07 PM PDT 24
Finished Jul 09 05:36:10 PM PDT 24
Peak memory 207048 kb
Host smart-772e0be9-5cc4-4703-8ce3-63ba185b52c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641732181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
3641732181
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2308672774
Short name T1081
Test name
Test status
Simulation time 14667362 ps
CPU time 0.72 seconds
Started Jul 09 05:36:05 PM PDT 24
Finished Jul 09 05:36:06 PM PDT 24
Peak memory 204316 kb
Host smart-d6e3de5f-0c81-420a-ab38-d77162e09fc0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308672774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
2308672774
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2402368668
Short name T140
Test name
Test status
Simulation time 1177302910 ps
CPU time 4 seconds
Started Jul 09 05:36:07 PM PDT 24
Finished Jul 09 05:36:12 PM PDT 24
Peak memory 215880 kb
Host smart-2b0a7b53-190c-49b9-ac76-2117b9db4c78
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402368668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.2402368668
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.2262517881
Short name T256
Test name
Test status
Simulation time 205511604 ps
CPU time 13.14 seconds
Started Jul 09 05:36:02 PM PDT 24
Finished Jul 09 05:36:16 PM PDT 24
Peak memory 215756 kb
Host smart-3d2fd4c1-9b52-4106-916c-3add29719ef7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262517881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.2262517881
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.4076358910
Short name T114
Test name
Test status
Simulation time 95856446 ps
CPU time 1.69 seconds
Started Jul 09 05:36:07 PM PDT 24
Finished Jul 09 05:36:10 PM PDT 24
Peak memory 215872 kb
Host smart-ce27a8dd-9d13-4202-8898-9a5f99c9a988
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076358910 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.4076358910
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.3445026026
Short name T1103
Test name
Test status
Simulation time 44272423 ps
CPU time 2.05 seconds
Started Jul 09 05:36:06 PM PDT 24
Finished Jul 09 05:36:09 PM PDT 24
Peak memory 207480 kb
Host smart-690ad79c-dfe5-474e-a2fb-6be79d4a8377
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445026026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
3445026026
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.4081925960
Short name T1094
Test name
Test status
Simulation time 55907657 ps
CPU time 0.69 seconds
Started Jul 09 05:36:07 PM PDT 24
Finished Jul 09 05:36:09 PM PDT 24
Peak memory 204244 kb
Host smart-afc29470-deeb-4814-8800-8752ecaf2a94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081925960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
4081925960
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.4015267589
Short name T143
Test name
Test status
Simulation time 53301313 ps
CPU time 1.69 seconds
Started Jul 09 05:36:06 PM PDT 24
Finished Jul 09 05:36:08 PM PDT 24
Peak memory 215668 kb
Host smart-037f118b-27ce-4ea5-938e-718d5cb07d18
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015267589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.4015267589
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3151391805
Short name T1067
Test name
Test status
Simulation time 50476721 ps
CPU time 3.6 seconds
Started Jul 09 05:36:02 PM PDT 24
Finished Jul 09 05:36:06 PM PDT 24
Peak memory 216044 kb
Host smart-ee527979-a210-429b-851d-9219896c238c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151391805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
3151391805
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3527995307
Short name T1120
Test name
Test status
Simulation time 127523353 ps
CPU time 3.6 seconds
Started Jul 09 05:36:07 PM PDT 24
Finished Jul 09 05:36:11 PM PDT 24
Peak memory 217900 kb
Host smart-354db0d6-2616-42fa-9d18-515ec9e0ffb9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527995307 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.3527995307
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.3225295645
Short name T128
Test name
Test status
Simulation time 39524010 ps
CPU time 1.34 seconds
Started Jul 09 05:36:04 PM PDT 24
Finished Jul 09 05:36:06 PM PDT 24
Peak memory 215736 kb
Host smart-1292f094-dbf2-40b6-bb8a-4342970d6828
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225295645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
3225295645
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3188387638
Short name T1095
Test name
Test status
Simulation time 15162797 ps
CPU time 0.8 seconds
Started Jul 09 05:36:05 PM PDT 24
Finished Jul 09 05:36:07 PM PDT 24
Peak memory 204304 kb
Host smart-8217414b-71a5-49e7-924d-c890e93b7bd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188387638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
3188387638
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.2633728225
Short name T1022
Test name
Test status
Simulation time 57483964 ps
CPU time 4.09 seconds
Started Jul 09 05:36:06 PM PDT 24
Finished Jul 09 05:36:11 PM PDT 24
Peak memory 215820 kb
Host smart-6a08e472-b7da-4e40-8da1-5941ac6fe64c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633728225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.2633728225
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.152988910
Short name T99
Test name
Test status
Simulation time 179997846 ps
CPU time 4.51 seconds
Started Jul 09 05:36:13 PM PDT 24
Finished Jul 09 05:36:18 PM PDT 24
Peak memory 215880 kb
Host smart-bf087634-1da3-4cbd-9876-ffaffb9bfb85
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152988910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.152988910
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2143279123
Short name T110
Test name
Test status
Simulation time 59460078 ps
CPU time 3.76 seconds
Started Jul 09 05:36:10 PM PDT 24
Finished Jul 09 05:36:15 PM PDT 24
Peak memory 219068 kb
Host smart-9a56125e-0e05-4427-9848-abda22cdd21f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143279123 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.2143279123
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3043047067
Short name T155
Test name
Test status
Simulation time 210659609 ps
CPU time 2.08 seconds
Started Jul 09 05:36:06 PM PDT 24
Finished Jul 09 05:36:09 PM PDT 24
Peak memory 207536 kb
Host smart-967a51fe-79fb-46b1-85dd-6a475176ea38
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043047067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
3043047067
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.1734901987
Short name T1085
Test name
Test status
Simulation time 51309922 ps
CPU time 0.73 seconds
Started Jul 09 05:36:04 PM PDT 24
Finished Jul 09 05:36:06 PM PDT 24
Peak memory 204312 kb
Host smart-b5602d2f-114e-45de-b518-7dba14bc3edb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734901987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
1734901987
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2601073422
Short name T1076
Test name
Test status
Simulation time 562081599 ps
CPU time 3.15 seconds
Started Jul 09 05:36:06 PM PDT 24
Finished Jul 09 05:36:10 PM PDT 24
Peak memory 215752 kb
Host smart-780b8036-b94b-4d0d-a6d7-2e253664f1ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601073422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.2601073422
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.536821416
Short name T103
Test name
Test status
Simulation time 162247559 ps
CPU time 4.14 seconds
Started Jul 09 05:36:07 PM PDT 24
Finished Jul 09 05:36:12 PM PDT 24
Peak memory 215980 kb
Host smart-54a206d5-45f4-424b-a52a-5190eb29b68b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536821416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.536821416
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3844164454
Short name T1045
Test name
Test status
Simulation time 66693120 ps
CPU time 2.43 seconds
Started Jul 09 05:36:13 PM PDT 24
Finished Jul 09 05:36:17 PM PDT 24
Peak memory 218436 kb
Host smart-4c67fdec-d3f5-454c-ab50-1f2461e67f01
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844164454 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.3844164454
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.4058714047
Short name T126
Test name
Test status
Simulation time 360310018 ps
CPU time 2.2 seconds
Started Jul 09 05:36:09 PM PDT 24
Finished Jul 09 05:36:12 PM PDT 24
Peak memory 215732 kb
Host smart-34e203cf-9e7b-49ce-8708-3138bc998465
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058714047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
4058714047
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2578265462
Short name T1054
Test name
Test status
Simulation time 31585565 ps
CPU time 0.7 seconds
Started Jul 09 05:36:09 PM PDT 24
Finished Jul 09 05:36:10 PM PDT 24
Peak memory 204324 kb
Host smart-07ab462b-bae7-4795-a2f5-77832cfdf271
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578265462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
2578265462
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2521423011
Short name T1125
Test name
Test status
Simulation time 96459648 ps
CPU time 2.99 seconds
Started Jul 09 05:36:10 PM PDT 24
Finished Jul 09 05:36:13 PM PDT 24
Peak memory 215612 kb
Host smart-e62fd82b-2982-41fa-b54a-e8e0ccac687a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521423011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.2521423011
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.319584108
Short name T1091
Test name
Test status
Simulation time 467199936 ps
CPU time 3.58 seconds
Started Jul 09 05:36:11 PM PDT 24
Finished Jul 09 05:36:15 PM PDT 24
Peak memory 216084 kb
Host smart-dc91d919-c76d-4175-96c0-e0f8a3724295
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319584108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.319584108
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2179323846
Short name T116
Test name
Test status
Simulation time 4191670008 ps
CPU time 22.35 seconds
Started Jul 09 05:36:09 PM PDT 24
Finished Jul 09 05:36:32 PM PDT 24
Peak memory 215924 kb
Host smart-ce2acf42-8f93-4a00-a3ec-29c6b0b3e223
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179323846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.2179323846
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1531671059
Short name T113
Test name
Test status
Simulation time 162837433 ps
CPU time 3.91 seconds
Started Jul 09 05:36:13 PM PDT 24
Finished Jul 09 05:36:18 PM PDT 24
Peak memory 218584 kb
Host smart-d970ef3a-2dc2-4c4c-9ce2-f7244d954e02
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531671059 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.1531671059
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1049722678
Short name T157
Test name
Test status
Simulation time 278513280 ps
CPU time 1.85 seconds
Started Jul 09 05:36:10 PM PDT 24
Finished Jul 09 05:36:12 PM PDT 24
Peak memory 207592 kb
Host smart-b529195a-36e1-41c4-9b3b-a79fb381ecbf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049722678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
1049722678
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.2309815302
Short name T1024
Test name
Test status
Simulation time 33568241 ps
CPU time 0.73 seconds
Started Jul 09 05:36:08 PM PDT 24
Finished Jul 09 05:36:09 PM PDT 24
Peak memory 204232 kb
Host smart-f1730496-6340-4053-bba8-3003238d708a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309815302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
2309815302
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1052148905
Short name T1100
Test name
Test status
Simulation time 232148550 ps
CPU time 3.1 seconds
Started Jul 09 05:36:13 PM PDT 24
Finished Jul 09 05:36:16 PM PDT 24
Peak memory 215724 kb
Host smart-9f62e764-153d-45d4-b128-b219634b7321
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052148905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.1052148905
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1244326022
Short name T1116
Test name
Test status
Simulation time 381482804 ps
CPU time 2.98 seconds
Started Jul 09 05:36:12 PM PDT 24
Finished Jul 09 05:36:15 PM PDT 24
Peak memory 216072 kb
Host smart-327ebfa1-4239-46cf-9728-12ac63682d16
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244326022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
1244326022
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3568193821
Short name T1083
Test name
Test status
Simulation time 2692511957 ps
CPU time 14.8 seconds
Started Jul 09 05:36:13 PM PDT 24
Finished Jul 09 05:36:29 PM PDT 24
Peak memory 216100 kb
Host smart-cb53322d-e132-42aa-93d9-2bb5b0db2e0c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568193821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.3568193821
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1525525997
Short name T1033
Test name
Test status
Simulation time 184145038 ps
CPU time 1.69 seconds
Started Jul 09 05:36:15 PM PDT 24
Finished Jul 09 05:36:17 PM PDT 24
Peak memory 215804 kb
Host smart-bbd7c9ea-0ab3-43f8-beba-f9594feb50c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525525997 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.1525525997
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1267709591
Short name T1112
Test name
Test status
Simulation time 661591117 ps
CPU time 2.9 seconds
Started Jul 09 05:36:19 PM PDT 24
Finished Jul 09 05:36:23 PM PDT 24
Peak memory 215768 kb
Host smart-63abd109-08f1-466f-b02f-8b404c59e524
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267709591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
1267709591
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.2586852521
Short name T1038
Test name
Test status
Simulation time 36480404 ps
CPU time 0.75 seconds
Started Jul 09 05:36:14 PM PDT 24
Finished Jul 09 05:36:16 PM PDT 24
Peak memory 204552 kb
Host smart-185c95bb-5c96-481e-b60f-3d63ec69e2f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586852521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
2586852521
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.2481005551
Short name T1074
Test name
Test status
Simulation time 792094781 ps
CPU time 4.29 seconds
Started Jul 09 05:36:13 PM PDT 24
Finished Jul 09 05:36:18 PM PDT 24
Peak memory 215652 kb
Host smart-6889d5c0-f634-48e7-ae34-451fd4251452
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481005551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.2481005551
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2454067856
Short name T262
Test name
Test status
Simulation time 4232616396 ps
CPU time 21.47 seconds
Started Jul 09 05:36:14 PM PDT 24
Finished Jul 09 05:36:36 PM PDT 24
Peak memory 215956 kb
Host smart-5ef04dd6-4533-4bb6-929d-b03e79ee973a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454067856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.2454067856
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3210178854
Short name T65
Test name
Test status
Simulation time 41052887 ps
CPU time 2.97 seconds
Started Jul 09 05:36:16 PM PDT 24
Finished Jul 09 05:36:20 PM PDT 24
Peak memory 218332 kb
Host smart-b1ca0ec8-4486-49f1-a460-05c66e2cdc27
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210178854 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.3210178854
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.2550426200
Short name T125
Test name
Test status
Simulation time 91896815 ps
CPU time 2.55 seconds
Started Jul 09 05:36:17 PM PDT 24
Finished Jul 09 05:36:20 PM PDT 24
Peak memory 215716 kb
Host smart-9b0bd16d-fbb8-4459-9d63-715fec6938cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550426200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
2550426200
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.992590355
Short name T1037
Test name
Test status
Simulation time 44157214 ps
CPU time 0.74 seconds
Started Jul 09 05:36:14 PM PDT 24
Finished Jul 09 05:36:15 PM PDT 24
Peak memory 204320 kb
Host smart-38031f64-cb55-4c57-8d05-6c64510c842c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992590355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.992590355
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2503854168
Short name T1068
Test name
Test status
Simulation time 110017564 ps
CPU time 3.66 seconds
Started Jul 09 05:36:15 PM PDT 24
Finished Jul 09 05:36:19 PM PDT 24
Peak memory 215740 kb
Host smart-d2a6f1bd-90e0-4b91-8341-4bc9456da73d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503854168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.2503854168
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3963962809
Short name T104
Test name
Test status
Simulation time 107897645 ps
CPU time 3.71 seconds
Started Jul 09 05:36:15 PM PDT 24
Finished Jul 09 05:36:19 PM PDT 24
Peak memory 216060 kb
Host smart-bc6aaceb-aa94-4c8f-a2c7-b9c42f689f3d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963962809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
3963962809
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.2897624551
Short name T1071
Test name
Test status
Simulation time 297613639 ps
CPU time 7.82 seconds
Started Jul 09 05:36:16 PM PDT 24
Finished Jul 09 05:36:25 PM PDT 24
Peak memory 215792 kb
Host smart-6eda57f2-36c0-49ff-b708-df6680d85bd6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897624551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.2897624551
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.1582853708
Short name T66
Test name
Test status
Simulation time 109123385 ps
CPU time 3.49 seconds
Started Jul 09 05:36:20 PM PDT 24
Finished Jul 09 05:36:24 PM PDT 24
Peak memory 218812 kb
Host smart-24a9ac01-7072-464f-86ba-3e7ddcf790ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582853708 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.1582853708
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3924622881
Short name T1130
Test name
Test status
Simulation time 79327217 ps
CPU time 2.04 seconds
Started Jul 09 05:36:16 PM PDT 24
Finished Jul 09 05:36:18 PM PDT 24
Peak memory 215720 kb
Host smart-158c3ff2-15b4-4d1a-910a-7b2253419132
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924622881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
3924622881
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.4101547794
Short name T1020
Test name
Test status
Simulation time 15885839 ps
CPU time 0.74 seconds
Started Jul 09 05:36:14 PM PDT 24
Finished Jul 09 05:36:16 PM PDT 24
Peak memory 204268 kb
Host smart-c162924f-23e8-49d2-b265-5670b46d2df8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101547794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
4101547794
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1196883594
Short name T1118
Test name
Test status
Simulation time 206425048 ps
CPU time 4.12 seconds
Started Jul 09 05:36:18 PM PDT 24
Finished Jul 09 05:36:22 PM PDT 24
Peak memory 215812 kb
Host smart-9d74e5df-7902-4730-ab25-75dc12f4dd6a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196883594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.1196883594
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.868622627
Short name T112
Test name
Test status
Simulation time 64659677 ps
CPU time 4.39 seconds
Started Jul 09 05:36:19 PM PDT 24
Finished Jul 09 05:36:24 PM PDT 24
Peak memory 216012 kb
Host smart-c51d4087-1ec7-4b06-b677-c5c9820420ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868622627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.868622627
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.3251971552
Short name T1056
Test name
Test status
Simulation time 1137157817 ps
CPU time 7.15 seconds
Started Jul 09 05:36:14 PM PDT 24
Finished Jul 09 05:36:21 PM PDT 24
Peak memory 216208 kb
Host smart-2f08c40a-70c5-479f-a5a3-5dc2e24ae959
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251971552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.3251971552
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1473793488
Short name T1053
Test name
Test status
Simulation time 187603249 ps
CPU time 4.36 seconds
Started Jul 09 05:36:16 PM PDT 24
Finished Jul 09 05:36:21 PM PDT 24
Peak memory 219092 kb
Host smart-020511f8-e2b7-4325-b2fe-fe86c9832767
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473793488 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.1473793488
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2381677992
Short name T145
Test name
Test status
Simulation time 140081783 ps
CPU time 1.41 seconds
Started Jul 09 05:36:19 PM PDT 24
Finished Jul 09 05:36:21 PM PDT 24
Peak memory 215740 kb
Host smart-ebccb1f6-7ce3-4b2e-931a-347c602b4932
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381677992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
2381677992
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2095785775
Short name T1017
Test name
Test status
Simulation time 40964534 ps
CPU time 0.71 seconds
Started Jul 09 05:36:21 PM PDT 24
Finished Jul 09 05:36:22 PM PDT 24
Peak memory 204304 kb
Host smart-27b7cbe6-5d7f-4617-bdab-00b09c0b662c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095785775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
2095785775
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2913206473
Short name T142
Test name
Test status
Simulation time 164186541 ps
CPU time 2.72 seconds
Started Jul 09 05:36:17 PM PDT 24
Finished Jul 09 05:36:20 PM PDT 24
Peak memory 215740 kb
Host smart-caa333ab-f306-4571-aeba-425fd64432e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913206473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.2913206473
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2232345693
Short name T1105
Test name
Test status
Simulation time 591654338 ps
CPU time 4.05 seconds
Started Jul 09 05:36:15 PM PDT 24
Finished Jul 09 05:36:20 PM PDT 24
Peak memory 216220 kb
Host smart-11d279e9-a383-4a12-bd4f-720a35e14f50
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232345693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
2232345693
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2303140183
Short name T261
Test name
Test status
Simulation time 213454001 ps
CPU time 6.9 seconds
Started Jul 09 05:36:15 PM PDT 24
Finished Jul 09 05:36:23 PM PDT 24
Peak memory 215760 kb
Host smart-8874c6a5-dd2f-4290-b919-8f7567ff3a66
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303140183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.2303140183
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.1770609082
Short name T1124
Test name
Test status
Simulation time 324786942 ps
CPU time 8.04 seconds
Started Jul 09 05:35:52 PM PDT 24
Finished Jul 09 05:36:01 PM PDT 24
Peak memory 207544 kb
Host smart-e2b43661-2935-4404-b1f0-da08cba75c77
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770609082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.1770609082
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2082021786
Short name T1084
Test name
Test status
Simulation time 7522806990 ps
CPU time 27.61 seconds
Started Jul 09 05:35:53 PM PDT 24
Finished Jul 09 05:36:21 PM PDT 24
Peak memory 215820 kb
Host smart-a869ce01-2a87-45f7-b24b-53f2e8143d02
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082021786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.2082021786
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3517105589
Short name T86
Test name
Test status
Simulation time 65690408 ps
CPU time 1.2 seconds
Started Jul 09 05:35:50 PM PDT 24
Finished Jul 09 05:35:52 PM PDT 24
Peak memory 216724 kb
Host smart-fb065a32-ccb3-40e6-809c-333e4f67f24b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517105589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.3517105589
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.984544139
Short name T1065
Test name
Test status
Simulation time 336681329 ps
CPU time 2.38 seconds
Started Jul 09 05:35:54 PM PDT 24
Finished Jul 09 05:35:58 PM PDT 24
Peak memory 215788 kb
Host smart-83935da2-2c21-4247-9e38-e8d6fc89a76f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984544139 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.984544139
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2491112171
Short name T1096
Test name
Test status
Simulation time 41707366 ps
CPU time 2.51 seconds
Started Jul 09 05:35:49 PM PDT 24
Finished Jul 09 05:35:52 PM PDT 24
Peak memory 215668 kb
Host smart-2c0ee165-7d16-40a1-b1e0-de0451b26693
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491112171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.2
491112171
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.2094049733
Short name T1108
Test name
Test status
Simulation time 34790921 ps
CPU time 0.66 seconds
Started Jul 09 05:35:48 PM PDT 24
Finished Jul 09 05:35:49 PM PDT 24
Peak memory 204184 kb
Host smart-24704517-5cb6-4b99-b2c3-0b9210947a6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094049733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.2
094049733
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3577925813
Short name T123
Test name
Test status
Simulation time 51568729 ps
CPU time 2.19 seconds
Started Jul 09 05:35:50 PM PDT 24
Finished Jul 09 05:35:53 PM PDT 24
Peak memory 215668 kb
Host smart-4753a926-b731-4d57-abac-bc95422e3aef
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577925813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.3577925813
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3160810468
Short name T1089
Test name
Test status
Simulation time 39308417 ps
CPU time 0.66 seconds
Started Jul 09 05:35:50 PM PDT 24
Finished Jul 09 05:35:51 PM PDT 24
Peak memory 204044 kb
Host smart-ba764bf0-bf79-4ef4-b791-5df67cd12e0c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160810468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.3160810468
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1367296262
Short name T1098
Test name
Test status
Simulation time 2136888331 ps
CPU time 3.95 seconds
Started Jul 09 05:35:51 PM PDT 24
Finished Jul 09 05:35:56 PM PDT 24
Peak memory 215768 kb
Host smart-b5d33245-fd79-4d67-bf72-e9dd30951c09
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367296262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.1367296262
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3719862646
Short name T105
Test name
Test status
Simulation time 72048274 ps
CPU time 2.13 seconds
Started Jul 09 05:35:49 PM PDT 24
Finished Jul 09 05:35:52 PM PDT 24
Peak memory 216020 kb
Host smart-50790959-055e-4059-89cd-358b1f585dff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719862646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.3
719862646
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.829640869
Short name T97
Test name
Test status
Simulation time 498978929 ps
CPU time 7.15 seconds
Started Jul 09 05:35:48 PM PDT 24
Finished Jul 09 05:35:56 PM PDT 24
Peak memory 222600 kb
Host smart-761e9e55-ae66-4ee0-8c5a-54329ea18479
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829640869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_
tl_intg_err.829640869
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2113785998
Short name T1026
Test name
Test status
Simulation time 205511495 ps
CPU time 0.76 seconds
Started Jul 09 05:36:16 PM PDT 24
Finished Jul 09 05:36:17 PM PDT 24
Peak memory 204260 kb
Host smart-b7493e86-0487-4e49-87d4-52ffd8997d7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113785998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
2113785998
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2556279564
Short name T1025
Test name
Test status
Simulation time 21948765 ps
CPU time 0.7 seconds
Started Jul 09 05:36:17 PM PDT 24
Finished Jul 09 05:36:19 PM PDT 24
Peak memory 204272 kb
Host smart-becf2244-be26-43fc-b6a2-2f33f938f3d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556279564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
2556279564
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.222382167
Short name T1018
Test name
Test status
Simulation time 67139177 ps
CPU time 0.73 seconds
Started Jul 09 05:36:15 PM PDT 24
Finished Jul 09 05:36:17 PM PDT 24
Peak memory 204512 kb
Host smart-38e81143-439a-41ee-892e-75ce372eafe1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222382167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.222382167
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.4095323283
Short name T1055
Test name
Test status
Simulation time 45889672 ps
CPU time 0.75 seconds
Started Jul 09 05:36:18 PM PDT 24
Finished Jul 09 05:36:20 PM PDT 24
Peak memory 204296 kb
Host smart-d274cf73-b1aa-4ada-910a-907c4b042317
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095323283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
4095323283
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.2064115830
Short name T1036
Test name
Test status
Simulation time 43127056 ps
CPU time 0.79 seconds
Started Jul 09 05:36:17 PM PDT 24
Finished Jul 09 05:36:18 PM PDT 24
Peak memory 204612 kb
Host smart-ab98a806-7784-41b4-8178-95a164fded98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064115830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
2064115830
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3501219081
Short name T1101
Test name
Test status
Simulation time 13325556 ps
CPU time 0.7 seconds
Started Jul 09 05:36:22 PM PDT 24
Finished Jul 09 05:36:23 PM PDT 24
Peak memory 204508 kb
Host smart-8255660d-7c3e-4ef3-8f2f-663e0e34c3a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501219081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
3501219081
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2212381036
Short name T1127
Test name
Test status
Simulation time 55328266 ps
CPU time 0.74 seconds
Started Jul 09 05:36:24 PM PDT 24
Finished Jul 09 05:36:26 PM PDT 24
Peak memory 204632 kb
Host smart-ad0e0b97-32e8-451e-b3e2-fac46c1252a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212381036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
2212381036
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.483545503
Short name T1090
Test name
Test status
Simulation time 14272823 ps
CPU time 0.74 seconds
Started Jul 09 05:36:22 PM PDT 24
Finished Jul 09 05:36:23 PM PDT 24
Peak memory 204228 kb
Host smart-d6d43f4c-cf87-44b0-ba04-c34c84d1824e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483545503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.483545503
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.2165328019
Short name T1087
Test name
Test status
Simulation time 36002738 ps
CPU time 0.7 seconds
Started Jul 09 05:36:19 PM PDT 24
Finished Jul 09 05:36:20 PM PDT 24
Peak memory 204320 kb
Host smart-09196ba9-15f1-4c20-a6b3-957ec1b8f955
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165328019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
2165328019
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2019371062
Short name T1109
Test name
Test status
Simulation time 166882296 ps
CPU time 0.67 seconds
Started Jul 09 05:36:25 PM PDT 24
Finished Jul 09 05:36:27 PM PDT 24
Peak memory 204320 kb
Host smart-6450947b-c86e-4dcc-8a27-752536a6d016
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019371062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
2019371062
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.173600745
Short name T1073
Test name
Test status
Simulation time 313366397 ps
CPU time 21.81 seconds
Started Jul 09 05:35:54 PM PDT 24
Finished Jul 09 05:36:17 PM PDT 24
Peak memory 215752 kb
Host smart-7bceaf6a-1517-4127-977b-1d6aea2a9224
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173600745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_aliasing.173600745
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.4193404025
Short name T119
Test name
Test status
Simulation time 367415008 ps
CPU time 24.83 seconds
Started Jul 09 05:35:55 PM PDT 24
Finished Jul 09 05:36:20 PM PDT 24
Peak memory 207600 kb
Host smart-1249543e-f02a-49b2-9550-535cb36d2a9d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193404025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.4193404025
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2522554414
Short name T87
Test name
Test status
Simulation time 36204982 ps
CPU time 1.21 seconds
Started Jul 09 05:35:53 PM PDT 24
Finished Jul 09 05:35:55 PM PDT 24
Peak memory 207432 kb
Host smart-b9ce9b7d-13a6-4141-b11c-aa32defe1276
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522554414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.2522554414
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.305724501
Short name T1104
Test name
Test status
Simulation time 110851759 ps
CPU time 2.95 seconds
Started Jul 09 05:35:52 PM PDT 24
Finished Jul 09 05:35:55 PM PDT 24
Peak memory 215948 kb
Host smart-c222a9a5-bbc7-4b3b-9321-445e2b9afc6b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305724501 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.305724501
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1367236146
Short name T122
Test name
Test status
Simulation time 314209553 ps
CPU time 2.04 seconds
Started Jul 09 05:35:51 PM PDT 24
Finished Jul 09 05:35:54 PM PDT 24
Peak memory 215672 kb
Host smart-8b92cb3b-7af5-45f0-9d37-db6cce1ab751
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367236146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.1
367236146
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3222139757
Short name T1041
Test name
Test status
Simulation time 25790969 ps
CPU time 0.71 seconds
Started Jul 09 05:35:52 PM PDT 24
Finished Jul 09 05:35:53 PM PDT 24
Peak memory 204556 kb
Host smart-40a93917-475c-457c-8c80-83801a10d339
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222139757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.3
222139757
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2016646545
Short name T1123
Test name
Test status
Simulation time 44568095 ps
CPU time 1.82 seconds
Started Jul 09 05:35:53 PM PDT 24
Finished Jul 09 05:35:56 PM PDT 24
Peak memory 215784 kb
Host smart-0cce6e7d-732c-44c9-80c7-387230ebb954
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016646545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.2016646545
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.2325855524
Short name T1093
Test name
Test status
Simulation time 37195257 ps
CPU time 0.67 seconds
Started Jul 09 05:35:54 PM PDT 24
Finished Jul 09 05:35:56 PM PDT 24
Peak memory 204108 kb
Host smart-ec393d1e-aa65-41af-9471-d2842533fbc0
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325855524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.2325855524
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.189152183
Short name T1121
Test name
Test status
Simulation time 519248131 ps
CPU time 2.93 seconds
Started Jul 09 05:35:56 PM PDT 24
Finished Jul 09 05:35:59 PM PDT 24
Peak memory 215656 kb
Host smart-2532d07d-eff5-4032-a713-a2970bb93e2e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189152183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sp
i_device_same_csr_outstanding.189152183
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2429894670
Short name T98
Test name
Test status
Simulation time 68280636 ps
CPU time 2.38 seconds
Started Jul 09 05:35:58 PM PDT 24
Finished Jul 09 05:36:00 PM PDT 24
Peak memory 216020 kb
Host smart-e33fd85b-2e18-4e73-9b3f-1d44897bc5a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429894670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.2
429894670
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2852210680
Short name T253
Test name
Test status
Simulation time 1207001064 ps
CPU time 18.54 seconds
Started Jul 09 05:35:54 PM PDT 24
Finished Jul 09 05:36:13 PM PDT 24
Peak memory 215940 kb
Host smart-e7267794-1477-4c32-b912-d8eb416ace7b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852210680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.2852210680
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1802552330
Short name T1114
Test name
Test status
Simulation time 10815824 ps
CPU time 0.75 seconds
Started Jul 09 05:36:22 PM PDT 24
Finished Jul 09 05:36:23 PM PDT 24
Peak memory 204324 kb
Host smart-8f3606bc-d5fd-4dbb-a3fb-e3958b70630a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802552330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
1802552330
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.1240563887
Short name T1078
Test name
Test status
Simulation time 13652007 ps
CPU time 0.72 seconds
Started Jul 09 05:36:22 PM PDT 24
Finished Jul 09 05:36:24 PM PDT 24
Peak memory 204272 kb
Host smart-4bb0f09d-8129-4bf5-9596-bc025813d3c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240563887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
1240563887
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.281386890
Short name T1043
Test name
Test status
Simulation time 12716930 ps
CPU time 0.73 seconds
Started Jul 09 05:36:21 PM PDT 24
Finished Jul 09 05:36:22 PM PDT 24
Peak memory 204268 kb
Host smart-749622b6-fdc2-4f73-8ff6-68bb9a5bc289
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281386890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.281386890
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.834576333
Short name T1035
Test name
Test status
Simulation time 47282981 ps
CPU time 0.72 seconds
Started Jul 09 05:36:22 PM PDT 24
Finished Jul 09 05:36:23 PM PDT 24
Peak memory 204268 kb
Host smart-d8e9254d-3bd0-422b-aa4b-e8eaea0f7de4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834576333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.834576333
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.2106078616
Short name T1063
Test name
Test status
Simulation time 50811895 ps
CPU time 0.77 seconds
Started Jul 09 05:36:24 PM PDT 24
Finished Jul 09 05:36:25 PM PDT 24
Peak memory 204324 kb
Host smart-bf0bc9d4-2e34-4444-82f4-7fbe169e8dc5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106078616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
2106078616
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.387088488
Short name T1092
Test name
Test status
Simulation time 68445499 ps
CPU time 0.74 seconds
Started Jul 09 05:36:21 PM PDT 24
Finished Jul 09 05:36:23 PM PDT 24
Peak memory 204308 kb
Host smart-01228b97-945c-4d79-8f8a-875bae03715e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387088488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.387088488
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2371378862
Short name T1015
Test name
Test status
Simulation time 18794309 ps
CPU time 0.7 seconds
Started Jul 09 05:36:21 PM PDT 24
Finished Jul 09 05:36:22 PM PDT 24
Peak memory 204296 kb
Host smart-61dee02f-5a16-4ead-b4b7-269e3ed18907
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371378862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
2371378862
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.2035773289
Short name T1047
Test name
Test status
Simulation time 71276710 ps
CPU time 0.7 seconds
Started Jul 09 05:36:21 PM PDT 24
Finished Jul 09 05:36:23 PM PDT 24
Peak memory 204672 kb
Host smart-e2499558-868b-4087-aeb8-970701aa640b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035773289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
2035773289
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.1032447967
Short name T1023
Test name
Test status
Simulation time 12970322 ps
CPU time 0.71 seconds
Started Jul 09 05:36:21 PM PDT 24
Finished Jul 09 05:36:22 PM PDT 24
Peak memory 204624 kb
Host smart-96681699-e929-49cc-9b3a-a4a41dd645e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032447967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
1032447967
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1073484174
Short name T1028
Test name
Test status
Simulation time 12735622 ps
CPU time 0.71 seconds
Started Jul 09 05:36:22 PM PDT 24
Finished Jul 09 05:36:23 PM PDT 24
Peak memory 204228 kb
Host smart-f1998887-95fa-4629-92fa-1f430bbbc5f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073484174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
1073484174
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3735901616
Short name T120
Test name
Test status
Simulation time 2711787848 ps
CPU time 16.52 seconds
Started Jul 09 05:35:56 PM PDT 24
Finished Jul 09 05:36:13 PM PDT 24
Peak memory 215672 kb
Host smart-5a1bc2d4-9ae6-4eff-b130-76c317c53e17
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735901616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.3735901616
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3073492316
Short name T129
Test name
Test status
Simulation time 2795711710 ps
CPU time 41.1 seconds
Started Jul 09 05:35:57 PM PDT 24
Finished Jul 09 05:36:38 PM PDT 24
Peak memory 207516 kb
Host smart-30753d4b-acf3-43ef-8ee5-5c5bdb63a606
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073492316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.3073492316
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3335163716
Short name T1102
Test name
Test status
Simulation time 23541817 ps
CPU time 1.3 seconds
Started Jul 09 05:35:56 PM PDT 24
Finished Jul 09 05:35:58 PM PDT 24
Peak memory 216752 kb
Host smart-df3dcc09-0146-4152-a703-0e9a2cfce866
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335163716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.3335163716
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1663952035
Short name T1077
Test name
Test status
Simulation time 54144789 ps
CPU time 3.37 seconds
Started Jul 09 05:35:54 PM PDT 24
Finished Jul 09 05:35:59 PM PDT 24
Peak memory 218572 kb
Host smart-fca49b5a-9122-446c-a3a4-ec0f1492fcd4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663952035 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.1663952035
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1140051063
Short name T127
Test name
Test status
Simulation time 131330618 ps
CPU time 2.12 seconds
Started Jul 09 05:35:55 PM PDT 24
Finished Jul 09 05:35:58 PM PDT 24
Peak memory 215608 kb
Host smart-e375b911-030b-4320-8f8d-83da9acce2ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140051063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.1
140051063
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3431994531
Short name T1088
Test name
Test status
Simulation time 15776866 ps
CPU time 0.77 seconds
Started Jul 09 05:35:55 PM PDT 24
Finished Jul 09 05:35:57 PM PDT 24
Peak memory 204236 kb
Host smart-eadaa498-3442-4d02-824e-e896effe75c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431994531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.3
431994531
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.4098749278
Short name T1126
Test name
Test status
Simulation time 68691983 ps
CPU time 1.35 seconds
Started Jul 09 05:35:55 PM PDT 24
Finished Jul 09 05:35:57 PM PDT 24
Peak memory 215748 kb
Host smart-14b89b4c-69a8-4b79-af7a-597006fff7f3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098749278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.4098749278
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2704516862
Short name T1046
Test name
Test status
Simulation time 18469335 ps
CPU time 0.66 seconds
Started Jul 09 05:35:54 PM PDT 24
Finished Jul 09 05:35:56 PM PDT 24
Peak memory 204084 kb
Host smart-47a29f64-b1c3-450c-917b-ee16091c2acf
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704516862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.2704516862
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1566804986
Short name T1034
Test name
Test status
Simulation time 258178474 ps
CPU time 3.03 seconds
Started Jul 09 05:35:54 PM PDT 24
Finished Jul 09 05:35:57 PM PDT 24
Peak memory 215692 kb
Host smart-41082042-90c2-4157-8aaa-8afd3602984e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566804986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.1566804986
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.3876066775
Short name T255
Test name
Test status
Simulation time 257766478 ps
CPU time 7.81 seconds
Started Jul 09 05:35:54 PM PDT 24
Finished Jul 09 05:36:03 PM PDT 24
Peak memory 222976 kb
Host smart-872319f4-ead3-4e2d-ae1c-36b4f462ab59
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876066775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.3876066775
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.1640155757
Short name T1039
Test name
Test status
Simulation time 64109581 ps
CPU time 0.73 seconds
Started Jul 09 05:36:26 PM PDT 24
Finished Jul 09 05:36:27 PM PDT 24
Peak memory 204348 kb
Host smart-ff4a9d5a-ba8c-4ff8-9760-4683adf85b9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640155757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
1640155757
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.822981464
Short name T1082
Test name
Test status
Simulation time 22469212 ps
CPU time 0.74 seconds
Started Jul 09 05:36:24 PM PDT 24
Finished Jul 09 05:36:26 PM PDT 24
Peak memory 204516 kb
Host smart-959d991e-9475-4c22-ae6b-83ed5c5e949b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822981464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.822981464
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.3134451968
Short name T1021
Test name
Test status
Simulation time 60549022 ps
CPU time 0.71 seconds
Started Jul 09 05:36:22 PM PDT 24
Finished Jul 09 05:36:23 PM PDT 24
Peak memory 204316 kb
Host smart-f459213b-419e-4c69-adc0-1c563a2e8b78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134451968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
3134451968
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.1705497925
Short name T1070
Test name
Test status
Simulation time 15179166 ps
CPU time 0.73 seconds
Started Jul 09 05:36:19 PM PDT 24
Finished Jul 09 05:36:21 PM PDT 24
Peak memory 204332 kb
Host smart-1291b24b-ad57-4e8c-a93d-153a15bd2be1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705497925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
1705497925
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.3482284745
Short name T1049
Test name
Test status
Simulation time 13638033 ps
CPU time 0.72 seconds
Started Jul 09 05:36:20 PM PDT 24
Finished Jul 09 05:36:21 PM PDT 24
Peak memory 204584 kb
Host smart-19d98bc6-01d9-4009-909d-5a0536fab081
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482284745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
3482284745
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3306681367
Short name T1064
Test name
Test status
Simulation time 22990690 ps
CPU time 0.77 seconds
Started Jul 09 05:36:21 PM PDT 24
Finished Jul 09 05:36:22 PM PDT 24
Peak memory 204596 kb
Host smart-852e0f87-76ea-4241-b379-ed18050c9ef6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306681367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
3306681367
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1744394879
Short name T1019
Test name
Test status
Simulation time 14256684 ps
CPU time 0.72 seconds
Started Jul 09 05:36:23 PM PDT 24
Finished Jul 09 05:36:25 PM PDT 24
Peak memory 204304 kb
Host smart-ef22aa76-70a9-409e-9ae1-9ba89b82e974
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744394879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
1744394879
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1611761494
Short name T1057
Test name
Test status
Simulation time 24570371 ps
CPU time 0.79 seconds
Started Jul 09 05:36:21 PM PDT 24
Finished Jul 09 05:36:23 PM PDT 24
Peak memory 204208 kb
Host smart-9056b851-35b8-4f5a-ac5c-ffc1e53fe819
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611761494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
1611761494
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.78557026
Short name T1061
Test name
Test status
Simulation time 44454034 ps
CPU time 0.72 seconds
Started Jul 09 05:36:27 PM PDT 24
Finished Jul 09 05:36:28 PM PDT 24
Peak memory 204268 kb
Host smart-ed0f0783-ff7e-4ce5-9675-d4b20bb5eec1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78557026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.78557026
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.2746245641
Short name T1029
Test name
Test status
Simulation time 14282459 ps
CPU time 0.78 seconds
Started Jul 09 05:36:24 PM PDT 24
Finished Jul 09 05:36:25 PM PDT 24
Peak memory 204612 kb
Host smart-8f77bb5b-87c0-4dea-b653-6db1c6f07c54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746245641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
2746245641
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2313103058
Short name T1032
Test name
Test status
Simulation time 322020956 ps
CPU time 3.93 seconds
Started Jul 09 05:35:59 PM PDT 24
Finished Jul 09 05:36:04 PM PDT 24
Peak memory 218552 kb
Host smart-6782271b-1b19-4270-9237-ead8c3603057
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313103058 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.2313103058
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1207499543
Short name T1051
Test name
Test status
Simulation time 36735506 ps
CPU time 2.22 seconds
Started Jul 09 05:35:58 PM PDT 24
Finished Jul 09 05:36:01 PM PDT 24
Peak memory 215644 kb
Host smart-bbbe6e8a-eb2d-4c1e-b9ae-65ea19339b69
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207499543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.1
207499543
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.1554095859
Short name T1128
Test name
Test status
Simulation time 31973136 ps
CPU time 0.7 seconds
Started Jul 09 05:35:55 PM PDT 24
Finished Jul 09 05:35:57 PM PDT 24
Peak memory 204268 kb
Host smart-db831419-cfd7-408f-bb4c-5dc2a056c63b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554095859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.1
554095859
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2258863560
Short name T144
Test name
Test status
Simulation time 58738563 ps
CPU time 3.95 seconds
Started Jul 09 05:35:59 PM PDT 24
Finished Jul 09 05:36:04 PM PDT 24
Peak memory 215704 kb
Host smart-9cf928ee-e6f1-4e33-8302-1104f088b3b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258863560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.2258863560
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.2830989962
Short name T1117
Test name
Test status
Simulation time 31257268 ps
CPU time 1.89 seconds
Started Jul 09 05:36:03 PM PDT 24
Finished Jul 09 05:36:05 PM PDT 24
Peak memory 215924 kb
Host smart-5d194e04-0bd3-4d07-9ae0-aa3b30dc15ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830989962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.2
830989962
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3298065412
Short name T260
Test name
Test status
Simulation time 194878969 ps
CPU time 13.11 seconds
Started Jul 09 05:35:57 PM PDT 24
Finished Jul 09 05:36:10 PM PDT 24
Peak memory 223144 kb
Host smart-da3a44dc-3561-4a86-8be6-5abe3ac15589
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298065412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.3298065412
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.4197016793
Short name T115
Test name
Test status
Simulation time 109733887 ps
CPU time 2.96 seconds
Started Jul 09 05:36:10 PM PDT 24
Finished Jul 09 05:36:14 PM PDT 24
Peak memory 217024 kb
Host smart-309942cc-c388-4712-b303-03e532eeae90
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197016793 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.4197016793
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.4062061103
Short name T1075
Test name
Test status
Simulation time 135720947 ps
CPU time 1.84 seconds
Started Jul 09 05:35:58 PM PDT 24
Finished Jul 09 05:36:01 PM PDT 24
Peak memory 207440 kb
Host smart-d5e22eb5-e638-4a46-90ee-8f9c80f4b7c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062061103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.4
062061103
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2294361016
Short name T1031
Test name
Test status
Simulation time 20661681 ps
CPU time 0.81 seconds
Started Jul 09 05:36:02 PM PDT 24
Finished Jul 09 05:36:04 PM PDT 24
Peak memory 204612 kb
Host smart-691f8d40-2522-4ed2-9e5d-95a44e019527
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294361016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.2
294361016
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.225566822
Short name T1050
Test name
Test status
Simulation time 145396105 ps
CPU time 3.15 seconds
Started Jul 09 05:36:10 PM PDT 24
Finished Jul 09 05:36:14 PM PDT 24
Peak memory 215792 kb
Host smart-a5150eac-0e6f-43dc-b98d-9efe7595ec8d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225566822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sp
i_device_same_csr_outstanding.225566822
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.3264883525
Short name T111
Test name
Test status
Simulation time 235907382 ps
CPU time 4.02 seconds
Started Jul 09 05:35:59 PM PDT 24
Finished Jul 09 05:36:04 PM PDT 24
Peak memory 216096 kb
Host smart-1481cc79-49be-4100-a16f-e6277beda77b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264883525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.3
264883525
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1213671936
Short name T254
Test name
Test status
Simulation time 2639367844 ps
CPU time 15.03 seconds
Started Jul 09 05:36:10 PM PDT 24
Finished Jul 09 05:36:26 PM PDT 24
Peak memory 216312 kb
Host smart-69ed78cb-7793-407d-8bb8-54772bdc47b1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213671936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.1213671936
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1451094445
Short name T1110
Test name
Test status
Simulation time 159520678 ps
CPU time 2.77 seconds
Started Jul 09 05:36:00 PM PDT 24
Finished Jul 09 05:36:03 PM PDT 24
Peak memory 217440 kb
Host smart-69e51a40-0846-4954-be06-1869ef6c175e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451094445 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.1451094445
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.4205070379
Short name T121
Test name
Test status
Simulation time 640520381 ps
CPU time 2.04 seconds
Started Jul 09 05:35:59 PM PDT 24
Finished Jul 09 05:36:02 PM PDT 24
Peak memory 215584 kb
Host smart-49457275-44d6-4b60-a24f-c0d543be8228
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205070379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.4
205070379
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.4105054468
Short name T1016
Test name
Test status
Simulation time 18345356 ps
CPU time 0.71 seconds
Started Jul 09 05:35:59 PM PDT 24
Finished Jul 09 05:36:00 PM PDT 24
Peak memory 204156 kb
Host smart-9b86934c-8383-42c1-83c2-94de3ee2c10d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105054468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.4
105054468
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.702683306
Short name T141
Test name
Test status
Simulation time 27662469 ps
CPU time 1.72 seconds
Started Jul 09 05:36:00 PM PDT 24
Finished Jul 09 05:36:03 PM PDT 24
Peak memory 207536 kb
Host smart-3c7e0626-5fbb-47aa-abfa-1deae40c326b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702683306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sp
i_device_same_csr_outstanding.702683306
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.2201070045
Short name T156
Test name
Test status
Simulation time 705986034 ps
CPU time 8.38 seconds
Started Jul 09 05:36:02 PM PDT 24
Finished Jul 09 05:36:11 PM PDT 24
Peak memory 216568 kb
Host smart-431c8fd7-0420-43fc-bfc3-0ff54ef959f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201070045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.2201070045
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3650639685
Short name T1069
Test name
Test status
Simulation time 132532047 ps
CPU time 3.98 seconds
Started Jul 09 05:36:10 PM PDT 24
Finished Jul 09 05:36:15 PM PDT 24
Peak memory 217692 kb
Host smart-cfc97b1f-592c-486b-9472-29cb26382097
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650639685 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.3650639685
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1194726314
Short name T1040
Test name
Test status
Simulation time 258036231 ps
CPU time 1.79 seconds
Started Jul 09 05:35:58 PM PDT 24
Finished Jul 09 05:36:01 PM PDT 24
Peak memory 215616 kb
Host smart-e26954bf-34e4-4627-9f59-a7c6cb75cf2e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194726314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.1
194726314
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1366169265
Short name T1097
Test name
Test status
Simulation time 14488133 ps
CPU time 0.7 seconds
Started Jul 09 05:36:03 PM PDT 24
Finished Jul 09 05:36:04 PM PDT 24
Peak memory 204240 kb
Host smart-1ef041d4-71fb-4270-8611-aa1b367d73a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366169265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.1
366169265
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3457880141
Short name T1059
Test name
Test status
Simulation time 49694054 ps
CPU time 1.63 seconds
Started Jul 09 05:36:10 PM PDT 24
Finished Jul 09 05:36:12 PM PDT 24
Peak memory 215792 kb
Host smart-41bbc1aa-49f3-45d8-bbe1-d6f0d4f9cfdc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457880141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.3457880141
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.3593441456
Short name T1113
Test name
Test status
Simulation time 526741709 ps
CPU time 4.27 seconds
Started Jul 09 05:36:00 PM PDT 24
Finished Jul 09 05:36:06 PM PDT 24
Peak memory 216164 kb
Host smart-991dcd65-adf5-4251-b46d-4d0f38bbe1c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593441456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.3
593441456
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3109683203
Short name T67
Test name
Test status
Simulation time 200889910 ps
CPU time 12.65 seconds
Started Jul 09 05:36:10 PM PDT 24
Finished Jul 09 05:36:23 PM PDT 24
Peak memory 215820 kb
Host smart-65463f59-53ee-4cda-948a-0ced5bca7bec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109683203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.3109683203
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1236047250
Short name T1066
Test name
Test status
Simulation time 181012306 ps
CPU time 1.7 seconds
Started Jul 09 05:36:04 PM PDT 24
Finished Jul 09 05:36:06 PM PDT 24
Peak memory 215768 kb
Host smart-0fc06ccd-9c85-42dd-9dc0-c555554a9ed4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236047250 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.1236047250
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2542116406
Short name T1080
Test name
Test status
Simulation time 58240248 ps
CPU time 1.12 seconds
Started Jul 09 05:36:03 PM PDT 24
Finished Jul 09 05:36:05 PM PDT 24
Peak memory 215708 kb
Host smart-f7093051-7b30-43c6-a251-957b54cac011
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542116406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.2
542116406
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3423531708
Short name T1062
Test name
Test status
Simulation time 17209985 ps
CPU time 0.85 seconds
Started Jul 09 05:36:04 PM PDT 24
Finished Jul 09 05:36:06 PM PDT 24
Peak memory 204280 kb
Host smart-bbca6d39-82d7-4114-a03f-bdeb99d34071
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423531708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.3
423531708
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2110855706
Short name T1107
Test name
Test status
Simulation time 974225774 ps
CPU time 4.21 seconds
Started Jul 09 05:36:03 PM PDT 24
Finished Jul 09 05:36:08 PM PDT 24
Peak memory 215636 kb
Host smart-b828ee7b-e28f-43cb-8cb0-67e393e9661e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110855706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.2110855706
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.150013281
Short name T1119
Test name
Test status
Simulation time 773083508 ps
CPU time 4.94 seconds
Started Jul 09 05:36:04 PM PDT 24
Finished Jul 09 05:36:09 PM PDT 24
Peak memory 216044 kb
Host smart-d47cc389-6592-484b-a0d4-9b4b7696d394
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150013281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.150013281
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.498855961
Short name T1086
Test name
Test status
Simulation time 321747756 ps
CPU time 7.41 seconds
Started Jul 09 05:36:10 PM PDT 24
Finished Jul 09 05:36:19 PM PDT 24
Peak memory 215788 kb
Host smart-52d5088d-1e24-4493-b22e-4c67c4b96a38
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498855961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_
tl_intg_err.498855961
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.1231736281
Short name T613
Test name
Test status
Simulation time 159359437 ps
CPU time 0.77 seconds
Started Jul 09 05:38:34 PM PDT 24
Finished Jul 09 05:38:36 PM PDT 24
Peak memory 205880 kb
Host smart-1ec5f81c-4fea-4016-9e15-5550fc3c872a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231736281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.1
231736281
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.1469526811
Short name T701
Test name
Test status
Simulation time 137464905 ps
CPU time 2.36 seconds
Started Jul 09 05:38:30 PM PDT 24
Finished Jul 09 05:38:34 PM PDT 24
Peak memory 232544 kb
Host smart-4bb03eb0-b61a-4ed1-b469-c0709b506bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469526811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.1469526811
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.2417061982
Short name T342
Test name
Test status
Simulation time 24720933 ps
CPU time 0.78 seconds
Started Jul 09 05:38:29 PM PDT 24
Finished Jul 09 05:38:30 PM PDT 24
Peak memory 206940 kb
Host smart-040bfbfc-80bb-4722-b7cf-039e27de5204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417061982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.2417061982
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.2530468151
Short name T638
Test name
Test status
Simulation time 9801436190 ps
CPU time 73.8 seconds
Started Jul 09 05:38:36 PM PDT 24
Finished Jul 09 05:39:51 PM PDT 24
Peak memory 257204 kb
Host smart-3015d02c-3e0b-4982-985b-749d4c9a3cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530468151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.2530468151
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.3017397350
Short name T217
Test name
Test status
Simulation time 124814651272 ps
CPU time 370.14 seconds
Started Jul 09 05:38:33 PM PDT 24
Finished Jul 09 05:44:44 PM PDT 24
Peak memory 264548 kb
Host smart-d9f87d9b-f252-4e6d-822c-4ed1ceb1df90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017397350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.3017397350
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.3688505341
Short name T979
Test name
Test status
Simulation time 1928458353 ps
CPU time 19.56 seconds
Started Jul 09 05:38:30 PM PDT 24
Finished Jul 09 05:38:51 PM PDT 24
Peak memory 217484 kb
Host smart-4e66c76e-5a49-4bbd-a8e8-954e5b885648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688505341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.3688505341
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.2389017723
Short name T79
Test name
Test status
Simulation time 117069020 ps
CPU time 4.5 seconds
Started Jul 09 05:38:36 PM PDT 24
Finished Jul 09 05:38:42 PM PDT 24
Peak memory 237176 kb
Host smart-75988a0a-5d2e-43a5-ae4c-0ec01dbade13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389017723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.2389017723
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.394640836
Short name T222
Test name
Test status
Simulation time 3043410648 ps
CPU time 77.71 seconds
Started Jul 09 05:38:30 PM PDT 24
Finished Jul 09 05:39:49 PM PDT 24
Peak memory 252308 kb
Host smart-340ae82e-8d21-4305-a34c-1302b15481e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394640836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds.
394640836
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_intercept.763336217
Short name T644
Test name
Test status
Simulation time 471787256 ps
CPU time 7.64 seconds
Started Jul 09 05:38:33 PM PDT 24
Finished Jul 09 05:38:41 PM PDT 24
Peak memory 224452 kb
Host smart-9451a62a-88b6-4933-b4ba-3b82d451a16d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763336217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.763336217
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.1978663636
Short name T840
Test name
Test status
Simulation time 7524686173 ps
CPU time 14.48 seconds
Started Jul 09 05:38:32 PM PDT 24
Finished Jul 09 05:38:47 PM PDT 24
Peak memory 224532 kb
Host smart-660aacde-23a2-403c-921b-14962e41cba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978663636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.1978663636
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.3302290130
Short name T594
Test name
Test status
Simulation time 128958404 ps
CPU time 2.2 seconds
Started Jul 09 05:38:30 PM PDT 24
Finished Jul 09 05:38:34 PM PDT 24
Peak memory 232400 kb
Host smart-bc779565-e112-4777-a760-a86a6155fa34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302290130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.3302290130
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.1655247034
Short name T271
Test name
Test status
Simulation time 16179407607 ps
CPU time 11.9 seconds
Started Jul 09 05:38:29 PM PDT 24
Finished Jul 09 05:38:42 PM PDT 24
Peak memory 240516 kb
Host smart-f21cbdcb-df1a-494e-9800-f111c2b7e58a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655247034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.1655247034
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.1018616726
Short name T867
Test name
Test status
Simulation time 1563079357 ps
CPU time 6.41 seconds
Started Jul 09 05:38:30 PM PDT 24
Finished Jul 09 05:38:38 PM PDT 24
Peak memory 223036 kb
Host smart-ee18a778-c107-4444-80bc-0fb69d0c41b0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1018616726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.1018616726
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.176165449
Short name T565
Test name
Test status
Simulation time 11925872901 ps
CPU time 26.11 seconds
Started Jul 09 05:38:33 PM PDT 24
Finished Jul 09 05:39:00 PM PDT 24
Peak memory 216720 kb
Host smart-41b70751-222d-4dc7-a7ea-9dc88a8d4988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176165449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.176165449
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.132320989
Short name T378
Test name
Test status
Simulation time 1911295307 ps
CPU time 5.49 seconds
Started Jul 09 05:38:33 PM PDT 24
Finished Jul 09 05:38:39 PM PDT 24
Peak memory 216168 kb
Host smart-82db4d82-5d3a-4793-a64f-8c41a2c2a04f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132320989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.132320989
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.4190562370
Short name T642
Test name
Test status
Simulation time 1232527656 ps
CPU time 3.31 seconds
Started Jul 09 05:38:30 PM PDT 24
Finished Jul 09 05:38:35 PM PDT 24
Peak memory 216260 kb
Host smart-3a647341-c062-4bea-ae07-aa61148a7f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190562370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.4190562370
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.3624222352
Short name T636
Test name
Test status
Simulation time 131843872 ps
CPU time 0.83 seconds
Started Jul 09 05:38:29 PM PDT 24
Finished Jul 09 05:38:31 PM PDT 24
Peak memory 205940 kb
Host smart-b136ef3b-248e-4e24-a0e5-3a633fbd201f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624222352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.3624222352
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.3306854248
Short name T494
Test name
Test status
Simulation time 484979291 ps
CPU time 3.88 seconds
Started Jul 09 05:38:30 PM PDT 24
Finished Jul 09 05:38:36 PM PDT 24
Peak memory 224520 kb
Host smart-bc6d30df-ea96-498e-bf8a-fd1eab06dbfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306854248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.3306854248
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.394275767
Short name T731
Test name
Test status
Simulation time 11329018 ps
CPU time 0.73 seconds
Started Jul 09 05:38:36 PM PDT 24
Finished Jul 09 05:38:38 PM PDT 24
Peak memory 205792 kb
Host smart-6e304cb9-471a-4aa2-b21f-ae495d9ed5ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394275767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.394275767
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.1567432311
Short name T181
Test name
Test status
Simulation time 74191763 ps
CPU time 2.7 seconds
Started Jul 09 05:38:36 PM PDT 24
Finished Jul 09 05:38:40 PM PDT 24
Peak memory 224228 kb
Host smart-012d3999-3126-4823-8da5-57ddcc7c7e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567432311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.1567432311
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.872134773
Short name T323
Test name
Test status
Simulation time 20270276 ps
CPU time 0.77 seconds
Started Jul 09 05:38:27 PM PDT 24
Finished Jul 09 05:38:29 PM PDT 24
Peak memory 205564 kb
Host smart-d4e8dfbf-b02a-4c21-a08e-87e9497bc308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872134773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.872134773
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.3402376026
Short name T875
Test name
Test status
Simulation time 8966625412 ps
CPU time 40.99 seconds
Started Jul 09 05:38:34 PM PDT 24
Finished Jul 09 05:39:16 PM PDT 24
Peak memory 252672 kb
Host smart-fb192508-37ef-4849-bf76-7613e45481e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402376026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.3402376026
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.833214612
Short name T517
Test name
Test status
Simulation time 6904136582 ps
CPU time 55.59 seconds
Started Jul 09 05:38:38 PM PDT 24
Finished Jul 09 05:39:34 PM PDT 24
Peak memory 248644 kb
Host smart-2e5fd77a-99f9-4d40-b27a-b42830633194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833214612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.833214612
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.1351061501
Short name T847
Test name
Test status
Simulation time 32771413591 ps
CPU time 73.45 seconds
Started Jul 09 05:38:34 PM PDT 24
Finished Jul 09 05:39:49 PM PDT 24
Peak memory 240388 kb
Host smart-02de20e1-9770-42ad-92ba-aee5ea7659fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351061501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.1351061501
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.2760543621
Short name T990
Test name
Test status
Simulation time 3921371428 ps
CPU time 22.58 seconds
Started Jul 09 05:38:32 PM PDT 24
Finished Jul 09 05:38:55 PM PDT 24
Peak memory 249176 kb
Host smart-ed92e645-3387-4009-92ad-d256d4094ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760543621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.2760543621
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.60294418
Short name T27
Test name
Test status
Simulation time 142999024502 ps
CPU time 505.11 seconds
Started Jul 09 05:38:34 PM PDT 24
Finished Jul 09 05:47:01 PM PDT 24
Peak memory 253180 kb
Host smart-f8edb0c2-2249-4719-a433-0b5869289fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60294418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds.60294418
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_intercept.2967077662
Short name T344
Test name
Test status
Simulation time 222220028 ps
CPU time 4.2 seconds
Started Jul 09 05:38:30 PM PDT 24
Finished Jul 09 05:38:35 PM PDT 24
Peak memory 232632 kb
Host smart-fe57e46a-8965-451a-a046-3a51b1edfb45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967077662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.2967077662
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.1219541960
Short name T185
Test name
Test status
Simulation time 7363920417 ps
CPU time 55.99 seconds
Started Jul 09 05:38:34 PM PDT 24
Finished Jul 09 05:39:31 PM PDT 24
Peak memory 233264 kb
Host smart-b91e32b9-f61f-42ce-8592-96758c162dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219541960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.1219541960
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.2942409304
Short name T598
Test name
Test status
Simulation time 4863038641 ps
CPU time 14.45 seconds
Started Jul 09 05:38:34 PM PDT 24
Finished Jul 09 05:38:49 PM PDT 24
Peak memory 232828 kb
Host smart-74fb27be-0810-4c59-9f67-ffb7649264dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942409304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.2942409304
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.1126111818
Short name T785
Test name
Test status
Simulation time 498819305 ps
CPU time 2.95 seconds
Started Jul 09 05:38:33 PM PDT 24
Finished Jul 09 05:38:38 PM PDT 24
Peak memory 232608 kb
Host smart-7b146f0f-ee61-4e31-b9d8-644da1321952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126111818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.1126111818
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.3862408861
Short name T563
Test name
Test status
Simulation time 254735797 ps
CPU time 6.33 seconds
Started Jul 09 05:38:35 PM PDT 24
Finished Jul 09 05:38:43 PM PDT 24
Peak memory 222628 kb
Host smart-77978c07-b925-4346-a6f3-ceee50728b1a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3862408861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.3862408861
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.2683628282
Short name T71
Test name
Test status
Simulation time 312137840 ps
CPU time 1.19 seconds
Started Jul 09 05:38:35 PM PDT 24
Finished Jul 09 05:38:38 PM PDT 24
Peak memory 236608 kb
Host smart-bddc83db-03e7-40f0-b777-fd4f4b7e7325
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683628282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.2683628282
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.4117881163
Short name T904
Test name
Test status
Simulation time 33538002697 ps
CPU time 63.49 seconds
Started Jul 09 05:38:34 PM PDT 24
Finished Jul 09 05:39:39 PM PDT 24
Peak memory 241076 kb
Host smart-6d4e4aff-42f1-488a-a62d-c64f4031b642
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117881163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.4117881163
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.3415072463
Short name T932
Test name
Test status
Simulation time 1155584999 ps
CPU time 17.05 seconds
Started Jul 09 05:38:30 PM PDT 24
Finished Jul 09 05:38:48 PM PDT 24
Peak memory 216548 kb
Host smart-6fbb61c5-c055-4c53-9eb5-c6e048eb4793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415072463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.3415072463
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.793667148
Short name T602
Test name
Test status
Simulation time 1085954331 ps
CPU time 4.53 seconds
Started Jul 09 05:38:30 PM PDT 24
Finished Jul 09 05:38:36 PM PDT 24
Peak memory 216144 kb
Host smart-a99121b7-71c3-42f5-a160-49565d50ea36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793667148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.793667148
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.4031354512
Short name T513
Test name
Test status
Simulation time 58146891 ps
CPU time 0.93 seconds
Started Jul 09 05:38:35 PM PDT 24
Finished Jul 09 05:38:37 PM PDT 24
Peak memory 207908 kb
Host smart-18a895fa-ab20-4f97-9949-29484f2c5720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031354512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.4031354512
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.3162102121
Short name T345
Test name
Test status
Simulation time 274110897 ps
CPU time 0.78 seconds
Started Jul 09 05:38:36 PM PDT 24
Finished Jul 09 05:38:38 PM PDT 24
Peak memory 205956 kb
Host smart-a18c929e-48d3-4adb-ab72-9a1eaa6c739a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162102121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.3162102121
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.3548247759
Short name T792
Test name
Test status
Simulation time 984355404 ps
CPU time 8.18 seconds
Started Jul 09 05:38:31 PM PDT 24
Finished Jul 09 05:38:40 PM PDT 24
Peak memory 232600 kb
Host smart-22569957-4abb-423b-a11c-ddf2472865d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548247759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.3548247759
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.752874455
Short name T835
Test name
Test status
Simulation time 26370195 ps
CPU time 0.77 seconds
Started Jul 09 05:39:07 PM PDT 24
Finished Jul 09 05:39:08 PM PDT 24
Peak memory 205532 kb
Host smart-b90ccab8-8c41-4872-94d8-278462dde712
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752874455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.752874455
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.3231759271
Short name T938
Test name
Test status
Simulation time 258740509 ps
CPU time 4.46 seconds
Started Jul 09 05:39:03 PM PDT 24
Finished Jul 09 05:39:09 PM PDT 24
Peak memory 219664 kb
Host smart-f3ec61de-990c-4132-871f-b88981808c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231759271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.3231759271
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.2390016281
Short name T446
Test name
Test status
Simulation time 59702688 ps
CPU time 0.84 seconds
Started Jul 09 05:39:03 PM PDT 24
Finished Jul 09 05:39:05 PM PDT 24
Peak memory 206624 kb
Host smart-b1a1e04b-1e85-4351-9176-0f632279eb42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390016281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.2390016281
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.3041678982
Short name T238
Test name
Test status
Simulation time 6561330590 ps
CPU time 55.32 seconds
Started Jul 09 05:39:05 PM PDT 24
Finished Jul 09 05:40:01 PM PDT 24
Peak memory 239116 kb
Host smart-2644c6cc-81a2-4c72-85fc-ef715d51fefd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041678982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.3041678982
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.3364732654
Short name T305
Test name
Test status
Simulation time 121806141736 ps
CPU time 120.61 seconds
Started Jul 09 05:39:16 PM PDT 24
Finished Jul 09 05:41:18 PM PDT 24
Peak memory 249172 kb
Host smart-7c08c23d-a040-4970-93ef-3c3330153859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364732654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.3364732654
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.2620862754
Short name T817
Test name
Test status
Simulation time 22057974435 ps
CPU time 196.19 seconds
Started Jul 09 05:39:09 PM PDT 24
Finished Jul 09 05:42:26 PM PDT 24
Peak memory 253480 kb
Host smart-21911763-4df9-4021-b474-e9db3154f62c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620862754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.2620862754
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.3326937229
Short name T294
Test name
Test status
Simulation time 8528511201 ps
CPU time 55.22 seconds
Started Jul 09 05:39:03 PM PDT 24
Finished Jul 09 05:39:59 PM PDT 24
Peak memory 249692 kb
Host smart-5c1514cd-2805-446d-94eb-5708a0d44a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326937229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.3326937229
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.1230062275
Short name T611
Test name
Test status
Simulation time 23828264 ps
CPU time 0.82 seconds
Started Jul 09 05:39:02 PM PDT 24
Finished Jul 09 05:39:03 PM PDT 24
Peak memory 215804 kb
Host smart-9b628090-ba2e-4395-a4a6-d72000d4a192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230062275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmd
s.1230062275
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.2212131981
Short name T881
Test name
Test status
Simulation time 6754552965 ps
CPU time 17.21 seconds
Started Jul 09 05:39:02 PM PDT 24
Finished Jul 09 05:39:20 PM PDT 24
Peak memory 224468 kb
Host smart-199bcc2f-4b7a-4980-8c15-cb9e6c572c75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212131981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.2212131981
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.2841277955
Short name T133
Test name
Test status
Simulation time 6530509087 ps
CPU time 78.43 seconds
Started Jul 09 05:39:04 PM PDT 24
Finished Jul 09 05:40:23 PM PDT 24
Peak memory 232768 kb
Host smart-c49e3685-6465-43bc-a98c-6a631cc16036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841277955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.2841277955
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.231977968
Short name T100
Test name
Test status
Simulation time 304480700 ps
CPU time 2.21 seconds
Started Jul 09 05:39:03 PM PDT 24
Finished Jul 09 05:39:06 PM PDT 24
Peak memory 224368 kb
Host smart-dca563e5-ae90-403c-b1d4-b8259ef8be8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231977968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swap
.231977968
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.1310464004
Short name T191
Test name
Test status
Simulation time 9429724166 ps
CPU time 9.2 seconds
Started Jul 09 05:39:03 PM PDT 24
Finished Jul 09 05:39:12 PM PDT 24
Peak memory 232748 kb
Host smart-ce7f2ba6-18ed-4b01-88ab-4ef62929cb07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310464004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.1310464004
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.4218952065
Short name T713
Test name
Test status
Simulation time 538323273 ps
CPU time 4.18 seconds
Started Jul 09 05:39:09 PM PDT 24
Finished Jul 09 05:39:14 PM PDT 24
Peak memory 222524 kb
Host smart-f834df67-3111-46ae-a6ca-28c792848334
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4218952065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.4218952065
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.3925381388
Short name T804
Test name
Test status
Simulation time 62905582 ps
CPU time 0.97 seconds
Started Jul 09 05:39:08 PM PDT 24
Finished Jul 09 05:39:09 PM PDT 24
Peak memory 206828 kb
Host smart-0d45fde9-5c6c-4dce-a513-1c4653e89689
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925381388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.3925381388
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.1096818128
Short name T314
Test name
Test status
Simulation time 24944726682 ps
CPU time 8.75 seconds
Started Jul 09 05:39:02 PM PDT 24
Finished Jul 09 05:39:11 PM PDT 24
Peak memory 216804 kb
Host smart-cd337405-c51a-4693-91e2-969cd523ed83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096818128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.1096818128
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.1041050854
Short name T873
Test name
Test status
Simulation time 10981286493 ps
CPU time 7.95 seconds
Started Jul 09 05:39:05 PM PDT 24
Finished Jul 09 05:39:14 PM PDT 24
Peak memory 217388 kb
Host smart-18dca3db-122f-4c25-9add-a541123e2680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041050854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.1041050854
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.3828637487
Short name T729
Test name
Test status
Simulation time 189803133 ps
CPU time 1.46 seconds
Started Jul 09 05:39:04 PM PDT 24
Finished Jul 09 05:39:06 PM PDT 24
Peak memory 216252 kb
Host smart-b6be5806-62f1-4c74-b882-eb962f91c724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828637487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.3828637487
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.1544747475
Short name T376
Test name
Test status
Simulation time 78348800 ps
CPU time 0.91 seconds
Started Jul 09 05:39:07 PM PDT 24
Finished Jul 09 05:39:08 PM PDT 24
Peak memory 206460 kb
Host smart-0db657d6-2937-433c-9c6e-8132f0b30573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544747475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.1544747475
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.610962227
Short name T15
Test name
Test status
Simulation time 13326422397 ps
CPU time 22.91 seconds
Started Jul 09 05:39:04 PM PDT 24
Finished Jul 09 05:39:27 PM PDT 24
Peak memory 232776 kb
Host smart-4d5299da-cd31-41ce-ada4-138e539a4732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610962227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.610962227
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.560041382
Short name T356
Test name
Test status
Simulation time 17414087 ps
CPU time 0.73 seconds
Started Jul 09 05:39:17 PM PDT 24
Finished Jul 09 05:39:19 PM PDT 24
Peak memory 205464 kb
Host smart-f2801200-9b55-4716-816b-8494a6b688ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560041382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.560041382
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.1773271315
Short name T497
Test name
Test status
Simulation time 515293287 ps
CPU time 8.44 seconds
Started Jul 09 05:39:08 PM PDT 24
Finished Jul 09 05:39:17 PM PDT 24
Peak memory 224508 kb
Host smart-f5cbdbcb-5d6b-4bd4-84a2-3a9772953f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773271315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.1773271315
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.2283032141
Short name T370
Test name
Test status
Simulation time 54281522 ps
CPU time 0.83 seconds
Started Jul 09 05:39:07 PM PDT 24
Finished Jul 09 05:39:09 PM PDT 24
Peak memory 205592 kb
Host smart-9817ba03-33bf-4e1d-83df-e126b95299f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283032141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.2283032141
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.2432042198
Short name T243
Test name
Test status
Simulation time 45776988360 ps
CPU time 209.92 seconds
Started Jul 09 05:39:11 PM PDT 24
Finished Jul 09 05:42:42 PM PDT 24
Peak memory 272752 kb
Host smart-3e587e45-a99c-445e-b3b5-2b074f76a129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432042198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.2432042198
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.2866601648
Short name T724
Test name
Test status
Simulation time 2235760748 ps
CPU time 56.13 seconds
Started Jul 09 05:39:13 PM PDT 24
Finished Jul 09 05:40:09 PM PDT 24
Peak memory 249184 kb
Host smart-52f1d9d5-636e-4fb9-a330-9a36dc9cc1f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866601648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.2866601648
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.3602062902
Short name T148
Test name
Test status
Simulation time 384711336 ps
CPU time 4.51 seconds
Started Jul 09 05:39:11 PM PDT 24
Finished Jul 09 05:39:17 PM PDT 24
Peak memory 232596 kb
Host smart-380cbc10-8619-47f6-b327-eb2195b15a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602062902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.3602062902
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.2834804470
Short name T886
Test name
Test status
Simulation time 18619960647 ps
CPU time 75.29 seconds
Started Jul 09 05:39:08 PM PDT 24
Finished Jul 09 05:40:24 PM PDT 24
Peak memory 240964 kb
Host smart-621a2ded-a295-4d77-a9d7-d20708435d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834804470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd
s.2834804470
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.1106873789
Short name T911
Test name
Test status
Simulation time 1315381401 ps
CPU time 14.29 seconds
Started Jul 09 05:39:06 PM PDT 24
Finished Jul 09 05:39:21 PM PDT 24
Peak memory 232604 kb
Host smart-e1d2a96c-301a-4b89-847a-bae2fa2ff7ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106873789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.1106873789
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.883273797
Short name T857
Test name
Test status
Simulation time 6189883563 ps
CPU time 19.67 seconds
Started Jul 09 05:39:11 PM PDT 24
Finished Jul 09 05:39:32 PM PDT 24
Peak memory 224572 kb
Host smart-83a4c674-683e-4da6-b7f9-8be5dd0fb235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883273797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.883273797
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.949159347
Short name T763
Test name
Test status
Simulation time 435407770 ps
CPU time 4.82 seconds
Started Jul 09 05:39:07 PM PDT 24
Finished Jul 09 05:39:12 PM PDT 24
Peak memory 224392 kb
Host smart-9e1207e9-fc97-46e3-a40c-f46a1259efc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949159347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swap
.949159347
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.1237682738
Short name T411
Test name
Test status
Simulation time 67603251 ps
CPU time 2.41 seconds
Started Jul 09 05:39:10 PM PDT 24
Finished Jul 09 05:39:13 PM PDT 24
Peak memory 232644 kb
Host smart-c7e20a9f-667f-4011-871d-0dae835eef70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237682738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.1237682738
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.2536389046
Short name T930
Test name
Test status
Simulation time 378004996 ps
CPU time 7.01 seconds
Started Jul 09 05:39:10 PM PDT 24
Finished Jul 09 05:39:17 PM PDT 24
Peak memory 222104 kb
Host smart-24cb1896-c5de-4ec5-8f9e-021b82300165
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2536389046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.2536389046
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.2755804273
Short name T759
Test name
Test status
Simulation time 14550476140 ps
CPU time 40.44 seconds
Started Jul 09 05:39:05 PM PDT 24
Finished Jul 09 05:39:45 PM PDT 24
Peak memory 216348 kb
Host smart-75f3a533-9bb7-4994-921e-0b7900be30e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755804273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.2755804273
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.506413311
Short name T794
Test name
Test status
Simulation time 8142445231 ps
CPU time 21.91 seconds
Started Jul 09 05:39:06 PM PDT 24
Finished Jul 09 05:39:29 PM PDT 24
Peak memory 216284 kb
Host smart-f8cb8e49-957f-4b2f-a73d-52ab2198ace5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506413311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.506413311
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.3750453875
Short name T475
Test name
Test status
Simulation time 58221113 ps
CPU time 0.95 seconds
Started Jul 09 05:39:05 PM PDT 24
Finished Jul 09 05:39:06 PM PDT 24
Peak memory 207164 kb
Host smart-d0aef033-f55c-44ee-b0a7-59ea7ef643ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750453875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.3750453875
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.1428751899
Short name T363
Test name
Test status
Simulation time 15632379 ps
CPU time 0.72 seconds
Started Jul 09 05:39:07 PM PDT 24
Finished Jul 09 05:39:09 PM PDT 24
Peak memory 205960 kb
Host smart-9100d1cb-ca78-44a0-a4cc-e09f811bb773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428751899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.1428751899
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.251549454
Short name T727
Test name
Test status
Simulation time 14646777 ps
CPU time 0.82 seconds
Started Jul 09 05:39:09 PM PDT 24
Finished Jul 09 05:39:11 PM PDT 24
Peak memory 204928 kb
Host smart-f22c14b2-1868-4d9f-9790-fc548e1222f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251549454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.251549454
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.755074222
Short name T48
Test name
Test status
Simulation time 1149575790 ps
CPU time 6.96 seconds
Started Jul 09 05:39:14 PM PDT 24
Finished Jul 09 05:39:22 PM PDT 24
Peak memory 232636 kb
Host smart-e25d06dc-95a2-48ba-8974-e0b925d6bdd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755074222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.755074222
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.3624096500
Short name T815
Test name
Test status
Simulation time 52584859 ps
CPU time 0.76 seconds
Started Jul 09 05:39:10 PM PDT 24
Finished Jul 09 05:39:11 PM PDT 24
Peak memory 206956 kb
Host smart-652f4e81-7209-4dd5-913b-9f6e1d6c85e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624096500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.3624096500
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.1859633243
Short name T467
Test name
Test status
Simulation time 35244520475 ps
CPU time 76.82 seconds
Started Jul 09 05:39:10 PM PDT 24
Finished Jul 09 05:40:28 PM PDT 24
Peak memory 241024 kb
Host smart-377f8a4b-8bad-4c37-8f9d-1530c8c1522e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859633243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.1859633243
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.3757775932
Short name T667
Test name
Test status
Simulation time 30271055842 ps
CPU time 49.97 seconds
Started Jul 09 05:39:11 PM PDT 24
Finished Jul 09 05:40:02 PM PDT 24
Peak memory 232892 kb
Host smart-b9726d23-2d58-4c37-ba43-64b17412944a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757775932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.3757775932
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.2335679898
Short name T630
Test name
Test status
Simulation time 147307997 ps
CPU time 2.54 seconds
Started Jul 09 05:39:16 PM PDT 24
Finished Jul 09 05:39:20 PM PDT 24
Peak memory 224400 kb
Host smart-2b96900b-6f90-48be-a7e5-ddf0a6c83933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335679898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.2335679898
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.1393192574
Short name T866
Test name
Test status
Simulation time 796349814 ps
CPU time 12.54 seconds
Started Jul 09 05:39:11 PM PDT 24
Finished Jul 09 05:39:25 PM PDT 24
Peak memory 249028 kb
Host smart-d6678dd4-fd23-4728-81d3-2952471ba101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393192574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmd
s.1393192574
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_intercept.2575050371
Short name T921
Test name
Test status
Simulation time 272403404 ps
CPU time 3.14 seconds
Started Jul 09 05:39:12 PM PDT 24
Finished Jul 09 05:39:16 PM PDT 24
Peak memory 224484 kb
Host smart-3913ace4-d921-43d2-842b-84bb969be35a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575050371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.2575050371
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.11923506
Short name T539
Test name
Test status
Simulation time 5349501317 ps
CPU time 17.28 seconds
Started Jul 09 05:39:08 PM PDT 24
Finished Jul 09 05:39:26 PM PDT 24
Peak memory 240720 kb
Host smart-81518ee8-e7b5-440b-83c5-7194e9eadf23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11923506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.11923506
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.2156909577
Short name T244
Test name
Test status
Simulation time 2022427836 ps
CPU time 8.26 seconds
Started Jul 09 05:39:11 PM PDT 24
Finished Jul 09 05:39:20 PM PDT 24
Peak memory 232688 kb
Host smart-0758886a-b5eb-44d7-836a-8101c3526360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156909577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.2156909577
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.4138868469
Short name T595
Test name
Test status
Simulation time 32842189 ps
CPU time 2.63 seconds
Started Jul 09 05:39:16 PM PDT 24
Finished Jul 09 05:39:20 PM PDT 24
Peak memory 232252 kb
Host smart-d0c32a29-1af4-4768-b426-4c5b4954370d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138868469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.4138868469
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.3297049371
Short name T798
Test name
Test status
Simulation time 6233711737 ps
CPU time 9.62 seconds
Started Jul 09 05:39:17 PM PDT 24
Finished Jul 09 05:39:28 PM PDT 24
Peak memory 223156 kb
Host smart-f4b08251-e895-4e29-8562-7a19ef4e14dc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3297049371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.3297049371
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.2910853623
Short name T163
Test name
Test status
Simulation time 4868638041 ps
CPU time 79.22 seconds
Started Jul 09 05:39:09 PM PDT 24
Finished Jul 09 05:40:29 PM PDT 24
Peak memory 265640 kb
Host smart-26f91019-6bd9-48da-8f8d-0a3b4df4d336
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910853623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.2910853623
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.1923301380
Short name T313
Test name
Test status
Simulation time 7495900400 ps
CPU time 12.95 seconds
Started Jul 09 05:39:17 PM PDT 24
Finished Jul 09 05:39:32 PM PDT 24
Peak memory 216336 kb
Host smart-ef28e09e-ca46-461f-a459-b550450c43ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923301380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.1923301380
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.353137753
Short name T604
Test name
Test status
Simulation time 1247710236 ps
CPU time 4.82 seconds
Started Jul 09 05:39:10 PM PDT 24
Finished Jul 09 05:39:16 PM PDT 24
Peak memory 216224 kb
Host smart-09ea5c29-8d44-446a-858f-29e7056ea32c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353137753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.353137753
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.1119919093
Short name T1009
Test name
Test status
Simulation time 71863301 ps
CPU time 0.82 seconds
Started Jul 09 05:39:17 PM PDT 24
Finished Jul 09 05:39:19 PM PDT 24
Peak memory 206864 kb
Host smart-710081e8-8774-42e3-a1c4-458f3875fd46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119919093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.1119919093
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.3222425582
Short name T779
Test name
Test status
Simulation time 21794579 ps
CPU time 0.75 seconds
Started Jul 09 05:39:10 PM PDT 24
Finished Jul 09 05:39:12 PM PDT 24
Peak memory 205976 kb
Host smart-f3a56349-466f-487f-b339-8920a077d0bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222425582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.3222425582
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.2646009687
Short name T928
Test name
Test status
Simulation time 2342490713 ps
CPU time 7.55 seconds
Started Jul 09 05:39:11 PM PDT 24
Finished Jul 09 05:39:19 PM PDT 24
Peak memory 232776 kb
Host smart-29f98d7a-5b38-4ef1-9cb1-321a38eb3924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646009687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.2646009687
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.1083118180
Short name T860
Test name
Test status
Simulation time 13913922 ps
CPU time 0.73 seconds
Started Jul 09 05:39:15 PM PDT 24
Finished Jul 09 05:39:17 PM PDT 24
Peak memory 205544 kb
Host smart-fafe81b0-b9df-4e5c-a73b-89ea34e4a6c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083118180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
1083118180
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.511075787
Short name T609
Test name
Test status
Simulation time 4828258924 ps
CPU time 4.37 seconds
Started Jul 09 05:39:14 PM PDT 24
Finished Jul 09 05:39:19 PM PDT 24
Peak memory 224568 kb
Host smart-cadd9360-55a4-48e5-beed-f8b9fca46c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511075787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.511075787
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.286966179
Short name T557
Test name
Test status
Simulation time 17687126 ps
CPU time 0.79 seconds
Started Jul 09 05:39:16 PM PDT 24
Finished Jul 09 05:39:18 PM PDT 24
Peak memory 206520 kb
Host smart-ccc68661-8648-49fe-aead-43d5e55ee8a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286966179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.286966179
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.460585529
Short name T220
Test name
Test status
Simulation time 8403606744 ps
CPU time 32.17 seconds
Started Jul 09 05:39:15 PM PDT 24
Finished Jul 09 05:39:48 PM PDT 24
Peak memory 241256 kb
Host smart-61ccc5c5-12c6-4d4e-ac32-492b50658110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460585529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.460585529
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.1809710945
Short name T755
Test name
Test status
Simulation time 28202955371 ps
CPU time 235.82 seconds
Started Jul 09 05:39:19 PM PDT 24
Finished Jul 09 05:43:16 PM PDT 24
Peak memory 265652 kb
Host smart-87bed8a6-1682-44be-9a3c-6e36ddd96624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809710945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.1809710945
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.1126008747
Short name T173
Test name
Test status
Simulation time 108065978402 ps
CPU time 263.01 seconds
Started Jul 09 05:39:18 PM PDT 24
Finished Jul 09 05:43:43 PM PDT 24
Peak memory 257416 kb
Host smart-8759546d-200e-49de-a4a9-7cdffcb51699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126008747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.1126008747
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.293880408
Short name T947
Test name
Test status
Simulation time 79875947 ps
CPU time 2.67 seconds
Started Jul 09 05:39:16 PM PDT 24
Finished Jul 09 05:39:20 PM PDT 24
Peak memory 232692 kb
Host smart-8a0e4cc6-8090-4fd7-9c01-8543cdc9faa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293880408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.293880408
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.4228882287
Short name T816
Test name
Test status
Simulation time 2574117285 ps
CPU time 27.11 seconds
Started Jul 09 05:39:15 PM PDT 24
Finished Jul 09 05:39:44 PM PDT 24
Peak memory 236316 kb
Host smart-dd798c40-1a05-4339-af37-34b4611b8242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228882287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd
s.4228882287
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_intercept.984057606
Short name T473
Test name
Test status
Simulation time 437469709 ps
CPU time 4.6 seconds
Started Jul 09 05:39:15 PM PDT 24
Finished Jul 09 05:39:20 PM PDT 24
Peak memory 224448 kb
Host smart-1f5f6e80-e506-4c18-acdc-4eab4653091c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984057606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.984057606
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.3178068220
Short name T486
Test name
Test status
Simulation time 2355072722 ps
CPU time 11.04 seconds
Started Jul 09 05:39:15 PM PDT 24
Finished Jul 09 05:39:27 PM PDT 24
Peak memory 232772 kb
Host smart-4a99ec0a-feb4-494f-b6a5-5b69f7e18d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178068220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.3178068220
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.26078891
Short name T14
Test name
Test status
Simulation time 741262342 ps
CPU time 4.24 seconds
Started Jul 09 05:39:16 PM PDT 24
Finished Jul 09 05:39:22 PM PDT 24
Peak memory 232704 kb
Host smart-46ad18f3-ded7-4b29-bd6c-17210a47772f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26078891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.26078891
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.1929581830
Short name T154
Test name
Test status
Simulation time 298122762 ps
CPU time 5.79 seconds
Started Jul 09 05:39:12 PM PDT 24
Finished Jul 09 05:39:18 PM PDT 24
Peak memory 218824 kb
Host smart-9edb1efd-9b70-49ee-a0a3-f638deb90eda
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1929581830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.1929581830
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.1537017774
Short name T17
Test name
Test status
Simulation time 84798072 ps
CPU time 1.06 seconds
Started Jul 09 05:39:13 PM PDT 24
Finished Jul 09 05:39:15 PM PDT 24
Peak memory 207672 kb
Host smart-20542b44-3347-4804-a50f-b2685415c238
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537017774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.1537017774
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.3592924044
Short name T524
Test name
Test status
Simulation time 7659964165 ps
CPU time 25.99 seconds
Started Jul 09 05:39:14 PM PDT 24
Finished Jul 09 05:39:41 PM PDT 24
Peak memory 216380 kb
Host smart-70e66f59-6f40-4d01-b5c1-119ff4352b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592924044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.3592924044
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.97810875
Short name T715
Test name
Test status
Simulation time 411162816 ps
CPU time 1.95 seconds
Started Jul 09 05:39:10 PM PDT 24
Finished Jul 09 05:39:13 PM PDT 24
Peak memory 207904 kb
Host smart-18ee8189-e47c-41bf-9940-c1bc028ccedb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97810875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.97810875
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.3362440644
Short name T624
Test name
Test status
Simulation time 53797410 ps
CPU time 1.01 seconds
Started Jul 09 05:39:15 PM PDT 24
Finished Jul 09 05:39:17 PM PDT 24
Peak memory 207432 kb
Host smart-43ecf9d2-0dc2-4370-a1cb-443bde162f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362440644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.3362440644
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.4045850721
Short name T503
Test name
Test status
Simulation time 331233397 ps
CPU time 0.95 seconds
Started Jul 09 05:39:14 PM PDT 24
Finished Jul 09 05:39:16 PM PDT 24
Peak memory 205976 kb
Host smart-b286dfc0-f883-4a0b-a0c2-d662206c2960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045850721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.4045850721
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.757346368
Short name T102
Test name
Test status
Simulation time 28744014642 ps
CPU time 13.29 seconds
Started Jul 09 05:39:16 PM PDT 24
Finished Jul 09 05:39:31 PM PDT 24
Peak memory 224648 kb
Host smart-f8bae1c9-3117-4703-8a37-c293584cee4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757346368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.757346368
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.371348030
Short name T799
Test name
Test status
Simulation time 75467017 ps
CPU time 0.73 seconds
Started Jul 09 05:39:18 PM PDT 24
Finished Jul 09 05:39:21 PM PDT 24
Peak memory 205556 kb
Host smart-84c24bf6-61f5-4f1f-a351-3a3a3e883812
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371348030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.371348030
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.3383320361
Short name T770
Test name
Test status
Simulation time 575139220 ps
CPU time 4.94 seconds
Started Jul 09 05:39:18 PM PDT 24
Finished Jul 09 05:39:25 PM PDT 24
Peak memory 232676 kb
Host smart-bafc0773-5aea-4a52-a734-07e439a87b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383320361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.3383320361
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.225551669
Short name T324
Test name
Test status
Simulation time 20864609 ps
CPU time 0.8 seconds
Started Jul 09 05:39:16 PM PDT 24
Finished Jul 09 05:39:19 PM PDT 24
Peak memory 206600 kb
Host smart-9098f9b2-c8a0-4c8e-adc6-d6a3522f7eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225551669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.225551669
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.364518446
Short name T251
Test name
Test status
Simulation time 12638473055 ps
CPU time 67.15 seconds
Started Jul 09 05:39:18 PM PDT 24
Finished Jul 09 05:40:27 PM PDT 24
Peak memory 250888 kb
Host smart-8024b92b-fc97-49a4-a91a-44671c900275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364518446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.364518446
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.998062573
Short name T684
Test name
Test status
Simulation time 7028806404 ps
CPU time 71.46 seconds
Started Jul 09 05:39:18 PM PDT 24
Finished Jul 09 05:40:32 PM PDT 24
Peak memory 239040 kb
Host smart-92d8bd4d-73d0-4290-a2ca-fc55004726c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998062573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.998062573
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.1093648283
Short name T635
Test name
Test status
Simulation time 789488750 ps
CPU time 18.36 seconds
Started Jul 09 05:39:16 PM PDT 24
Finished Jul 09 05:39:35 PM PDT 24
Peak memory 232732 kb
Host smart-31912e58-4f2b-4b24-b62e-e89fd8d9a8b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093648283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.1093648283
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.3541785702
Short name T374
Test name
Test status
Simulation time 15227097029 ps
CPU time 122.23 seconds
Started Jul 09 05:39:18 PM PDT 24
Finished Jul 09 05:41:22 PM PDT 24
Peak memory 251392 kb
Host smart-9281b910-9eea-4c2f-9239-eebe07064625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541785702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmd
s.3541785702
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_intercept.984416488
Short name T61
Test name
Test status
Simulation time 5733412246 ps
CPU time 21 seconds
Started Jul 09 05:39:15 PM PDT 24
Finished Jul 09 05:39:37 PM PDT 24
Peak memory 224620 kb
Host smart-5f37ac11-f5ae-411d-b787-896c2b273ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984416488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.984416488
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.3190379483
Short name T502
Test name
Test status
Simulation time 9409480641 ps
CPU time 51.55 seconds
Started Jul 09 05:39:15 PM PDT 24
Finished Jul 09 05:40:07 PM PDT 24
Peak memory 237924 kb
Host smart-66517d3c-e564-4f67-abd6-e86c52dd774c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190379483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.3190379483
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.61789687
Short name T828
Test name
Test status
Simulation time 117103200 ps
CPU time 2.56 seconds
Started Jul 09 05:39:16 PM PDT 24
Finished Jul 09 05:39:20 PM PDT 24
Peak memory 232236 kb
Host smart-e0e57dd6-d867-446f-9d51-21b79a63765a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61789687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swap.61789687
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.1280639588
Short name T385
Test name
Test status
Simulation time 2085536168 ps
CPU time 9.15 seconds
Started Jul 09 05:39:15 PM PDT 24
Finished Jul 09 05:39:25 PM PDT 24
Peak memory 232656 kb
Host smart-558af110-e1e4-4a0d-b9a9-3bae53e5a474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280639588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.1280639588
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.726203607
Short name T448
Test name
Test status
Simulation time 521480494 ps
CPU time 4.13 seconds
Started Jul 09 05:39:17 PM PDT 24
Finished Jul 09 05:39:22 PM PDT 24
Peak memory 220408 kb
Host smart-d6e735a7-3a5b-456b-8600-3d459066aa22
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=726203607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dire
ct.726203607
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.303556559
Short name T521
Test name
Test status
Simulation time 396374437 ps
CPU time 7.34 seconds
Started Jul 09 05:39:19 PM PDT 24
Finished Jul 09 05:39:28 PM PDT 24
Peak memory 216552 kb
Host smart-973121ef-c032-445a-82c9-1c49ede8f363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303556559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.303556559
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.2136653733
Short name T457
Test name
Test status
Simulation time 8700121832 ps
CPU time 7.57 seconds
Started Jul 09 05:39:17 PM PDT 24
Finished Jul 09 05:39:26 PM PDT 24
Peak memory 216328 kb
Host smart-ce338339-3e60-4feb-ac77-f81852b4a93f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136653733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.2136653733
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.2260568156
Short name T350
Test name
Test status
Simulation time 19949446 ps
CPU time 0.74 seconds
Started Jul 09 05:39:16 PM PDT 24
Finished Jul 09 05:39:18 PM PDT 24
Peak memory 205572 kb
Host smart-c92883ac-1b30-4a09-90df-b8a9edad0570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260568156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.2260568156
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.1839157535
Short name T358
Test name
Test status
Simulation time 169037550 ps
CPU time 1.19 seconds
Started Jul 09 05:39:15 PM PDT 24
Finished Jul 09 05:39:17 PM PDT 24
Peak memory 206952 kb
Host smart-d688ccc5-99da-4738-8941-416e4b1f2d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839157535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.1839157535
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.3310859502
Short name T797
Test name
Test status
Simulation time 158206959 ps
CPU time 2.5 seconds
Started Jul 09 05:39:13 PM PDT 24
Finished Jul 09 05:39:16 PM PDT 24
Peak memory 232576 kb
Host smart-025bce3e-54d7-46be-888a-ac551dff1e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310859502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.3310859502
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.178507430
Short name T675
Test name
Test status
Simulation time 42704602 ps
CPU time 0.74 seconds
Started Jul 09 05:39:21 PM PDT 24
Finished Jul 09 05:39:22 PM PDT 24
Peak memory 205520 kb
Host smart-725c56bf-4087-4308-a5eb-a6f5f651de1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178507430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.178507430
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.625254315
Short name T209
Test name
Test status
Simulation time 527141434 ps
CPU time 7.94 seconds
Started Jul 09 05:39:22 PM PDT 24
Finished Jul 09 05:39:31 PM PDT 24
Peak memory 224448 kb
Host smart-a3683f6e-02c9-41d6-bfe4-d8be11de6181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625254315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.625254315
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.3576177966
Short name T733
Test name
Test status
Simulation time 43496155 ps
CPU time 0.82 seconds
Started Jul 09 05:39:17 PM PDT 24
Finished Jul 09 05:39:19 PM PDT 24
Peak memory 206580 kb
Host smart-07132ef8-41c3-4f0c-9530-132c7d992d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576177966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.3576177966
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.3077356056
Short name T232
Test name
Test status
Simulation time 6483129521 ps
CPU time 59.79 seconds
Started Jul 09 05:39:20 PM PDT 24
Finished Jul 09 05:40:21 PM PDT 24
Peak memory 241056 kb
Host smart-f5fa4c1e-e0ce-4f02-a742-a7ef0deb121a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077356056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.3077356056
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.3946437053
Short name T425
Test name
Test status
Simulation time 149889571542 ps
CPU time 234.48 seconds
Started Jul 09 05:39:26 PM PDT 24
Finished Jul 09 05:43:22 PM PDT 24
Peak memory 254632 kb
Host smart-2336c20d-b4f1-4640-b27d-452f57bbb929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946437053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.3946437053
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.476791594
Short name T795
Test name
Test status
Simulation time 33678141858 ps
CPU time 118.01 seconds
Started Jul 09 05:39:23 PM PDT 24
Finished Jul 09 05:41:22 PM PDT 24
Peak memory 257340 kb
Host smart-fa4eaf01-0094-4539-af25-485c3c796860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476791594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idle
.476791594
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.3946470632
Short name T957
Test name
Test status
Simulation time 844737728 ps
CPU time 4.02 seconds
Started Jul 09 05:39:22 PM PDT 24
Finished Jul 09 05:39:27 PM PDT 24
Peak memory 224404 kb
Host smart-8990684d-319a-489f-b665-c313aadf67b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946470632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.3946470632
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.3635979268
Short name T196
Test name
Test status
Simulation time 71341099594 ps
CPU time 242.77 seconds
Started Jul 09 05:39:21 PM PDT 24
Finished Jul 09 05:43:25 PM PDT 24
Peak memory 265572 kb
Host smart-e42a2787-b32d-4e0c-bccd-b05b1a91180f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635979268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmd
s.3635979268
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.1425574590
Short name T704
Test name
Test status
Simulation time 3822836943 ps
CPU time 42.2 seconds
Started Jul 09 05:39:20 PM PDT 24
Finished Jul 09 05:40:03 PM PDT 24
Peak memory 220140 kb
Host smart-41244a93-3e87-4a32-b29f-f24d92e5aa24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425574590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.1425574590
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.147508437
Short name T516
Test name
Test status
Simulation time 1062000628 ps
CPU time 5.78 seconds
Started Jul 09 05:39:20 PM PDT 24
Finished Jul 09 05:39:27 PM PDT 24
Peak memory 232664 kb
Host smart-ddae13d4-3354-4751-bcc6-04d555e0b9df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147508437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.147508437
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.2759355984
Short name T194
Test name
Test status
Simulation time 6746187702 ps
CPU time 7.71 seconds
Started Jul 09 05:39:16 PM PDT 24
Finished Jul 09 05:39:25 PM PDT 24
Peak memory 224620 kb
Host smart-e98b5a80-da4a-4763-9187-99e56fb3f9f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759355984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.2759355984
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.2573112063
Short name T1001
Test name
Test status
Simulation time 8400889494 ps
CPU time 7.95 seconds
Started Jul 09 05:39:17 PM PDT 24
Finished Jul 09 05:39:27 PM PDT 24
Peak memory 232760 kb
Host smart-9c989b73-73cc-49b3-82e8-918c67fe41a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573112063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.2573112063
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.1243420701
Short name T152
Test name
Test status
Simulation time 387610127 ps
CPU time 6.46 seconds
Started Jul 09 05:39:23 PM PDT 24
Finished Jul 09 05:39:30 PM PDT 24
Peak memory 220624 kb
Host smart-b7097a02-7ef4-4d0d-99b3-a11cd3a43f1d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1243420701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.1243420701
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.1408402227
Short name T310
Test name
Test status
Simulation time 7710883534 ps
CPU time 27.59 seconds
Started Jul 09 05:39:18 PM PDT 24
Finished Jul 09 05:39:47 PM PDT 24
Peak memory 216360 kb
Host smart-e71f0a50-76f8-4969-bc1d-c111ea327eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408402227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.1408402227
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.2084039154
Short name T730
Test name
Test status
Simulation time 1386025777 ps
CPU time 8.08 seconds
Started Jul 09 05:39:16 PM PDT 24
Finished Jul 09 05:39:25 PM PDT 24
Peak memory 216196 kb
Host smart-98b2fb3f-527e-42c2-bac0-c259e9dce2a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084039154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.2084039154
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.2695435211
Short name T950
Test name
Test status
Simulation time 79874057 ps
CPU time 1.25 seconds
Started Jul 09 05:39:19 PM PDT 24
Finished Jul 09 05:39:22 PM PDT 24
Peak memory 215980 kb
Host smart-6cc56147-dbf6-4013-9509-07824569f034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695435211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.2695435211
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.2818887842
Short name T1000
Test name
Test status
Simulation time 28957649 ps
CPU time 0.74 seconds
Started Jul 09 05:39:18 PM PDT 24
Finished Jul 09 05:39:20 PM PDT 24
Peak memory 205664 kb
Host smart-c1006af7-cc9a-4548-a1a3-ec921f9cbfb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818887842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.2818887842
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.1003119109
Short name T50
Test name
Test status
Simulation time 433509410 ps
CPU time 3.72 seconds
Started Jul 09 05:39:18 PM PDT 24
Finished Jul 09 05:39:24 PM PDT 24
Peak memory 232784 kb
Host smart-588adccf-59e5-4195-a51d-e6b273fccf9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003119109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.1003119109
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.1824490437
Short name T538
Test name
Test status
Simulation time 34656082 ps
CPU time 0.73 seconds
Started Jul 09 05:39:25 PM PDT 24
Finished Jul 09 05:39:26 PM PDT 24
Peak memory 204964 kb
Host smart-f6ed8c7d-c583-4cdb-8783-e7f250ea07af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824490437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
1824490437
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.678080563
Short name T495
Test name
Test status
Simulation time 596737067 ps
CPU time 7.52 seconds
Started Jul 09 05:39:19 PM PDT 24
Finished Jul 09 05:39:28 PM PDT 24
Peak memory 232600 kb
Host smart-e94660b7-e851-4453-92bc-e1118b230ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678080563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.678080563
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.2400620124
Short name T519
Test name
Test status
Simulation time 47232617 ps
CPU time 0.81 seconds
Started Jul 09 05:39:21 PM PDT 24
Finished Jul 09 05:39:23 PM PDT 24
Peak memory 206596 kb
Host smart-634c0ab5-5a71-4305-8dc3-b92918e429f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400620124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.2400620124
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.1974318816
Short name T562
Test name
Test status
Simulation time 43431723118 ps
CPU time 175.44 seconds
Started Jul 09 05:39:24 PM PDT 24
Finished Jul 09 05:42:20 PM PDT 24
Peak memory 256136 kb
Host smart-8504348a-987c-4584-bd55-7e86ee999e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974318816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.1974318816
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.3699271834
Short name T725
Test name
Test status
Simulation time 27910486543 ps
CPU time 275.05 seconds
Started Jul 09 05:39:23 PM PDT 24
Finished Jul 09 05:43:59 PM PDT 24
Peak memory 263056 kb
Host smart-2e98472b-235c-496c-a24a-6daa2770c213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699271834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.3699271834
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.3524468090
Short name T768
Test name
Test status
Simulation time 629464872 ps
CPU time 8.2 seconds
Started Jul 09 05:39:20 PM PDT 24
Finished Jul 09 05:39:29 PM PDT 24
Peak memory 234516 kb
Host smart-a590fae9-a20a-4f93-a518-f9bdb4d9e85e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524468090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.3524468090
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.1611505277
Short name T90
Test name
Test status
Simulation time 38816559116 ps
CPU time 60.73 seconds
Started Jul 09 05:39:26 PM PDT 24
Finished Jul 09 05:40:28 PM PDT 24
Peak memory 237792 kb
Host smart-73f5c51a-62ac-4555-be1b-997df9446c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611505277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmd
s.1611505277
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.873090651
Short name T420
Test name
Test status
Simulation time 1535313581 ps
CPU time 14.07 seconds
Started Jul 09 05:39:21 PM PDT 24
Finished Jul 09 05:39:35 PM PDT 24
Peak memory 224476 kb
Host smart-f3ae9378-4fc7-4895-8552-cd6824afc7f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873090651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.873090651
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.2286612938
Short name T726
Test name
Test status
Simulation time 3361988562 ps
CPU time 22.92 seconds
Started Jul 09 05:39:25 PM PDT 24
Finished Jul 09 05:39:48 PM PDT 24
Peak memory 224604 kb
Host smart-5338d92c-3c92-44fd-8e84-a59442703bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286612938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.2286612938
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.2155505628
Short name T749
Test name
Test status
Simulation time 3100057585 ps
CPU time 6.14 seconds
Started Jul 09 05:39:23 PM PDT 24
Finished Jul 09 05:39:29 PM PDT 24
Peak memory 232784 kb
Host smart-1379e031-5933-473a-a70e-9ec32cc7b628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155505628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.2155505628
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.1401503357
Short name T887
Test name
Test status
Simulation time 276307483 ps
CPU time 4.21 seconds
Started Jul 09 05:39:21 PM PDT 24
Finished Jul 09 05:39:26 PM PDT 24
Peak memory 232704 kb
Host smart-d2b2d31d-6e50-4f66-83f3-09b46fd2fc07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401503357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.1401503357
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.2146003461
Short name T397
Test name
Test status
Simulation time 893435168 ps
CPU time 5.66 seconds
Started Jul 09 05:39:19 PM PDT 24
Finished Jul 09 05:39:26 PM PDT 24
Peak memory 220316 kb
Host smart-7b2b7bc3-0730-4379-9ee6-5ca49e045b4b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2146003461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.2146003461
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.1870091194
Short name T765
Test name
Test status
Simulation time 63591173749 ps
CPU time 297.53 seconds
Started Jul 09 05:39:23 PM PDT 24
Finished Jul 09 05:44:21 PM PDT 24
Peak memory 251252 kb
Host smart-b3e85221-e185-43a7-9d29-4b97ee5f76c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870091194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.1870091194
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.2810051562
Short name T308
Test name
Test status
Simulation time 12925397970 ps
CPU time 16.04 seconds
Started Jul 09 05:39:22 PM PDT 24
Finished Jul 09 05:39:39 PM PDT 24
Peak memory 220100 kb
Host smart-b491f748-b2f5-4c44-bb92-2e545016d020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810051562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.2810051562
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.4130654034
Short name T453
Test name
Test status
Simulation time 4137832072 ps
CPU time 9.98 seconds
Started Jul 09 05:39:25 PM PDT 24
Finished Jul 09 05:39:35 PM PDT 24
Peak memory 216296 kb
Host smart-0a49234d-64b0-4d89-8234-18b86032bbba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130654034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.4130654034
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.3033284535
Short name T937
Test name
Test status
Simulation time 1638847154 ps
CPU time 2.94 seconds
Started Jul 09 05:39:22 PM PDT 24
Finished Jul 09 05:39:26 PM PDT 24
Peak memory 216248 kb
Host smart-17441201-c14f-4f29-8217-c5e895c8b6d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033284535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.3033284535
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.4148356049
Short name T640
Test name
Test status
Simulation time 74873279 ps
CPU time 0.77 seconds
Started Jul 09 05:39:22 PM PDT 24
Finished Jul 09 05:39:23 PM PDT 24
Peak memory 205960 kb
Host smart-0dc290f3-23cd-4587-af24-9aea08caed58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148356049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.4148356049
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.1943038660
Short name T543
Test name
Test status
Simulation time 6995588416 ps
CPU time 4.92 seconds
Started Jul 09 05:39:21 PM PDT 24
Finished Jul 09 05:39:27 PM PDT 24
Peak memory 224576 kb
Host smart-d150192f-4e2c-42e0-adae-1387f73964ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943038660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.1943038660
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.1035977038
Short name T4
Test name
Test status
Simulation time 208069103 ps
CPU time 4.82 seconds
Started Jul 09 05:39:26 PM PDT 24
Finished Jul 09 05:39:32 PM PDT 24
Peak memory 232476 kb
Host smart-11bc50f0-b1d6-4547-9cd9-ce21b1cd8d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035977038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.1035977038
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.2510819804
Short name T63
Test name
Test status
Simulation time 40272135 ps
CPU time 0.76 seconds
Started Jul 09 05:39:21 PM PDT 24
Finished Jul 09 05:39:23 PM PDT 24
Peak memory 206888 kb
Host smart-5f0ea535-4582-42c0-8fe8-963d1a8e58b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510819804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.2510819804
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.3046099571
Short name T801
Test name
Test status
Simulation time 36925502238 ps
CPU time 109.97 seconds
Started Jul 09 05:39:29 PM PDT 24
Finished Jul 09 05:41:20 PM PDT 24
Peak memory 254628 kb
Host smart-adab9a5c-26b0-420f-a4a3-9e0e5894f60c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046099571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.3046099571
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.804078317
Short name T77
Test name
Test status
Simulation time 39540867685 ps
CPU time 374.01 seconds
Started Jul 09 05:39:26 PM PDT 24
Finished Jul 09 05:45:41 PM PDT 24
Peak memory 251380 kb
Host smart-e70626ca-9539-491f-992e-5d6485af7096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804078317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.804078317
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.4187402724
Short name T42
Test name
Test status
Simulation time 124546276 ps
CPU time 5.15 seconds
Started Jul 09 05:39:26 PM PDT 24
Finished Jul 09 05:39:32 PM PDT 24
Peak memory 232728 kb
Host smart-5824ee71-5412-46f5-a300-b063388a79b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187402724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.4187402724
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.4058451988
Short name T236
Test name
Test status
Simulation time 8220543270 ps
CPU time 60.38 seconds
Started Jul 09 05:39:30 PM PDT 24
Finished Jul 09 05:40:32 PM PDT 24
Peak memory 241032 kb
Host smart-43ea2787-195b-40a3-a4dd-0c6682c12071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058451988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmd
s.4058451988
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_intercept.1229941130
Short name T631
Test name
Test status
Simulation time 1204283522 ps
CPU time 6.06 seconds
Started Jul 09 05:39:27 PM PDT 24
Finished Jul 09 05:39:34 PM PDT 24
Peak memory 232596 kb
Host smart-2f1b42d6-bdd3-4499-9a42-f0361042c6c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229941130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.1229941130
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.1822545827
Short name T676
Test name
Test status
Simulation time 101588390969 ps
CPU time 94.48 seconds
Started Jul 09 05:39:25 PM PDT 24
Finished Jul 09 05:41:01 PM PDT 24
Peak memory 232764 kb
Host smart-e2f1a411-9714-4a65-8501-75c6926dfb36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822545827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.1822545827
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.1678202668
Short name T288
Test name
Test status
Simulation time 5537697331 ps
CPU time 5.3 seconds
Started Jul 09 05:39:29 PM PDT 24
Finished Jul 09 05:39:36 PM PDT 24
Peak memory 232760 kb
Host smart-df87909b-d613-4135-815f-611fb9612080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678202668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.1678202668
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.898736945
Short name T920
Test name
Test status
Simulation time 60296711 ps
CPU time 2.3 seconds
Started Jul 09 05:39:24 PM PDT 24
Finished Jul 09 05:39:26 PM PDT 24
Peak memory 232324 kb
Host smart-e47a9bd9-03d3-4cfd-a9a2-38b803e55c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898736945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.898736945
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.123475151
Short name T615
Test name
Test status
Simulation time 205372078 ps
CPU time 4.97 seconds
Started Jul 09 05:39:29 PM PDT 24
Finished Jul 09 05:39:35 PM PDT 24
Peak memory 223060 kb
Host smart-c6cba372-0ea2-4702-bc1a-5b5763f07d86
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=123475151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dire
ct.123475151
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.3042762166
Short name T732
Test name
Test status
Simulation time 30203798889 ps
CPU time 210.31 seconds
Started Jul 09 05:39:34 PM PDT 24
Finished Jul 09 05:43:06 PM PDT 24
Peak memory 251828 kb
Host smart-a312a2c5-8144-46f7-a500-05c88e56f49c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042762166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.3042762166
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.3122166116
Short name T929
Test name
Test status
Simulation time 5818237158 ps
CPU time 7.71 seconds
Started Jul 09 05:39:25 PM PDT 24
Finished Jul 09 05:39:33 PM PDT 24
Peak memory 216312 kb
Host smart-2838e2f1-136b-4033-a95c-c22368f5b295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122166116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.3122166116
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.2983316703
Short name T728
Test name
Test status
Simulation time 3503155632 ps
CPU time 13.01 seconds
Started Jul 09 05:39:25 PM PDT 24
Finished Jul 09 05:39:39 PM PDT 24
Peak memory 216324 kb
Host smart-22bd048b-2129-4902-abf6-85d063f67760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983316703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.2983316703
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.2862404315
Short name T412
Test name
Test status
Simulation time 18773749 ps
CPU time 1.03 seconds
Started Jul 09 05:39:24 PM PDT 24
Finished Jul 09 05:39:25 PM PDT 24
Peak memory 207324 kb
Host smart-28fd0f81-e143-4b4c-8641-d774bbad8e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862404315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.2862404315
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.4147130799
Short name T803
Test name
Test status
Simulation time 100378198 ps
CPU time 0.88 seconds
Started Jul 09 05:39:34 PM PDT 24
Finished Jul 09 05:39:37 PM PDT 24
Peak memory 207000 kb
Host smart-8b4dd99b-4899-4558-b05b-ae7ee75abc2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147130799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.4147130799
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.3285047620
Short name T449
Test name
Test status
Simulation time 1098278096 ps
CPU time 9.18 seconds
Started Jul 09 05:39:25 PM PDT 24
Finished Jul 09 05:39:34 PM PDT 24
Peak memory 232644 kb
Host smart-8f385f8d-e5bb-4351-9dde-69f9077db2f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285047620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.3285047620
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.2560589077
Short name T466
Test name
Test status
Simulation time 19592640 ps
CPU time 0.72 seconds
Started Jul 09 05:39:31 PM PDT 24
Finished Jul 09 05:39:33 PM PDT 24
Peak memory 204908 kb
Host smart-edee3c25-0977-454d-8c26-acdb6ff40750
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560589077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
2560589077
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.3166590528
Short name T688
Test name
Test status
Simulation time 30387285 ps
CPU time 2.02 seconds
Started Jul 09 05:39:28 PM PDT 24
Finished Jul 09 05:39:31 PM PDT 24
Peak memory 224080 kb
Host smart-31fffb36-67b6-45c9-a9ca-46eee6991fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166590528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.3166590528
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.1381129575
Short name T317
Test name
Test status
Simulation time 37679793 ps
CPU time 0.76 seconds
Started Jul 09 05:39:34 PM PDT 24
Finished Jul 09 05:39:36 PM PDT 24
Peak memory 206592 kb
Host smart-60c1d503-f1a7-4d9b-8bb5-2d5238a81fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381129575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.1381129575
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.539105442
Short name T656
Test name
Test status
Simulation time 11303968292 ps
CPU time 59.73 seconds
Started Jul 09 05:39:29 PM PDT 24
Finished Jul 09 05:40:30 PM PDT 24
Peak memory 249184 kb
Host smart-3a899428-abaa-48fd-ad02-814f26122f5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539105442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.539105442
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.2717587287
Short name T885
Test name
Test status
Simulation time 22901428859 ps
CPU time 75.37 seconds
Started Jul 09 05:39:33 PM PDT 24
Finished Jul 09 05:40:50 PM PDT 24
Peak memory 254488 kb
Host smart-556bcfd4-cd23-4a2e-8d0a-6b1ae76c4e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717587287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.2717587287
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.1714772773
Short name T812
Test name
Test status
Simulation time 11074119594 ps
CPU time 112.66 seconds
Started Jul 09 05:39:34 PM PDT 24
Finished Jul 09 05:41:28 PM PDT 24
Peak memory 257448 kb
Host smart-bc70202c-de0f-4d48-b649-ef07a7dc1b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714772773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.1714772773
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.1529782162
Short name T488
Test name
Test status
Simulation time 3268556224 ps
CPU time 4.44 seconds
Started Jul 09 05:39:25 PM PDT 24
Finished Jul 09 05:39:30 PM PDT 24
Peak memory 224628 kb
Host smart-6575e90f-1a0d-4e5d-a09e-a23aa37129d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529782162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.1529782162
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.2948644357
Short name T225
Test name
Test status
Simulation time 2574915650 ps
CPU time 61.25 seconds
Started Jul 09 05:39:34 PM PDT 24
Finished Jul 09 05:40:37 PM PDT 24
Peak memory 263420 kb
Host smart-18bca455-af26-4565-9fa0-f59be8b7ab69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948644357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmd
s.2948644357
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_intercept.1556808593
Short name T760
Test name
Test status
Simulation time 559699308 ps
CPU time 6.33 seconds
Started Jul 09 05:39:25 PM PDT 24
Finished Jul 09 05:39:32 PM PDT 24
Peak memory 224496 kb
Host smart-0823bbd3-c370-46c4-b358-58a29ae73d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556808593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.1556808593
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.4025565149
Short name T465
Test name
Test status
Simulation time 3631218519 ps
CPU time 29.51 seconds
Started Jul 09 05:39:28 PM PDT 24
Finished Jul 09 05:39:58 PM PDT 24
Peak memory 224592 kb
Host smart-0da65982-bff3-401f-bef8-85f197672af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025565149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.4025565149
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.2630542007
Short name T870
Test name
Test status
Simulation time 285395148 ps
CPU time 2.95 seconds
Started Jul 09 05:39:24 PM PDT 24
Finished Jul 09 05:39:27 PM PDT 24
Peak memory 224452 kb
Host smart-b5a42653-41de-40d2-9d60-48595e90c863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630542007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.2630542007
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.2986728770
Short name T522
Test name
Test status
Simulation time 400513855 ps
CPU time 4.08 seconds
Started Jul 09 05:39:28 PM PDT 24
Finished Jul 09 05:39:33 PM PDT 24
Peak memory 224500 kb
Host smart-c4e7bc7f-dc2c-43a2-8a85-fd67d24fbbb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986728770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.2986728770
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.1641575993
Short name T400
Test name
Test status
Simulation time 162751563 ps
CPU time 3.57 seconds
Started Jul 09 05:39:34 PM PDT 24
Finished Jul 09 05:39:39 PM PDT 24
Peak memory 219312 kb
Host smart-e76d13ef-8980-48ee-86eb-a8e87bda4664
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1641575993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.1641575993
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.3233460691
Short name T775
Test name
Test status
Simulation time 1074885564 ps
CPU time 10.1 seconds
Started Jul 09 05:39:26 PM PDT 24
Finished Jul 09 05:39:37 PM PDT 24
Peak memory 224444 kb
Host smart-e952a47b-4bbb-4aa6-8b0c-2a1f126475a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233460691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.3233460691
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.3196536900
Short name T1
Test name
Test status
Simulation time 9048098202 ps
CPU time 25.88 seconds
Started Jul 09 05:39:25 PM PDT 24
Finished Jul 09 05:39:52 PM PDT 24
Peak memory 216384 kb
Host smart-4c50a7c0-61ec-4563-be61-ce9aedc8a40d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196536900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.3196536900
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.2191735157
Short name T791
Test name
Test status
Simulation time 5424820931 ps
CPU time 4.33 seconds
Started Jul 09 05:39:25 PM PDT 24
Finished Jul 09 05:39:30 PM PDT 24
Peak memory 216400 kb
Host smart-3b487089-2044-4f05-af4b-0d7cc5367d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191735157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.2191735157
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.396806485
Short name T882
Test name
Test status
Simulation time 36762501 ps
CPU time 0.8 seconds
Started Jul 09 05:39:26 PM PDT 24
Finished Jul 09 05:39:28 PM PDT 24
Peak memory 205940 kb
Host smart-d1f1bde3-d992-4fd9-9c6f-5a5d74043e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396806485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.396806485
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.1221097706
Short name T459
Test name
Test status
Simulation time 13621271 ps
CPU time 0.68 seconds
Started Jul 09 05:39:28 PM PDT 24
Finished Jul 09 05:39:29 PM PDT 24
Peak memory 205648 kb
Host smart-bfb5715c-a5e5-472a-8ae2-1d373479a2f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221097706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.1221097706
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.2442097192
Short name T383
Test name
Test status
Simulation time 3413523927 ps
CPU time 10.09 seconds
Started Jul 09 05:39:24 PM PDT 24
Finished Jul 09 05:39:35 PM PDT 24
Peak memory 241004 kb
Host smart-fc8767df-1b4c-4b17-9d74-030dd754ba21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442097192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.2442097192
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.2143582870
Short name T35
Test name
Test status
Simulation time 39440553 ps
CPU time 0.73 seconds
Started Jul 09 05:39:32 PM PDT 24
Finished Jul 09 05:39:34 PM PDT 24
Peak memory 205532 kb
Host smart-cdd9c7d3-8a85-4457-83e1-c69c27c8751f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143582870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
2143582870
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.3114048755
Short name T970
Test name
Test status
Simulation time 184146494 ps
CPU time 2.61 seconds
Started Jul 09 05:39:30 PM PDT 24
Finished Jul 09 05:39:34 PM PDT 24
Peak memory 232624 kb
Host smart-614bb758-fd6e-42ab-8f4d-27a5750582c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114048755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.3114048755
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.522605583
Short name T944
Test name
Test status
Simulation time 12347234 ps
CPU time 0.81 seconds
Started Jul 09 05:39:32 PM PDT 24
Finished Jul 09 05:39:34 PM PDT 24
Peak memory 205560 kb
Host smart-12b3cf82-60f5-4cb4-b530-a40b470d0492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522605583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.522605583
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.1497102977
Short name T637
Test name
Test status
Simulation time 11873236690 ps
CPU time 26.33 seconds
Started Jul 09 05:39:28 PM PDT 24
Finished Jul 09 05:39:55 PM PDT 24
Peak memory 249184 kb
Host smart-1b950623-cc38-4430-812f-109a6839b7c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497102977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.1497102977
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.3118138499
Short name T529
Test name
Test status
Simulation time 9249369279 ps
CPU time 110.45 seconds
Started Jul 09 05:39:29 PM PDT 24
Finished Jul 09 05:41:20 PM PDT 24
Peak memory 253428 kb
Host smart-d2a83601-fb06-411f-9d14-c15a09693bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118138499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.3118138499
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.2710433675
Short name T81
Test name
Test status
Simulation time 36008953162 ps
CPU time 160.22 seconds
Started Jul 09 05:39:31 PM PDT 24
Finished Jul 09 05:42:12 PM PDT 24
Peak memory 249256 kb
Host smart-ee2b0a2b-7113-44a2-8171-c56741f80891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710433675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.2710433675
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.1067904400
Short name T390
Test name
Test status
Simulation time 66440027 ps
CPU time 3.59 seconds
Started Jul 09 05:39:31 PM PDT 24
Finished Jul 09 05:39:36 PM PDT 24
Peak memory 224464 kb
Host smart-9167455f-928e-4656-9cd4-80df8866465a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067904400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.1067904400
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.2663277738
Short name T607
Test name
Test status
Simulation time 49323357842 ps
CPU time 85.67 seconds
Started Jul 09 05:39:31 PM PDT 24
Finished Jul 09 05:40:57 PM PDT 24
Peak memory 233796 kb
Host smart-7308a5f1-a5d7-43dd-950e-456b604f040f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663277738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.2663277738
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_intercept.4239587709
Short name T282
Test name
Test status
Simulation time 503975332 ps
CPU time 4.51 seconds
Started Jul 09 05:39:35 PM PDT 24
Finished Jul 09 05:39:41 PM PDT 24
Peak memory 232576 kb
Host smart-72bb77ac-c1cc-4504-8b2a-49c17b6431d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239587709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.4239587709
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.3118292775
Short name T807
Test name
Test status
Simulation time 18343283932 ps
CPU time 45.07 seconds
Started Jul 09 05:39:30 PM PDT 24
Finished Jul 09 05:40:16 PM PDT 24
Peak memory 249088 kb
Host smart-5f49e792-0ec2-4c9f-8f3d-4630ed7d3673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118292775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.3118292775
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.475347715
Short name T841
Test name
Test status
Simulation time 150513513 ps
CPU time 2.79 seconds
Started Jul 09 05:39:29 PM PDT 24
Finished Jul 09 05:39:33 PM PDT 24
Peak memory 232636 kb
Host smart-e185b1dc-07d8-47a4-8033-d248afc8a473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475347715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swap
.475347715
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.705602758
Short name T831
Test name
Test status
Simulation time 1162679085 ps
CPU time 9.78 seconds
Started Jul 09 05:39:29 PM PDT 24
Finished Jul 09 05:39:40 PM PDT 24
Peak memory 232632 kb
Host smart-c63a0669-ccb0-427b-a660-6ea86e174216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705602758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.705602758
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.3598285013
Short name T578
Test name
Test status
Simulation time 948315738 ps
CPU time 8.23 seconds
Started Jul 09 05:39:33 PM PDT 24
Finished Jul 09 05:39:42 PM PDT 24
Peak memory 220960 kb
Host smart-d5551891-9dcc-44cf-a3fd-97e12c28c0dc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3598285013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.3598285013
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.4055878855
Short name T215
Test name
Test status
Simulation time 321715638029 ps
CPU time 713.15 seconds
Started Jul 09 05:39:30 PM PDT 24
Finished Jul 09 05:51:24 PM PDT 24
Peak memory 281412 kb
Host smart-d02dd3b9-b187-4f35-aacc-d0034daadef6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055878855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.4055878855
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.1962592113
Short name T757
Test name
Test status
Simulation time 413300540 ps
CPU time 4.92 seconds
Started Jul 09 05:39:34 PM PDT 24
Finished Jul 09 05:39:41 PM PDT 24
Peak memory 216432 kb
Host smart-12949e90-4b64-4014-84da-d9a35dc898a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962592113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.1962592113
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.3319589214
Short name T409
Test name
Test status
Simulation time 17257516236 ps
CPU time 12.44 seconds
Started Jul 09 05:39:31 PM PDT 24
Finished Jul 09 05:39:44 PM PDT 24
Peak memory 216300 kb
Host smart-39c044bf-1733-4f93-a75b-919dd3c88279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319589214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.3319589214
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.3774853472
Short name T902
Test name
Test status
Simulation time 75937162 ps
CPU time 0.69 seconds
Started Jul 09 05:39:32 PM PDT 24
Finished Jul 09 05:39:33 PM PDT 24
Peak memory 205620 kb
Host smart-e217ce80-f565-479c-9052-bc1382654b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774853472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.3774853472
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.3897758231
Short name T330
Test name
Test status
Simulation time 169004364 ps
CPU time 0.85 seconds
Started Jul 09 05:39:29 PM PDT 24
Finished Jul 09 05:39:30 PM PDT 24
Peak memory 205944 kb
Host smart-37bac434-a623-4b28-95a9-cf54805df92b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897758231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.3897758231
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.948098796
Short name T479
Test name
Test status
Simulation time 13581777460 ps
CPU time 31.47 seconds
Started Jul 09 05:39:31 PM PDT 24
Finished Jul 09 05:40:03 PM PDT 24
Peak memory 224608 kb
Host smart-315580d3-9724-46b0-b7a5-12f620b116cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948098796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.948098796
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.3390443299
Short name T338
Test name
Test status
Simulation time 43419731 ps
CPU time 0.73 seconds
Started Jul 09 05:38:45 PM PDT 24
Finished Jul 09 05:38:48 PM PDT 24
Peak memory 204980 kb
Host smart-bd97e033-b076-47a2-a41e-08dc5a8386f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390443299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.3
390443299
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.62303043
Short name T793
Test name
Test status
Simulation time 1612636108 ps
CPU time 8.64 seconds
Started Jul 09 05:38:34 PM PDT 24
Finished Jul 09 05:38:44 PM PDT 24
Peak memory 224424 kb
Host smart-b9e30884-083a-4f38-bacf-23d3f8f3ad44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62303043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.62303043
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.913843042
Short name T620
Test name
Test status
Simulation time 39526568 ps
CPU time 0.78 seconds
Started Jul 09 05:38:35 PM PDT 24
Finished Jul 09 05:38:37 PM PDT 24
Peak memory 205548 kb
Host smart-eb9f5908-9807-4b46-95fa-89a578e517b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913843042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.913843042
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.2250239014
Short name T47
Test name
Test status
Simulation time 30775720874 ps
CPU time 222.27 seconds
Started Jul 09 05:38:37 PM PDT 24
Finished Jul 09 05:42:20 PM PDT 24
Peak memory 249208 kb
Host smart-c49b8aaa-efc2-4dbc-bb00-6598378f0496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250239014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.2250239014
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.2150900978
Short name T171
Test name
Test status
Simulation time 8143701562 ps
CPU time 97.78 seconds
Started Jul 09 05:38:45 PM PDT 24
Finished Jul 09 05:40:25 PM PDT 24
Peak memory 250264 kb
Host smart-4d8c9360-c876-4110-98d2-58522163282b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150900978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.2150900978
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.2224768951
Short name T242
Test name
Test status
Simulation time 187247991801 ps
CPU time 505.89 seconds
Started Jul 09 05:38:45 PM PDT 24
Finished Jul 09 05:47:12 PM PDT 24
Peak memory 265828 kb
Host smart-7f48f8bd-5608-4f1b-abfe-4e5aff0bdd8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224768951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.2224768951
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.4242161831
Short name T58
Test name
Test status
Simulation time 326092300 ps
CPU time 4.39 seconds
Started Jul 09 05:38:35 PM PDT 24
Finished Jul 09 05:38:41 PM PDT 24
Peak memory 232720 kb
Host smart-a8b6b965-d3ab-4b15-b1d5-d180ebdd466a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242161831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.4242161831
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.2196712315
Short name T740
Test name
Test status
Simulation time 6175748400 ps
CPU time 34.84 seconds
Started Jul 09 05:38:46 PM PDT 24
Finished Jul 09 05:39:23 PM PDT 24
Peak memory 252284 kb
Host smart-4af8437d-ab39-4ae1-b0ca-d84bbd806303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196712315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds
.2196712315
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.144914226
Short name T862
Test name
Test status
Simulation time 44167597 ps
CPU time 2.48 seconds
Started Jul 09 05:38:34 PM PDT 24
Finished Jul 09 05:38:38 PM PDT 24
Peak memory 232340 kb
Host smart-436b4d2a-a60a-475d-9223-6d7bf8d7f1cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144914226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.144914226
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.591005888
Short name T614
Test name
Test status
Simulation time 2253996510 ps
CPU time 11.37 seconds
Started Jul 09 05:38:34 PM PDT 24
Finished Jul 09 05:38:47 PM PDT 24
Peak memory 240520 kb
Host smart-32e94be8-5a08-4898-911c-ba0e82aa125f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591005888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.591005888
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.1826324404
Short name T477
Test name
Test status
Simulation time 432650282 ps
CPU time 3.43 seconds
Started Jul 09 05:38:34 PM PDT 24
Finished Jul 09 05:38:39 PM PDT 24
Peak memory 224460 kb
Host smart-d4f49cd4-0f1b-4e4d-ab86-c78ae42e1e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826324404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.1826324404
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.1378888880
Short name T445
Test name
Test status
Simulation time 5318979439 ps
CPU time 8.11 seconds
Started Jul 09 05:38:36 PM PDT 24
Finished Jul 09 05:38:45 PM PDT 24
Peak memory 224476 kb
Host smart-500787f1-2600-4bbf-be0f-910dcf3d2790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378888880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.1378888880
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.31298173
Short name T753
Test name
Test status
Simulation time 9542376739 ps
CPU time 15.94 seconds
Started Jul 09 05:38:48 PM PDT 24
Finished Jul 09 05:39:07 PM PDT 24
Peak memory 220040 kb
Host smart-7d637e92-cda8-478a-a3a4-181a773faf5e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=31298173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_direct
.31298173
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.862568613
Short name T34
Test name
Test status
Simulation time 136967144 ps
CPU time 1.06 seconds
Started Jul 09 05:38:44 PM PDT 24
Finished Jul 09 05:38:47 PM PDT 24
Peak memory 236580 kb
Host smart-5c41e9ef-8088-4e0b-9654-5d2020e56d0a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862568613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.862568613
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.3499867121
Short name T705
Test name
Test status
Simulation time 15331410 ps
CPU time 0.72 seconds
Started Jul 09 05:38:33 PM PDT 24
Finished Jul 09 05:38:34 PM PDT 24
Peak memory 205676 kb
Host smart-849913ef-f3e1-4281-a11a-3ae9e80b423d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499867121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.3499867121
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.3797060462
Short name T719
Test name
Test status
Simulation time 13150440940 ps
CPU time 19.03 seconds
Started Jul 09 05:38:34 PM PDT 24
Finished Jul 09 05:38:54 PM PDT 24
Peak memory 216332 kb
Host smart-77fb3942-bbc8-44b3-81c6-9053219fa152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797060462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.3797060462
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.4078409871
Short name T658
Test name
Test status
Simulation time 17674465 ps
CPU time 0.85 seconds
Started Jul 09 05:38:34 PM PDT 24
Finished Jul 09 05:38:36 PM PDT 24
Peak memory 205984 kb
Host smart-b7110c86-bd21-462b-adde-772ac51845cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078409871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.4078409871
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.2546054978
Short name T695
Test name
Test status
Simulation time 61635471 ps
CPU time 0.74 seconds
Started Jul 09 05:38:33 PM PDT 24
Finished Jul 09 05:38:34 PM PDT 24
Peak memory 205980 kb
Host smart-d9c3e163-7b3d-4526-a7ae-41e92fa5f3a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546054978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.2546054978
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.2405561674
Short name T626
Test name
Test status
Simulation time 441019158 ps
CPU time 7.07 seconds
Started Jul 09 05:38:34 PM PDT 24
Finished Jul 09 05:38:42 PM PDT 24
Peak memory 240212 kb
Host smart-66c99cfe-71ca-4ffe-bc2c-ece121458946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405561674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.2405561674
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.4050512292
Short name T5
Test name
Test status
Simulation time 51327362 ps
CPU time 0.71 seconds
Started Jul 09 05:39:28 PM PDT 24
Finished Jul 09 05:39:30 PM PDT 24
Peak memory 205496 kb
Host smart-ef9ffd09-2bc2-4c3a-962a-63a2acd85f29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050512292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
4050512292
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.2460479869
Short name T668
Test name
Test status
Simulation time 3699087898 ps
CPU time 13.84 seconds
Started Jul 09 05:39:31 PM PDT 24
Finished Jul 09 05:39:45 PM PDT 24
Peak memory 224608 kb
Host smart-fc2c30ef-3b9f-4ded-b8fb-5fc1442c48d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460479869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.2460479869
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.3834732998
Short name T545
Test name
Test status
Simulation time 14136267 ps
CPU time 0.75 seconds
Started Jul 09 05:39:27 PM PDT 24
Finished Jul 09 05:39:29 PM PDT 24
Peak memory 206936 kb
Host smart-cfe02a2e-f04c-452d-9a45-c286f4c88432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834732998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.3834732998
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.3589820200
Short name T452
Test name
Test status
Simulation time 36816246715 ps
CPU time 80.95 seconds
Started Jul 09 05:39:33 PM PDT 24
Finished Jul 09 05:40:55 PM PDT 24
Peak memory 248484 kb
Host smart-6792385d-3a1d-408d-8915-b0b270b618b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589820200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.3589820200
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.3717755493
Short name T237
Test name
Test status
Simulation time 27184609290 ps
CPU time 256.96 seconds
Started Jul 09 05:39:33 PM PDT 24
Finished Jul 09 05:43:51 PM PDT 24
Peak memory 249220 kb
Host smart-ea3fa7d8-ea73-4aa2-b479-94d300963b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717755493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.3717755493
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.1156805356
Short name T922
Test name
Test status
Simulation time 106810237374 ps
CPU time 150.74 seconds
Started Jul 09 05:39:33 PM PDT 24
Finished Jul 09 05:42:05 PM PDT 24
Peak memory 251596 kb
Host smart-a12c0c6a-a80e-467f-8c78-5a8480d226aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156805356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmd
s.1156805356
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_intercept.4001124665
Short name T39
Test name
Test status
Simulation time 767904300 ps
CPU time 12.26 seconds
Started Jul 09 05:39:29 PM PDT 24
Finished Jul 09 05:39:43 PM PDT 24
Peak memory 224424 kb
Host smart-6b081b40-40f9-4df5-a44b-de83fcc99a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001124665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.4001124665
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.3538248231
Short name T270
Test name
Test status
Simulation time 8388263267 ps
CPU time 83.6 seconds
Started Jul 09 05:39:29 PM PDT 24
Finished Jul 09 05:40:54 PM PDT 24
Peak memory 232772 kb
Host smart-a07d855a-b3e7-4f71-935c-7e785e857402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538248231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.3538248231
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.754786099
Short name T655
Test name
Test status
Simulation time 3496286456 ps
CPU time 6.17 seconds
Started Jul 09 05:39:33 PM PDT 24
Finished Jul 09 05:39:40 PM PDT 24
Peak memory 223688 kb
Host smart-630b92cc-16d4-4797-b510-45bb147f7a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754786099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swap
.754786099
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.1647542502
Short name T718
Test name
Test status
Simulation time 884465252 ps
CPU time 2.69 seconds
Started Jul 09 05:39:32 PM PDT 24
Finished Jul 09 05:39:36 PM PDT 24
Peak memory 224488 kb
Host smart-6d2c8786-01b1-4fd9-93e9-48b8eaccd13e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647542502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.1647542502
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.2767446357
Short name T153
Test name
Test status
Simulation time 1934749240 ps
CPU time 12.04 seconds
Started Jul 09 05:39:30 PM PDT 24
Finished Jul 09 05:39:43 PM PDT 24
Peak memory 220516 kb
Host smart-3c7e937c-d7c7-4f74-bca7-e844a1db8188
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2767446357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.2767446357
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.3657655800
Short name T894
Test name
Test status
Simulation time 2172346726 ps
CPU time 15.21 seconds
Started Jul 09 05:39:30 PM PDT 24
Finished Jul 09 05:39:46 PM PDT 24
Peak memory 216352 kb
Host smart-6dba3b1b-f16d-46f0-ac6f-0becfad39266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657655800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.3657655800
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.1875431338
Short name T876
Test name
Test status
Simulation time 37501972828 ps
CPU time 14.79 seconds
Started Jul 09 05:39:29 PM PDT 24
Finished Jul 09 05:39:45 PM PDT 24
Peak memory 216396 kb
Host smart-31b3fb35-56ba-4bba-a1b1-5f8c1fe9a158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875431338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.1875431338
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.824557078
Short name T601
Test name
Test status
Simulation time 279147349 ps
CPU time 2.08 seconds
Started Jul 09 05:39:29 PM PDT 24
Finished Jul 09 05:39:31 PM PDT 24
Peak memory 216256 kb
Host smart-d3256e22-af2b-4636-9261-e773687472e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824557078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.824557078
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.1540027936
Short name T334
Test name
Test status
Simulation time 112755603 ps
CPU time 0.91 seconds
Started Jul 09 05:39:29 PM PDT 24
Finished Jul 09 05:39:30 PM PDT 24
Peak memory 206980 kb
Host smart-55b8d0ac-047a-4545-b370-e99f55f97496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540027936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.1540027936
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.4106427333
Short name T198
Test name
Test status
Simulation time 10270268131 ps
CPU time 28.37 seconds
Started Jul 09 05:39:29 PM PDT 24
Finished Jul 09 05:39:59 PM PDT 24
Peak memory 232828 kb
Host smart-3807d854-9bad-49dc-8395-21af8615f7f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106427333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.4106427333
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.2615020291
Short name T331
Test name
Test status
Simulation time 34209655 ps
CPU time 0.71 seconds
Started Jul 09 05:39:57 PM PDT 24
Finished Jul 09 05:39:59 PM PDT 24
Peak memory 204928 kb
Host smart-e82513ca-b758-4d34-84f6-8bd92d8cebb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615020291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
2615020291
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.589120079
Short name T525
Test name
Test status
Simulation time 665438182 ps
CPU time 3.38 seconds
Started Jul 09 05:39:35 PM PDT 24
Finished Jul 09 05:39:40 PM PDT 24
Peak memory 224508 kb
Host smart-c77ef198-d4f4-46b0-be5a-69afb8b14e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589120079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.589120079
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.3494634550
Short name T6
Test name
Test status
Simulation time 28358193 ps
CPU time 0.79 seconds
Started Jul 09 05:39:31 PM PDT 24
Finished Jul 09 05:39:33 PM PDT 24
Peak memory 206612 kb
Host smart-cca3438a-e624-43c1-9b13-f538de2f271b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494634550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.3494634550
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.1181121694
Short name T437
Test name
Test status
Simulation time 34361323356 ps
CPU time 116.59 seconds
Started Jul 09 05:39:33 PM PDT 24
Finished Jul 09 05:41:31 PM PDT 24
Peak memory 249200 kb
Host smart-f2ffe98a-2c17-4ac2-b70b-58701bc87c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181121694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.1181121694
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.720750357
Short name T52
Test name
Test status
Simulation time 35184363495 ps
CPU time 364.07 seconds
Started Jul 09 05:39:34 PM PDT 24
Finished Jul 09 05:45:39 PM PDT 24
Peak memory 255872 kb
Host smart-e7915d49-3fae-4f0a-8acd-a55d8c97c7d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720750357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idle
.720750357
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.2923716172
Short name T296
Test name
Test status
Simulation time 30117683943 ps
CPU time 55.89 seconds
Started Jul 09 05:39:35 PM PDT 24
Finished Jul 09 05:40:32 PM PDT 24
Peak memory 249224 kb
Host smart-73e78822-3573-4313-b6b8-d0fc250d811e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923716172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.2923716172
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.202685654
Short name T267
Test name
Test status
Simulation time 16657181634 ps
CPU time 36.95 seconds
Started Jul 09 05:39:34 PM PDT 24
Finished Jul 09 05:40:13 PM PDT 24
Peak memory 254236 kb
Host smart-c3e41d8d-7618-4391-9abc-e7ca4d8a8708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202685654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmds
.202685654
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.1992656946
Short name T645
Test name
Test status
Simulation time 2935792727 ps
CPU time 14.59 seconds
Started Jul 09 05:39:37 PM PDT 24
Finished Jul 09 05:39:53 PM PDT 24
Peak memory 224540 kb
Host smart-6b8731b8-0d5d-4962-b6cd-7980e794a035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992656946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.1992656946
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.2401631834
Short name T851
Test name
Test status
Simulation time 1444248689 ps
CPU time 14.37 seconds
Started Jul 09 05:39:32 PM PDT 24
Finished Jul 09 05:39:48 PM PDT 24
Peak memory 248836 kb
Host smart-88c7c7b9-8b49-4012-b561-0f674e200a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401631834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.2401631834
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.3423645030
Short name T227
Test name
Test status
Simulation time 698665577 ps
CPU time 3.87 seconds
Started Jul 09 05:39:35 PM PDT 24
Finished Jul 09 05:39:41 PM PDT 24
Peak memory 232632 kb
Host smart-30cad485-0583-46b4-a659-d7a1a9bcf19a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423645030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.3423645030
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.218708132
Short name T953
Test name
Test status
Simulation time 1513367996 ps
CPU time 7.22 seconds
Started Jul 09 05:39:34 PM PDT 24
Finished Jul 09 05:39:42 PM PDT 24
Peak memory 232704 kb
Host smart-e6726d29-d404-4227-a2a8-a1c77e6655db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218708132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.218708132
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.120555885
Short name T844
Test name
Test status
Simulation time 1867749273 ps
CPU time 11.63 seconds
Started Jul 09 05:39:35 PM PDT 24
Finished Jul 09 05:39:48 PM PDT 24
Peak memory 218840 kb
Host smart-0cb343de-072a-4ccb-8eb1-98846d8a5104
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=120555885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dire
ct.120555885
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.264994316
Short name T20
Test name
Test status
Simulation time 135983478 ps
CPU time 1.04 seconds
Started Jul 09 05:39:32 PM PDT 24
Finished Jul 09 05:39:34 PM PDT 24
Peak memory 206824 kb
Host smart-7da4c99a-0fbd-415b-8c82-2ae942451d8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264994316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stres
s_all.264994316
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.1339296606
Short name T530
Test name
Test status
Simulation time 894146554 ps
CPU time 11.56 seconds
Started Jul 09 05:39:32 PM PDT 24
Finished Jul 09 05:39:45 PM PDT 24
Peak memory 216144 kb
Host smart-407aeb9c-5713-47e9-8c56-b6a1dad5de6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339296606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.1339296606
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.2252727757
Short name T315
Test name
Test status
Simulation time 614916031 ps
CPU time 3.93 seconds
Started Jul 09 05:39:30 PM PDT 24
Finished Jul 09 05:39:35 PM PDT 24
Peak memory 216248 kb
Host smart-8088a8b9-3543-49d8-b810-18e38d5e47b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252727757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.2252727757
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.2609625277
Short name T964
Test name
Test status
Simulation time 184572507 ps
CPU time 1.57 seconds
Started Jul 09 05:39:35 PM PDT 24
Finished Jul 09 05:39:39 PM PDT 24
Peak memory 216228 kb
Host smart-d08b064e-5cb1-4624-b9ec-6c15381701ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609625277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.2609625277
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.2244630149
Short name T339
Test name
Test status
Simulation time 40845673 ps
CPU time 0.76 seconds
Started Jul 09 05:39:32 PM PDT 24
Finished Jul 09 05:39:34 PM PDT 24
Peak memory 205992 kb
Host smart-68837189-c239-48fb-ac26-197c6b086243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244630149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.2244630149
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.2038226400
Short name T117
Test name
Test status
Simulation time 443633300 ps
CPU time 3.63 seconds
Started Jul 09 05:39:32 PM PDT 24
Finished Jul 09 05:39:36 PM PDT 24
Peak memory 224456 kb
Host smart-282b365d-9e46-4d3f-a847-92226699bf69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038226400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.2038226400
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.583514356
Short name T23
Test name
Test status
Simulation time 16358074 ps
CPU time 0.88 seconds
Started Jul 09 05:39:35 PM PDT 24
Finished Jul 09 05:39:37 PM PDT 24
Peak memory 204892 kb
Host smart-ac125574-1798-470c-ac43-425de8b0bd3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583514356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.583514356
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.2570021857
Short name T606
Test name
Test status
Simulation time 589419303 ps
CPU time 9.27 seconds
Started Jul 09 05:39:35 PM PDT 24
Finished Jul 09 05:39:46 PM PDT 24
Peak memory 232616 kb
Host smart-418e344d-7ab3-4f10-b58a-d328512a16c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570021857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.2570021857
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.2714216605
Short name T456
Test name
Test status
Simulation time 64091195 ps
CPU time 0.8 seconds
Started Jul 09 05:39:37 PM PDT 24
Finished Jul 09 05:39:39 PM PDT 24
Peak memory 206904 kb
Host smart-03a31c28-def2-4560-aefb-8b0d5d196a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714216605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.2714216605
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.4266753689
Short name T275
Test name
Test status
Simulation time 13325069677 ps
CPU time 63.14 seconds
Started Jul 09 05:39:33 PM PDT 24
Finished Jul 09 05:40:37 PM PDT 24
Peak memory 256200 kb
Host smart-b8ffbcf8-9ffe-417f-bcbf-ddef5ed311c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266753689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.4266753689
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.3413817563
Short name T429
Test name
Test status
Simulation time 28681428573 ps
CPU time 99.42 seconds
Started Jul 09 05:39:40 PM PDT 24
Finished Jul 09 05:41:20 PM PDT 24
Peak memory 258452 kb
Host smart-430c3f65-243e-42c8-9f7f-97f655eeadd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413817563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.3413817563
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.1504594621
Short name T230
Test name
Test status
Simulation time 108613423894 ps
CPU time 419.83 seconds
Started Jul 09 05:39:34 PM PDT 24
Finished Jul 09 05:46:35 PM PDT 24
Peak memory 259752 kb
Host smart-07aa4adf-9e21-4003-bcd8-106225cec571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504594621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.1504594621
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.3155504677
Short name T151
Test name
Test status
Simulation time 1467701371 ps
CPU time 16.45 seconds
Started Jul 09 05:39:34 PM PDT 24
Finished Jul 09 05:39:51 PM PDT 24
Peak memory 249088 kb
Host smart-57cfc6af-0b93-4628-bf6a-78ce5f8b400f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155504677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.3155504677
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.1056440303
Short name T229
Test name
Test status
Simulation time 62565781266 ps
CPU time 460.53 seconds
Started Jul 09 05:39:35 PM PDT 24
Finished Jul 09 05:47:17 PM PDT 24
Peak memory 267264 kb
Host smart-1ce9e8c7-830d-4571-9bdc-3cbfc6cb9f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056440303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmd
s.1056440303
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.254039581
Short name T406
Test name
Test status
Simulation time 1349488506 ps
CPU time 3.27 seconds
Started Jul 09 05:39:37 PM PDT 24
Finished Jul 09 05:39:41 PM PDT 24
Peak memory 224416 kb
Host smart-3f1008a1-4744-4f60-801c-98c84255ec0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254039581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.254039581
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.3571304199
Short name T698
Test name
Test status
Simulation time 1341528692 ps
CPU time 8.6 seconds
Started Jul 09 05:39:34 PM PDT 24
Finished Jul 09 05:39:44 PM PDT 24
Peak memory 224432 kb
Host smart-19f77b1a-b6dc-444c-a7b8-946d9030b34f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571304199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.3571304199
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.995007623
Short name T619
Test name
Test status
Simulation time 178475877 ps
CPU time 3.04 seconds
Started Jul 09 05:39:33 PM PDT 24
Finished Jul 09 05:39:38 PM PDT 24
Peak memory 232576 kb
Host smart-71b27be6-2445-41bd-bb6d-c486e3636638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995007623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swap
.995007623
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.3612103437
Short name T430
Test name
Test status
Simulation time 194262043 ps
CPU time 2.64 seconds
Started Jul 09 05:39:36 PM PDT 24
Finished Jul 09 05:39:40 PM PDT 24
Peak memory 224460 kb
Host smart-bef19f07-0c23-4345-9c63-a5452b489ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612103437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.3612103437
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.1426475874
Short name T450
Test name
Test status
Simulation time 299421108 ps
CPU time 5.44 seconds
Started Jul 09 05:39:36 PM PDT 24
Finished Jul 09 05:39:47 PM PDT 24
Peak memory 220436 kb
Host smart-3edcdca7-fbd0-4bc0-a9bf-b163f0a3b1c2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1426475874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.1426475874
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.4004686786
Short name T160
Test name
Test status
Simulation time 75251282 ps
CPU time 1.16 seconds
Started Jul 09 05:39:35 PM PDT 24
Finished Jul 09 05:39:38 PM PDT 24
Peak memory 206932 kb
Host smart-0f70af1a-485f-4edd-ad01-6d32c7fa736c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004686786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.4004686786
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.3998227426
Short name T576
Test name
Test status
Simulation time 126927507 ps
CPU time 0.75 seconds
Started Jul 09 05:39:32 PM PDT 24
Finished Jul 09 05:39:34 PM PDT 24
Peak memory 205732 kb
Host smart-7684f77e-6ba2-43ed-ac44-4c6f23ccf0ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998227426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.3998227426
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.2853766620
Short name T551
Test name
Test status
Simulation time 3841457094 ps
CPU time 3.22 seconds
Started Jul 09 05:39:34 PM PDT 24
Finished Jul 09 05:39:39 PM PDT 24
Peak memory 216284 kb
Host smart-c968fe2c-4db7-47ea-a3a8-ac16bf7d7519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853766620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.2853766620
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.2539286814
Short name T332
Test name
Test status
Simulation time 497821923 ps
CPU time 4.66 seconds
Started Jul 09 05:39:36 PM PDT 24
Finished Jul 09 05:39:42 PM PDT 24
Peak memory 216200 kb
Host smart-8dae7e43-2723-421b-9ba1-55f96d4a1406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539286814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.2539286814
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.132308558
Short name T388
Test name
Test status
Simulation time 31912222 ps
CPU time 0.85 seconds
Started Jul 09 05:39:33 PM PDT 24
Finished Jul 09 05:39:35 PM PDT 24
Peak memory 205988 kb
Host smart-35f17e06-80b6-4de9-a657-8030aba3753d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132308558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.132308558
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.910201825
Short name T776
Test name
Test status
Simulation time 703014923 ps
CPU time 4.16 seconds
Started Jul 09 05:39:35 PM PDT 24
Finished Jul 09 05:39:41 PM PDT 24
Peak memory 224496 kb
Host smart-ac521ee5-61da-43de-9b33-f5bd6cf1a336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910201825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.910201825
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.3858353074
Short name T362
Test name
Test status
Simulation time 15533547 ps
CPU time 0.74 seconds
Started Jul 09 05:39:37 PM PDT 24
Finished Jul 09 05:39:40 PM PDT 24
Peak memory 204924 kb
Host smart-6e2b5b9a-d47a-48a2-9c29-28e9642610c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858353074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
3858353074
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.57715808
Short name T925
Test name
Test status
Simulation time 149990560 ps
CPU time 2.24 seconds
Started Jul 09 05:39:38 PM PDT 24
Finished Jul 09 05:39:41 PM PDT 24
Peak memory 224468 kb
Host smart-5da57fe8-4089-4b05-b656-755c9418ec9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57715808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.57715808
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.3335573028
Short name T25
Test name
Test status
Simulation time 59966929 ps
CPU time 0.76 seconds
Started Jul 09 05:39:35 PM PDT 24
Finished Jul 09 05:39:37 PM PDT 24
Peak memory 205504 kb
Host smart-6cea627f-36a2-4d44-982e-396ca6a095ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335573028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.3335573028
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.599087674
Short name T890
Test name
Test status
Simulation time 87972092571 ps
CPU time 296.03 seconds
Started Jul 09 05:39:41 PM PDT 24
Finished Jul 09 05:44:38 PM PDT 24
Peak memory 257372 kb
Host smart-124afb4c-c066-411c-82a0-fbc4b3f3660e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599087674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.599087674
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.1396210607
Short name T823
Test name
Test status
Simulation time 31529902743 ps
CPU time 214.65 seconds
Started Jul 09 05:39:38 PM PDT 24
Finished Jul 09 05:43:14 PM PDT 24
Peak memory 254008 kb
Host smart-5c100a1b-15ae-4e3e-9b8f-7fa939ce17f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396210607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.1396210607
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.1587013601
Short name T897
Test name
Test status
Simulation time 8069185673 ps
CPU time 96.57 seconds
Started Jul 09 05:39:39 PM PDT 24
Finished Jul 09 05:41:16 PM PDT 24
Peak memory 249260 kb
Host smart-83eb057f-4ff9-4adb-9463-fed18dad5326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587013601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.1587013601
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.940072678
Short name T418
Test name
Test status
Simulation time 34413719 ps
CPU time 2.66 seconds
Started Jul 09 05:39:42 PM PDT 24
Finished Jul 09 05:39:45 PM PDT 24
Peak memory 232692 kb
Host smart-a5cf713f-e26d-4d3c-a2ed-4cca21fbd4aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940072678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.940072678
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.3416800214
Short name T781
Test name
Test status
Simulation time 6053718260 ps
CPU time 42.75 seconds
Started Jul 09 05:39:36 PM PDT 24
Finished Jul 09 05:40:20 PM PDT 24
Peak memory 236784 kb
Host smart-728efe24-7a5a-4242-97ce-c0193eea5786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416800214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmd
s.3416800214
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.2628962904
Short name T696
Test name
Test status
Simulation time 499794899 ps
CPU time 2.43 seconds
Started Jul 09 05:39:44 PM PDT 24
Finished Jul 09 05:39:47 PM PDT 24
Peak memory 232660 kb
Host smart-e248d011-5cea-4b03-a59f-a4c71176bf30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628962904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.2628962904
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.2960773472
Short name T711
Test name
Test status
Simulation time 648977851 ps
CPU time 5.6 seconds
Started Jul 09 05:39:36 PM PDT 24
Finished Jul 09 05:39:43 PM PDT 24
Peak memory 224456 kb
Host smart-58627110-00fe-456d-aebe-4f156dc940a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960773472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.2960773472
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.4133955181
Short name T476
Test name
Test status
Simulation time 28687664822 ps
CPU time 27.02 seconds
Started Jul 09 05:39:37 PM PDT 24
Finished Jul 09 05:40:05 PM PDT 24
Peak memory 240520 kb
Host smart-9cb2e89c-5ca8-45b5-84f3-4073606a882c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133955181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.4133955181
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.3751741912
Short name T410
Test name
Test status
Simulation time 8442366727 ps
CPU time 13.36 seconds
Started Jul 09 05:39:39 PM PDT 24
Finished Jul 09 05:39:53 PM PDT 24
Peak memory 232792 kb
Host smart-885de6fe-92ee-431f-bd22-5e40f01185e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751741912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.3751741912
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.2048103016
Short name T485
Test name
Test status
Simulation time 753737472 ps
CPU time 4.99 seconds
Started Jul 09 05:39:40 PM PDT 24
Finished Jul 09 05:39:46 PM PDT 24
Peak memory 220252 kb
Host smart-dee844b9-82f3-49fa-baa4-5527ee213c67
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2048103016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.2048103016
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.2886682721
Short name T982
Test name
Test status
Simulation time 90881598311 ps
CPU time 307.27 seconds
Started Jul 09 05:39:38 PM PDT 24
Finished Jul 09 05:44:47 PM PDT 24
Peak memory 265680 kb
Host smart-3381e5b4-234d-44eb-a1f7-0a78de60e1ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886682721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.2886682721
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.4168051388
Short name T306
Test name
Test status
Simulation time 937439485 ps
CPU time 13.75 seconds
Started Jul 09 05:39:36 PM PDT 24
Finished Jul 09 05:39:51 PM PDT 24
Peak memory 216280 kb
Host smart-28e52c0e-7f99-41fb-812c-c928664b2c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168051388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.4168051388
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.3123022383
Short name T134
Test name
Test status
Simulation time 4168842279 ps
CPU time 6.82 seconds
Started Jul 09 05:39:34 PM PDT 24
Finished Jul 09 05:39:42 PM PDT 24
Peak memory 216320 kb
Host smart-148f06a2-6ecc-4a90-b3cc-f2f25902f217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123022383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.3123022383
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.4285468303
Short name T846
Test name
Test status
Simulation time 76905780 ps
CPU time 0.87 seconds
Started Jul 09 05:39:36 PM PDT 24
Finished Jul 09 05:39:38 PM PDT 24
Peak memory 206604 kb
Host smart-23b31577-062f-4100-889d-f452f4fab4e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285468303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.4285468303
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.2559261662
Short name T137
Test name
Test status
Simulation time 28679613 ps
CPU time 0.79 seconds
Started Jul 09 05:39:34 PM PDT 24
Finished Jul 09 05:39:37 PM PDT 24
Peak memory 206004 kb
Host smart-e64c0784-c8b7-4018-bb09-3fab0c6175fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559261662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.2559261662
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.1230235030
Short name T510
Test name
Test status
Simulation time 2548168183 ps
CPU time 5.23 seconds
Started Jul 09 05:39:38 PM PDT 24
Finished Jul 09 05:39:45 PM PDT 24
Peak memory 232736 kb
Host smart-cb7d522c-5ebb-438d-ac33-6542216a4b7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230235030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.1230235030
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.3363654177
Short name T461
Test name
Test status
Simulation time 12662724 ps
CPU time 0.71 seconds
Started Jul 09 05:39:39 PM PDT 24
Finished Jul 09 05:39:41 PM PDT 24
Peak memory 204948 kb
Host smart-743e328b-69f9-484c-b86f-3179a1aca1f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363654177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
3363654177
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.1767881167
Short name T318
Test name
Test status
Simulation time 531277730 ps
CPU time 7.47 seconds
Started Jul 09 05:39:37 PM PDT 24
Finished Jul 09 05:39:45 PM PDT 24
Peak memory 224432 kb
Host smart-97e49256-094b-4674-b5f4-78ad97a93dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767881167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.1767881167
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.2381229137
Short name T366
Test name
Test status
Simulation time 54433333 ps
CPU time 0.88 seconds
Started Jul 09 05:39:40 PM PDT 24
Finished Jul 09 05:39:42 PM PDT 24
Peak memory 206880 kb
Host smart-3006421c-8e47-4b72-bdfe-c3201f1f06a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381229137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.2381229137
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.3522795983
Short name T281
Test name
Test status
Simulation time 118252409107 ps
CPU time 133.33 seconds
Started Jul 09 05:39:57 PM PDT 24
Finished Jul 09 05:42:11 PM PDT 24
Peak memory 257324 kb
Host smart-e3243e9c-8d33-4098-97a7-ef932c6ae9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522795983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.3522795983
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.1212251447
Short name T74
Test name
Test status
Simulation time 1441856583 ps
CPU time 20.6 seconds
Started Jul 09 05:39:47 PM PDT 24
Finished Jul 09 05:40:08 PM PDT 24
Peak memory 249176 kb
Host smart-fe105b91-43e8-4fc0-9457-f31bbd5088a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212251447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.1212251447
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.805395456
Short name T649
Test name
Test status
Simulation time 7161425013 ps
CPU time 101.08 seconds
Started Jul 09 05:39:39 PM PDT 24
Finished Jul 09 05:41:21 PM PDT 24
Peak memory 250116 kb
Host smart-3aceba04-2380-4e83-92f9-b2a3dfe6eb02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805395456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idle
.805395456
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.1259436265
Short name T391
Test name
Test status
Simulation time 279103383 ps
CPU time 2.96 seconds
Started Jul 09 05:39:44 PM PDT 24
Finished Jul 09 05:39:48 PM PDT 24
Peak memory 232612 kb
Host smart-69215d46-b96d-49e0-b417-00889aad861d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259436265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.1259436265
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.3190312096
Short name T43
Test name
Test status
Simulation time 85243920159 ps
CPU time 182.76 seconds
Started Jul 09 05:39:34 PM PDT 24
Finished Jul 09 05:42:39 PM PDT 24
Peak memory 270008 kb
Host smart-d484977a-55f9-4df9-9e4e-f9667fdff144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190312096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmd
s.3190312096
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.2107572654
Short name T872
Test name
Test status
Simulation time 4180385280 ps
CPU time 11.54 seconds
Started Jul 09 05:39:40 PM PDT 24
Finished Jul 09 05:39:52 PM PDT 24
Peak memory 224428 kb
Host smart-41a82c2b-3b17-4f98-8952-321162fceb26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107572654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.2107572654
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.1933160505
Short name T76
Test name
Test status
Simulation time 129741199 ps
CPU time 4.22 seconds
Started Jul 09 05:39:37 PM PDT 24
Finished Jul 09 05:39:43 PM PDT 24
Peak memory 235048 kb
Host smart-34c1b795-0004-400d-a299-4f035077b70a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933160505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.1933160505
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.1894396286
Short name T7
Test name
Test status
Simulation time 6020404475 ps
CPU time 7.39 seconds
Started Jul 09 05:39:37 PM PDT 24
Finished Jul 09 05:39:46 PM PDT 24
Peak memory 232736 kb
Host smart-fcffc884-9c65-46f9-86c6-313bf7f23426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894396286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.1894396286
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.914470820
Short name T436
Test name
Test status
Simulation time 1524158372 ps
CPU time 2.8 seconds
Started Jul 09 05:39:37 PM PDT 24
Finished Jul 09 05:39:41 PM PDT 24
Peak memory 232660 kb
Host smart-dd1a7153-d232-43dd-bf50-01e9829c3a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914470820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.914470820
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.31464388
Short name T743
Test name
Test status
Simulation time 431334669 ps
CPU time 4.12 seconds
Started Jul 09 05:39:37 PM PDT 24
Finished Jul 09 05:39:42 PM PDT 24
Peak memory 220208 kb
Host smart-54f4643d-f0b1-4d81-88c9-5b15e4c3f450
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=31464388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_direc
t.31464388
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.1870160915
Short name T1002
Test name
Test status
Simulation time 20802808593 ps
CPU time 85.66 seconds
Started Jul 09 05:39:44 PM PDT 24
Finished Jul 09 05:41:11 PM PDT 24
Peak memory 232916 kb
Host smart-7fea846e-ff64-4f2e-8cbc-d301233cf5d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870160915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.1870160915
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.4246216169
Short name T580
Test name
Test status
Simulation time 483376064 ps
CPU time 5.16 seconds
Started Jul 09 05:39:35 PM PDT 24
Finished Jul 09 05:39:42 PM PDT 24
Peak memory 216280 kb
Host smart-8d08bf8f-e025-408a-8b01-ece303300025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246216169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.4246216169
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.680694840
Short name T359
Test name
Test status
Simulation time 1057128706 ps
CPU time 5.66 seconds
Started Jul 09 05:39:36 PM PDT 24
Finished Jul 09 05:39:44 PM PDT 24
Peak memory 216116 kb
Host smart-1c763389-4a2a-4477-a2c2-e01aeb713cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680694840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.680694840
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.3086784904
Short name T514
Test name
Test status
Simulation time 80974511 ps
CPU time 0.91 seconds
Started Jul 09 05:39:36 PM PDT 24
Finished Jul 09 05:39:39 PM PDT 24
Peak memory 206920 kb
Host smart-63fcfda8-cb07-4b53-87de-a2efe14a6a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086784904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.3086784904
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.2921413234
Short name T661
Test name
Test status
Simulation time 84604831 ps
CPU time 0.75 seconds
Started Jul 09 05:39:40 PM PDT 24
Finished Jul 09 05:39:42 PM PDT 24
Peak memory 205980 kb
Host smart-023a25ab-035a-4f63-8e56-1e44bcd93fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921413234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.2921413234
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.2682860172
Short name T541
Test name
Test status
Simulation time 27777290177 ps
CPU time 16.5 seconds
Started Jul 09 05:39:37 PM PDT 24
Finished Jul 09 05:39:55 PM PDT 24
Peak memory 232816 kb
Host smart-3f8f0f5b-1ea1-41e0-9c2d-89da4a2f1807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682860172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.2682860172
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.149749869
Short name T648
Test name
Test status
Simulation time 25131033 ps
CPU time 0.68 seconds
Started Jul 09 05:39:44 PM PDT 24
Finished Jul 09 05:39:46 PM PDT 24
Peak memory 205496 kb
Host smart-c9443519-68bc-4ef3-bd7d-3aba106fab70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149749869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.149749869
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.2301486303
Short name T496
Test name
Test status
Simulation time 5896369185 ps
CPU time 17.01 seconds
Started Jul 09 05:39:39 PM PDT 24
Finished Jul 09 05:39:57 PM PDT 24
Peak memory 224612 kb
Host smart-e1cea9ed-0c9c-4aee-9e1b-a107c15517d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301486303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.2301486303
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.1026424126
Short name T326
Test name
Test status
Simulation time 128095991 ps
CPU time 0.78 seconds
Started Jul 09 05:39:39 PM PDT 24
Finished Jul 09 05:39:40 PM PDT 24
Peak memory 205520 kb
Host smart-c2c7ab3e-4212-4c09-afd6-aef72f1f53ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026424126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.1026424126
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.1488952931
Short name T12
Test name
Test status
Simulation time 46956318002 ps
CPU time 156.53 seconds
Started Jul 09 05:39:39 PM PDT 24
Finished Jul 09 05:42:16 PM PDT 24
Peak memory 251248 kb
Host smart-8c51aea8-fea5-4e49-a4f9-c691299a8402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488952931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.1488952931
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.4180553448
Short name T864
Test name
Test status
Simulation time 18685939363 ps
CPU time 106.65 seconds
Started Jul 09 05:39:44 PM PDT 24
Finished Jul 09 05:41:32 PM PDT 24
Peak memory 249236 kb
Host smart-8eb60220-653d-4400-bcf8-e665e06051ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180553448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.4180553448
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.608665392
Short name T501
Test name
Test status
Simulation time 9776424053 ps
CPU time 97.93 seconds
Started Jul 09 05:39:44 PM PDT 24
Finished Jul 09 05:41:23 PM PDT 24
Peak memory 249300 kb
Host smart-c79af78d-fe90-420f-bb5f-82df06683a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608665392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idle
.608665392
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.3903246271
Short name T150
Test name
Test status
Simulation time 2653429415 ps
CPU time 35.01 seconds
Started Jul 09 05:39:46 PM PDT 24
Finished Jul 09 05:40:22 PM PDT 24
Peak memory 232720 kb
Host smart-f431bbbd-319e-482f-b54e-d5de9f9dd916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903246271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.3903246271
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.1678930180
Short name T515
Test name
Test status
Simulation time 19988722 ps
CPU time 0.76 seconds
Started Jul 09 05:39:48 PM PDT 24
Finished Jul 09 05:39:50 PM PDT 24
Peak memory 215776 kb
Host smart-db543688-2a3b-46b4-aedf-95f914473e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678930180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmd
s.1678930180
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.3679357149
Short name T203
Test name
Test status
Simulation time 2023583135 ps
CPU time 20.18 seconds
Started Jul 09 05:39:46 PM PDT 24
Finished Jul 09 05:40:07 PM PDT 24
Peak memory 224500 kb
Host smart-373ae672-93f4-4941-8970-5526e74bee71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679357149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.3679357149
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.2938213970
Short name T292
Test name
Test status
Simulation time 7492704007 ps
CPU time 15.25 seconds
Started Jul 09 05:39:44 PM PDT 24
Finished Jul 09 05:40:01 PM PDT 24
Peak memory 240816 kb
Host smart-39a834fa-f3b2-44c8-b22d-ce5465cdd367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938213970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.2938213970
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.2281048093
Short name T889
Test name
Test status
Simulation time 68324960 ps
CPU time 2.68 seconds
Started Jul 09 05:39:44 PM PDT 24
Finished Jul 09 05:39:48 PM PDT 24
Peak memory 232636 kb
Host smart-6c0dfb45-d75e-49dd-a6cf-d1e31f47c957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281048093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.2281048093
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.1338197218
Short name T751
Test name
Test status
Simulation time 970997347 ps
CPU time 4.73 seconds
Started Jul 09 05:39:40 PM PDT 24
Finished Jul 09 05:39:46 PM PDT 24
Peak memory 224440 kb
Host smart-e95ac950-5db8-485c-ad56-9dd49997f78c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338197218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.1338197218
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.985994130
Short name T874
Test name
Test status
Simulation time 1176937985 ps
CPU time 7.72 seconds
Started Jul 09 05:39:40 PM PDT 24
Finished Jul 09 05:39:49 PM PDT 24
Peak memory 222552 kb
Host smart-8b14fe84-1234-4c08-bd7d-921c60c95079
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=985994130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dire
ct.985994130
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.2957457205
Short name T958
Test name
Test status
Simulation time 2880432625 ps
CPU time 24.16 seconds
Started Jul 09 05:39:41 PM PDT 24
Finished Jul 09 05:40:06 PM PDT 24
Peak memory 216664 kb
Host smart-2dfdaee0-049d-4bcd-8d89-335f97179797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957457205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.2957457205
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.1808563551
Short name T341
Test name
Test status
Simulation time 3523069630 ps
CPU time 10.62 seconds
Started Jul 09 05:39:39 PM PDT 24
Finished Jul 09 05:39:50 PM PDT 24
Peak memory 216324 kb
Host smart-d2e21e52-5288-49af-8606-da7cca473580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808563551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.1808563551
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.2728533384
Short name T761
Test name
Test status
Simulation time 170549960 ps
CPU time 2.62 seconds
Started Jul 09 05:39:41 PM PDT 24
Finished Jul 09 05:39:44 PM PDT 24
Peak memory 216188 kb
Host smart-57995332-898f-4854-a2a9-a311903c40d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728533384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.2728533384
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.785537691
Short name T912
Test name
Test status
Simulation time 130665850 ps
CPU time 0.83 seconds
Started Jul 09 05:39:42 PM PDT 24
Finished Jul 09 05:39:44 PM PDT 24
Peak memory 205940 kb
Host smart-889fcfed-10e6-41ff-ad6c-10a527ecc45e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785537691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.785537691
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.1207693814
Short name T424
Test name
Test status
Simulation time 218535486 ps
CPU time 2.29 seconds
Started Jul 09 05:39:49 PM PDT 24
Finished Jul 09 05:39:53 PM PDT 24
Peak memory 224120 kb
Host smart-708b98f6-d950-47ae-b491-6183fd8188dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207693814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.1207693814
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.2558044802
Short name T764
Test name
Test status
Simulation time 35641880 ps
CPU time 0.71 seconds
Started Jul 09 05:39:51 PM PDT 24
Finished Jul 09 05:39:52 PM PDT 24
Peak memory 204972 kb
Host smart-03787565-8921-4c02-8b8f-4ae7541b6094
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558044802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
2558044802
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.890676325
Short name T511
Test name
Test status
Simulation time 2893121107 ps
CPU time 3.9 seconds
Started Jul 09 05:39:47 PM PDT 24
Finished Jul 09 05:39:52 PM PDT 24
Peak memory 232716 kb
Host smart-14fabfc8-a0e5-4023-a49c-a84c350eac64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890676325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.890676325
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.2927170261
Short name T343
Test name
Test status
Simulation time 18103020 ps
CPU time 0.82 seconds
Started Jul 09 05:39:41 PM PDT 24
Finished Jul 09 05:39:42 PM PDT 24
Peak memory 205548 kb
Host smart-9f28a5a0-0c02-4897-82e4-067e6dd147d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927170261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.2927170261
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.3100907632
Short name T838
Test name
Test status
Simulation time 1071982652 ps
CPU time 23.96 seconds
Started Jul 09 05:39:49 PM PDT 24
Finished Jul 09 05:40:14 PM PDT 24
Peak memory 250120 kb
Host smart-d89833ad-5887-49c0-a8d7-97163551625b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100907632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.3100907632
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.2836201063
Short name T231
Test name
Test status
Simulation time 3703625026 ps
CPU time 72.62 seconds
Started Jul 09 05:39:43 PM PDT 24
Finished Jul 09 05:40:56 PM PDT 24
Peak memory 254392 kb
Host smart-fa769de9-d48a-4ff2-8c94-a1c1e618bf28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836201063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.2836201063
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.2303272295
Short name T279
Test name
Test status
Simulation time 3588944637 ps
CPU time 39.65 seconds
Started Jul 09 05:39:54 PM PDT 24
Finished Jul 09 05:40:34 PM PDT 24
Peak memory 237864 kb
Host smart-abfa8dab-207a-4207-924c-aba4a1fe03d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303272295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.2303272295
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.1158654670
Short name T916
Test name
Test status
Simulation time 8218911903 ps
CPU time 29.54 seconds
Started Jul 09 05:39:44 PM PDT 24
Finished Jul 09 05:40:14 PM PDT 24
Peak memory 232820 kb
Host smart-810247ab-53cf-4b09-b964-2ea512cde719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158654670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.1158654670
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.1941392762
Short name T435
Test name
Test status
Simulation time 779940763 ps
CPU time 4.15 seconds
Started Jul 09 05:39:45 PM PDT 24
Finished Jul 09 05:39:51 PM PDT 24
Peak memory 224364 kb
Host smart-b29ee6fe-97cd-4f41-9608-f12f6fa70749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941392762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.1941392762
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.3896762242
Short name T321
Test name
Test status
Simulation time 91841011 ps
CPU time 3.62 seconds
Started Jul 09 05:39:48 PM PDT 24
Finished Jul 09 05:39:53 PM PDT 24
Peak memory 232580 kb
Host smart-ac0a797f-55ff-4583-84eb-759b37a41ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896762242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.3896762242
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.3334875017
Short name T986
Test name
Test status
Simulation time 896144589 ps
CPU time 2.9 seconds
Started Jul 09 05:39:52 PM PDT 24
Finished Jul 09 05:39:55 PM PDT 24
Peak memory 224452 kb
Host smart-5ffcd3e6-ff7e-42b6-ab98-5fc39c718ef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334875017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.3334875017
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.311417034
Short name T167
Test name
Test status
Simulation time 23919796360 ps
CPU time 30.31 seconds
Started Jul 09 05:39:45 PM PDT 24
Finished Jul 09 05:40:17 PM PDT 24
Peak memory 232760 kb
Host smart-26a36d30-d402-4254-aba5-54cc161845d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311417034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.311417034
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.3567440457
Short name T367
Test name
Test status
Simulation time 423889518 ps
CPU time 4.91 seconds
Started Jul 09 05:39:52 PM PDT 24
Finished Jul 09 05:39:58 PM PDT 24
Peak memory 220368 kb
Host smart-a090c85e-ecd4-4186-b979-92bcdb5c454f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3567440457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.3567440457
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.1169906613
Short name T933
Test name
Test status
Simulation time 1347642750 ps
CPU time 18.42 seconds
Started Jul 09 05:39:44 PM PDT 24
Finished Jul 09 05:40:03 PM PDT 24
Peak memory 216380 kb
Host smart-9642bcbb-f19a-401e-b395-28dbeee16c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169906613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.1169906613
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.949668832
Short name T821
Test name
Test status
Simulation time 1167320582 ps
CPU time 4.61 seconds
Started Jul 09 05:39:41 PM PDT 24
Finished Jul 09 05:39:46 PM PDT 24
Peak memory 216188 kb
Host smart-25bb7209-f846-43df-aff6-1c355a8456bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949668832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.949668832
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.688553172
Short name T856
Test name
Test status
Simulation time 108134892 ps
CPU time 1.41 seconds
Started Jul 09 05:39:46 PM PDT 24
Finished Jul 09 05:39:48 PM PDT 24
Peak memory 216212 kb
Host smart-4fbdc1e4-7e33-4e07-8e4a-5c718d399fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688553172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.688553172
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.560128126
Short name T858
Test name
Test status
Simulation time 51767436 ps
CPU time 0.94 seconds
Started Jul 09 05:39:40 PM PDT 24
Finished Jul 09 05:39:42 PM PDT 24
Peak memory 207048 kb
Host smart-abb380d8-1bca-4aa6-a627-c84cde10cd1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560128126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.560128126
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.1239852905
Short name T200
Test name
Test status
Simulation time 8986878530 ps
CPU time 12.13 seconds
Started Jul 09 05:39:51 PM PDT 24
Finished Jul 09 05:40:04 PM PDT 24
Peak memory 232832 kb
Host smart-e59db75f-9ee5-4d2e-8e84-172c57c9f94a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239852905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.1239852905
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.3115674381
Short name T758
Test name
Test status
Simulation time 32996316 ps
CPU time 0.69 seconds
Started Jul 09 05:40:02 PM PDT 24
Finished Jul 09 05:40:05 PM PDT 24
Peak memory 205852 kb
Host smart-dc3ebf0d-6cc2-4cf2-8749-2ec3689da0f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115674381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
3115674381
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.3940361204
Short name T690
Test name
Test status
Simulation time 819996735 ps
CPU time 9.1 seconds
Started Jul 09 05:40:01 PM PDT 24
Finished Jul 09 05:40:11 PM PDT 24
Peak memory 232712 kb
Host smart-dee12ccc-c859-4d6f-94f4-dce04f9c5791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940361204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.3940361204
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.2526489193
Short name T442
Test name
Test status
Simulation time 31590518 ps
CPU time 0.78 seconds
Started Jul 09 05:39:45 PM PDT 24
Finished Jul 09 05:39:47 PM PDT 24
Peak memory 205896 kb
Host smart-66cc94ed-bf4a-4d7b-bc25-e2415daa786c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526489193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.2526489193
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.2486633031
Short name T361
Test name
Test status
Simulation time 2674001629 ps
CPU time 24.46 seconds
Started Jul 09 05:39:51 PM PDT 24
Finished Jul 09 05:40:16 PM PDT 24
Peak memory 240992 kb
Host smart-621575d7-8423-4d21-abbd-f9a9101837b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486633031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.2486633031
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.4233989758
Short name T31
Test name
Test status
Simulation time 15311000966 ps
CPU time 163.62 seconds
Started Jul 09 05:39:49 PM PDT 24
Finished Jul 09 05:42:33 PM PDT 24
Peak memory 263788 kb
Host smart-4f8ffa8d-f9c6-468b-b30d-01fb6056f61a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233989758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.4233989758
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.3491672545
Short name T670
Test name
Test status
Simulation time 16875142251 ps
CPU time 58.21 seconds
Started Jul 09 05:39:51 PM PDT 24
Finished Jul 09 05:40:50 PM PDT 24
Peak memory 240400 kb
Host smart-f8f887a1-7122-4507-ba48-418156e08839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491672545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.3491672545
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.4059261030
Short name T213
Test name
Test status
Simulation time 8440314033 ps
CPU time 89.64 seconds
Started Jul 09 05:39:48 PM PDT 24
Finished Jul 09 05:41:18 PM PDT 24
Peak memory 264536 kb
Host smart-a6f4fc6d-f2b4-4180-95ee-3da83c8c8fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059261030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmd
s.4059261030
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.3104672255
Short name T1010
Test name
Test status
Simulation time 183718135 ps
CPU time 2.85 seconds
Started Jul 09 05:39:49 PM PDT 24
Finished Jul 09 05:39:52 PM PDT 24
Peak memory 224404 kb
Host smart-ecee5e43-f379-48a6-802c-cbf25273c8a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104672255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.3104672255
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.4235161691
Short name T379
Test name
Test status
Simulation time 190041540 ps
CPU time 3.1 seconds
Started Jul 09 05:39:59 PM PDT 24
Finished Jul 09 05:40:02 PM PDT 24
Peak memory 232684 kb
Host smart-6b512308-bca3-42af-a970-a1343db128f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235161691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.4235161691
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.3479837673
Short name T491
Test name
Test status
Simulation time 266438252 ps
CPU time 2.42 seconds
Started Jul 09 05:39:50 PM PDT 24
Finished Jul 09 05:39:53 PM PDT 24
Peak memory 224424 kb
Host smart-adb9c9a3-0567-4e14-9f56-185ad5a3a365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479837673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.3479837673
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.161301389
Short name T677
Test name
Test status
Simulation time 16711748544 ps
CPU time 11.79 seconds
Started Jul 09 05:39:44 PM PDT 24
Finished Jul 09 05:39:57 PM PDT 24
Peak memory 224608 kb
Host smart-6773f85e-e91a-4ec1-b876-d764373e3f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161301389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.161301389
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.394753490
Short name T773
Test name
Test status
Simulation time 539719080 ps
CPU time 4.57 seconds
Started Jul 09 05:39:49 PM PDT 24
Finished Jul 09 05:39:54 PM PDT 24
Peak memory 219220 kb
Host smart-543af00c-bc55-4cf0-9165-4f61f613352a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=394753490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dire
ct.394753490
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.53291162
Short name T992
Test name
Test status
Simulation time 69145693528 ps
CPU time 331.4 seconds
Started Jul 09 05:39:48 PM PDT 24
Finished Jul 09 05:45:20 PM PDT 24
Peak memory 265652 kb
Host smart-5338253f-17d7-44a1-9141-569b974ac2f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53291162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stress
_all.53291162
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.1263225574
Short name T548
Test name
Test status
Simulation time 18727653608 ps
CPU time 42.64 seconds
Started Jul 09 05:39:55 PM PDT 24
Finished Jul 09 05:40:38 PM PDT 24
Peak memory 216496 kb
Host smart-d4828bc8-dd5c-4987-9395-feff08ca1a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263225574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.1263225574
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.956276247
Short name T569
Test name
Test status
Simulation time 724146563 ps
CPU time 3.1 seconds
Started Jul 09 05:39:51 PM PDT 24
Finished Jul 09 05:39:55 PM PDT 24
Peak memory 216100 kb
Host smart-732012de-aa11-44df-81ba-5f90ab1cfa8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956276247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.956276247
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.1315590951
Short name T504
Test name
Test status
Simulation time 44845058 ps
CPU time 0.89 seconds
Started Jul 09 05:39:42 PM PDT 24
Finished Jul 09 05:39:44 PM PDT 24
Peak memory 206636 kb
Host smart-ae959c52-1078-4fdc-8d5b-ce168d51a838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315590951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.1315590951
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.3994039970
Short name T88
Test name
Test status
Simulation time 38286425 ps
CPU time 0.74 seconds
Started Jul 09 05:39:56 PM PDT 24
Finished Jul 09 05:39:58 PM PDT 24
Peak memory 205996 kb
Host smart-b79cc803-1dfe-4b8d-a331-2c03e80ab053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994039970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.3994039970
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.2442402004
Short name T554
Test name
Test status
Simulation time 684795152 ps
CPU time 5.18 seconds
Started Jul 09 05:39:58 PM PDT 24
Finished Jul 09 05:40:04 PM PDT 24
Peak memory 224436 kb
Host smart-54e00065-3cf5-42cf-a097-f70fcf7390e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442402004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.2442402004
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.910629870
Short name T808
Test name
Test status
Simulation time 15992060 ps
CPU time 0.79 seconds
Started Jul 09 05:39:59 PM PDT 24
Finished Jul 09 05:40:01 PM PDT 24
Peak memory 205488 kb
Host smart-af96db55-81f4-4035-b0b5-8772d91826f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910629870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.910629870
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.2671857176
Short name T566
Test name
Test status
Simulation time 628895458 ps
CPU time 6.68 seconds
Started Jul 09 05:39:49 PM PDT 24
Finished Jul 09 05:39:57 PM PDT 24
Peak memory 232588 kb
Host smart-40099054-43a3-43ae-89fe-0ec3c8138aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671857176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.2671857176
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.721487701
Short name T991
Test name
Test status
Simulation time 67365723 ps
CPU time 0.81 seconds
Started Jul 09 05:39:57 PM PDT 24
Finished Jul 09 05:39:58 PM PDT 24
Peak memory 206572 kb
Host smart-03312cf6-869f-4251-a241-5d191b287e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721487701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.721487701
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.4255443978
Short name T584
Test name
Test status
Simulation time 56872155111 ps
CPU time 122.92 seconds
Started Jul 09 05:39:49 PM PDT 24
Finished Jul 09 05:41:52 PM PDT 24
Peak memory 252424 kb
Host smart-065d64d3-fabb-4f53-ab3d-21b11e5c84ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255443978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.4255443978
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.1377228422
Short name T38
Test name
Test status
Simulation time 20877056166 ps
CPU time 83.06 seconds
Started Jul 09 05:39:55 PM PDT 24
Finished Jul 09 05:41:19 PM PDT 24
Peak memory 250612 kb
Host smart-c15625c5-0c0f-45ab-892c-f710709317b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377228422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.1377228422
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.1586416487
Short name T988
Test name
Test status
Simulation time 5137809953 ps
CPU time 43.25 seconds
Started Jul 09 05:39:51 PM PDT 24
Finished Jul 09 05:40:34 PM PDT 24
Peak memory 249212 kb
Host smart-6d6aafca-bc66-40e6-9e2c-40bb5b6de13a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586416487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.1586416487
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.1399221210
Short name T468
Test name
Test status
Simulation time 13820570004 ps
CPU time 50.33 seconds
Started Jul 09 05:39:54 PM PDT 24
Finished Jul 09 05:40:45 PM PDT 24
Peak memory 249220 kb
Host smart-10805c2d-b1a1-4598-84ff-37a3942f75dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399221210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmd
s.1399221210
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.511286925
Short name T283
Test name
Test status
Simulation time 160289926 ps
CPU time 3.67 seconds
Started Jul 09 05:39:52 PM PDT 24
Finished Jul 09 05:39:56 PM PDT 24
Peak memory 224404 kb
Host smart-2e639a04-1dc6-4711-9384-a91f208db2a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511286925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.511286925
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.2108611312
Short name T286
Test name
Test status
Simulation time 3805899531 ps
CPU time 16.89 seconds
Started Jul 09 05:39:57 PM PDT 24
Finished Jul 09 05:40:14 PM PDT 24
Peak memory 224576 kb
Host smart-06ee3845-f138-4488-9538-00c04e80606f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108611312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.2108611312
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.870031263
Short name T417
Test name
Test status
Simulation time 4143568278 ps
CPU time 16.41 seconds
Started Jul 09 05:39:58 PM PDT 24
Finished Jul 09 05:40:15 PM PDT 24
Peak memory 236812 kb
Host smart-e23822a7-80df-4bc7-9828-24b3680354ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870031263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swap
.870031263
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.106320543
Short name T575
Test name
Test status
Simulation time 239287341 ps
CPU time 2.08 seconds
Started Jul 09 05:39:51 PM PDT 24
Finished Jul 09 05:39:54 PM PDT 24
Peak memory 223016 kb
Host smart-127998c7-a5d6-416f-a52e-fd47ce93ee97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106320543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.106320543
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.1859703865
Short name T1012
Test name
Test status
Simulation time 724706077 ps
CPU time 10.23 seconds
Started Jul 09 05:39:47 PM PDT 24
Finished Jul 09 05:39:58 PM PDT 24
Peak memory 223180 kb
Host smart-44aecea7-cc0c-44bb-945d-f3cc6185faa1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1859703865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.1859703865
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.3538623040
Short name T162
Test name
Test status
Simulation time 143607079677 ps
CPU time 162.62 seconds
Started Jul 09 05:39:51 PM PDT 24
Finished Jul 09 05:42:34 PM PDT 24
Peak memory 255332 kb
Host smart-c698c223-4a52-4565-8727-5524e3ab5925
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538623040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.3538623040
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.2177523825
Short name T304
Test name
Test status
Simulation time 17370193314 ps
CPU time 20 seconds
Started Jul 09 05:39:58 PM PDT 24
Finished Jul 09 05:40:18 PM PDT 24
Peak memory 216368 kb
Host smart-6ce01a20-ddb3-4a9b-a9b1-0a36e9176fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177523825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.2177523825
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.2342381594
Short name T506
Test name
Test status
Simulation time 3397666593 ps
CPU time 2.79 seconds
Started Jul 09 05:39:57 PM PDT 24
Finished Jul 09 05:40:00 PM PDT 24
Peak memory 216236 kb
Host smart-0ed1a1aa-ec9e-41c3-8f2e-732a28dfab64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342381594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.2342381594
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.3320617806
Short name T685
Test name
Test status
Simulation time 226139391 ps
CPU time 1.9 seconds
Started Jul 09 05:39:54 PM PDT 24
Finished Jul 09 05:39:56 PM PDT 24
Peak memory 216264 kb
Host smart-88c48c1c-31fe-475c-a48e-c43f27773ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320617806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.3320617806
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.1845835442
Short name T608
Test name
Test status
Simulation time 78162025 ps
CPU time 0.79 seconds
Started Jul 09 05:39:57 PM PDT 24
Finished Jul 09 05:39:59 PM PDT 24
Peak memory 206008 kb
Host smart-462ba671-3639-467b-9efb-e5851a167ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845835442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.1845835442
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.2379224282
Short name T11
Test name
Test status
Simulation time 1496696064 ps
CPU time 2.53 seconds
Started Jul 09 05:39:56 PM PDT 24
Finished Jul 09 05:39:59 PM PDT 24
Peak memory 232620 kb
Host smart-97b2044e-15da-41b4-8576-719fba9362ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379224282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.2379224282
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.2992436681
Short name T349
Test name
Test status
Simulation time 45794535 ps
CPU time 0.76 seconds
Started Jul 09 05:40:03 PM PDT 24
Finished Jul 09 05:40:05 PM PDT 24
Peak memory 205516 kb
Host smart-3d47e38e-2705-4692-88e0-6e62b23bed99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992436681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
2992436681
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.1155390587
Short name T536
Test name
Test status
Simulation time 948941704 ps
CPU time 5.93 seconds
Started Jul 09 05:40:00 PM PDT 24
Finished Jul 09 05:40:06 PM PDT 24
Peak memory 232656 kb
Host smart-578653b6-820c-4a2e-a621-a52ebe182f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155390587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.1155390587
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.1511014693
Short name T878
Test name
Test status
Simulation time 16059850 ps
CPU time 0.75 seconds
Started Jul 09 05:39:58 PM PDT 24
Finished Jul 09 05:39:59 PM PDT 24
Peak memory 206564 kb
Host smart-2c7bffa2-51e2-4c16-92d0-6a4f03c8ba65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511014693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.1511014693
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.4014639046
Short name T247
Test name
Test status
Simulation time 10147917304 ps
CPU time 66.71 seconds
Started Jul 09 05:40:01 PM PDT 24
Finished Jul 09 05:41:08 PM PDT 24
Peak memory 266492 kb
Host smart-321625b3-bc6e-4a5b-bdee-5acc7c7f88f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014639046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.4014639046
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.483245787
Short name T382
Test name
Test status
Simulation time 31539035784 ps
CPU time 301.16 seconds
Started Jul 09 05:39:58 PM PDT 24
Finished Jul 09 05:44:59 PM PDT 24
Peak memory 256624 kb
Host smart-6e655631-c221-49ce-8e10-ba6573f3e102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483245787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.483245787
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.1172467289
Short name T240
Test name
Test status
Simulation time 5901725582 ps
CPU time 81.14 seconds
Started Jul 09 05:39:53 PM PDT 24
Finished Jul 09 05:41:14 PM PDT 24
Peak memory 265976 kb
Host smart-896e9243-d9fb-4db4-8650-df5d6f0af763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172467289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.1172467289
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.809662041
Short name T899
Test name
Test status
Simulation time 386571621 ps
CPU time 5.1 seconds
Started Jul 09 05:39:49 PM PDT 24
Finished Jul 09 05:39:55 PM PDT 24
Peak memory 238240 kb
Host smart-bda229fc-d7f9-4bfa-bca3-db9dcd96ad0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809662041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.809662041
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.36751176
Short name T959
Test name
Test status
Simulation time 1377737614 ps
CPU time 11.54 seconds
Started Jul 09 05:40:06 PM PDT 24
Finished Jul 09 05:40:20 PM PDT 24
Peak memory 232636 kb
Host smart-d0646ce3-2e93-45bc-ba67-438e40a69877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36751176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.36751176
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.1986726116
Short name T833
Test name
Test status
Simulation time 2483492254 ps
CPU time 19.53 seconds
Started Jul 09 05:40:02 PM PDT 24
Finished Jul 09 05:40:22 PM PDT 24
Peak memory 238408 kb
Host smart-a7c1677c-157e-4dc5-ae19-bb0e69360026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986726116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.1986726116
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.3304532756
Short name T480
Test name
Test status
Simulation time 843125366 ps
CPU time 2.67 seconds
Started Jul 09 05:39:59 PM PDT 24
Finished Jul 09 05:40:02 PM PDT 24
Peak memory 224476 kb
Host smart-8eb6263b-3385-4345-8cc3-0ed02cedd7b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304532756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.3304532756
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.2321659982
Short name T478
Test name
Test status
Simulation time 442638961 ps
CPU time 7.32 seconds
Started Jul 09 05:39:49 PM PDT 24
Finished Jul 09 05:39:57 PM PDT 24
Peak memory 238020 kb
Host smart-bb872b74-9a31-4b67-9a33-a3b76bc8ce80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321659982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.2321659982
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.1305057486
Short name T965
Test name
Test status
Simulation time 660383589 ps
CPU time 8.02 seconds
Started Jul 09 05:39:57 PM PDT 24
Finished Jul 09 05:40:06 PM PDT 24
Peak memory 218736 kb
Host smart-e3bbb4eb-3e22-4e18-a44b-6c23fa17cd1a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1305057486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.1305057486
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.1181078377
Short name T250
Test name
Test status
Simulation time 35480825716 ps
CPU time 314.19 seconds
Started Jul 09 05:40:03 PM PDT 24
Finished Jul 09 05:45:19 PM PDT 24
Peak memory 251692 kb
Host smart-66835576-11eb-40a4-b351-0c718aba773c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181078377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.1181078377
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.1401094859
Short name T455
Test name
Test status
Simulation time 3057373533 ps
CPU time 16.95 seconds
Started Jul 09 05:40:01 PM PDT 24
Finished Jul 09 05:40:19 PM PDT 24
Peak memory 216292 kb
Host smart-b86fb98f-e307-4c08-a0c0-45d7586416ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401094859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.1401094859
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.3764732951
Short name T978
Test name
Test status
Simulation time 6690950902 ps
CPU time 16.17 seconds
Started Jul 09 05:40:00 PM PDT 24
Finished Jul 09 05:40:17 PM PDT 24
Peak memory 216348 kb
Host smart-904c4a80-b665-4fd5-97e7-82431dce836e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764732951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.3764732951
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.1922050419
Short name T340
Test name
Test status
Simulation time 51019114 ps
CPU time 0.81 seconds
Started Jul 09 05:40:00 PM PDT 24
Finished Jul 09 05:40:02 PM PDT 24
Peak memory 205972 kb
Host smart-22376b57-c1c0-4d10-a4da-96e4d821e6d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922050419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.1922050419
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.647053653
Short name T769
Test name
Test status
Simulation time 318613447 ps
CPU time 0.77 seconds
Started Jul 09 05:40:01 PM PDT 24
Finished Jul 09 05:40:03 PM PDT 24
Peak memory 205972 kb
Host smart-7da00fc4-9473-4140-a1a8-0422224ec9c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647053653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.647053653
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.2155011206
Short name T810
Test name
Test status
Simulation time 8807431256 ps
CPU time 9.85 seconds
Started Jul 09 05:39:59 PM PDT 24
Finished Jul 09 05:40:09 PM PDT 24
Peak memory 224508 kb
Host smart-7a164f6c-ec0d-42f6-9824-29ebf8fa81fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155011206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.2155011206
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.3392150071
Short name T333
Test name
Test status
Simulation time 14215659 ps
CPU time 0.76 seconds
Started Jul 09 05:38:47 PM PDT 24
Finished Jul 09 05:38:50 PM PDT 24
Peak memory 204900 kb
Host smart-59482d07-c05b-42a8-9c26-7569b160f0af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392150071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.3
392150071
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.1652675880
Short name T652
Test name
Test status
Simulation time 537179745 ps
CPU time 2.53 seconds
Started Jul 09 05:38:44 PM PDT 24
Finished Jul 09 05:38:47 PM PDT 24
Peak memory 224452 kb
Host smart-54148c1e-d4af-46db-8597-e84195dad8d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652675880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.1652675880
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.1250266978
Short name T57
Test name
Test status
Simulation time 17110659 ps
CPU time 0.82 seconds
Started Jul 09 05:38:47 PM PDT 24
Finished Jul 09 05:38:51 PM PDT 24
Peak memory 205520 kb
Host smart-048d27d8-b296-4d34-94d6-b95a9d01f27e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250266978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.1250266978
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.493004673
Short name T983
Test name
Test status
Simulation time 22715856799 ps
CPU time 75.8 seconds
Started Jul 09 05:38:49 PM PDT 24
Finished Jul 09 05:40:08 PM PDT 24
Peak memory 249196 kb
Host smart-deb4d4c8-9cc2-4dbb-9714-75fc3a9e8324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493004673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.493004673
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.4178331715
Short name T499
Test name
Test status
Simulation time 4788268492 ps
CPU time 58.4 seconds
Started Jul 09 05:38:46 PM PDT 24
Finished Jul 09 05:39:46 PM PDT 24
Peak memory 249276 kb
Host smart-e4fddaa0-2425-44ed-b83a-a27bd0cb6fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178331715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.4178331715
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.1437403505
Short name T735
Test name
Test status
Simulation time 2956468319 ps
CPU time 58.03 seconds
Started Jul 09 05:38:47 PM PDT 24
Finished Jul 09 05:39:47 PM PDT 24
Peak memory 250428 kb
Host smart-29e1f381-c2cd-4872-8fdf-cc19fe40fe15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437403505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.1437403505
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.3486288795
Short name T820
Test name
Test status
Simulation time 39942145 ps
CPU time 2.96 seconds
Started Jul 09 05:38:45 PM PDT 24
Finished Jul 09 05:38:49 PM PDT 24
Peak memory 232684 kb
Host smart-c1b3a844-8901-4578-ad96-8e820c3802d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486288795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.3486288795
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.3223866218
Short name T546
Test name
Test status
Simulation time 59594843424 ps
CPU time 125.01 seconds
Started Jul 09 05:38:48 PM PDT 24
Finished Jul 09 05:40:56 PM PDT 24
Peak memory 250300 kb
Host smart-fd007af5-0be9-4072-b3a6-ceb1de1818c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223866218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds
.3223866218
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.1783068459
Short name T174
Test name
Test status
Simulation time 1853148458 ps
CPU time 3.97 seconds
Started Jul 09 05:38:44 PM PDT 24
Finished Jul 09 05:38:49 PM PDT 24
Peak memory 232684 kb
Host smart-c5595a37-210a-4919-bc38-1c5d2b435470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783068459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.1783068459
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.2513551969
Short name T269
Test name
Test status
Simulation time 1325285775 ps
CPU time 8.82 seconds
Started Jul 09 05:38:46 PM PDT 24
Finished Jul 09 05:38:57 PM PDT 24
Peak memory 224424 kb
Host smart-efcd9098-8437-4982-8832-e29adc9f72dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513551969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.2513551969
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.802183441
Short name T852
Test name
Test status
Simulation time 2001430691 ps
CPU time 9.96 seconds
Started Jul 09 05:38:47 PM PDT 24
Finished Jul 09 05:38:59 PM PDT 24
Peak memory 232644 kb
Host smart-81020e38-3aa2-43cf-83d5-ebd3a6810c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802183441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap.
802183441
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.1782426419
Short name T723
Test name
Test status
Simulation time 23183323511 ps
CPU time 12.4 seconds
Started Jul 09 05:38:37 PM PDT 24
Finished Jul 09 05:38:50 PM PDT 24
Peak memory 232756 kb
Host smart-11d7a753-b2df-45f5-8e1d-a322e4f0374b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782426419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.1782426419
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.1966990579
Short name T396
Test name
Test status
Simulation time 493227968 ps
CPU time 7.72 seconds
Started Jul 09 05:38:48 PM PDT 24
Finished Jul 09 05:38:59 PM PDT 24
Peak memory 223216 kb
Host smart-ea75950c-78f3-4609-b4c8-738bb07cd807
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1966990579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.1966990579
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.2785435306
Short name T72
Test name
Test status
Simulation time 332176315 ps
CPU time 1.19 seconds
Started Jul 09 05:38:47 PM PDT 24
Finished Jul 09 05:38:51 PM PDT 24
Peak memory 237632 kb
Host smart-828d96ea-f953-469e-9f6b-7871069415c2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785435306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.2785435306
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.1911842957
Short name T818
Test name
Test status
Simulation time 78553899 ps
CPU time 1.28 seconds
Started Jul 09 05:38:45 PM PDT 24
Finished Jul 09 05:38:48 PM PDT 24
Peak memory 207088 kb
Host smart-956c30d8-0ae3-42c3-adbe-2ca0c2b0d642
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911842957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.1911842957
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.1449484877
Short name T579
Test name
Test status
Simulation time 2247836449 ps
CPU time 21.64 seconds
Started Jul 09 05:38:48 PM PDT 24
Finished Jul 09 05:39:13 PM PDT 24
Peak memory 216640 kb
Host smart-862e035f-0d5c-4748-932b-74de57069566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449484877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.1449484877
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.226898659
Short name T364
Test name
Test status
Simulation time 7273391735 ps
CPU time 10.29 seconds
Started Jul 09 05:38:45 PM PDT 24
Finished Jul 09 05:38:57 PM PDT 24
Peak memory 216320 kb
Host smart-14f4f8fd-946e-4c98-be66-7cf2aa611665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226898659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.226898659
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.3601618908
Short name T544
Test name
Test status
Simulation time 181716541 ps
CPU time 1.64 seconds
Started Jul 09 05:38:36 PM PDT 24
Finished Jul 09 05:38:39 PM PDT 24
Peak memory 216184 kb
Host smart-03461818-326d-44e6-9138-717e11b51b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601618908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.3601618908
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.1673292114
Short name T777
Test name
Test status
Simulation time 30828617 ps
CPU time 0.83 seconds
Started Jul 09 05:38:48 PM PDT 24
Finished Jul 09 05:38:51 PM PDT 24
Peak memory 205948 kb
Host smart-3c12215e-afbd-4f2f-983e-db79a9b20b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673292114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.1673292114
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.373798153
Short name T643
Test name
Test status
Simulation time 3073383768 ps
CPU time 11.8 seconds
Started Jul 09 05:38:45 PM PDT 24
Finished Jul 09 05:38:59 PM PDT 24
Peak memory 237580 kb
Host smart-29a6097b-39b3-49c1-b7db-08b7fa8266b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373798153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.373798153
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.64829698
Short name T327
Test name
Test status
Simulation time 13258673 ps
CPU time 0.74 seconds
Started Jul 09 05:40:02 PM PDT 24
Finished Jul 09 05:40:05 PM PDT 24
Peak memory 204892 kb
Host smart-0241a1e9-c7a4-4505-b7c2-5588f7c4ae1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64829698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.64829698
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.1921126178
Short name T36
Test name
Test status
Simulation time 340912750 ps
CPU time 5.83 seconds
Started Jul 09 05:40:04 PM PDT 24
Finished Jul 09 05:40:12 PM PDT 24
Peak memory 224376 kb
Host smart-c0571d67-ba5e-49ec-a0ba-085da0a84095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921126178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.1921126178
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.3213479843
Short name T969
Test name
Test status
Simulation time 166382432 ps
CPU time 0.8 seconds
Started Jul 09 05:40:02 PM PDT 24
Finished Jul 09 05:40:04 PM PDT 24
Peak memory 206884 kb
Host smart-06ef13cd-ed20-4c28-9b47-0e4094c56de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213479843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.3213479843
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.3087768016
Short name T742
Test name
Test status
Simulation time 4492520617 ps
CPU time 44.79 seconds
Started Jul 09 05:40:08 PM PDT 24
Finished Jul 09 05:40:55 PM PDT 24
Peak memory 249208 kb
Host smart-a1a7aaa1-6ec0-4e99-8721-6530a81ac585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087768016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.3087768016
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.3427786455
Short name T1007
Test name
Test status
Simulation time 2166761644 ps
CPU time 21.8 seconds
Started Jul 09 05:40:05 PM PDT 24
Finished Jul 09 05:40:29 PM PDT 24
Peak memory 217484 kb
Host smart-34d1226c-ee0d-4125-aea0-18a6241204c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427786455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.3427786455
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.4181095104
Short name T949
Test name
Test status
Simulation time 22478628102 ps
CPU time 215.6 seconds
Started Jul 09 05:40:00 PM PDT 24
Finished Jul 09 05:43:36 PM PDT 24
Peak memory 253596 kb
Host smart-732b19da-8080-4b18-93c3-7040291bc63e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181095104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.4181095104
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.261224618
Short name T994
Test name
Test status
Simulation time 1220072489 ps
CPU time 11.98 seconds
Started Jul 09 05:39:55 PM PDT 24
Finished Jul 09 05:40:08 PM PDT 24
Peak memory 233512 kb
Host smart-b1d6ec58-b489-4427-b268-361f613322c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261224618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.261224618
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.343849786
Short name T531
Test name
Test status
Simulation time 2499875692 ps
CPU time 32.07 seconds
Started Jul 09 05:39:59 PM PDT 24
Finished Jul 09 05:40:32 PM PDT 24
Peak memory 250164 kb
Host smart-2d96b31a-f3a2-46d0-93aa-a8053d7f01c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343849786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmds
.343849786
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.1522341392
Short name T581
Test name
Test status
Simulation time 526047681 ps
CPU time 6.93 seconds
Started Jul 09 05:40:00 PM PDT 24
Finished Jul 09 05:40:08 PM PDT 24
Peak memory 232664 kb
Host smart-425a8c05-b2f3-4c3b-89ef-cb5b7b2e7e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522341392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.1522341392
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.2927643344
Short name T674
Test name
Test status
Simulation time 14586982331 ps
CPU time 57.55 seconds
Started Jul 09 05:39:58 PM PDT 24
Finished Jul 09 05:40:56 PM PDT 24
Peak memory 232784 kb
Host smart-30afe84c-02ff-4e45-86fe-2fad7d978432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927643344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.2927643344
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.1558439552
Short name T186
Test name
Test status
Simulation time 990063347 ps
CPU time 4.78 seconds
Started Jul 09 05:40:01 PM PDT 24
Finished Jul 09 05:40:07 PM PDT 24
Peak memory 232644 kb
Host smart-af0bf8e7-7a6c-4c3e-9487-c195c6f0ea66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558439552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.1558439552
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.2442432306
Short name T190
Test name
Test status
Simulation time 13611858007 ps
CPU time 9.58 seconds
Started Jul 09 05:39:54 PM PDT 24
Finished Jul 09 05:40:04 PM PDT 24
Peak memory 235044 kb
Host smart-c79799e4-fdb6-422a-93da-7f3835553bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442432306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.2442432306
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.3386936741
Short name T41
Test name
Test status
Simulation time 93513064 ps
CPU time 3.83 seconds
Started Jul 09 05:40:02 PM PDT 24
Finished Jul 09 05:40:08 PM PDT 24
Peak memory 222564 kb
Host smart-0822edee-76b5-479c-a1fc-5dc1d4750044
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3386936741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.3386936741
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.3901415676
Short name T962
Test name
Test status
Simulation time 210843708 ps
CPU time 1.11 seconds
Started Jul 09 05:40:02 PM PDT 24
Finished Jul 09 05:40:05 PM PDT 24
Peak memory 206884 kb
Host smart-6b1071eb-6553-47ee-a756-adab2ee1f63c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901415676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.3901415676
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.2568193568
Short name T800
Test name
Test status
Simulation time 6199951273 ps
CPU time 18.87 seconds
Started Jul 09 05:39:53 PM PDT 24
Finished Jul 09 05:40:12 PM PDT 24
Peak memory 216636 kb
Host smart-cf71dc44-1e3c-4d57-933c-db47ca1f901d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568193568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.2568193568
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.3504385520
Short name T395
Test name
Test status
Simulation time 597436980 ps
CPU time 3.03 seconds
Started Jul 09 05:40:02 PM PDT 24
Finished Jul 09 05:40:07 PM PDT 24
Peak memory 216268 kb
Host smart-ec26eeb9-44bd-413f-b6bf-abb7ff1a7270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504385520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.3504385520
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.2508334280
Short name T353
Test name
Test status
Simulation time 141414145 ps
CPU time 1.37 seconds
Started Jul 09 05:40:02 PM PDT 24
Finished Jul 09 05:40:04 PM PDT 24
Peak memory 216160 kb
Host smart-5e6b95dd-cb03-4e0e-8cae-169e01920517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508334280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.2508334280
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.2649256385
Short name T956
Test name
Test status
Simulation time 200478780 ps
CPU time 0.89 seconds
Started Jul 09 05:39:55 PM PDT 24
Finished Jul 09 05:39:57 PM PDT 24
Peak memory 205844 kb
Host smart-4ff8b36a-69f4-4981-834c-ee1c987be1e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649256385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.2649256385
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.1933455237
Short name T650
Test name
Test status
Simulation time 116849375 ps
CPU time 2.5 seconds
Started Jul 09 05:39:53 PM PDT 24
Finished Jul 09 05:39:56 PM PDT 24
Peak memory 224456 kb
Host smart-c7b1785f-3d3e-461b-9556-10528cf87105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933455237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.1933455237
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.4152332031
Short name T935
Test name
Test status
Simulation time 22824990 ps
CPU time 0.72 seconds
Started Jul 09 05:40:01 PM PDT 24
Finished Jul 09 05:40:03 PM PDT 24
Peak memory 205880 kb
Host smart-60fb1f99-76f4-4581-96c0-4fc0c3691ce7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152332031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
4152332031
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.3377557989
Short name T533
Test name
Test status
Simulation time 393969277 ps
CPU time 5.31 seconds
Started Jul 09 05:40:03 PM PDT 24
Finished Jul 09 05:40:11 PM PDT 24
Peak memory 224352 kb
Host smart-8e98ecf7-d5bf-4ae7-bf64-2d2798db26f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377557989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.3377557989
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.1027906008
Short name T458
Test name
Test status
Simulation time 50270169 ps
CPU time 0.88 seconds
Started Jul 09 05:40:02 PM PDT 24
Finished Jul 09 05:40:05 PM PDT 24
Peak memory 206868 kb
Host smart-37895a83-ba70-4ed2-b129-cfef892e101a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027906008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.1027906008
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.2314201477
Short name T474
Test name
Test status
Simulation time 23709111051 ps
CPU time 40.32 seconds
Started Jul 09 05:40:01 PM PDT 24
Finished Jul 09 05:40:42 PM PDT 24
Peak memory 241004 kb
Host smart-53c8b0e7-e03e-4c59-b9e4-925fc8bfc97f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314201477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.2314201477
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.3917095335
Short name T274
Test name
Test status
Simulation time 60346942028 ps
CPU time 133.62 seconds
Started Jul 09 05:40:01 PM PDT 24
Finished Jul 09 05:42:16 PM PDT 24
Peak memory 257408 kb
Host smart-23d34a10-bfa1-455c-a0ec-8628ffa7ae45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917095335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.3917095335
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.1509401661
Short name T599
Test name
Test status
Simulation time 9410398647 ps
CPU time 101.28 seconds
Started Jul 09 05:40:04 PM PDT 24
Finished Jul 09 05:41:48 PM PDT 24
Peak memory 253228 kb
Host smart-c07f8241-9170-49e9-861a-529cc8846832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509401661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.1509401661
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.191691887
Short name T843
Test name
Test status
Simulation time 3517341094 ps
CPU time 33.79 seconds
Started Jul 09 05:40:04 PM PDT 24
Finished Jul 09 05:40:40 PM PDT 24
Peak memory 235724 kb
Host smart-4c39e01f-2c80-4cbf-a766-73c005f80a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191691887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.191691887
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.151078517
Short name T89
Test name
Test status
Simulation time 7706897527 ps
CPU time 47.65 seconds
Started Jul 09 05:40:03 PM PDT 24
Finished Jul 09 05:40:52 PM PDT 24
Peak memory 249168 kb
Host smart-a5e9e517-d3a8-4593-9005-ced80cb7067a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151078517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmds
.151078517
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.3184403809
Short name T277
Test name
Test status
Simulation time 1033111284 ps
CPU time 8.93 seconds
Started Jul 09 05:40:03 PM PDT 24
Finished Jul 09 05:40:14 PM PDT 24
Peak memory 224432 kb
Host smart-cccf7e3f-10c6-43f3-a6cb-feb436c416fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184403809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.3184403809
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.4147973610
Short name T273
Test name
Test status
Simulation time 2356154562 ps
CPU time 15.74 seconds
Started Jul 09 05:40:03 PM PDT 24
Finished Jul 09 05:40:21 PM PDT 24
Peak memory 233748 kb
Host smart-477d9635-1350-467b-aab8-c62e80a51080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147973610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.4147973610
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.2668030696
Short name T954
Test name
Test status
Simulation time 633506646 ps
CPU time 4.99 seconds
Started Jul 09 05:39:59 PM PDT 24
Finished Jul 09 05:40:05 PM PDT 24
Peak memory 224488 kb
Host smart-5dad310f-dc43-4ea0-897d-a10047f1b0d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668030696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.2668030696
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.2482729925
Short name T413
Test name
Test status
Simulation time 58453038 ps
CPU time 2.56 seconds
Started Jul 09 05:39:58 PM PDT 24
Finished Jul 09 05:40:01 PM PDT 24
Peak memory 232660 kb
Host smart-8e584a43-3d67-4421-83c2-267da308e47c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482729925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.2482729925
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.950461347
Short name T588
Test name
Test status
Simulation time 1491813273 ps
CPU time 4.45 seconds
Started Jul 09 05:39:57 PM PDT 24
Finished Jul 09 05:40:02 PM PDT 24
Peak memory 219980 kb
Host smart-5d1325d9-a99b-46be-ba98-a2880455867e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=950461347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dire
ct.950461347
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.2928203369
Short name T720
Test name
Test status
Simulation time 237501438 ps
CPU time 1.05 seconds
Started Jul 09 05:39:59 PM PDT 24
Finished Jul 09 05:40:01 PM PDT 24
Peak memory 207728 kb
Host smart-d83d68b4-53ae-490d-8fef-e6b6ca4c9706
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928203369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.2928203369
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.943595931
Short name T814
Test name
Test status
Simulation time 59940559814 ps
CPU time 30.48 seconds
Started Jul 09 05:39:57 PM PDT 24
Finished Jul 09 05:40:28 PM PDT 24
Peak memory 216464 kb
Host smart-95edd5ea-a4dd-4e69-9cff-9247d9c649f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943595931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.943595931
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.2717463565
Short name T625
Test name
Test status
Simulation time 258691468 ps
CPU time 2.41 seconds
Started Jul 09 05:40:07 PM PDT 24
Finished Jul 09 05:40:11 PM PDT 24
Peak memory 216200 kb
Host smart-65ec0eb2-c1ee-4067-8a36-3cafedf554c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717463565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.2717463565
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.3037235314
Short name T392
Test name
Test status
Simulation time 47581666 ps
CPU time 1.17 seconds
Started Jul 09 05:40:02 PM PDT 24
Finished Jul 09 05:40:05 PM PDT 24
Peak memory 207428 kb
Host smart-70589177-e60d-4cb9-80b1-999d3b3ab393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037235314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.3037235314
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.1146347141
Short name T767
Test name
Test status
Simulation time 128061301 ps
CPU time 0.85 seconds
Started Jul 09 05:39:59 PM PDT 24
Finished Jul 09 05:40:01 PM PDT 24
Peak memory 205924 kb
Host smart-6c94fecd-8dd8-4e2e-9e6a-21354116875a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146347141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.1146347141
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.4012621465
Short name T136
Test name
Test status
Simulation time 82443297907 ps
CPU time 27.12 seconds
Started Jul 09 05:40:03 PM PDT 24
Finished Jul 09 05:40:32 PM PDT 24
Peak memory 240908 kb
Host smart-f358625b-81d3-4d1d-b574-95afcfd89d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012621465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.4012621465
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.4265866146
Short name T963
Test name
Test status
Simulation time 46365334 ps
CPU time 0.79 seconds
Started Jul 09 05:40:02 PM PDT 24
Finished Jul 09 05:40:04 PM PDT 24
Peak memory 205828 kb
Host smart-2d9ba6f7-d323-465f-a9fd-30b38fe38213
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265866146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
4265866146
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.2156906330
Short name T861
Test name
Test status
Simulation time 121130161 ps
CPU time 2.4 seconds
Started Jul 09 05:40:02 PM PDT 24
Finished Jul 09 05:40:06 PM PDT 24
Peak memory 232620 kb
Host smart-6dc62b15-6b25-4f7e-9895-b5ba8df14b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156906330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.2156906330
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.2893522543
Short name T320
Test name
Test status
Simulation time 46462311 ps
CPU time 0.81 seconds
Started Jul 09 05:40:00 PM PDT 24
Finished Jul 09 05:40:02 PM PDT 24
Peak memory 206936 kb
Host smart-48e533d8-c47b-4ab7-ae01-39e36ee3f8f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893522543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.2893522543
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.3114808899
Short name T268
Test name
Test status
Simulation time 19675234467 ps
CPU time 154.92 seconds
Started Jul 09 05:40:05 PM PDT 24
Finished Jul 09 05:42:42 PM PDT 24
Peak memory 251876 kb
Host smart-91fb9e17-29ed-4548-9d17-fb58d06d55da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114808899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.3114808899
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.305974967
Short name T421
Test name
Test status
Simulation time 5138225009 ps
CPU time 80.71 seconds
Started Jul 09 05:40:04 PM PDT 24
Finished Jul 09 05:41:27 PM PDT 24
Peak memory 257380 kb
Host smart-d6f54c2b-3f74-4252-82f4-4448f2ab7e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305974967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.305974967
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.829929919
Short name T509
Test name
Test status
Simulation time 14771482666 ps
CPU time 12.61 seconds
Started Jul 09 05:40:02 PM PDT 24
Finished Jul 09 05:40:17 PM PDT 24
Peak memory 217836 kb
Host smart-58cd9156-3af3-44c7-ac54-332ad2ffbac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829929919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idle
.829929919
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.3915638295
Short name T399
Test name
Test status
Simulation time 544003281 ps
CPU time 3.76 seconds
Started Jul 09 05:39:57 PM PDT 24
Finished Jul 09 05:40:02 PM PDT 24
Peak memory 224516 kb
Host smart-fc137bf6-4a8a-43f7-bd94-2e5d3e00f83c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915638295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.3915638295
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.135786635
Short name T924
Test name
Test status
Simulation time 4160865898 ps
CPU time 55.26 seconds
Started Jul 09 05:40:04 PM PDT 24
Finished Jul 09 05:41:02 PM PDT 24
Peak memory 249208 kb
Host smart-1c9f6642-f23d-4f95-912c-eefcf0b24835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135786635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmds
.135786635
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.4257948167
Short name T291
Test name
Test status
Simulation time 4253520175 ps
CPU time 17.18 seconds
Started Jul 09 05:40:00 PM PDT 24
Finished Jul 09 05:40:18 PM PDT 24
Peak memory 224564 kb
Host smart-5e134511-79c2-48a6-8644-220d8d2a9d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257948167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.4257948167
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.2112463288
Short name T558
Test name
Test status
Simulation time 28846979593 ps
CPU time 54.89 seconds
Started Jul 09 05:40:02 PM PDT 24
Finished Jul 09 05:40:59 PM PDT 24
Peak memory 232768 kb
Host smart-1f93110a-d9dd-47fe-bdc4-64dbd711b2e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112463288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.2112463288
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.630376437
Short name T985
Test name
Test status
Simulation time 3560633406 ps
CPU time 12.72 seconds
Started Jul 09 05:40:07 PM PDT 24
Finished Jul 09 05:40:22 PM PDT 24
Peak memory 232772 kb
Host smart-b65b0d4a-d9b2-4661-94ae-ef306a365874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630376437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swap
.630376437
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.1227044405
Short name T285
Test name
Test status
Simulation time 187066977 ps
CPU time 2.52 seconds
Started Jul 09 05:40:04 PM PDT 24
Finished Jul 09 05:40:09 PM PDT 24
Peak memory 232664 kb
Host smart-ddfc65b8-2044-46ac-b9a7-148486469db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227044405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.1227044405
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.2528011546
Short name T427
Test name
Test status
Simulation time 800773204 ps
CPU time 3.49 seconds
Started Jul 09 05:40:02 PM PDT 24
Finished Jul 09 05:40:07 PM PDT 24
Peak memory 221588 kb
Host smart-8ec04901-574c-48bc-9789-6455d52abebf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2528011546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.2528011546
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.1001627829
Short name T80
Test name
Test status
Simulation time 5388224142 ps
CPU time 46.62 seconds
Started Jul 09 05:40:04 PM PDT 24
Finished Jul 09 05:40:53 PM PDT 24
Peak memory 238128 kb
Host smart-64d10139-0d52-46b4-b61d-22bc6cb7c8ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001627829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.1001627829
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.667117840
Short name T871
Test name
Test status
Simulation time 11422121882 ps
CPU time 34.9 seconds
Started Jul 09 05:40:02 PM PDT 24
Finished Jul 09 05:40:39 PM PDT 24
Peak memory 220392 kb
Host smart-074bdbd6-f185-43f6-9281-948a4b40daed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667117840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.667117840
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.2963984182
Short name T665
Test name
Test status
Simulation time 2582746744 ps
CPU time 6.39 seconds
Started Jul 09 05:40:01 PM PDT 24
Finished Jul 09 05:40:09 PM PDT 24
Peak memory 216304 kb
Host smart-f0bc8669-e804-4579-bfb7-c19be471675c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963984182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.2963984182
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.1857860713
Short name T951
Test name
Test status
Simulation time 44317096 ps
CPU time 2.4 seconds
Started Jul 09 05:40:02 PM PDT 24
Finished Jul 09 05:40:05 PM PDT 24
Peak memory 216176 kb
Host smart-326ad1eb-c6a2-4820-a89f-00b4952ec54f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857860713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.1857860713
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.3543187509
Short name T329
Test name
Test status
Simulation time 40248926 ps
CPU time 0.81 seconds
Started Jul 09 05:40:04 PM PDT 24
Finished Jul 09 05:40:07 PM PDT 24
Peak memory 205976 kb
Host smart-7f0cb248-6d45-4d8d-a524-e357ac031c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543187509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.3543187509
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.2474753627
Short name T498
Test name
Test status
Simulation time 286121125 ps
CPU time 2.69 seconds
Started Jul 09 05:40:01 PM PDT 24
Finished Jul 09 05:40:05 PM PDT 24
Peak memory 232692 kb
Host smart-111c73dc-cfb4-45c7-acca-d03aebba2e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474753627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.2474753627
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.2496845495
Short name T444
Test name
Test status
Simulation time 23678414 ps
CPU time 0.71 seconds
Started Jul 09 05:40:08 PM PDT 24
Finished Jul 09 05:40:11 PM PDT 24
Peak memory 204968 kb
Host smart-4992ac6e-be2e-47dd-8580-36d2ac055b06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496845495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
2496845495
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.1249378700
Short name T169
Test name
Test status
Simulation time 284013769 ps
CPU time 5.69 seconds
Started Jul 09 05:40:00 PM PDT 24
Finished Jul 09 05:40:07 PM PDT 24
Peak memory 232568 kb
Host smart-61894717-d147-4acc-94bc-eed6ada21cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249378700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.1249378700
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.3750471938
Short name T915
Test name
Test status
Simulation time 53181925 ps
CPU time 0.74 seconds
Started Jul 09 05:40:02 PM PDT 24
Finished Jul 09 05:40:04 PM PDT 24
Peak memory 205588 kb
Host smart-083311b5-1f08-4eca-a583-97a3485a4b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750471938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.3750471938
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.1368360811
Short name T335
Test name
Test status
Simulation time 1402985463 ps
CPU time 20.4 seconds
Started Jul 09 05:40:06 PM PDT 24
Finished Jul 09 05:40:29 PM PDT 24
Peak memory 249008 kb
Host smart-e7c37416-0d8c-46d1-9357-4daf4e8ff37a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368360811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.1368360811
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.238959115
Short name T995
Test name
Test status
Simulation time 21195096244 ps
CPU time 101.38 seconds
Started Jul 09 05:40:05 PM PDT 24
Finished Jul 09 05:41:48 PM PDT 24
Peak memory 237368 kb
Host smart-f89a6a00-ac04-45a1-aa46-4b96f1f64ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238959115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idle
.238959115
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.232398131
Short name T721
Test name
Test status
Simulation time 1095385876 ps
CPU time 7.16 seconds
Started Jul 09 05:40:07 PM PDT 24
Finished Jul 09 05:40:16 PM PDT 24
Peak memory 232700 kb
Host smart-e390e4c9-ec0d-46e8-9314-48672e77d951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232398131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.232398131
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.42489428
Short name T199
Test name
Test status
Simulation time 536044271 ps
CPU time 6.3 seconds
Started Jul 09 05:40:05 PM PDT 24
Finished Jul 09 05:40:13 PM PDT 24
Peak memory 224432 kb
Host smart-791b706b-2ca4-48b8-a593-ff59956e6391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42489428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.42489428
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.1899880218
Short name T540
Test name
Test status
Simulation time 282573588 ps
CPU time 7.7 seconds
Started Jul 09 05:40:04 PM PDT 24
Finished Jul 09 05:40:14 PM PDT 24
Peak memory 224400 kb
Host smart-d2292bb2-16ad-4089-8c37-46253d6c2b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899880218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.1899880218
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.1715249547
Short name T941
Test name
Test status
Simulation time 2899732370 ps
CPU time 4.07 seconds
Started Jul 09 05:40:03 PM PDT 24
Finished Jul 09 05:40:10 PM PDT 24
Peak memory 224488 kb
Host smart-c7b5ebdb-17e2-421a-a063-693b01ca2b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715249547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.1715249547
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.779018284
Short name T572
Test name
Test status
Simulation time 1175870354 ps
CPU time 4.52 seconds
Started Jul 09 05:40:05 PM PDT 24
Finished Jul 09 05:40:12 PM PDT 24
Peak memory 224372 kb
Host smart-f01c20a0-2079-4ca0-9293-327392ad604c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779018284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.779018284
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.2789142864
Short name T893
Test name
Test status
Simulation time 541212970 ps
CPU time 8.93 seconds
Started Jul 09 05:40:04 PM PDT 24
Finished Jul 09 05:40:15 PM PDT 24
Peak memory 221552 kb
Host smart-d2c77d36-b15c-4e08-8ebe-4618533d2aa4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2789142864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.2789142864
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.2522334571
Short name T426
Test name
Test status
Simulation time 5019087475 ps
CPU time 99.45 seconds
Started Jul 09 05:40:05 PM PDT 24
Finished Jul 09 05:41:47 PM PDT 24
Peak memory 257460 kb
Host smart-675c5eca-289a-49c1-a9e4-97f32b4e86de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522334571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.2522334571
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.1588915688
Short name T1003
Test name
Test status
Simulation time 9513343187 ps
CPU time 53.01 seconds
Started Jul 09 05:40:06 PM PDT 24
Finished Jul 09 05:41:02 PM PDT 24
Peak memory 216320 kb
Host smart-c90e0cbf-b560-49cb-9bdc-a2148aac89fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588915688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.1588915688
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.4146599965
Short name T616
Test name
Test status
Simulation time 6623669190 ps
CPU time 4.57 seconds
Started Jul 09 05:39:59 PM PDT 24
Finished Jul 09 05:40:05 PM PDT 24
Peak memory 216348 kb
Host smart-0e476803-23f3-4199-9101-b5df3321e15b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146599965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.4146599965
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.3114883996
Short name T748
Test name
Test status
Simulation time 1042353839 ps
CPU time 5.34 seconds
Started Jul 09 05:40:04 PM PDT 24
Finished Jul 09 05:40:11 PM PDT 24
Peak memory 216164 kb
Host smart-abb3e21a-512c-4993-b622-5c182b289600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114883996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.3114883996
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.2711470864
Short name T375
Test name
Test status
Simulation time 121707336 ps
CPU time 0.85 seconds
Started Jul 09 05:39:58 PM PDT 24
Finished Jul 09 05:40:00 PM PDT 24
Peak memory 206000 kb
Host smart-842e0c89-a87d-417a-b730-6481de8a411a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711470864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.2711470864
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.1969160532
Short name T3
Test name
Test status
Simulation time 4194165846 ps
CPU time 7.95 seconds
Started Jul 09 05:40:02 PM PDT 24
Finished Jul 09 05:40:12 PM PDT 24
Peak memory 224616 kb
Host smart-3b8402f2-878a-4dcb-a394-bfa19198ccc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969160532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.1969160532
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.4118292985
Short name T590
Test name
Test status
Simulation time 14862218 ps
CPU time 0.72 seconds
Started Jul 09 05:40:12 PM PDT 24
Finished Jul 09 05:40:14 PM PDT 24
Peak memory 204928 kb
Host smart-28f21819-af28-42b0-ac11-d753470130fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118292985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
4118292985
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.2788885973
Short name T788
Test name
Test status
Simulation time 314534887 ps
CPU time 2.89 seconds
Started Jul 09 05:40:02 PM PDT 24
Finished Jul 09 05:40:07 PM PDT 24
Peak memory 224476 kb
Host smart-d2f5f90b-969a-4315-930d-a682a2e9c6dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788885973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.2788885973
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.1594849642
Short name T996
Test name
Test status
Simulation time 20497395 ps
CPU time 0.76 seconds
Started Jul 09 05:40:09 PM PDT 24
Finished Jul 09 05:40:11 PM PDT 24
Peak memory 206624 kb
Host smart-adcad6fa-a8ce-4fe7-b8cd-47db0a3adacd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594849642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.1594849642
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.3941079409
Short name T997
Test name
Test status
Simulation time 82094569778 ps
CPU time 130.13 seconds
Started Jul 09 05:40:05 PM PDT 24
Finished Jul 09 05:42:17 PM PDT 24
Peak memory 239272 kb
Host smart-05b5e971-4539-4f9a-a69a-ebcb50ea47ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941079409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.3941079409
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.1457052461
Short name T139
Test name
Test status
Simulation time 6575155535 ps
CPU time 111.55 seconds
Started Jul 09 05:40:12 PM PDT 24
Finished Jul 09 05:42:05 PM PDT 24
Peak memory 249740 kb
Host smart-2a557106-ab20-43d7-bd10-fc0152c9cfd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457052461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.1457052461
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.3893904594
Short name T218
Test name
Test status
Simulation time 51200543284 ps
CPU time 367.96 seconds
Started Jul 09 05:40:06 PM PDT 24
Finished Jul 09 05:46:17 PM PDT 24
Peak memory 265660 kb
Host smart-254725e8-55e1-457a-a962-97dcf2f9625a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893904594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.3893904594
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.4228840380
Short name T955
Test name
Test status
Simulation time 394790669 ps
CPU time 6.96 seconds
Started Jul 09 05:40:05 PM PDT 24
Finished Jul 09 05:40:14 PM PDT 24
Peak memory 224500 kb
Host smart-21fef1d5-b787-4893-ac39-1a088c432a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228840380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.4228840380
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.2748202418
Short name T973
Test name
Test status
Simulation time 30632145256 ps
CPU time 212.2 seconds
Started Jul 09 05:40:10 PM PDT 24
Finished Jul 09 05:43:43 PM PDT 24
Peak memory 254544 kb
Host smart-91995b06-baa4-4ddb-8a89-a046fcfb5275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748202418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmd
s.2748202418
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.2886614109
Short name T205
Test name
Test status
Simulation time 2560794236 ps
CPU time 24.14 seconds
Started Jul 09 05:40:08 PM PDT 24
Finished Jul 09 05:40:34 PM PDT 24
Peak memory 232816 kb
Host smart-546dac35-1803-4433-a389-16a68dc243ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886614109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.2886614109
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.1475526758
Short name T336
Test name
Test status
Simulation time 55852810 ps
CPU time 2.15 seconds
Started Jul 09 05:40:06 PM PDT 24
Finished Jul 09 05:40:10 PM PDT 24
Peak memory 224124 kb
Host smart-45e6fb87-99ad-4068-8873-88280b141e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475526758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.1475526758
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.4128399775
Short name T703
Test name
Test status
Simulation time 818783539 ps
CPU time 3.1 seconds
Started Jul 09 05:40:07 PM PDT 24
Finished Jul 09 05:40:12 PM PDT 24
Peak memory 232700 kb
Host smart-62e14ee1-0b51-4e0a-a2b4-53c3cbda3330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128399775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.4128399775
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.2350641736
Short name T195
Test name
Test status
Simulation time 7837636233 ps
CPU time 22.95 seconds
Started Jul 09 05:40:06 PM PDT 24
Finished Jul 09 05:40:31 PM PDT 24
Peak memory 224600 kb
Host smart-17149eb4-93e1-4abc-b8a5-86efc92d8b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350641736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.2350641736
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.968977157
Short name T736
Test name
Test status
Simulation time 158116346 ps
CPU time 3.59 seconds
Started Jul 09 05:40:06 PM PDT 24
Finished Jul 09 05:40:11 PM PDT 24
Peak memory 220324 kb
Host smart-43b2b763-910e-49e7-b9fa-f278c8cd5702
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=968977157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dire
ct.968977157
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.2690004160
Short name T307
Test name
Test status
Simulation time 3596281761 ps
CPU time 29.84 seconds
Started Jul 09 05:40:03 PM PDT 24
Finished Jul 09 05:40:35 PM PDT 24
Peak memory 220016 kb
Host smart-d413ae0a-9c06-459a-8400-10e07f5567e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690004160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.2690004160
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.391829412
Short name T2
Test name
Test status
Simulation time 1787408871 ps
CPU time 5.78 seconds
Started Jul 09 05:40:06 PM PDT 24
Finished Jul 09 05:40:14 PM PDT 24
Peak memory 216216 kb
Host smart-eed74906-b647-4d07-85fd-6c87be90151d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391829412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.391829412
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.3695601447
Short name T639
Test name
Test status
Simulation time 146579723 ps
CPU time 1.35 seconds
Started Jul 09 05:40:08 PM PDT 24
Finished Jul 09 05:40:11 PM PDT 24
Peak memory 216432 kb
Host smart-4c40007c-a04f-4e59-87aa-8e5c149f4439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695601447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.3695601447
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.255119686
Short name T651
Test name
Test status
Simulation time 39925411 ps
CPU time 0.7 seconds
Started Jul 09 05:40:05 PM PDT 24
Finished Jul 09 05:40:08 PM PDT 24
Peak memory 205660 kb
Host smart-99441828-1002-4ea7-8452-6fa8c0324aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255119686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.255119686
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.4117706322
Short name T433
Test name
Test status
Simulation time 5439100993 ps
CPU time 10 seconds
Started Jul 09 05:40:06 PM PDT 24
Finished Jul 09 05:40:18 PM PDT 24
Peak memory 232744 kb
Host smart-27bfcc1d-aff5-418f-856a-2fe394176f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117706322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.4117706322
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.1323730269
Short name T877
Test name
Test status
Simulation time 33021547 ps
CPU time 0.73 seconds
Started Jul 09 05:40:08 PM PDT 24
Finished Jul 09 05:40:10 PM PDT 24
Peak memory 205564 kb
Host smart-4042c3e6-b40f-4b13-8101-ac955d9c701f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323730269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
1323730269
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.2250554197
Short name T908
Test name
Test status
Simulation time 223809142 ps
CPU time 3.44 seconds
Started Jul 09 05:40:16 PM PDT 24
Finished Jul 09 05:40:20 PM PDT 24
Peak memory 232684 kb
Host smart-b41804fa-9877-4602-a22d-2299d7e31f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250554197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.2250554197
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.2394378590
Short name T407
Test name
Test status
Simulation time 20521221 ps
CPU time 0.79 seconds
Started Jul 09 05:40:04 PM PDT 24
Finished Jul 09 05:40:07 PM PDT 24
Peak memory 206592 kb
Host smart-65f24276-8bf3-468e-bb1d-0a24523a50ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394378590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.2394378590
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.325660774
Short name T202
Test name
Test status
Simulation time 776610878 ps
CPU time 10.99 seconds
Started Jul 09 05:40:10 PM PDT 24
Finished Jul 09 05:40:22 PM PDT 24
Peak memory 249064 kb
Host smart-a57dd89f-7218-43ad-9330-be73d6e8a30f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325660774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.325660774
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.476000792
Short name T853
Test name
Test status
Simulation time 22594217158 ps
CPU time 39.67 seconds
Started Jul 09 05:40:08 PM PDT 24
Finished Jul 09 05:40:50 PM PDT 24
Peak memory 238680 kb
Host smart-fdacf0f7-4183-4240-914d-940ef4ccb7ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476000792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.476000792
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.2978930156
Short name T248
Test name
Test status
Simulation time 52881960900 ps
CPU time 472.48 seconds
Started Jul 09 05:40:10 PM PDT 24
Finished Jul 09 05:48:04 PM PDT 24
Peak memory 266600 kb
Host smart-8ac2ba78-db55-42ba-9547-9f265b7a4eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978930156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.2978930156
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.4064346012
Short name T438
Test name
Test status
Simulation time 2872752797 ps
CPU time 21.05 seconds
Started Jul 09 05:40:07 PM PDT 24
Finished Jul 09 05:40:30 PM PDT 24
Peak memory 241000 kb
Host smart-96ad7f0f-080d-4a09-b6dd-84673c1420f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064346012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.4064346012
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.1199994306
Short name T854
Test name
Test status
Simulation time 1426950555 ps
CPU time 7.16 seconds
Started Jul 09 05:40:11 PM PDT 24
Finished Jul 09 05:40:19 PM PDT 24
Peak memory 234484 kb
Host smart-f0689296-0db8-4247-ab4b-8dbcfcde559d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199994306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmd
s.1199994306
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.1943763974
Short name T131
Test name
Test status
Simulation time 3430925222 ps
CPU time 33.19 seconds
Started Jul 09 05:40:07 PM PDT 24
Finished Jul 09 05:40:43 PM PDT 24
Peak memory 224568 kb
Host smart-0f5c7f4d-a642-4358-963f-fa73d6c9a378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943763974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.1943763974
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.177772939
Short name T454
Test name
Test status
Simulation time 3889253776 ps
CPU time 29.23 seconds
Started Jul 09 05:40:08 PM PDT 24
Finished Jul 09 05:40:39 PM PDT 24
Peak memory 240132 kb
Host smart-7e7403dd-8ed9-4d3d-8948-06695b510b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177772939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.177772939
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.1055526910
Short name T903
Test name
Test status
Simulation time 6637456809 ps
CPU time 8.14 seconds
Started Jul 09 05:40:14 PM PDT 24
Finished Jul 09 05:40:24 PM PDT 24
Peak memory 224600 kb
Host smart-4b020d93-0791-4d30-bea2-8c4fe918d078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055526910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.1055526910
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.4142079397
Short name T975
Test name
Test status
Simulation time 116640731 ps
CPU time 2.34 seconds
Started Jul 09 05:40:08 PM PDT 24
Finished Jul 09 05:40:12 PM PDT 24
Peak memory 232372 kb
Host smart-4f8c6543-5bd5-45d1-953b-d9c22233b648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142079397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.4142079397
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.657093941
Short name T419
Test name
Test status
Simulation time 1647877934 ps
CPU time 6.02 seconds
Started Jul 09 05:40:09 PM PDT 24
Finished Jul 09 05:40:16 PM PDT 24
Peak memory 222072 kb
Host smart-99624798-ebd7-40bb-9170-1d892550fc24
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=657093941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dire
ct.657093941
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.37326710
Short name T984
Test name
Test status
Simulation time 20716124599 ps
CPU time 60.16 seconds
Started Jul 09 05:40:11 PM PDT 24
Finished Jul 09 05:41:12 PM PDT 24
Peak memory 249160 kb
Host smart-4e1534a0-a02f-4e76-8a46-f114982e1ff2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37326710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stress
_all.37326710
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.3682594498
Short name T837
Test name
Test status
Simulation time 1345513533 ps
CPU time 7.7 seconds
Started Jul 09 05:40:09 PM PDT 24
Finished Jul 09 05:40:18 PM PDT 24
Peak memory 216224 kb
Host smart-ae01f2b4-6f37-4e9d-8d3a-55755b450a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682594498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.3682594498
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.3789209532
Short name T943
Test name
Test status
Simulation time 6752438922 ps
CPU time 20.53 seconds
Started Jul 09 05:40:10 PM PDT 24
Finished Jul 09 05:40:32 PM PDT 24
Peak memory 216264 kb
Host smart-c35f257f-14fa-470b-9638-bf2af2f63544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789209532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.3789209532
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.2370113430
Short name T593
Test name
Test status
Simulation time 71931133 ps
CPU time 1.24 seconds
Started Jul 09 05:40:06 PM PDT 24
Finished Jul 09 05:40:09 PM PDT 24
Peak memory 207916 kb
Host smart-f0cd64b6-a5a5-4089-8671-47df936874b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370113430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.2370113430
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.3474411458
Short name T790
Test name
Test status
Simulation time 67720958 ps
CPU time 0.73 seconds
Started Jul 09 05:40:06 PM PDT 24
Finished Jul 09 05:40:09 PM PDT 24
Peak memory 205980 kb
Host smart-4e8ecc68-1df4-4dc7-8832-c47931001fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474411458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.3474411458
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.3294045533
Short name T884
Test name
Test status
Simulation time 32770091109 ps
CPU time 25.17 seconds
Started Jul 09 05:40:06 PM PDT 24
Finished Jul 09 05:40:33 PM PDT 24
Peak memory 232808 kb
Host smart-6656ffe2-00f3-4593-b365-c65669e9e6d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294045533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.3294045533
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.3936610626
Short name T931
Test name
Test status
Simulation time 127385205 ps
CPU time 0.69 seconds
Started Jul 09 05:40:13 PM PDT 24
Finished Jul 09 05:40:15 PM PDT 24
Peak memory 204992 kb
Host smart-c887d218-722c-4296-8d1a-51ac2bac0a1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936610626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
3936610626
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.2987195463
Short name T428
Test name
Test status
Simulation time 143665965 ps
CPU time 4.8 seconds
Started Jul 09 05:40:10 PM PDT 24
Finished Jul 09 05:40:16 PM PDT 24
Peak memory 232664 kb
Host smart-fe1cdd32-7463-4d63-a141-f031c21d7fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987195463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.2987195463
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.748241099
Short name T528
Test name
Test status
Simulation time 34827628 ps
CPU time 0.8 seconds
Started Jul 09 05:40:11 PM PDT 24
Finished Jul 09 05:40:13 PM PDT 24
Peak memory 206908 kb
Host smart-e115cec9-a2a1-4956-a5d6-54362df48259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748241099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.748241099
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.1780854246
Short name T278
Test name
Test status
Simulation time 17096804908 ps
CPU time 33.33 seconds
Started Jul 09 05:40:16 PM PDT 24
Finished Jul 09 05:40:50 PM PDT 24
Peak memory 224596 kb
Host smart-024f1228-4ca7-4da0-bcd2-291cfb37028d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780854246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.1780854246
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.248937794
Short name T895
Test name
Test status
Simulation time 4973565965 ps
CPU time 37.87 seconds
Started Jul 09 05:40:09 PM PDT 24
Finished Jul 09 05:40:48 PM PDT 24
Peak memory 224624 kb
Host smart-de392910-2782-49ff-a1af-341a68f75068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248937794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.248937794
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.908713315
Short name T739
Test name
Test status
Simulation time 111494345483 ps
CPU time 120.23 seconds
Started Jul 09 05:40:11 PM PDT 24
Finished Jul 09 05:42:12 PM PDT 24
Peak memory 264952 kb
Host smart-697192b8-478e-468c-9820-df60215e235c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908713315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idle
.908713315
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.2376509119
Short name T302
Test name
Test status
Simulation time 12764050119 ps
CPU time 11.85 seconds
Started Jul 09 05:40:08 PM PDT 24
Finished Jul 09 05:40:22 PM PDT 24
Peak memory 224604 kb
Host smart-14327dd1-cda2-49b7-9e00-393e91d521a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376509119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.2376509119
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.1471508265
Short name T263
Test name
Test status
Simulation time 34576257894 ps
CPU time 124.53 seconds
Started Jul 09 05:40:09 PM PDT 24
Finished Jul 09 05:42:15 PM PDT 24
Peak memory 249156 kb
Host smart-47f30f6f-e32f-4fa7-b468-ea8468964e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471508265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.1471508265
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.1976062474
Short name T451
Test name
Test status
Simulation time 1308115735 ps
CPU time 4.79 seconds
Started Jul 09 05:40:07 PM PDT 24
Finished Jul 09 05:40:14 PM PDT 24
Peak memory 224416 kb
Host smart-679a5234-1aaf-4795-9d9b-24857cc3e9ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976062474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.1976062474
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.2009766583
Short name T73
Test name
Test status
Simulation time 26531966131 ps
CPU time 44.18 seconds
Started Jul 09 05:40:14 PM PDT 24
Finished Jul 09 05:40:59 PM PDT 24
Peak memory 232752 kb
Host smart-fb1d69f1-12ea-44b9-90a9-fb8559bb19e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009766583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.2009766583
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.2987943198
Short name T172
Test name
Test status
Simulation time 2290773128 ps
CPU time 6.1 seconds
Started Jul 09 05:40:06 PM PDT 24
Finished Jul 09 05:40:14 PM PDT 24
Peak memory 232728 kb
Host smart-a84a99df-49b1-450c-906d-190c550d6065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987943198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.2987943198
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.941490978
Short name T481
Test name
Test status
Simulation time 1670176072 ps
CPU time 12.22 seconds
Started Jul 09 05:40:06 PM PDT 24
Finished Jul 09 05:40:21 PM PDT 24
Peak memory 232740 kb
Host smart-79d2f24e-b720-4b47-8d8c-8e2268d51fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941490978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.941490978
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.3318060090
Short name T573
Test name
Test status
Simulation time 1241395855 ps
CPU time 5.79 seconds
Started Jul 09 05:40:24 PM PDT 24
Finished Jul 09 05:40:31 PM PDT 24
Peak memory 222548 kb
Host smart-2b722f0e-81a3-4115-bf75-994c575d1e64
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3318060090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.3318060090
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.2005042699
Short name T471
Test name
Test status
Simulation time 3767615528 ps
CPU time 18.89 seconds
Started Jul 09 05:40:05 PM PDT 24
Finished Jul 09 05:40:26 PM PDT 24
Peak memory 216356 kb
Host smart-a6bd4d53-080d-4778-83b1-5f2117ae2004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005042699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.2005042699
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.3521286041
Short name T589
Test name
Test status
Simulation time 34788012215 ps
CPU time 9.88 seconds
Started Jul 09 05:40:17 PM PDT 24
Finished Jul 09 05:40:28 PM PDT 24
Peak memory 216372 kb
Host smart-42fdc443-bd30-46e7-911f-3ab7e91bea28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521286041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.3521286041
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.1185042270
Short name T706
Test name
Test status
Simulation time 117290183 ps
CPU time 1.28 seconds
Started Jul 09 05:40:04 PM PDT 24
Finished Jul 09 05:40:08 PM PDT 24
Peak memory 216220 kb
Host smart-2c0534b1-08b2-4d6a-b774-da9c4471c0b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185042270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.1185042270
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.4263106437
Short name T346
Test name
Test status
Simulation time 28123436 ps
CPU time 0.87 seconds
Started Jul 09 05:40:10 PM PDT 24
Finished Jul 09 05:40:12 PM PDT 24
Peak memory 205964 kb
Host smart-26107d8b-7028-4eb7-a3fb-2e2abff0e8e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263106437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.4263106437
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.2030841813
Short name T560
Test name
Test status
Simulation time 6189944939 ps
CPU time 22.33 seconds
Started Jul 09 05:40:10 PM PDT 24
Finished Jul 09 05:40:34 PM PDT 24
Peak memory 224572 kb
Host smart-2991c433-3abb-4421-a66b-28e05bde0b77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030841813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.2030841813
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.2825082607
Short name T574
Test name
Test status
Simulation time 18194183 ps
CPU time 0.71 seconds
Started Jul 09 05:40:22 PM PDT 24
Finished Jul 09 05:40:24 PM PDT 24
Peak memory 205552 kb
Host smart-e68720b9-0445-4d79-8de0-4c846f290e89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825082607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
2825082607
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.374100900
Short name T946
Test name
Test status
Simulation time 157048679 ps
CPU time 2.6 seconds
Started Jul 09 05:40:13 PM PDT 24
Finished Jul 09 05:40:17 PM PDT 24
Peak memory 232608 kb
Host smart-cdb9d30d-f6a9-4bef-9f4e-2101b24518d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374100900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.374100900
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.2967931349
Short name T422
Test name
Test status
Simulation time 37217688 ps
CPU time 0.76 seconds
Started Jul 09 05:40:15 PM PDT 24
Finished Jul 09 05:40:17 PM PDT 24
Peak memory 206580 kb
Host smart-f006ea32-531f-4e25-8967-2cec357e62d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967931349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.2967931349
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.1116922361
Short name T168
Test name
Test status
Simulation time 22177955355 ps
CPU time 75.8 seconds
Started Jul 09 05:40:23 PM PDT 24
Finished Jul 09 05:41:45 PM PDT 24
Peak memory 250252 kb
Host smart-fc184e76-a530-4859-bf8b-86ecb1835c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116922361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.1116922361
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.2085624681
Short name T782
Test name
Test status
Simulation time 3290162178 ps
CPU time 75.09 seconds
Started Jul 09 05:40:22 PM PDT 24
Finished Jul 09 05:41:39 PM PDT 24
Peak memory 249288 kb
Host smart-68cb5817-1f5d-4607-8253-3fddc005c775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085624681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.2085624681
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.2817916786
Short name T1004
Test name
Test status
Simulation time 5047367628 ps
CPU time 61.1 seconds
Started Jul 09 05:40:12 PM PDT 24
Finished Jul 09 05:41:14 PM PDT 24
Peak memory 249268 kb
Host smart-c0089f41-f473-4063-add5-1c93bc136cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817916786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.2817916786
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.2523417303
Short name T680
Test name
Test status
Simulation time 424924524 ps
CPU time 10.62 seconds
Started Jul 09 05:40:15 PM PDT 24
Finished Jul 09 05:40:27 PM PDT 24
Peak memory 240656 kb
Host smart-eb6e3c9f-39b7-40d2-b2aa-45aab9cab52d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523417303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.2523417303
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.3773712392
Short name T977
Test name
Test status
Simulation time 63945263687 ps
CPU time 121.85 seconds
Started Jul 09 05:40:10 PM PDT 24
Finished Jul 09 05:42:13 PM PDT 24
Peak memory 257000 kb
Host smart-722eb26a-4503-4cce-9168-a21664b58116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773712392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmd
s.3773712392
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.1117132416
Short name T693
Test name
Test status
Simulation time 414754465 ps
CPU time 3.27 seconds
Started Jul 09 05:40:14 PM PDT 24
Finished Jul 09 05:40:19 PM PDT 24
Peak memory 227968 kb
Host smart-4c078e46-d002-4281-a6f1-b418b2ef7bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117132416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.1117132416
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.1734041941
Short name T440
Test name
Test status
Simulation time 568804547 ps
CPU time 10.67 seconds
Started Jul 09 05:40:21 PM PDT 24
Finished Jul 09 05:40:33 PM PDT 24
Peak memory 232636 kb
Host smart-18afaf16-4a61-4926-ac63-3c19c25a131e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734041941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.1734041941
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.3982849448
Short name T825
Test name
Test status
Simulation time 15861868016 ps
CPU time 9.61 seconds
Started Jul 09 05:40:22 PM PDT 24
Finished Jul 09 05:40:33 PM PDT 24
Peak memory 232776 kb
Host smart-38e0c90b-17cd-4e76-8c77-015574b87119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982849448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.3982849448
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.3255456616
Short name T284
Test name
Test status
Simulation time 9138936880 ps
CPU time 30.03 seconds
Started Jul 09 05:40:25 PM PDT 24
Finished Jul 09 05:40:56 PM PDT 24
Peak memory 241028 kb
Host smart-d34efa63-6c95-4d80-aa2e-1b9ca8457645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255456616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.3255456616
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.842388891
Short name T1006
Test name
Test status
Simulation time 844980830 ps
CPU time 4.37 seconds
Started Jul 09 05:40:19 PM PDT 24
Finished Jul 09 05:40:24 PM PDT 24
Peak memory 219020 kb
Host smart-d7db1cc7-adcd-4340-9b31-e030723c4de3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=842388891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dire
ct.842388891
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.2810515276
Short name T21
Test name
Test status
Simulation time 212532553 ps
CPU time 1.06 seconds
Started Jul 09 05:40:07 PM PDT 24
Finished Jul 09 05:40:11 PM PDT 24
Peak memory 207092 kb
Host smart-0d085004-bab7-4a5c-9788-572530eef0fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810515276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.2810515276
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.3178081898
Short name T316
Test name
Test status
Simulation time 7724989918 ps
CPU time 17.25 seconds
Started Jul 09 05:40:08 PM PDT 24
Finished Jul 09 05:40:27 PM PDT 24
Peak memory 216360 kb
Host smart-e5dbf037-abf3-4232-a86d-f413fbb53215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178081898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.3178081898
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.2950745723
Short name T605
Test name
Test status
Simulation time 1946040246 ps
CPU time 7.52 seconds
Started Jul 09 05:40:12 PM PDT 24
Finished Jul 09 05:40:20 PM PDT 24
Peak memory 216196 kb
Host smart-de54acde-b168-4a3b-b2a0-5b05e42c4eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950745723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.2950745723
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.1622612107
Short name T472
Test name
Test status
Simulation time 130068144 ps
CPU time 1.24 seconds
Started Jul 09 05:40:10 PM PDT 24
Finished Jul 09 05:40:12 PM PDT 24
Peak memory 207864 kb
Host smart-9d60f252-e246-4120-811c-9adfd0ca5454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622612107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.1622612107
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.1965292858
Short name T387
Test name
Test status
Simulation time 116887882 ps
CPU time 0.86 seconds
Started Jul 09 05:40:13 PM PDT 24
Finished Jul 09 05:40:16 PM PDT 24
Peak memory 205916 kb
Host smart-e770a793-6a14-4d04-9420-2161231e29c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965292858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.1965292858
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.2817837203
Short name T906
Test name
Test status
Simulation time 4232522057 ps
CPU time 9.99 seconds
Started Jul 09 05:40:09 PM PDT 24
Finished Jul 09 05:40:20 PM PDT 24
Peak memory 232780 kb
Host smart-385c1170-be1d-491a-b6ca-f3c49ed72fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817837203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.2817837203
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.2594832220
Short name T934
Test name
Test status
Simulation time 20396810 ps
CPU time 0.71 seconds
Started Jul 09 05:40:13 PM PDT 24
Finished Jul 09 05:40:14 PM PDT 24
Peak memory 205852 kb
Host smart-44753070-b04e-4de6-99bc-c2569280c1f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594832220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
2594832220
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.1250061360
Short name T431
Test name
Test status
Simulation time 1518556686 ps
CPU time 12.42 seconds
Started Jul 09 05:40:15 PM PDT 24
Finished Jul 09 05:40:28 PM PDT 24
Peak memory 232700 kb
Host smart-5b816b1d-8e76-40c7-9cb1-07ce1e7ddfdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250061360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.1250061360
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.1269377871
Short name T357
Test name
Test status
Simulation time 27572496 ps
CPU time 0.76 seconds
Started Jul 09 05:40:07 PM PDT 24
Finished Jul 09 05:40:10 PM PDT 24
Peak memory 205540 kb
Host smart-54f15091-d657-462d-8d18-b5fb424c5b1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269377871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.1269377871
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.3951948510
Short name T135
Test name
Test status
Simulation time 627379135506 ps
CPU time 223.79 seconds
Started Jul 09 05:40:13 PM PDT 24
Finished Jul 09 05:43:58 PM PDT 24
Peak memory 249196 kb
Host smart-2ee5ba03-d801-420a-a64d-4b041076a3d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951948510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.3951948510
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.3064260807
Short name T666
Test name
Test status
Simulation time 25261294881 ps
CPU time 267.11 seconds
Started Jul 09 05:40:14 PM PDT 24
Finished Jul 09 05:44:43 PM PDT 24
Peak memory 260048 kb
Host smart-a9b1ab1f-8335-42f3-9e50-4b9d2386da86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064260807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.3064260807
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.2536884155
Short name T365
Test name
Test status
Simulation time 12870993095 ps
CPU time 66.63 seconds
Started Jul 09 05:40:26 PM PDT 24
Finished Jul 09 05:41:33 PM PDT 24
Peak memory 249264 kb
Host smart-ab451296-df2d-42ca-a5ce-0ab5cc8d2c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536884155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.2536884155
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.581573895
Short name T744
Test name
Test status
Simulation time 95069307 ps
CPU time 3.9 seconds
Started Jul 09 05:40:12 PM PDT 24
Finished Jul 09 05:40:17 PM PDT 24
Peak memory 234184 kb
Host smart-6ec49708-54f5-4597-95b7-20cfa753409a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581573895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.581573895
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.1360798793
Short name T869
Test name
Test status
Simulation time 21651777750 ps
CPU time 47.42 seconds
Started Jul 09 05:40:13 PM PDT 24
Finished Jul 09 05:41:02 PM PDT 24
Peak memory 241356 kb
Host smart-d4779787-e9f6-4670-ac0f-98caa043b73a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360798793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmd
s.1360798793
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.35346644
Short name T774
Test name
Test status
Simulation time 4616268288 ps
CPU time 33.85 seconds
Started Jul 09 05:40:21 PM PDT 24
Finished Jul 09 05:40:56 PM PDT 24
Peak memory 224572 kb
Host smart-f554322b-54db-4037-a1c3-113fdff3c5a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35346644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.35346644
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.3668065493
Short name T859
Test name
Test status
Simulation time 10018580885 ps
CPU time 16.58 seconds
Started Jul 09 05:40:12 PM PDT 24
Finished Jul 09 05:40:30 PM PDT 24
Peak memory 237836 kb
Host smart-60d5ab47-81eb-4b7d-8650-8e5f2d34ab98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668065493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.3668065493
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.4244784071
Short name T839
Test name
Test status
Simulation time 1249873651 ps
CPU time 7.1 seconds
Started Jul 09 05:40:21 PM PDT 24
Finished Jul 09 05:40:29 PM PDT 24
Peak memory 238252 kb
Host smart-9919c787-3e50-4916-9dbd-653ef9b61817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244784071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.4244784071
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.583065689
Short name T547
Test name
Test status
Simulation time 170589719 ps
CPU time 4.9 seconds
Started Jul 09 05:40:13 PM PDT 24
Finished Jul 09 05:40:20 PM PDT 24
Peak memory 240404 kb
Host smart-e67eb9ef-ed0b-4915-a2c7-abcd0c077af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583065689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.583065689
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.3591727042
Short name T146
Test name
Test status
Simulation time 1460695271 ps
CPU time 6.23 seconds
Started Jul 09 05:40:22 PM PDT 24
Finished Jul 09 05:40:30 PM PDT 24
Peak memory 219256 kb
Host smart-3755cb56-83aa-4ccc-b78e-baf5a9923c1b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3591727042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.3591727042
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.1157910799
Short name T880
Test name
Test status
Simulation time 827912693 ps
CPU time 13.61 seconds
Started Jul 09 05:40:12 PM PDT 24
Finished Jul 09 05:40:27 PM PDT 24
Peak memory 233188 kb
Host smart-d415d4c4-01c3-457e-914c-eeaca1e1fa85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157910799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.1157910799
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.938101306
Short name T309
Test name
Test status
Simulation time 31142414958 ps
CPU time 32.6 seconds
Started Jul 09 05:40:17 PM PDT 24
Finished Jul 09 05:40:50 PM PDT 24
Peak memory 216588 kb
Host smart-51afa7ce-5ee5-4cfb-af02-627ce5f63c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938101306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.938101306
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.1089541126
Short name T82
Test name
Test status
Simulation time 21825360 ps
CPU time 0.7 seconds
Started Jul 09 05:40:11 PM PDT 24
Finished Jul 09 05:40:13 PM PDT 24
Peak memory 205656 kb
Host smart-84e8917e-90eb-4753-8310-9b0a16b3d9a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089541126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.1089541126
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.1307768828
Short name T702
Test name
Test status
Simulation time 214718615 ps
CPU time 4.57 seconds
Started Jul 09 05:40:13 PM PDT 24
Finished Jul 09 05:40:20 PM PDT 24
Peak memory 216280 kb
Host smart-e53e4317-452c-4693-8ec2-b1eaf6575230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307768828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.1307768828
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.190575631
Short name T783
Test name
Test status
Simulation time 54056440 ps
CPU time 0.89 seconds
Started Jul 09 05:40:19 PM PDT 24
Finished Jul 09 05:40:20 PM PDT 24
Peak memory 206476 kb
Host smart-b892d0b4-067b-432c-b666-ef38f673a6ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190575631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.190575631
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.3466901597
Short name T535
Test name
Test status
Simulation time 34262727579 ps
CPU time 29.6 seconds
Started Jul 09 05:40:13 PM PDT 24
Finished Jul 09 05:40:44 PM PDT 24
Peak memory 232748 kb
Host smart-dba1e942-c9ae-418a-8e00-140e7f7ec520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466901597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.3466901597
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.723304586
Short name T712
Test name
Test status
Simulation time 35635972 ps
CPU time 0.71 seconds
Started Jul 09 05:40:31 PM PDT 24
Finished Jul 09 05:40:32 PM PDT 24
Peak memory 205564 kb
Host smart-d9f88c34-40b2-4081-ada2-f35c76ba3668
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723304586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.723304586
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.2021855298
Short name T998
Test name
Test status
Simulation time 4604725779 ps
CPU time 11.76 seconds
Started Jul 09 05:40:37 PM PDT 24
Finished Jul 09 05:40:51 PM PDT 24
Peak memory 232800 kb
Host smart-623b7f7c-d98d-4ba0-a569-5c659dc07cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021855298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.2021855298
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.3229017169
Short name T434
Test name
Test status
Simulation time 110107383 ps
CPU time 0.74 seconds
Started Jul 09 05:40:16 PM PDT 24
Finished Jul 09 05:40:18 PM PDT 24
Peak memory 205916 kb
Host smart-9a10d481-45bc-4714-8f21-ced838645d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229017169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.3229017169
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.678421456
Short name T842
Test name
Test status
Simulation time 4842903829 ps
CPU time 38.92 seconds
Started Jul 09 05:40:20 PM PDT 24
Finished Jul 09 05:40:59 PM PDT 24
Peak memory 250160 kb
Host smart-ed13a736-3831-4296-8920-96d2f95baa23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678421456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.678421456
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.2130082288
Short name T183
Test name
Test status
Simulation time 164622396181 ps
CPU time 177 seconds
Started Jul 09 05:40:18 PM PDT 24
Finished Jul 09 05:43:16 PM PDT 24
Peak memory 262660 kb
Host smart-5bea0741-a930-4b22-8f6b-13151b20a0e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130082288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.2130082288
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.1798085801
Short name T999
Test name
Test status
Simulation time 5032071105 ps
CPU time 25.53 seconds
Started Jul 09 05:40:23 PM PDT 24
Finished Jul 09 05:40:50 PM PDT 24
Peak memory 217836 kb
Host smart-73a4dd03-69e3-4593-ae80-650b5642a2f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798085801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.1798085801
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.3727185416
Short name T289
Test name
Test status
Simulation time 157646105915 ps
CPU time 295.17 seconds
Started Jul 09 05:40:14 PM PDT 24
Finished Jul 09 05:45:10 PM PDT 24
Peak memory 254528 kb
Host smart-0e424b78-9193-4f9a-893b-3c41728b0e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727185416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmd
s.3727185416
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.3977233054
Short name T919
Test name
Test status
Simulation time 766288384 ps
CPU time 6.71 seconds
Started Jul 09 05:40:32 PM PDT 24
Finished Jul 09 05:40:39 PM PDT 24
Peak memory 232644 kb
Host smart-7c5f5f86-6dc1-4a69-8c84-7ab54664eb14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977233054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.3977233054
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.584441532
Short name T184
Test name
Test status
Simulation time 2739701695 ps
CPU time 8.46 seconds
Started Jul 09 05:40:13 PM PDT 24
Finished Jul 09 05:40:23 PM PDT 24
Peak memory 232716 kb
Host smart-ec873b4b-4aaf-4f98-abdd-19bec318cbfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584441532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.584441532
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.2248245069
Short name T403
Test name
Test status
Simulation time 310689313 ps
CPU time 4.26 seconds
Started Jul 09 05:40:14 PM PDT 24
Finished Jul 09 05:40:20 PM PDT 24
Peak memory 224452 kb
Host smart-c5611b3e-a5f3-4a17-914f-872375db10c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248245069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.2248245069
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.1862291507
Short name T180
Test name
Test status
Simulation time 12418021018 ps
CPU time 16.35 seconds
Started Jul 09 05:40:12 PM PDT 24
Finished Jul 09 05:40:29 PM PDT 24
Peak memory 248708 kb
Host smart-c7e7eff0-f7e2-4022-8702-414a45806904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862291507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.1862291507
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.661197078
Short name T784
Test name
Test status
Simulation time 182844258 ps
CPU time 4.36 seconds
Started Jul 09 05:40:22 PM PDT 24
Finished Jul 09 05:40:27 PM PDT 24
Peak memory 218800 kb
Host smart-ba7f7714-96bd-4858-8fd6-da844d79cb77
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=661197078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dire
ct.661197078
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.930124421
Short name T787
Test name
Test status
Simulation time 66651964 ps
CPU time 1.16 seconds
Started Jul 09 05:40:22 PM PDT 24
Finished Jul 09 05:40:24 PM PDT 24
Peak memory 215252 kb
Host smart-72ba056e-689b-42ad-85c8-c8c4828b3837
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930124421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stres
s_all.930124421
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.1839316453
Short name T312
Test name
Test status
Simulation time 1049608086 ps
CPU time 12.63 seconds
Started Jul 09 05:40:12 PM PDT 24
Finished Jul 09 05:40:25 PM PDT 24
Peak memory 216404 kb
Host smart-c0449d28-006b-48ae-9f24-0ce715cd89ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839316453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.1839316453
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.1558013697
Short name T337
Test name
Test status
Simulation time 5879315865 ps
CPU time 9.72 seconds
Started Jul 09 05:40:13 PM PDT 24
Finished Jul 09 05:40:25 PM PDT 24
Peak memory 216244 kb
Host smart-1829e005-5a0b-4f99-b7f7-4d35e95d3e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558013697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.1558013697
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.1270384279
Short name T552
Test name
Test status
Simulation time 107035006 ps
CPU time 3.06 seconds
Started Jul 09 05:40:14 PM PDT 24
Finished Jul 09 05:40:18 PM PDT 24
Peak memory 216264 kb
Host smart-ce9f2631-4828-4f20-9afc-e52dd674ce0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270384279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.1270384279
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.3879373262
Short name T423
Test name
Test status
Simulation time 83872283 ps
CPU time 0.96 seconds
Started Jul 09 05:40:12 PM PDT 24
Finished Jul 09 05:40:14 PM PDT 24
Peak memory 206956 kb
Host smart-1b96d831-07ce-4f93-a739-78bc086d72ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879373262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.3879373262
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.3387598688
Short name T401
Test name
Test status
Simulation time 3194558592 ps
CPU time 11.64 seconds
Started Jul 09 05:40:19 PM PDT 24
Finished Jul 09 05:40:32 PM PDT 24
Peak memory 232772 kb
Host smart-ba385ce9-d8c0-4e87-a132-6f28641a7e16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387598688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.3387598688
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.2266028
Short name T697
Test name
Test status
Simulation time 15538302 ps
CPU time 0.73 seconds
Started Jul 09 05:38:44 PM PDT 24
Finished Jul 09 05:38:45 PM PDT 24
Peak memory 205528 kb
Host smart-06f0130a-bb5d-475c-82fd-c3c0cb8ddb3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.2266028
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.3369619183
Short name T936
Test name
Test status
Simulation time 736215911 ps
CPU time 4.26 seconds
Started Jul 09 05:38:45 PM PDT 24
Finished Jul 09 05:38:50 PM PDT 24
Peak memory 224492 kb
Host smart-5b1106f5-6b34-4441-8c26-b0a983c126af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369619183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.3369619183
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.3437617022
Short name T381
Test name
Test status
Simulation time 62235302 ps
CPU time 0.78 seconds
Started Jul 09 05:38:44 PM PDT 24
Finished Jul 09 05:38:45 PM PDT 24
Peak memory 206612 kb
Host smart-fee8e5e9-7f8c-443e-a3a3-d88d58c339c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437617022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.3437617022
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.1358073852
Short name T879
Test name
Test status
Simulation time 36542301171 ps
CPU time 241.91 seconds
Started Jul 09 05:38:45 PM PDT 24
Finished Jul 09 05:42:49 PM PDT 24
Peak memory 249200 kb
Host smart-94fa1a06-92cd-40d2-b719-b117cf5c87f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358073852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.1358073852
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.208895814
Short name T778
Test name
Test status
Simulation time 19209924849 ps
CPU time 119.66 seconds
Started Jul 09 05:38:48 PM PDT 24
Finished Jul 09 05:40:50 PM PDT 24
Peak memory 249012 kb
Host smart-8d40afc7-ce71-4757-b4bf-8b2352387005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208895814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.208895814
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.1145781532
Short name T850
Test name
Test status
Simulation time 2775051707 ps
CPU time 29.02 seconds
Started Jul 09 05:38:48 PM PDT 24
Finished Jul 09 05:39:19 PM PDT 24
Peak memory 217652 kb
Host smart-ef2b5803-39c5-43f9-bf28-f96e944c64cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145781532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.1145781532
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.1169524312
Short name T300
Test name
Test status
Simulation time 490726613 ps
CPU time 7.27 seconds
Started Jul 09 05:38:45 PM PDT 24
Finished Jul 09 05:38:54 PM PDT 24
Peak memory 232724 kb
Host smart-262f1f0e-4f14-4216-8ed1-60ca907d320f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169524312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.1169524312
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.3420941531
Short name T45
Test name
Test status
Simulation time 267371537326 ps
CPU time 200.19 seconds
Started Jul 09 05:38:48 PM PDT 24
Finished Jul 09 05:42:11 PM PDT 24
Peak memory 251680 kb
Host smart-ae96f21e-7afe-4d4c-bfe5-1189f207cef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420941531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds
.3420941531
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.3914916026
Short name T987
Test name
Test status
Simulation time 3936449755 ps
CPU time 6.02 seconds
Started Jul 09 05:38:45 PM PDT 24
Finished Jul 09 05:38:53 PM PDT 24
Peak memory 224612 kb
Host smart-127104f2-887f-48c7-b74f-d4389b0ad5d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914916026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.3914916026
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.876880285
Short name T679
Test name
Test status
Simulation time 337401151 ps
CPU time 5.8 seconds
Started Jul 09 05:38:49 PM PDT 24
Finished Jul 09 05:38:57 PM PDT 24
Peak memory 224428 kb
Host smart-bd8f0532-0851-46d9-8c13-ad81e5a58350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876880285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.876880285
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.2661205467
Short name T368
Test name
Test status
Simulation time 4084145469 ps
CPU time 12.35 seconds
Started Jul 09 05:38:49 PM PDT 24
Finished Jul 09 05:39:04 PM PDT 24
Peak memory 232692 kb
Host smart-d688b89b-2f64-47cd-8392-f57420990350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661205467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.2661205467
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.2018150002
Short name T276
Test name
Test status
Simulation time 385858591 ps
CPU time 5.41 seconds
Started Jul 09 05:38:48 PM PDT 24
Finished Jul 09 05:38:56 PM PDT 24
Peak memory 224516 kb
Host smart-717e0d3a-555c-41ac-b6ca-a45b6b9ae6b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018150002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.2018150002
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.215116025
Short name T967
Test name
Test status
Simulation time 385184922 ps
CPU time 4.17 seconds
Started Jul 09 05:38:45 PM PDT 24
Finished Jul 09 05:38:51 PM PDT 24
Peak memory 223144 kb
Host smart-7dde6ac9-ec0e-4d23-96bd-140becd01a32
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=215116025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_direc
t.215116025
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.192903356
Short name T69
Test name
Test status
Simulation time 73592021 ps
CPU time 1.12 seconds
Started Jul 09 05:38:49 PM PDT 24
Finished Jul 09 05:38:53 PM PDT 24
Peak memory 236500 kb
Host smart-6c34d3d5-3ce0-4681-ae64-a08fb31d62ec
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192903356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.192903356
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.2293332767
Short name T653
Test name
Test status
Simulation time 61054758 ps
CPU time 1.02 seconds
Started Jul 09 05:38:47 PM PDT 24
Finished Jul 09 05:38:51 PM PDT 24
Peak memory 206788 kb
Host smart-ccdec635-5590-41dc-9f00-9024ae7eedb6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293332767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.2293332767
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.2255921853
Short name T892
Test name
Test status
Simulation time 2295686151 ps
CPU time 6.42 seconds
Started Jul 09 05:38:45 PM PDT 24
Finished Jul 09 05:38:52 PM PDT 24
Peak memory 216308 kb
Host smart-2e2c500c-10df-4856-9a18-e0c1826a7046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255921853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.2255921853
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.3367787137
Short name T829
Test name
Test status
Simulation time 13905151 ps
CPU time 0.74 seconds
Started Jul 09 05:38:45 PM PDT 24
Finished Jul 09 05:38:46 PM PDT 24
Peak memory 205704 kb
Host smart-6a6915d4-de08-4cae-86b9-003790e4bbdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367787137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.3367787137
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.3310987895
Short name T827
Test name
Test status
Simulation time 40874366 ps
CPU time 0.68 seconds
Started Jul 09 05:38:49 PM PDT 24
Finished Jul 09 05:38:52 PM PDT 24
Peak memory 205660 kb
Host smart-9ab753f7-1524-4810-9f83-605e27891c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310987895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.3310987895
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.2983671844
Short name T384
Test name
Test status
Simulation time 16363357 ps
CPU time 0.73 seconds
Started Jul 09 05:38:47 PM PDT 24
Finished Jul 09 05:38:50 PM PDT 24
Peak memory 205932 kb
Host smart-9738829f-1aa4-4eda-b733-6cbcb4e023d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983671844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.2983671844
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.250919008
Short name T352
Test name
Test status
Simulation time 33300902 ps
CPU time 2.21 seconds
Started Jul 09 05:38:48 PM PDT 24
Finished Jul 09 05:38:52 PM PDT 24
Peak memory 223776 kb
Host smart-8b99fcbb-bdee-4cf7-b5a3-82daec5f9520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250919008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.250919008
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.3469278781
Short name T628
Test name
Test status
Simulation time 15151762 ps
CPU time 0.7 seconds
Started Jul 09 05:40:23 PM PDT 24
Finished Jul 09 05:40:25 PM PDT 24
Peak memory 205560 kb
Host smart-0b109768-ebc8-48b2-a114-e4662282ffb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469278781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
3469278781
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.2063491616
Short name T570
Test name
Test status
Simulation time 62306137 ps
CPU time 2.21 seconds
Started Jul 09 05:40:17 PM PDT 24
Finished Jul 09 05:40:20 PM PDT 24
Peak memory 232624 kb
Host smart-104f9175-44ef-4ecc-8b2a-6ea8d3dc9bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063491616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.2063491616
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.1447180924
Short name T556
Test name
Test status
Simulation time 59939068 ps
CPU time 0.77 seconds
Started Jul 09 05:40:27 PM PDT 24
Finished Jul 09 05:40:29 PM PDT 24
Peak memory 206584 kb
Host smart-429f3b1d-c395-489b-b7d5-5926ba18dc8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447180924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.1447180924
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.2954823494
Short name T826
Test name
Test status
Simulation time 17168921611 ps
CPU time 61.97 seconds
Started Jul 09 05:40:28 PM PDT 24
Finished Jul 09 05:41:31 PM PDT 24
Peak memory 256140 kb
Host smart-f37f2126-b6a6-49d2-83af-0e0de7b4d20f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954823494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.2954823494
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.1596833819
Short name T210
Test name
Test status
Simulation time 2682162378 ps
CPU time 48.46 seconds
Started Jul 09 05:40:25 PM PDT 24
Finished Jul 09 05:41:14 PM PDT 24
Peak memory 249292 kb
Host smart-d8477e07-c02a-4e1b-8c95-7c975d678ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596833819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.1596833819
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.1228369564
Short name T272
Test name
Test status
Simulation time 10436711043 ps
CPU time 79.43 seconds
Started Jul 09 05:40:19 PM PDT 24
Finished Jul 09 05:41:39 PM PDT 24
Peak memory 249280 kb
Host smart-fd91c1fc-d397-423a-be14-8cce11d0e025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228369564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.1228369564
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.2761218384
Short name T771
Test name
Test status
Simulation time 422387781 ps
CPU time 9.45 seconds
Started Jul 09 05:40:25 PM PDT 24
Finished Jul 09 05:40:36 PM PDT 24
Peak memory 224412 kb
Host smart-7bc5b1c9-ded5-4d81-ae00-26af326d5494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761218384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.2761218384
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.1831269112
Short name T692
Test name
Test status
Simulation time 1830076623 ps
CPU time 17.38 seconds
Started Jul 09 05:40:16 PM PDT 24
Finished Jul 09 05:40:34 PM PDT 24
Peak memory 224596 kb
Host smart-520951fa-2d8b-4da8-bac0-69e9d7ffe3bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831269112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmd
s.1831269112
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.473060593
Short name T672
Test name
Test status
Simulation time 188506672 ps
CPU time 4.23 seconds
Started Jul 09 05:40:25 PM PDT 24
Finished Jul 09 05:40:30 PM PDT 24
Peak memory 227900 kb
Host smart-e9d0b784-c8c0-47cd-814c-c0bc1c250ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473060593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.473060593
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.3185395072
Short name T980
Test name
Test status
Simulation time 1260787583 ps
CPU time 7.46 seconds
Started Jul 09 05:40:15 PM PDT 24
Finished Jul 09 05:40:23 PM PDT 24
Peak memory 224436 kb
Host smart-ca4f67f2-e09a-4aee-a4cd-1a78f2965a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185395072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.3185395072
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.3011478520
Short name T863
Test name
Test status
Simulation time 2181767074 ps
CPU time 4.92 seconds
Started Jul 09 05:40:25 PM PDT 24
Finished Jul 09 05:40:31 PM PDT 24
Peak memory 224516 kb
Host smart-d063f5b1-e164-415d-9892-bace3c589036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011478520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.3011478520
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.2547642710
Short name T806
Test name
Test status
Simulation time 2643459020 ps
CPU time 13.63 seconds
Started Jul 09 05:40:16 PM PDT 24
Finished Jul 09 05:40:31 PM PDT 24
Peak memory 248580 kb
Host smart-463af52a-9f35-46b0-872e-535f222d4f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547642710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.2547642710
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.3015237964
Short name T891
Test name
Test status
Simulation time 81388750 ps
CPU time 3.55 seconds
Started Jul 09 05:40:22 PM PDT 24
Finished Jul 09 05:40:26 PM PDT 24
Peak memory 222600 kb
Host smart-dbc3015a-56a7-4f3b-9629-ed51ffdf1a54
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3015237964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.3015237964
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.288591805
Short name T166
Test name
Test status
Simulation time 11803203802 ps
CPU time 94.03 seconds
Started Jul 09 05:40:21 PM PDT 24
Finished Jul 09 05:41:56 PM PDT 24
Peak memory 233872 kb
Host smart-0420d3f8-35dd-4547-92a8-3b371cb53f2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288591805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stres
s_all.288591805
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.1817044529
Short name T913
Test name
Test status
Simulation time 3578501006 ps
CPU time 6.56 seconds
Started Jul 09 05:40:24 PM PDT 24
Finished Jul 09 05:40:31 PM PDT 24
Peak memory 216332 kb
Host smart-d17c048a-1b9a-474c-90b8-d43458fa3d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817044529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.1817044529
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.2846653588
Short name T618
Test name
Test status
Simulation time 758832911 ps
CPU time 2.73 seconds
Started Jul 09 05:40:26 PM PDT 24
Finished Jul 09 05:40:30 PM PDT 24
Peak memory 216096 kb
Host smart-63971679-8015-4196-8080-f7e95c2783fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846653588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.2846653588
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.201995470
Short name T647
Test name
Test status
Simulation time 56198186 ps
CPU time 1.22 seconds
Started Jul 09 05:40:20 PM PDT 24
Finished Jul 09 05:40:22 PM PDT 24
Peak memory 207984 kb
Host smart-be7a2ed6-0758-495d-b8f4-ba043fa8cd0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201995470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.201995470
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.1300502013
Short name T662
Test name
Test status
Simulation time 186023302 ps
CPU time 0.9 seconds
Started Jul 09 05:40:20 PM PDT 24
Finished Jul 09 05:40:22 PM PDT 24
Peak memory 205968 kb
Host smart-783c568d-c1c0-4e79-b616-9682fb7a5647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300502013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.1300502013
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.4035960574
Short name T500
Test name
Test status
Simulation time 108701537 ps
CPU time 2.44 seconds
Started Jul 09 05:40:24 PM PDT 24
Finished Jul 09 05:40:27 PM PDT 24
Peak memory 224056 kb
Host smart-d9560df8-b4d6-4972-93d6-bdd3fa2e07ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035960574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.4035960574
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.1490094584
Short name T686
Test name
Test status
Simulation time 16098586 ps
CPU time 0.71 seconds
Started Jul 09 05:40:29 PM PDT 24
Finished Jul 09 05:40:30 PM PDT 24
Peak memory 204960 kb
Host smart-3fafebbc-c87b-469f-b543-0c2150532aa6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490094584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
1490094584
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.3801586537
Short name T549
Test name
Test status
Simulation time 270945533 ps
CPU time 2.94 seconds
Started Jul 09 05:40:24 PM PDT 24
Finished Jul 09 05:40:28 PM PDT 24
Peak memory 232636 kb
Host smart-0152ec10-acb1-453f-9af3-d228f8df4860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801586537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.3801586537
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.691173773
Short name T132
Test name
Test status
Simulation time 17335307 ps
CPU time 0.76 seconds
Started Jul 09 05:40:23 PM PDT 24
Finished Jul 09 05:40:24 PM PDT 24
Peak memory 206628 kb
Host smart-bd231cc1-920f-4820-bf8e-454df0947aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691173773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.691173773
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.2463493446
Short name T490
Test name
Test status
Simulation time 5236595784 ps
CPU time 70.89 seconds
Started Jul 09 05:40:21 PM PDT 24
Finished Jul 09 05:41:32 PM PDT 24
Peak memory 249232 kb
Host smart-4fc12732-9c31-4b7d-85fc-2a9911df33ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463493446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.2463493446
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.1615122746
Short name T44
Test name
Test status
Simulation time 8268627449 ps
CPU time 64.67 seconds
Started Jul 09 05:40:25 PM PDT 24
Finished Jul 09 05:41:30 PM PDT 24
Peak memory 257136 kb
Host smart-6d7f6034-ff5b-4c14-906d-4654d52a5a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615122746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.1615122746
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.3136822837
Short name T49
Test name
Test status
Simulation time 38787737286 ps
CPU time 49.05 seconds
Started Jul 09 05:40:26 PM PDT 24
Finished Jul 09 05:41:17 PM PDT 24
Peak memory 224496 kb
Host smart-0938f2be-2b91-4a78-8726-ef88f5934a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136822837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.3136822837
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.3126205277
Short name T295
Test name
Test status
Simulation time 1054604626 ps
CPU time 21.87 seconds
Started Jul 09 05:40:18 PM PDT 24
Finished Jul 09 05:40:40 PM PDT 24
Peak memory 232700 kb
Host smart-060d55b8-631c-4969-bccc-43cb21a5c269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126205277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.3126205277
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.3974409193
Short name T710
Test name
Test status
Simulation time 54980953922 ps
CPU time 122.5 seconds
Started Jul 09 05:40:25 PM PDT 24
Finished Jul 09 05:42:28 PM PDT 24
Peak memory 263628 kb
Host smart-2e3d113e-d7e6-4e92-9da9-673960f0a5ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974409193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmd
s.3974409193
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.3425595524
Short name T94
Test name
Test status
Simulation time 618563466 ps
CPU time 4.13 seconds
Started Jul 09 05:40:26 PM PDT 24
Finished Jul 09 05:40:31 PM PDT 24
Peak memory 232596 kb
Host smart-b9993999-fa06-4b3a-a1e0-7f88d393cd0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425595524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.3425595524
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.1235506047
Short name T550
Test name
Test status
Simulation time 95186167 ps
CPU time 2.34 seconds
Started Jul 09 05:40:24 PM PDT 24
Finished Jul 09 05:40:27 PM PDT 24
Peak memory 232404 kb
Host smart-96ca351f-768f-4fef-a4c0-eeef07bf71ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235506047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.1235506047
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.1999079368
Short name T208
Test name
Test status
Simulation time 2392460086 ps
CPU time 14.45 seconds
Started Jul 09 05:40:27 PM PDT 24
Finished Jul 09 05:40:42 PM PDT 24
Peak memory 240912 kb
Host smart-04840f6e-8a2f-49db-be09-b0fc0fea84f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999079368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.1999079368
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.1461023908
Short name T483
Test name
Test status
Simulation time 1797085444 ps
CPU time 7.1 seconds
Started Jul 09 05:40:22 PM PDT 24
Finished Jul 09 05:40:30 PM PDT 24
Peak memory 224464 kb
Host smart-d1b270a4-68f5-4922-9a42-2eceab137aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461023908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.1461023908
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.926171696
Short name T745
Test name
Test status
Simulation time 7329501951 ps
CPU time 10.17 seconds
Started Jul 09 05:40:19 PM PDT 24
Finished Jul 09 05:40:30 PM PDT 24
Peak memory 220936 kb
Host smart-b9f3961a-1e76-4d8f-a914-b25e22aeb0de
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=926171696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dire
ct.926171696
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.2053183898
Short name T489
Test name
Test status
Simulation time 36357703076 ps
CPU time 169.04 seconds
Started Jul 09 05:40:22 PM PDT 24
Finished Jul 09 05:43:12 PM PDT 24
Peak memory 272460 kb
Host smart-23b538f8-25e1-4729-a1eb-8108fdc3d1c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053183898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.2053183898
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.3862160914
Short name T311
Test name
Test status
Simulation time 7349991712 ps
CPU time 41.87 seconds
Started Jul 09 05:40:17 PM PDT 24
Finished Jul 09 05:40:59 PM PDT 24
Peak memory 216276 kb
Host smart-79bea9ac-67c8-4460-af69-83a9ed0df43c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862160914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.3862160914
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.1772972739
Short name T369
Test name
Test status
Simulation time 5688214249 ps
CPU time 17.27 seconds
Started Jul 09 05:40:22 PM PDT 24
Finished Jul 09 05:40:41 PM PDT 24
Peak memory 216316 kb
Host smart-922f2da6-a268-4fe3-ac53-16fa529f318f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772972739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.1772972739
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.902166735
Short name T414
Test name
Test status
Simulation time 51322392 ps
CPU time 1.28 seconds
Started Jul 09 05:40:23 PM PDT 24
Finished Jul 09 05:40:26 PM PDT 24
Peak memory 207980 kb
Host smart-e3483146-6291-44a5-9a9e-fc2cb53e8094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902166735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.902166735
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.693041687
Short name T966
Test name
Test status
Simulation time 370290583 ps
CPU time 0.84 seconds
Started Jul 09 05:40:22 PM PDT 24
Finished Jul 09 05:40:24 PM PDT 24
Peak memory 205980 kb
Host smart-dbc94cb8-d73d-433b-a27b-574608680b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693041687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.693041687
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.1755313328
Short name T527
Test name
Test status
Simulation time 89888419 ps
CPU time 2.43 seconds
Started Jul 09 05:40:22 PM PDT 24
Finished Jul 09 05:40:25 PM PDT 24
Peak memory 224452 kb
Host smart-1053d436-57a0-4284-a567-c42642c06b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755313328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.1755313328
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.2464978122
Short name T24
Test name
Test status
Simulation time 26583301 ps
CPU time 0.72 seconds
Started Jul 09 05:40:22 PM PDT 24
Finished Jul 09 05:40:24 PM PDT 24
Peak memory 204956 kb
Host smart-368a188c-9185-4e66-a960-ab6f1a10dd68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464978122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
2464978122
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.2829053721
Short name T898
Test name
Test status
Simulation time 1052362255 ps
CPU time 5.4 seconds
Started Jul 09 05:40:39 PM PDT 24
Finished Jul 09 05:40:45 PM PDT 24
Peak memory 232684 kb
Host smart-7f7cb3d5-0b00-45ad-86a4-e40bc8036342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829053721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.2829053721
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.445428047
Short name T738
Test name
Test status
Simulation time 21293411 ps
CPU time 0.76 seconds
Started Jul 09 05:40:32 PM PDT 24
Finished Jul 09 05:40:34 PM PDT 24
Peak memory 206920 kb
Host smart-cea6fbf1-7b40-4313-ae64-809c256d60ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445428047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.445428047
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.2737925024
Short name T398
Test name
Test status
Simulation time 35001682368 ps
CPU time 139.3 seconds
Started Jul 09 05:40:24 PM PDT 24
Finished Jul 09 05:42:45 PM PDT 24
Peak memory 253460 kb
Host smart-fcb9b03e-5b4e-489c-8f87-ed23fcc0a608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737925024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.2737925024
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.67487358
Short name T671
Test name
Test status
Simulation time 5700481592 ps
CPU time 54.24 seconds
Started Jul 09 05:40:35 PM PDT 24
Finished Jul 09 05:41:30 PM PDT 24
Peak memory 224636 kb
Host smart-a0947cc5-cf14-4871-b528-6c1ef77c9c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67487358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.67487358
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.2806369602
Short name T960
Test name
Test status
Simulation time 41703997054 ps
CPU time 94.04 seconds
Started Jul 09 05:40:26 PM PDT 24
Finished Jul 09 05:42:00 PM PDT 24
Peak memory 249452 kb
Host smart-2d877f1b-e7ab-4e73-b6bb-37a5c7eaf079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806369602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.2806369602
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.411338388
Short name T660
Test name
Test status
Simulation time 22681594396 ps
CPU time 43.94 seconds
Started Jul 09 05:40:36 PM PDT 24
Finished Jul 09 05:41:21 PM PDT 24
Peak memory 250016 kb
Host smart-dad3f382-6b6d-4730-95dd-1953e5b3094f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411338388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmds
.411338388
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.3617953928
Short name T386
Test name
Test status
Simulation time 8150297536 ps
CPU time 17.26 seconds
Started Jul 09 05:40:40 PM PDT 24
Finished Jul 09 05:40:59 PM PDT 24
Peak memory 232776 kb
Host smart-f3ea86ea-87d1-4d99-86aa-1c325efe58ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617953928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.3617953928
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.3799516109
Short name T523
Test name
Test status
Simulation time 20192956825 ps
CPU time 52.52 seconds
Started Jul 09 05:40:36 PM PDT 24
Finished Jul 09 05:41:29 PM PDT 24
Peak memory 232796 kb
Host smart-ac11e79a-c896-498c-8e65-85c0453eca5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799516109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.3799516109
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.3763843725
Short name T805
Test name
Test status
Simulation time 24587413771 ps
CPU time 17.91 seconds
Started Jul 09 05:40:30 PM PDT 24
Finished Jul 09 05:40:48 PM PDT 24
Peak memory 232732 kb
Host smart-f16f9ae1-fc67-47d8-a41e-de876639782b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763843725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.3763843725
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.3543947140
Short name T182
Test name
Test status
Simulation time 12159100265 ps
CPU time 13 seconds
Started Jul 09 05:40:24 PM PDT 24
Finished Jul 09 05:40:38 PM PDT 24
Peak memory 240724 kb
Host smart-bab87cc8-5046-4bd0-b642-ca1bf60902ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543947140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.3543947140
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.4278095020
Short name T627
Test name
Test status
Simulation time 5030466699 ps
CPU time 20.49 seconds
Started Jul 09 05:40:40 PM PDT 24
Finished Jul 09 05:41:02 PM PDT 24
Peak memory 222452 kb
Host smart-803291e8-b0f3-4d0d-b6bc-0008a5a25a3d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4278095020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.4278095020
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.4014063564
Short name T404
Test name
Test status
Simulation time 40893130 ps
CPU time 0.96 seconds
Started Jul 09 05:40:47 PM PDT 24
Finished Jul 09 05:40:49 PM PDT 24
Peak memory 206660 kb
Host smart-86ec7d4f-d7b5-4c01-8576-4e77d6049aa3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014063564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.4014063564
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.4049105008
Short name T460
Test name
Test status
Simulation time 19149179282 ps
CPU time 26.91 seconds
Started Jul 09 05:40:27 PM PDT 24
Finished Jul 09 05:40:55 PM PDT 24
Peak memory 216432 kb
Host smart-a578f3a0-39af-4b9c-a9c9-510a1f2c1e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049105008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.4049105008
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.3983156739
Short name T561
Test name
Test status
Simulation time 4409546128 ps
CPU time 14.7 seconds
Started Jul 09 05:40:26 PM PDT 24
Finished Jul 09 05:40:42 PM PDT 24
Peak memory 216344 kb
Host smart-115107cf-cb2f-4947-9859-bbac46b4f493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983156739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.3983156739
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.4164604235
Short name T734
Test name
Test status
Simulation time 14394053 ps
CPU time 0.8 seconds
Started Jul 09 05:40:23 PM PDT 24
Finished Jul 09 05:40:25 PM PDT 24
Peak memory 205984 kb
Host smart-812ddb9d-9ce9-4ff9-883d-531babc77447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164604235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.4164604235
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.1435960130
Short name T586
Test name
Test status
Simulation time 14437721 ps
CPU time 0.71 seconds
Started Jul 09 05:40:32 PM PDT 24
Finished Jul 09 05:40:33 PM PDT 24
Peak memory 205648 kb
Host smart-eff365ce-2de7-42fd-b9fc-d797f6fe7ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435960130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.1435960130
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.2839815704
Short name T187
Test name
Test status
Simulation time 23869126978 ps
CPU time 14.62 seconds
Started Jul 09 05:40:27 PM PDT 24
Finished Jul 09 05:40:42 PM PDT 24
Peak memory 224556 kb
Host smart-00649d4b-3319-4a75-a28e-12a954bc2c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839815704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.2839815704
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.3586865870
Short name T780
Test name
Test status
Simulation time 12039622 ps
CPU time 0.73 seconds
Started Jul 09 05:40:28 PM PDT 24
Finished Jul 09 05:40:29 PM PDT 24
Peak memory 205844 kb
Host smart-7c607d08-0009-4513-8608-6c4727c3cd18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586865870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
3586865870
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.4103986242
Short name T354
Test name
Test status
Simulation time 233879283 ps
CPU time 4.38 seconds
Started Jul 09 05:40:31 PM PDT 24
Finished Jul 09 05:40:36 PM PDT 24
Peak memory 224392 kb
Host smart-d0805226-b8a9-40ab-b24f-23970fa625f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103986242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.4103986242
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.3288522314
Short name T482
Test name
Test status
Simulation time 67873197 ps
CPU time 0.8 seconds
Started Jul 09 05:40:30 PM PDT 24
Finished Jul 09 05:40:31 PM PDT 24
Peak memory 205604 kb
Host smart-11ab6559-ef2d-47e5-9107-7fdb3f6e1e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288522314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.3288522314
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.1152100010
Short name T989
Test name
Test status
Simulation time 29271524211 ps
CPU time 174.98 seconds
Started Jul 09 05:40:34 PM PDT 24
Finished Jul 09 05:43:30 PM PDT 24
Peak memory 252844 kb
Host smart-6508663b-e7c5-41d3-ac8d-b8aa594c7983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152100010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.1152100010
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.603440228
Short name T138
Test name
Test status
Simulation time 3386170254 ps
CPU time 50.69 seconds
Started Jul 09 05:40:29 PM PDT 24
Finished Jul 09 05:41:21 PM PDT 24
Peak memory 250552 kb
Host smart-f7968b5c-f8c4-463e-a4e0-1e67d50c7ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603440228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.603440228
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.3303118790
Short name T716
Test name
Test status
Simulation time 174429538996 ps
CPU time 243.19 seconds
Started Jul 09 05:40:24 PM PDT 24
Finished Jul 09 05:44:28 PM PDT 24
Peak memory 257464 kb
Host smart-2310cbbf-1ec0-4b2c-afa4-feb6e085ef19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303118790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.3303118790
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.1490862185
Short name T9
Test name
Test status
Simulation time 1672869654 ps
CPU time 6.17 seconds
Started Jul 09 05:40:24 PM PDT 24
Finished Jul 09 05:40:31 PM PDT 24
Peak memory 232712 kb
Host smart-444bd646-666d-4086-bb45-4248d5309fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490862185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.1490862185
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.32623916
Short name T789
Test name
Test status
Simulation time 120144956 ps
CPU time 2.62 seconds
Started Jul 09 05:40:32 PM PDT 24
Finished Jul 09 05:40:36 PM PDT 24
Peak memory 232308 kb
Host smart-97756c6a-4433-44b3-8e37-2ad3973c752d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32623916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.32623916
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.4005194872
Short name T923
Test name
Test status
Simulation time 96082701 ps
CPU time 2.71 seconds
Started Jul 09 05:40:23 PM PDT 24
Finished Jul 09 05:40:26 PM PDT 24
Peak memory 232640 kb
Host smart-ee3ad3c7-a324-4e85-b6ca-df521c79794f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005194872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.4005194872
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.3401661781
Short name T290
Test name
Test status
Simulation time 3495719443 ps
CPU time 10.09 seconds
Started Jul 09 05:40:29 PM PDT 24
Finished Jul 09 05:40:40 PM PDT 24
Peak memory 240704 kb
Host smart-883db2d3-fb47-44e6-be9e-ee0f2daf6963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401661781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.3401661781
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.4187317109
Short name T855
Test name
Test status
Simulation time 1251972698 ps
CPU time 3.82 seconds
Started Jul 09 05:40:25 PM PDT 24
Finished Jul 09 05:40:29 PM PDT 24
Peak memory 224468 kb
Host smart-e144f821-08b2-4d5d-b5e7-3728d791da0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187317109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.4187317109
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.3133112287
Short name T585
Test name
Test status
Simulation time 4022280205 ps
CPU time 10.05 seconds
Started Jul 09 05:40:36 PM PDT 24
Finished Jul 09 05:40:46 PM PDT 24
Peak memory 220348 kb
Host smart-e00b05e9-9d63-452b-98f2-955bef38b918
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3133112287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.3133112287
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.4123099381
Short name T974
Test name
Test status
Simulation time 5318591866 ps
CPU time 89.63 seconds
Started Jul 09 05:40:29 PM PDT 24
Finished Jul 09 05:42:00 PM PDT 24
Peak memory 249496 kb
Host smart-6e04b45b-bd20-487b-a10f-60ef05c7b3fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123099381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.4123099381
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.1699274629
Short name T439
Test name
Test status
Simulation time 1874064966 ps
CPU time 12.27 seconds
Started Jul 09 05:40:32 PM PDT 24
Finished Jul 09 05:40:45 PM PDT 24
Peak memory 216480 kb
Host smart-4d401b84-3a54-43a6-ad64-a4fea51d372f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699274629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.1699274629
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.315333349
Short name T664
Test name
Test status
Simulation time 7097404096 ps
CPU time 21.89 seconds
Started Jul 09 05:40:27 PM PDT 24
Finished Jul 09 05:40:50 PM PDT 24
Peak memory 216316 kb
Host smart-30a063d3-07b9-43b2-adcd-a718b8727063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315333349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.315333349
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.3334050778
Short name T101
Test name
Test status
Simulation time 165488773 ps
CPU time 4.62 seconds
Started Jul 09 05:40:31 PM PDT 24
Finished Jul 09 05:40:36 PM PDT 24
Peak memory 216160 kb
Host smart-348c6396-4384-4b6b-ba79-c5b3c0151179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334050778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.3334050778
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.2313044536
Short name T654
Test name
Test status
Simulation time 32703595 ps
CPU time 0.76 seconds
Started Jul 09 05:40:30 PM PDT 24
Finished Jul 09 05:40:32 PM PDT 24
Peak memory 205988 kb
Host smart-8b4b1b3b-62dc-4deb-be7a-d2b222fa5fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313044536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.2313044536
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.1045730911
Short name T737
Test name
Test status
Simulation time 237470753 ps
CPU time 4.1 seconds
Started Jul 09 05:40:25 PM PDT 24
Finished Jul 09 05:40:30 PM PDT 24
Peak memory 224468 kb
Host smart-c4961623-8344-469f-83a7-ab8bd13242e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045730911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.1045730911
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.206950444
Short name T926
Test name
Test status
Simulation time 13801535 ps
CPU time 0.73 seconds
Started Jul 09 05:40:38 PM PDT 24
Finished Jul 09 05:40:40 PM PDT 24
Peak memory 204992 kb
Host smart-c6c7fd08-56a9-4627-9a72-fb394acb3414
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206950444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.206950444
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.1237814104
Short name T910
Test name
Test status
Simulation time 3749200470 ps
CPU time 30.43 seconds
Started Jul 09 05:40:34 PM PDT 24
Finished Jul 09 05:41:05 PM PDT 24
Peak memory 232720 kb
Host smart-a0ddc29d-aa2f-4dc1-af01-4db00251d8d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237814104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.1237814104
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.2863017746
Short name T905
Test name
Test status
Simulation time 25357721 ps
CPU time 0.77 seconds
Started Jul 09 05:40:35 PM PDT 24
Finished Jul 09 05:40:37 PM PDT 24
Peak memory 206636 kb
Host smart-be9f9d64-9e16-4a32-a166-3887f9b34464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863017746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.2863017746
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.1750644448
Short name T212
Test name
Test status
Simulation time 70378800486 ps
CPU time 494.03 seconds
Started Jul 09 05:40:40 PM PDT 24
Finished Jul 09 05:48:55 PM PDT 24
Peak memory 254844 kb
Host smart-c80d97eb-3f55-4451-803c-a978e5755daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750644448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.1750644448
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.2876652219
Short name T678
Test name
Test status
Simulation time 5862478678 ps
CPU time 90.01 seconds
Started Jul 09 05:40:35 PM PDT 24
Finished Jul 09 05:42:06 PM PDT 24
Peak memory 249468 kb
Host smart-8d933581-f954-4748-9c30-49cf01ee5827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876652219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.2876652219
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.1761666014
Short name T223
Test name
Test status
Simulation time 16648155474 ps
CPU time 55.37 seconds
Started Jul 09 05:40:34 PM PDT 24
Finished Jul 09 05:41:30 PM PDT 24
Peak memory 232796 kb
Host smart-428244dc-4f9e-4726-bcbe-7976bd89e33c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761666014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.1761666014
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.2370540582
Short name T299
Test name
Test status
Simulation time 4501535001 ps
CPU time 5.75 seconds
Started Jul 09 05:40:34 PM PDT 24
Finished Jul 09 05:40:40 PM PDT 24
Peak memory 224576 kb
Host smart-53ee2032-1980-4685-ac40-b11132ba2a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370540582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.2370540582
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.317290511
Short name T179
Test name
Test status
Simulation time 176137157989 ps
CPU time 237.25 seconds
Started Jul 09 05:40:45 PM PDT 24
Finished Jul 09 05:44:43 PM PDT 24
Peak memory 256780 kb
Host smart-cc493af6-4cb5-4852-83f6-6504bceb7673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317290511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmds
.317290511
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.3220830447
Short name T752
Test name
Test status
Simulation time 204176972 ps
CPU time 2.29 seconds
Started Jul 09 05:40:35 PM PDT 24
Finished Jul 09 05:40:38 PM PDT 24
Peak memory 223044 kb
Host smart-63634d83-d018-4557-8abf-810cbaa46d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220830447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.3220830447
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.2466833430
Short name T917
Test name
Test status
Simulation time 6560506149 ps
CPU time 20.99 seconds
Started Jul 09 05:40:41 PM PDT 24
Finished Jul 09 05:41:04 PM PDT 24
Peak memory 240484 kb
Host smart-18d3025b-9c68-4f80-a900-8be929566f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466833430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.2466833430
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.2589110553
Short name T347
Test name
Test status
Simulation time 123300825 ps
CPU time 2.21 seconds
Started Jul 09 05:40:33 PM PDT 24
Finished Jul 09 05:40:35 PM PDT 24
Peak memory 232324 kb
Host smart-9e44c426-95b5-4e31-9394-575915189b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589110553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.2589110553
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.3404072058
Short name T772
Test name
Test status
Simulation time 34157166 ps
CPU time 2.53 seconds
Started Jul 09 05:40:35 PM PDT 24
Finished Jul 09 05:40:38 PM PDT 24
Peak memory 232276 kb
Host smart-3c290bf8-4f89-4184-950b-586b8aaec345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404072058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.3404072058
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.1015632494
Short name T534
Test name
Test status
Simulation time 952064534 ps
CPU time 6.04 seconds
Started Jul 09 05:40:54 PM PDT 24
Finished Jul 09 05:41:01 PM PDT 24
Peak memory 223032 kb
Host smart-b93db429-8df1-4093-b805-955bbfa2f0fa
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1015632494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.1015632494
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.689432037
Short name T165
Test name
Test status
Simulation time 38288585592 ps
CPU time 116.07 seconds
Started Jul 09 05:40:42 PM PDT 24
Finished Jul 09 05:42:39 PM PDT 24
Peak memory 249320 kb
Host smart-789b1477-9057-4108-9e5b-1647b47037ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689432037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stres
s_all.689432037
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.59872780
Short name T756
Test name
Test status
Simulation time 5550515476 ps
CPU time 12.94 seconds
Started Jul 09 05:40:37 PM PDT 24
Finished Jul 09 05:40:52 PM PDT 24
Peak memory 216396 kb
Host smart-c21f48d7-ebc4-49a0-ba66-1c8a3924a9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59872780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.59872780
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.3705645815
Short name T75
Test name
Test status
Simulation time 271329279 ps
CPU time 1.55 seconds
Started Jul 09 05:40:37 PM PDT 24
Finished Jul 09 05:40:40 PM PDT 24
Peak memory 207004 kb
Host smart-56ffbfba-e10f-4822-b8ce-1dd7a7476861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705645815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.3705645815
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.4139205351
Short name T28
Test name
Test status
Simulation time 175462009 ps
CPU time 2.42 seconds
Started Jul 09 05:40:26 PM PDT 24
Finished Jul 09 05:40:30 PM PDT 24
Peak memory 216260 kb
Host smart-51b01188-be2c-4905-8247-b05412f8f3c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139205351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.4139205351
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.3494805403
Short name T646
Test name
Test status
Simulation time 189010962 ps
CPU time 0.88 seconds
Started Jul 09 05:40:40 PM PDT 24
Finished Jul 09 05:40:42 PM PDT 24
Peak memory 205960 kb
Host smart-8f70fac2-b0d1-4daf-93a3-d00d0eebf2a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494805403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.3494805403
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.2572527454
Short name T809
Test name
Test status
Simulation time 2295391163 ps
CPU time 10.42 seconds
Started Jul 09 05:40:36 PM PDT 24
Finished Jul 09 05:40:47 PM PDT 24
Peak memory 232796 kb
Host smart-a30fb000-7de0-4a95-96cb-efcdba657312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572527454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.2572527454
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.1647866052
Short name T26
Test name
Test status
Simulation time 13582946 ps
CPU time 0.7 seconds
Started Jul 09 05:40:40 PM PDT 24
Finished Jul 09 05:40:42 PM PDT 24
Peak memory 205512 kb
Host smart-0268bf4c-582d-4fc2-8ff3-94f77d0ba4e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647866052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
1647866052
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.1740636365
Short name T673
Test name
Test status
Simulation time 1463658405 ps
CPU time 12.05 seconds
Started Jul 09 05:40:35 PM PDT 24
Finished Jul 09 05:40:48 PM PDT 24
Peak memory 232624 kb
Host smart-bffc622d-a6c1-4a07-bf5f-a5a500fa5eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740636365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.1740636365
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.1521954181
Short name T836
Test name
Test status
Simulation time 166405886 ps
CPU time 0.78 seconds
Started Jul 09 05:40:36 PM PDT 24
Finished Jul 09 05:40:38 PM PDT 24
Peak memory 206912 kb
Host smart-fbb5e813-676b-454d-b33a-9ce77571ebbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521954181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.1521954181
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.79103699
Short name T663
Test name
Test status
Simulation time 22630328875 ps
CPU time 188.89 seconds
Started Jul 09 05:40:43 PM PDT 24
Finished Jul 09 05:43:53 PM PDT 24
Peak memory 252148 kb
Host smart-28902265-d577-4045-9a57-ccfa7ff60c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79103699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.79103699
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.1822625162
Short name T264
Test name
Test status
Simulation time 6821248053 ps
CPU time 48.03 seconds
Started Jul 09 05:40:38 PM PDT 24
Finished Jul 09 05:41:28 PM PDT 24
Peak memory 249272 kb
Host smart-51c9bd59-5c27-4408-8cc4-c27770040143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822625162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.1822625162
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.3377656635
Short name T694
Test name
Test status
Simulation time 39916493668 ps
CPU time 83.28 seconds
Started Jul 09 05:40:49 PM PDT 24
Finished Jul 09 05:42:14 PM PDT 24
Peak memory 249276 kb
Host smart-e22955f1-4d0b-4a8a-8441-659e9255232f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377656635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.3377656635
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.3489169236
Short name T553
Test name
Test status
Simulation time 892679765 ps
CPU time 9.21 seconds
Started Jul 09 05:40:42 PM PDT 24
Finished Jul 09 05:40:52 PM PDT 24
Peak memory 233740 kb
Host smart-837e2fef-29e4-49ef-8628-6a14aef7f152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489169236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.3489169236
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.961952135
Short name T834
Test name
Test status
Simulation time 1175246467 ps
CPU time 22.22 seconds
Started Jul 09 05:40:37 PM PDT 24
Finished Jul 09 05:41:01 PM PDT 24
Peak memory 233940 kb
Host smart-cadc47a8-1067-4113-a42d-0e117fb829c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961952135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmds
.961952135
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.1080221423
Short name T945
Test name
Test status
Simulation time 139579900 ps
CPU time 2.6 seconds
Started Jul 09 05:40:43 PM PDT 24
Finished Jul 09 05:40:47 PM PDT 24
Peak memory 232712 kb
Host smart-3653510c-ac3b-48cb-b10e-5777d88a5b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080221423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.1080221423
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.4206451275
Short name T700
Test name
Test status
Simulation time 37822478698 ps
CPU time 64.81 seconds
Started Jul 09 05:40:42 PM PDT 24
Finished Jul 09 05:41:48 PM PDT 24
Peak memory 240684 kb
Host smart-d23d63f1-8791-48bf-acb0-3cbf740d6a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206451275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.4206451275
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.1287052317
Short name T197
Test name
Test status
Simulation time 219244980 ps
CPU time 4.92 seconds
Started Jul 09 05:40:39 PM PDT 24
Finished Jul 09 05:40:45 PM PDT 24
Peak memory 232612 kb
Host smart-0e01c203-7900-45da-a6ea-359d688289a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287052317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.1287052317
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.3496913898
Short name T587
Test name
Test status
Simulation time 1348297113 ps
CPU time 5.6 seconds
Started Jul 09 05:40:44 PM PDT 24
Finished Jul 09 05:40:51 PM PDT 24
Peak memory 224504 kb
Host smart-5b678241-7714-46a8-a8e5-5322e342a99a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496913898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.3496913898
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.2859347943
Short name T600
Test name
Test status
Simulation time 1630868317 ps
CPU time 6.72 seconds
Started Jul 09 05:40:40 PM PDT 24
Finished Jul 09 05:40:48 PM PDT 24
Peak memory 222624 kb
Host smart-1ab6ab85-8fa6-4368-be06-32876e1b6ea6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2859347943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.2859347943
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.1976931915
Short name T484
Test name
Test status
Simulation time 3236508949 ps
CPU time 23 seconds
Started Jul 09 05:40:36 PM PDT 24
Finished Jul 09 05:40:59 PM PDT 24
Peak memory 217908 kb
Host smart-ed28fb6f-071a-46b4-b8b3-39a0767a2323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976931915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.1976931915
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.858827919
Short name T443
Test name
Test status
Simulation time 806075115 ps
CPU time 5.09 seconds
Started Jul 09 05:40:42 PM PDT 24
Finished Jul 09 05:40:49 PM PDT 24
Peak memory 216208 kb
Host smart-5f25feea-0250-496c-bcd1-bdbb1e5f74ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858827919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.858827919
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.2906120593
Short name T971
Test name
Test status
Simulation time 123828440 ps
CPU time 2.6 seconds
Started Jul 09 05:40:41 PM PDT 24
Finished Jul 09 05:40:46 PM PDT 24
Peak memory 216152 kb
Host smart-119c2372-eb31-468a-aa87-9f0509829ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906120593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.2906120593
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.618483083
Short name T447
Test name
Test status
Simulation time 74151339 ps
CPU time 0.75 seconds
Started Jul 09 05:40:37 PM PDT 24
Finished Jul 09 05:40:39 PM PDT 24
Peak memory 205924 kb
Host smart-5110a443-ec46-49cc-91de-c67c3814836a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618483083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.618483083
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.2191368325
Short name T206
Test name
Test status
Simulation time 6100611143 ps
CPU time 8.39 seconds
Started Jul 09 05:40:43 PM PDT 24
Finished Jul 09 05:40:52 PM PDT 24
Peak memory 224576 kb
Host smart-3a3070e5-f2a8-433e-8da7-3224c5c17bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191368325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.2191368325
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.2986908011
Short name T708
Test name
Test status
Simulation time 28600803 ps
CPU time 0.79 seconds
Started Jul 09 05:40:52 PM PDT 24
Finished Jul 09 05:40:54 PM PDT 24
Peak memory 204900 kb
Host smart-7a2efb82-4a74-4857-b176-c08a06b765b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986908011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
2986908011
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.1101661230
Short name T564
Test name
Test status
Simulation time 171551192 ps
CPU time 3.92 seconds
Started Jul 09 05:40:46 PM PDT 24
Finished Jul 09 05:40:50 PM PDT 24
Peak memory 232672 kb
Host smart-ca6bfa2d-ac38-47f8-a9bf-7776355ecf8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101661230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.1101661230
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.2680338286
Short name T819
Test name
Test status
Simulation time 14558083 ps
CPU time 0.78 seconds
Started Jul 09 05:40:38 PM PDT 24
Finished Jul 09 05:40:40 PM PDT 24
Peak memory 206888 kb
Host smart-373d03c3-c83b-46d4-91bb-0223c886be44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680338286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.2680338286
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.2911984011
Short name T1013
Test name
Test status
Simulation time 41050684258 ps
CPU time 268.18 seconds
Started Jul 09 05:40:37 PM PDT 24
Finished Jul 09 05:45:06 PM PDT 24
Peak memory 257384 kb
Host smart-9df96ec9-733a-4e93-a215-cd67986b038b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911984011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.2911984011
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.2917425363
Short name T245
Test name
Test status
Simulation time 41283231992 ps
CPU time 225.81 seconds
Started Jul 09 05:40:42 PM PDT 24
Finished Jul 09 05:44:29 PM PDT 24
Peak memory 265160 kb
Host smart-47d23299-3e9a-436a-9236-8f130d9c94b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917425363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.2917425363
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.3608412158
Short name T30
Test name
Test status
Simulation time 19690935279 ps
CPU time 168.21 seconds
Started Jul 09 05:40:41 PM PDT 24
Finished Jul 09 05:43:31 PM PDT 24
Peak memory 249248 kb
Host smart-0035502f-9d1b-4167-9d15-e707a073e5a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608412158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.3608412158
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.4253505794
Short name T487
Test name
Test status
Simulation time 1305383132 ps
CPU time 25.58 seconds
Started Jul 09 05:40:41 PM PDT 24
Finished Jul 09 05:41:09 PM PDT 24
Peak memory 249096 kb
Host smart-f8bc3be1-70a0-459f-9f00-efb6dd6535cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253505794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.4253505794
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.4151557987
Short name T714
Test name
Test status
Simulation time 11682735387 ps
CPU time 63.48 seconds
Started Jul 09 05:40:44 PM PDT 24
Finished Jul 09 05:41:48 PM PDT 24
Peak memory 249212 kb
Host smart-12d0e1b9-e8a3-41c6-897b-ce4c1292c3b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151557987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmd
s.4151557987
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.3129874485
Short name T591
Test name
Test status
Simulation time 158436996 ps
CPU time 2.02 seconds
Started Jul 09 05:40:40 PM PDT 24
Finished Jul 09 05:40:44 PM PDT 24
Peak memory 223844 kb
Host smart-207236f3-9669-46f5-9e30-43546991a4ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129874485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.3129874485
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.3510378242
Short name T464
Test name
Test status
Simulation time 2426748330 ps
CPU time 19.34 seconds
Started Jul 09 05:40:45 PM PDT 24
Finished Jul 09 05:41:05 PM PDT 24
Peak memory 232820 kb
Host smart-31e9da53-b1fd-4c23-aea7-6f45d9f96d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510378242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.3510378242
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.1946162872
Short name T221
Test name
Test status
Simulation time 1774661348 ps
CPU time 9.03 seconds
Started Jul 09 05:40:42 PM PDT 24
Finished Jul 09 05:40:52 PM PDT 24
Peak memory 232624 kb
Host smart-bef42d21-49e3-4ba1-b845-7dee7cb3e311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946162872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.1946162872
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.163524017
Short name T868
Test name
Test status
Simulation time 302404562 ps
CPU time 3.53 seconds
Started Jul 09 05:40:44 PM PDT 24
Finished Jul 09 05:40:49 PM PDT 24
Peak memory 232640 kb
Host smart-6521ec8a-0460-4e8a-893c-378d0047d236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163524017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.163524017
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.1383876557
Short name T927
Test name
Test status
Simulation time 3053264146 ps
CPU time 9.94 seconds
Started Jul 09 05:40:42 PM PDT 24
Finished Jul 09 05:40:53 PM PDT 24
Peak memory 220796 kb
Host smart-8ab91d79-1f54-465a-8487-f5f3090cc8c8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1383876557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.1383876557
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.3879678842
Short name T228
Test name
Test status
Simulation time 46039825490 ps
CPU time 373.65 seconds
Started Jul 09 05:40:41 PM PDT 24
Finished Jul 09 05:46:56 PM PDT 24
Peak memory 273836 kb
Host smart-5dccb1e3-42db-4b3d-83e5-d3b435ce8ee7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879678842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.3879678842
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.2225598648
Short name T582
Test name
Test status
Simulation time 225189036 ps
CPU time 2.93 seconds
Started Jul 09 05:40:40 PM PDT 24
Finished Jul 09 05:40:44 PM PDT 24
Peak memory 216456 kb
Host smart-17a0642a-2afb-4daf-ab83-cc1bf5638d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225598648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.2225598648
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.1594112064
Short name T709
Test name
Test status
Simulation time 2101787585 ps
CPU time 6.87 seconds
Started Jul 09 05:40:38 PM PDT 24
Finished Jul 09 05:40:46 PM PDT 24
Peak memory 216232 kb
Host smart-914e75f5-4f74-4a5e-b7f8-94659480e5f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594112064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.1594112064
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.703982431
Short name T623
Test name
Test status
Simulation time 16034607 ps
CPU time 0.77 seconds
Started Jul 09 05:40:36 PM PDT 24
Finished Jul 09 05:40:37 PM PDT 24
Peak memory 205992 kb
Host smart-bafa7c87-a79e-4d0a-ba27-a723b874077b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703982431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.703982431
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.3711037146
Short name T355
Test name
Test status
Simulation time 137558633 ps
CPU time 0.79 seconds
Started Jul 09 05:40:40 PM PDT 24
Finished Jul 09 05:40:42 PM PDT 24
Peak memory 205964 kb
Host smart-61ec5824-1ddb-404c-a30c-eba41278e3a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711037146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.3711037146
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.3849104122
Short name T940
Test name
Test status
Simulation time 6376459006 ps
CPU time 21.42 seconds
Started Jul 09 05:40:44 PM PDT 24
Finished Jul 09 05:41:06 PM PDT 24
Peak memory 240988 kb
Host smart-faa52e32-61fb-4ccc-960c-c46429e64488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849104122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.3849104122
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.571693647
Short name T1008
Test name
Test status
Simulation time 56935446 ps
CPU time 0.71 seconds
Started Jul 09 05:40:48 PM PDT 24
Finished Jul 09 05:40:50 PM PDT 24
Peak memory 205508 kb
Host smart-dfed2461-74ce-454b-af40-95b0c1d91ac5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571693647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.571693647
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.355553973
Short name T976
Test name
Test status
Simulation time 2752451655 ps
CPU time 3.58 seconds
Started Jul 09 05:40:53 PM PDT 24
Finished Jul 09 05:40:57 PM PDT 24
Peak memory 224596 kb
Host smart-d0625e36-c9b8-406d-ae3f-e3fdeb92aa2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355553973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.355553973
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.1472501395
Short name T568
Test name
Test status
Simulation time 68761629 ps
CPU time 0.8 seconds
Started Jul 09 05:40:53 PM PDT 24
Finished Jul 09 05:40:55 PM PDT 24
Peak memory 206552 kb
Host smart-8ee362b7-972e-4d62-babb-7cc2c1d13894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472501395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.1472501395
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.2543023214
Short name T811
Test name
Test status
Simulation time 17617366680 ps
CPU time 87.38 seconds
Started Jul 09 05:40:38 PM PDT 24
Finished Jul 09 05:42:07 PM PDT 24
Peak memory 257380 kb
Host smart-30a62ecb-f089-4d3d-8c84-cf720822da71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543023214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.2543023214
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.763493167
Short name T59
Test name
Test status
Simulation time 36568562886 ps
CPU time 282.87 seconds
Started Jul 09 05:40:40 PM PDT 24
Finished Jul 09 05:45:24 PM PDT 24
Peak memory 249280 kb
Host smart-ec434904-fe61-46d0-8168-74d5b8327af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763493167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.763493167
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.3847551924
Short name T373
Test name
Test status
Simulation time 43289994965 ps
CPU time 91.53 seconds
Started Jul 09 05:40:45 PM PDT 24
Finished Jul 09 05:42:18 PM PDT 24
Peak memory 250880 kb
Host smart-da063dfc-973b-4876-835c-58bd3a2eec14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847551924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.3847551924
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.3651349939
Short name T293
Test name
Test status
Simulation time 1287596788 ps
CPU time 17.05 seconds
Started Jul 09 05:40:46 PM PDT 24
Finished Jul 09 05:41:04 PM PDT 24
Peak memory 232168 kb
Host smart-5de807f4-6bb6-4aa1-8e2d-48f625965b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651349939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.3651349939
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.3425572497
Short name T741
Test name
Test status
Simulation time 20175036647 ps
CPU time 40.94 seconds
Started Jul 09 05:40:38 PM PDT 24
Finished Jul 09 05:41:21 PM PDT 24
Peak memory 240992 kb
Host smart-226d1f15-9ef1-406a-813a-0180f8163215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425572497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmd
s.3425572497
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.3541113912
Short name T750
Test name
Test status
Simulation time 659933446 ps
CPU time 6.3 seconds
Started Jul 09 05:40:45 PM PDT 24
Finished Jul 09 05:40:52 PM PDT 24
Peak memory 232620 kb
Host smart-cdfd0b95-971a-4fd3-995d-91491e57c564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541113912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.3541113912
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.3494680228
Short name T796
Test name
Test status
Simulation time 1801546236 ps
CPU time 16.79 seconds
Started Jul 09 05:40:49 PM PDT 24
Finished Jul 09 05:41:07 PM PDT 24
Peak memory 232712 kb
Host smart-1241edeb-a84d-4e6d-aaf5-bde06fd06de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494680228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.3494680228
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.1349081697
Short name T505
Test name
Test status
Simulation time 1268808043 ps
CPU time 5.56 seconds
Started Jul 09 05:40:35 PM PDT 24
Finished Jul 09 05:40:42 PM PDT 24
Peak memory 224496 kb
Host smart-09e66cc2-75ce-4291-81f8-d557f9979683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349081697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.1349081697
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.123676963
Short name T532
Test name
Test status
Simulation time 806378485 ps
CPU time 4.03 seconds
Started Jul 09 05:40:44 PM PDT 24
Finished Jul 09 05:40:49 PM PDT 24
Peak memory 232648 kb
Host smart-de6730ca-6afc-436f-b40c-46ccc0ac5241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123676963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.123676963
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.862821609
Short name T469
Test name
Test status
Simulation time 348705083 ps
CPU time 6.83 seconds
Started Jul 09 05:40:53 PM PDT 24
Finished Jul 09 05:41:00 PM PDT 24
Peak memory 223120 kb
Host smart-ab73bd1c-4d92-443f-a747-0b0e3c2133c6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=862821609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dire
ct.862821609
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.3333220959
Short name T972
Test name
Test status
Simulation time 30500121282 ps
CPU time 182.58 seconds
Started Jul 09 05:40:54 PM PDT 24
Finished Jul 09 05:43:58 PM PDT 24
Peak memory 255036 kb
Host smart-3b619411-d3d2-4152-9d95-3feeafe1bc77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333220959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.3333220959
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.1307166019
Short name T393
Test name
Test status
Simulation time 47764716921 ps
CPU time 38.12 seconds
Started Jul 09 05:40:48 PM PDT 24
Finished Jul 09 05:41:27 PM PDT 24
Peak memory 216340 kb
Host smart-f5660207-adfa-4921-a1ab-6d8807c82207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307166019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.1307166019
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.3469913815
Short name T470
Test name
Test status
Simulation time 19962263298 ps
CPU time 9.46 seconds
Started Jul 09 05:40:40 PM PDT 24
Finished Jul 09 05:40:51 PM PDT 24
Peak memory 216380 kb
Host smart-31e022b8-188c-49db-9182-13e6f38a5c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469913815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.3469913815
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.384390372
Short name T372
Test name
Test status
Simulation time 59949805 ps
CPU time 1.27 seconds
Started Jul 09 05:40:47 PM PDT 24
Finished Jul 09 05:40:49 PM PDT 24
Peak memory 216064 kb
Host smart-f0051cda-47b8-46ae-9cdd-bbbe21b8828f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384390372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.384390372
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.1736346568
Short name T8
Test name
Test status
Simulation time 47968632 ps
CPU time 0.79 seconds
Started Jul 09 05:40:45 PM PDT 24
Finished Jul 09 05:40:47 PM PDT 24
Peak memory 205952 kb
Host smart-69adc4e4-f78a-4ae2-9dd9-7fea47c2afbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736346568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.1736346568
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.705919961
Short name T641
Test name
Test status
Simulation time 162574353 ps
CPU time 2.86 seconds
Started Jul 09 05:40:46 PM PDT 24
Finished Jul 09 05:40:49 PM PDT 24
Peak memory 224416 kb
Host smart-830cd975-8e2c-4dfb-8cf9-61dfdd0021fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705919961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.705919961
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.3818564841
Short name T657
Test name
Test status
Simulation time 184010473 ps
CPU time 0.72 seconds
Started Jul 09 05:40:43 PM PDT 24
Finished Jul 09 05:40:45 PM PDT 24
Peak memory 205880 kb
Host smart-e8c597e4-86ef-43e1-ba9c-a99088bd4e97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818564841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
3818564841
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.2419854458
Short name T597
Test name
Test status
Simulation time 2509216451 ps
CPU time 6.54 seconds
Started Jul 09 05:40:52 PM PDT 24
Finished Jul 09 05:41:00 PM PDT 24
Peak memory 232800 kb
Host smart-d812261e-ca66-4d5f-b93d-a4b91ce12758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419854458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.2419854458
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.1898832831
Short name T377
Test name
Test status
Simulation time 35877118 ps
CPU time 0.73 seconds
Started Jul 09 05:40:42 PM PDT 24
Finished Jul 09 05:40:44 PM PDT 24
Peak memory 205852 kb
Host smart-75da2ac6-d55d-4be5-954a-7947692fbf9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898832831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.1898832831
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.4080924279
Short name T682
Test name
Test status
Simulation time 19044696873 ps
CPU time 38.23 seconds
Started Jul 09 05:40:50 PM PDT 24
Finished Jul 09 05:41:30 PM PDT 24
Peak memory 237308 kb
Host smart-0dd12205-9b2b-48f4-a912-cd8b54e0fab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080924279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.4080924279
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.3550790634
Short name T303
Test name
Test status
Simulation time 7465411976 ps
CPU time 29.38 seconds
Started Jul 09 05:40:49 PM PDT 24
Finished Jul 09 05:41:20 PM PDT 24
Peak memory 241080 kb
Host smart-2d537012-528b-421e-aac6-dcba67bc56bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550790634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.3550790634
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.1853411745
Short name T830
Test name
Test status
Simulation time 40781239562 ps
CPU time 84.94 seconds
Started Jul 09 05:40:46 PM PDT 24
Finished Jul 09 05:42:12 PM PDT 24
Peak memory 249904 kb
Host smart-943e5eba-67e1-4d9e-b4ac-c15886bfc47a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853411745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.1853411745
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.3341673298
Short name T617
Test name
Test status
Simulation time 757082664 ps
CPU time 16.62 seconds
Started Jul 09 05:40:46 PM PDT 24
Finished Jul 09 05:41:04 PM PDT 24
Peak memory 232656 kb
Host smart-3f770d4a-db39-4610-97a1-489b2a48f7ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341673298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.3341673298
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.1946253885
Short name T201
Test name
Test status
Simulation time 6453648706 ps
CPU time 14.26 seconds
Started Jul 09 05:40:44 PM PDT 24
Finished Jul 09 05:40:59 PM PDT 24
Peak memory 232748 kb
Host smart-715b9088-08a1-4a59-a9fd-658f1f7ca14d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946253885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.1946253885
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.3044396124
Short name T559
Test name
Test status
Simulation time 1315241951 ps
CPU time 6.28 seconds
Started Jul 09 05:40:46 PM PDT 24
Finished Jul 09 05:40:54 PM PDT 24
Peak memory 232600 kb
Host smart-2a416a7d-1a5e-4261-be56-68440d6179b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044396124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.3044396124
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.1725731695
Short name T246
Test name
Test status
Simulation time 1137974142 ps
CPU time 5.57 seconds
Started Jul 09 05:40:50 PM PDT 24
Finished Jul 09 05:40:57 PM PDT 24
Peak memory 224500 kb
Host smart-e0892724-53e5-4f03-bf40-7684dd44f0ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725731695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.1725731695
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.3784592559
Short name T848
Test name
Test status
Simulation time 9476001885 ps
CPU time 9.72 seconds
Started Jul 09 05:40:50 PM PDT 24
Finished Jul 09 05:41:01 PM PDT 24
Peak memory 232772 kb
Host smart-b2bc8efd-1d73-4926-9923-e6f3c259a28d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784592559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.3784592559
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.283234533
Short name T762
Test name
Test status
Simulation time 657831774 ps
CPU time 5.55 seconds
Started Jul 09 05:40:45 PM PDT 24
Finished Jul 09 05:40:51 PM PDT 24
Peak memory 222908 kb
Host smart-dd8c8e2e-d0f5-43e0-96f9-34ce73e1395c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=283234533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dire
ct.283234533
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.3168508644
Short name T164
Test name
Test status
Simulation time 72182032 ps
CPU time 1.11 seconds
Started Jul 09 05:40:51 PM PDT 24
Finished Jul 09 05:40:54 PM PDT 24
Peak memory 206896 kb
Host smart-0d7f50f6-7695-4b35-8b1c-e5c4b8ff243e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168508644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.3168508644
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.4274199185
Short name T766
Test name
Test status
Simulation time 3687582521 ps
CPU time 23.07 seconds
Started Jul 09 05:40:48 PM PDT 24
Finished Jul 09 05:41:12 PM PDT 24
Peak memory 220288 kb
Host smart-e2d6f7bf-0999-4eb3-8d3e-d3e4f79ce73a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274199185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.4274199185
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.257377545
Short name T37
Test name
Test status
Simulation time 479611902 ps
CPU time 3.11 seconds
Started Jul 09 05:40:44 PM PDT 24
Finished Jul 09 05:40:48 PM PDT 24
Peak memory 216112 kb
Host smart-41d8aa05-480a-4367-a75b-e3ddd704fd0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257377545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.257377545
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.932476652
Short name T603
Test name
Test status
Simulation time 107804646 ps
CPU time 3.83 seconds
Started Jul 09 05:40:45 PM PDT 24
Finished Jul 09 05:40:50 PM PDT 24
Peak memory 216172 kb
Host smart-902e4d21-b11c-40af-be2b-be47155753b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932476652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.932476652
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.605047249
Short name T865
Test name
Test status
Simulation time 120410780 ps
CPU time 0.84 seconds
Started Jul 09 05:40:46 PM PDT 24
Finished Jul 09 05:40:48 PM PDT 24
Peak memory 205992 kb
Host smart-480a933b-fc53-47b3-91bb-8b8064de62fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605047249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.605047249
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.677406517
Short name T592
Test name
Test status
Simulation time 18610895064 ps
CPU time 15.57 seconds
Started Jul 09 05:40:41 PM PDT 24
Finished Jul 09 05:40:59 PM PDT 24
Peak memory 232792 kb
Host smart-9fa35500-81c8-4ef3-9db6-090c9c9ae8b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677406517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.677406517
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.2605893820
Short name T325
Test name
Test status
Simulation time 50838614 ps
CPU time 0.72 seconds
Started Jul 09 05:40:54 PM PDT 24
Finished Jul 09 05:40:55 PM PDT 24
Peak memory 204992 kb
Host smart-663e11ea-92be-42df-a6c0-3ea689f3e97f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605893820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
2605893820
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.1067486133
Short name T512
Test name
Test status
Simulation time 133844291 ps
CPU time 2.78 seconds
Started Jul 09 05:40:47 PM PDT 24
Finished Jul 09 05:40:51 PM PDT 24
Peak memory 232692 kb
Host smart-e5ef8242-6cc0-4ed9-99d6-e2d5c6edbed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067486133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.1067486133
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.2280559484
Short name T520
Test name
Test status
Simulation time 55516503 ps
CPU time 0.86 seconds
Started Jul 09 05:40:48 PM PDT 24
Finished Jul 09 05:40:50 PM PDT 24
Peak memory 206596 kb
Host smart-1cf7f57c-29b3-4d06-b23d-b0ef92bbecd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280559484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.2280559484
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.3263066400
Short name T265
Test name
Test status
Simulation time 6352080880 ps
CPU time 36.72 seconds
Started Jul 09 05:40:47 PM PDT 24
Finished Jul 09 05:41:25 PM PDT 24
Peak memory 240988 kb
Host smart-b6b0ffac-e51c-491c-bd40-70f35c44c4c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263066400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.3263066400
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.2016015307
Short name T1005
Test name
Test status
Simulation time 4080267896 ps
CPU time 65.45 seconds
Started Jul 09 05:40:49 PM PDT 24
Finished Jul 09 05:41:56 PM PDT 24
Peak memory 253980 kb
Host smart-d2163540-fd59-497f-aef3-c11cdd6ea713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016015307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.2016015307
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.1136767247
Short name T883
Test name
Test status
Simulation time 4843700307 ps
CPU time 65.04 seconds
Started Jul 09 05:40:48 PM PDT 24
Finished Jul 09 05:41:54 PM PDT 24
Peak memory 234084 kb
Host smart-883edbc7-20c2-4501-90d4-77c7a55ee28e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136767247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.1136767247
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.4156400381
Short name T211
Test name
Test status
Simulation time 41436915889 ps
CPU time 310.99 seconds
Started Jul 09 05:40:52 PM PDT 24
Finished Jul 09 05:46:04 PM PDT 24
Peak memory 265804 kb
Host smart-1e25a19d-8452-4cc8-899c-513e844b4086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156400381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmd
s.4156400381
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.4239537337
Short name T699
Test name
Test status
Simulation time 710204454 ps
CPU time 3.91 seconds
Started Jul 09 05:40:41 PM PDT 24
Finished Jul 09 05:40:47 PM PDT 24
Peak memory 232608 kb
Host smart-4571efaa-4f69-4426-b35d-a4f525e63cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239537337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.4239537337
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.3397539463
Short name T92
Test name
Test status
Simulation time 715514666 ps
CPU time 7.73 seconds
Started Jul 09 05:40:50 PM PDT 24
Finished Jul 09 05:40:59 PM PDT 24
Peak memory 232636 kb
Host smart-d8c75e83-8859-4492-8340-c67cb63553e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397539463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.3397539463
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.3129163634
Short name T1011
Test name
Test status
Simulation time 32300449413 ps
CPU time 18.94 seconds
Started Jul 09 05:40:53 PM PDT 24
Finished Jul 09 05:41:13 PM PDT 24
Peak memory 232832 kb
Host smart-cba89eee-3000-4ca7-b31c-c1e132456a66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129163634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.3129163634
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.1114512648
Short name T405
Test name
Test status
Simulation time 9728326464 ps
CPU time 14.43 seconds
Started Jul 09 05:40:42 PM PDT 24
Finished Jul 09 05:40:58 PM PDT 24
Peak memory 224592 kb
Host smart-61703321-48fb-49c4-a0ce-a3b1828ed076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114512648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.1114512648
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.3362180497
Short name T918
Test name
Test status
Simulation time 2750264906 ps
CPU time 9.64 seconds
Started Jul 09 05:40:54 PM PDT 24
Finished Jul 09 05:41:05 PM PDT 24
Peak memory 218800 kb
Host smart-e31426df-cd25-4f93-be3c-6878afeb67ce
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3362180497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.3362180497
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.4245508966
Short name T621
Test name
Test status
Simulation time 13446235104 ps
CPU time 134.86 seconds
Started Jul 09 05:40:45 PM PDT 24
Finished Jul 09 05:43:00 PM PDT 24
Peak memory 249268 kb
Host smart-4a619103-5b9a-4d16-99b8-47dc70d27f0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245508966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.4245508966
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.3171528244
Short name T633
Test name
Test status
Simulation time 5308478239 ps
CPU time 29.95 seconds
Started Jul 09 05:40:54 PM PDT 24
Finished Jul 09 05:41:26 PM PDT 24
Peak memory 216256 kb
Host smart-924d5fbe-341d-4ea9-9a9c-d3881341005d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171528244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.3171528244
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.3058329344
Short name T849
Test name
Test status
Simulation time 379162324 ps
CPU time 3.18 seconds
Started Jul 09 05:40:46 PM PDT 24
Finished Jul 09 05:40:50 PM PDT 24
Peak memory 216176 kb
Host smart-a252d549-fc26-457e-a140-59c64b7cf2c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058329344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.3058329344
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.1999335359
Short name T939
Test name
Test status
Simulation time 272585136 ps
CPU time 3.58 seconds
Started Jul 09 05:40:50 PM PDT 24
Finished Jul 09 05:40:55 PM PDT 24
Peak memory 216212 kb
Host smart-cce17b26-4154-4e19-942d-d0795bee7642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999335359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.1999335359
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.1537381122
Short name T981
Test name
Test status
Simulation time 56381536 ps
CPU time 0.88 seconds
Started Jul 09 05:40:54 PM PDT 24
Finished Jul 09 05:40:56 PM PDT 24
Peak memory 207004 kb
Host smart-f1874ac4-319f-40e8-a0a2-64c5415df83b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537381122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.1537381122
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.2254835179
Short name T907
Test name
Test status
Simulation time 11756112045 ps
CPU time 12.65 seconds
Started Jul 09 05:40:54 PM PDT 24
Finished Jul 09 05:41:08 PM PDT 24
Peak memory 232812 kb
Host smart-8a05a4f4-f1eb-4b34-bc3f-d18595d25cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254835179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.2254835179
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.3681568320
Short name T1014
Test name
Test status
Simulation time 48352504 ps
CPU time 0.72 seconds
Started Jul 09 05:38:49 PM PDT 24
Finished Jul 09 05:38:53 PM PDT 24
Peak memory 205536 kb
Host smart-b4ccf89c-5690-426c-8871-be790c54ea56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681568320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.3
681568320
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.3771429839
Short name T746
Test name
Test status
Simulation time 781335352 ps
CPU time 4.57 seconds
Started Jul 09 05:38:47 PM PDT 24
Finished Jul 09 05:38:54 PM PDT 24
Peak memory 224428 kb
Host smart-30db7275-d2f2-4ecb-9bca-a5146ed3ca73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771429839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.3771429839
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.3129009563
Short name T659
Test name
Test status
Simulation time 77667436 ps
CPU time 0.82 seconds
Started Jul 09 05:38:44 PM PDT 24
Finished Jul 09 05:38:46 PM PDT 24
Peak memory 206616 kb
Host smart-c4fe28e9-df46-4b2f-81cd-1ea1499a7129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129009563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.3129009563
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.2673750945
Short name T577
Test name
Test status
Simulation time 12293336499 ps
CPU time 59.44 seconds
Started Jul 09 05:38:48 PM PDT 24
Finished Jul 09 05:39:50 PM PDT 24
Peak memory 250668 kb
Host smart-88b43344-4ab4-43d0-a939-dea631aeb22e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673750945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.2673750945
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.3406833986
Short name T717
Test name
Test status
Simulation time 14852311420 ps
CPU time 43.12 seconds
Started Jul 09 05:38:49 PM PDT 24
Finished Jul 09 05:39:35 PM PDT 24
Peak memory 250432 kb
Host smart-ba77f06b-60a3-487d-a953-d5708a05c65e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406833986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.3406833986
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.4040997509
Short name T280
Test name
Test status
Simulation time 17025706272 ps
CPU time 139.56 seconds
Started Jul 09 05:38:49 PM PDT 24
Finished Jul 09 05:41:11 PM PDT 24
Peak memory 251688 kb
Host smart-c92be509-2da3-4161-b943-ae53fc17f21e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040997509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.4040997509
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.2772301843
Short name T149
Test name
Test status
Simulation time 139502093 ps
CPU time 5.84 seconds
Started Jul 09 05:38:44 PM PDT 24
Finished Jul 09 05:38:51 PM PDT 24
Peak memory 239332 kb
Host smart-06a6c9f5-cb87-4b7d-9a95-6f753ef226f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772301843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.2772301843
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.2179632433
Short name T832
Test name
Test status
Simulation time 2790170757 ps
CPU time 23.38 seconds
Started Jul 09 05:38:45 PM PDT 24
Finished Jul 09 05:39:10 PM PDT 24
Peak memory 232736 kb
Host smart-778d2036-b773-437e-b40f-156266a387b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179632433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.2179632433
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.2152232859
Short name T287
Test name
Test status
Simulation time 1854515349 ps
CPU time 11.86 seconds
Started Jul 09 05:38:51 PM PDT 24
Finished Jul 09 05:39:05 PM PDT 24
Peak memory 232708 kb
Host smart-fbd21ef0-6d92-49bb-8f10-46cd144862a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152232859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.2152232859
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.2341525647
Short name T707
Test name
Test status
Simulation time 521356391 ps
CPU time 5.6 seconds
Started Jul 09 05:38:47 PM PDT 24
Finished Jul 09 05:38:55 PM PDT 24
Peak memory 232620 kb
Host smart-09cf4e91-70a3-468f-b5c3-28ef0a70c458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341525647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.2341525647
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.2086150534
Short name T207
Test name
Test status
Simulation time 1234086473 ps
CPU time 3.84 seconds
Started Jul 09 05:38:51 PM PDT 24
Finished Jul 09 05:38:57 PM PDT 24
Peak memory 232600 kb
Host smart-d0673fab-e55b-438f-a3a7-55f38290ec97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086150534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.2086150534
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.464770652
Short name T462
Test name
Test status
Simulation time 1549010344 ps
CPU time 5.5 seconds
Started Jul 09 05:38:49 PM PDT 24
Finished Jul 09 05:38:58 PM PDT 24
Peak memory 222956 kb
Host smart-8b0ac81b-da35-47dd-996c-7a04e953ae6e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=464770652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_direc
t.464770652
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.2066577152
Short name T394
Test name
Test status
Simulation time 50364986 ps
CPU time 1.07 seconds
Started Jul 09 05:38:49 PM PDT 24
Finished Jul 09 05:38:53 PM PDT 24
Peak memory 207672 kb
Host smart-e861f0fb-30be-4219-8a7f-1256749a152b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066577152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.2066577152
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.1466483518
Short name T689
Test name
Test status
Simulation time 668257494 ps
CPU time 6.64 seconds
Started Jul 09 05:38:47 PM PDT 24
Finished Jul 09 05:38:56 PM PDT 24
Peak memory 216512 kb
Host smart-dd1e43ed-8ef5-4057-85da-5adc19960204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466483518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.1466483518
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.60325177
Short name T537
Test name
Test status
Simulation time 5204255281 ps
CPU time 15.73 seconds
Started Jul 09 05:38:45 PM PDT 24
Finished Jul 09 05:39:03 PM PDT 24
Peak memory 216388 kb
Host smart-b75bcce1-f79a-4c41-88f6-b1e25801ce87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60325177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.60325177
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.1359152129
Short name T824
Test name
Test status
Simulation time 16546815 ps
CPU time 0.8 seconds
Started Jul 09 05:38:51 PM PDT 24
Finished Jul 09 05:38:54 PM PDT 24
Peak memory 205992 kb
Host smart-c72e2ad9-7e34-4c4a-b0a0-0e2f9ca84d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359152129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.1359152129
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.3052872959
Short name T687
Test name
Test status
Simulation time 12124620 ps
CPU time 0.7 seconds
Started Jul 09 05:38:47 PM PDT 24
Finished Jul 09 05:38:50 PM PDT 24
Peak memory 205628 kb
Host smart-097c7d88-2d87-41ca-8703-798e90a970b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052872959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.3052872959
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.3608351643
Short name T177
Test name
Test status
Simulation time 327010272 ps
CPU time 2.48 seconds
Started Jul 09 05:38:46 PM PDT 24
Finished Jul 09 05:38:50 PM PDT 24
Peak memory 224404 kb
Host smart-91eca8a2-9af0-4f0f-9925-2a4739d678f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608351643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.3608351643
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.1928065001
Short name T634
Test name
Test status
Simulation time 13758908 ps
CPU time 0.78 seconds
Started Jul 09 05:38:53 PM PDT 24
Finished Jul 09 05:38:55 PM PDT 24
Peak memory 205536 kb
Host smart-afed1c6c-1124-420c-b11c-d243461308ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928065001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.1
928065001
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.3395161187
Short name T402
Test name
Test status
Simulation time 32917357 ps
CPU time 2.18 seconds
Started Jul 09 05:38:52 PM PDT 24
Finished Jul 09 05:38:56 PM PDT 24
Peak memory 224432 kb
Host smart-09f22cb2-f6d2-446d-9041-062993255c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395161187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.3395161187
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.690701294
Short name T629
Test name
Test status
Simulation time 52976894 ps
CPU time 0.76 seconds
Started Jul 09 05:38:50 PM PDT 24
Finished Jul 09 05:38:54 PM PDT 24
Peak memory 206564 kb
Host smart-dbf9ea54-7a75-4492-9806-1b5aafd1e4f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690701294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.690701294
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.1472480846
Short name T408
Test name
Test status
Simulation time 101096895 ps
CPU time 0.79 seconds
Started Jul 09 05:38:54 PM PDT 24
Finished Jul 09 05:38:56 PM PDT 24
Peak memory 215748 kb
Host smart-23f7bc76-a336-4205-a90b-7543415ff476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472480846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.1472480846
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.3612270868
Short name T669
Test name
Test status
Simulation time 4704411965 ps
CPU time 42.3 seconds
Started Jul 09 05:38:53 PM PDT 24
Finished Jul 09 05:39:36 PM PDT 24
Peak memory 241024 kb
Host smart-fbf60171-d16d-496b-b690-f7b280a91936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612270868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.3612270868
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.4261822071
Short name T193
Test name
Test status
Simulation time 73680438470 ps
CPU time 91.33 seconds
Started Jul 09 05:38:54 PM PDT 24
Finished Jul 09 05:40:27 PM PDT 24
Peak memory 251144 kb
Host smart-00cdf756-8363-429b-aa1b-55f917f29678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261822071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.4261822071
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.592024984
Short name T298
Test name
Test status
Simulation time 13351911683 ps
CPU time 50.84 seconds
Started Jul 09 05:38:53 PM PDT 24
Finished Jul 09 05:39:45 PM PDT 24
Peak memory 234816 kb
Host smart-0f91acb0-3a87-4319-9eec-954acca55eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592024984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.592024984
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.3932612642
Short name T909
Test name
Test status
Simulation time 8634397193 ps
CPU time 79.47 seconds
Started Jul 09 05:38:52 PM PDT 24
Finished Jul 09 05:40:13 PM PDT 24
Peak memory 240976 kb
Host smart-0e3cf4c9-1276-404c-8360-fd202edf0602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932612642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds
.3932612642
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.470668045
Short name T56
Test name
Test status
Simulation time 4287612373 ps
CPU time 24.44 seconds
Started Jul 09 05:38:49 PM PDT 24
Finished Jul 09 05:39:16 PM PDT 24
Peak memory 224608 kb
Host smart-78366a86-b5c7-41b7-96e8-a1d7a08ef473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470668045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.470668045
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.2679866448
Short name T942
Test name
Test status
Simulation time 4820258727 ps
CPU time 52.34 seconds
Started Jul 09 05:38:56 PM PDT 24
Finished Jul 09 05:39:50 PM PDT 24
Peak memory 240136 kb
Host smart-3b1e34d3-b8d8-40b7-a19b-2442e3886310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679866448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.2679866448
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.1466368402
Short name T968
Test name
Test status
Simulation time 2362610750 ps
CPU time 7.93 seconds
Started Jul 09 05:38:47 PM PDT 24
Finished Jul 09 05:38:57 PM PDT 24
Peak memory 240816 kb
Host smart-7d056323-bf4a-4731-ac58-f9da0b179466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466368402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.1466368402
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.3205047898
Short name T508
Test name
Test status
Simulation time 39701392201 ps
CPU time 31.08 seconds
Started Jul 09 05:38:49 PM PDT 24
Finished Jul 09 05:39:23 PM PDT 24
Peak memory 251168 kb
Host smart-4911aa30-c1dd-4ee0-910b-5db63af4ed3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205047898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.3205047898
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.67224073
Short name T845
Test name
Test status
Simulation time 443235963 ps
CPU time 5.47 seconds
Started Jul 09 05:38:51 PM PDT 24
Finished Jul 09 05:38:59 PM PDT 24
Peak memory 220476 kb
Host smart-eb26afb9-8e58-4529-8c24-738cc68fd8c9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=67224073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_direct
.67224073
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.1577578016
Short name T813
Test name
Test status
Simulation time 75688659061 ps
CPU time 122.79 seconds
Started Jul 09 05:38:56 PM PDT 24
Finished Jul 09 05:41:00 PM PDT 24
Peak memory 249228 kb
Host smart-9ea18ffb-610b-4da8-b25c-a1f041139264
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577578016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.1577578016
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.4068130926
Short name T526
Test name
Test status
Simulation time 6850828415 ps
CPU time 44.49 seconds
Started Jul 09 05:38:48 PM PDT 24
Finished Jul 09 05:39:36 PM PDT 24
Peak memory 216288 kb
Host smart-998e7c7d-12d5-468a-956f-dc9b85d5b823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068130926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.4068130926
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.3203997830
Short name T632
Test name
Test status
Simulation time 14343769987 ps
CPU time 10.64 seconds
Started Jul 09 05:38:49 PM PDT 24
Finished Jul 09 05:39:02 PM PDT 24
Peak memory 216292 kb
Host smart-c79d95b7-14b0-445a-a5fb-b76c22bde456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203997830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.3203997830
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.3479596340
Short name T567
Test name
Test status
Simulation time 62075040 ps
CPU time 0.98 seconds
Started Jul 09 05:38:47 PM PDT 24
Finished Jul 09 05:38:50 PM PDT 24
Peak memory 216092 kb
Host smart-75ddaa97-ec57-4ec9-935e-05b888c6f22e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479596340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.3479596340
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.3023926794
Short name T492
Test name
Test status
Simulation time 83117892 ps
CPU time 1.02 seconds
Started Jul 09 05:38:49 PM PDT 24
Finished Jul 09 05:38:54 PM PDT 24
Peak memory 207020 kb
Host smart-2e9726d4-13d9-49d1-bd68-b30dad0a0779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023926794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.3023926794
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.2740051822
Short name T754
Test name
Test status
Simulation time 410336839 ps
CPU time 4.7 seconds
Started Jul 09 05:38:53 PM PDT 24
Finished Jul 09 05:38:59 PM PDT 24
Peak memory 232704 kb
Host smart-04a7b7d0-1cc7-409b-9062-30d276deac92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740051822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.2740051822
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.454894211
Short name T328
Test name
Test status
Simulation time 37229468 ps
CPU time 0.73 seconds
Started Jul 09 05:38:59 PM PDT 24
Finished Jul 09 05:39:00 PM PDT 24
Peak memory 205872 kb
Host smart-33c8915b-2e5b-47d0-9532-1ad980001378
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454894211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.454894211
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.2815410441
Short name T583
Test name
Test status
Simulation time 93962987 ps
CPU time 2.31 seconds
Started Jul 09 05:38:52 PM PDT 24
Finished Jul 09 05:38:56 PM PDT 24
Peak memory 232316 kb
Host smart-5ff6e6c5-d4a3-4dd9-af68-4f6a75b368da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815410441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.2815410441
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.1696649447
Short name T441
Test name
Test status
Simulation time 78327570 ps
CPU time 0.75 seconds
Started Jul 09 05:38:51 PM PDT 24
Finished Jul 09 05:38:54 PM PDT 24
Peak memory 205892 kb
Host smart-58ebe63b-09b0-4edd-b755-e35c9baef4f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696649447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.1696649447
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.152897282
Short name T239
Test name
Test status
Simulation time 51423012677 ps
CPU time 113.7 seconds
Started Jul 09 05:38:52 PM PDT 24
Finished Jul 09 05:40:48 PM PDT 24
Peak memory 251056 kb
Host smart-d55e9aee-f33e-4076-807a-076b1b47a9ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152897282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.152897282
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.3319414879
Short name T681
Test name
Test status
Simulation time 56821297666 ps
CPU time 104.82 seconds
Started Jul 09 05:38:56 PM PDT 24
Finished Jul 09 05:40:42 PM PDT 24
Peak memory 251904 kb
Host smart-5086aab3-327c-4862-8329-adad838d25bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319414879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.3319414879
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.4130500520
Short name T380
Test name
Test status
Simulation time 1174868497 ps
CPU time 4.28 seconds
Started Jul 09 05:38:53 PM PDT 24
Finished Jul 09 05:38:58 PM PDT 24
Peak memory 224412 kb
Host smart-8ebae46b-bdea-4565-a58f-c73dc5b57197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130500520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.4130500520
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.61894970
Short name T415
Test name
Test status
Simulation time 225096292 ps
CPU time 4.13 seconds
Started Jul 09 05:38:55 PM PDT 24
Finished Jul 09 05:39:00 PM PDT 24
Peak memory 233716 kb
Host smart-232bce5b-c4f9-4f8a-aad9-2adda38e2f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61894970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds.61894970
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.1879858193
Short name T948
Test name
Test status
Simulation time 909550668 ps
CPU time 5.94 seconds
Started Jul 09 05:38:54 PM PDT 24
Finished Jul 09 05:39:01 PM PDT 24
Peak memory 232652 kb
Host smart-bde7d56d-7493-458c-b48a-9e0817a47a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879858193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.1879858193
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.2955805519
Short name T786
Test name
Test status
Simulation time 499019699 ps
CPU time 11.5 seconds
Started Jul 09 05:38:55 PM PDT 24
Finished Jul 09 05:39:08 PM PDT 24
Peak memory 224504 kb
Host smart-1844cc4a-2027-4ce1-9c5d-1b3b8506e97e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955805519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.2955805519
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.408971593
Short name T463
Test name
Test status
Simulation time 32277521 ps
CPU time 2.38 seconds
Started Jul 09 05:38:54 PM PDT 24
Finished Jul 09 05:38:58 PM PDT 24
Peak memory 232632 kb
Host smart-ff9aeb53-0487-440b-a19d-428a15b898bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408971593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap.
408971593
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.393032592
Short name T900
Test name
Test status
Simulation time 19696717507 ps
CPU time 10.63 seconds
Started Jul 09 05:38:52 PM PDT 24
Finished Jul 09 05:39:04 PM PDT 24
Peak memory 224492 kb
Host smart-5252d1ab-d261-43ef-b73c-4bde4816991e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393032592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.393032592
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.1585317366
Short name T40
Test name
Test status
Simulation time 2985535783 ps
CPU time 8.06 seconds
Started Jul 09 05:38:55 PM PDT 24
Finished Jul 09 05:39:05 PM PDT 24
Peak memory 222860 kb
Host smart-3842ebe5-fc75-4eb9-825d-39149324c088
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1585317366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.1585317366
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.3763499602
Short name T901
Test name
Test status
Simulation time 10153413586 ps
CPU time 99.88 seconds
Started Jul 09 05:38:55 PM PDT 24
Finished Jul 09 05:40:36 PM PDT 24
Peak memory 241108 kb
Host smart-5f332659-22f6-45ef-86d9-a0ad009793f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763499602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.3763499602
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.4160506324
Short name T596
Test name
Test status
Simulation time 15435108156 ps
CPU time 43.5 seconds
Started Jul 09 05:38:54 PM PDT 24
Finished Jul 09 05:39:38 PM PDT 24
Peak memory 216392 kb
Host smart-3242bb8a-7281-4d52-a25b-abfdb25bd278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160506324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.4160506324
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.921954507
Short name T351
Test name
Test status
Simulation time 5198384364 ps
CPU time 8.3 seconds
Started Jul 09 05:38:54 PM PDT 24
Finished Jul 09 05:39:03 PM PDT 24
Peak memory 216316 kb
Host smart-bde88dc6-65c7-40bb-9872-c527a9cb07e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921954507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.921954507
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.3610709515
Short name T130
Test name
Test status
Simulation time 116583470 ps
CPU time 1.02 seconds
Started Jul 09 05:38:52 PM PDT 24
Finished Jul 09 05:38:55 PM PDT 24
Peak memory 207328 kb
Host smart-426ae9f1-2607-445e-b561-13dbede3d147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610709515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.3610709515
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.2821512798
Short name T683
Test name
Test status
Simulation time 72733966 ps
CPU time 0.89 seconds
Started Jul 09 05:38:52 PM PDT 24
Finished Jul 09 05:38:55 PM PDT 24
Peak memory 207004 kb
Host smart-8a3d397a-b725-47c8-b9dc-8e9a94c26344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821512798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.2821512798
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.2632741544
Short name T571
Test name
Test status
Simulation time 4235491386 ps
CPU time 5.25 seconds
Started Jul 09 05:38:55 PM PDT 24
Finished Jul 09 05:39:01 PM PDT 24
Peak memory 224552 kb
Host smart-c21a25ff-480f-46c1-bb22-ff22123473e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632741544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.2632741544
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.120064670
Short name T319
Test name
Test status
Simulation time 22086185 ps
CPU time 0.74 seconds
Started Jul 09 05:39:00 PM PDT 24
Finished Jul 09 05:39:02 PM PDT 24
Peak memory 205832 kb
Host smart-ecde488a-5cae-4405-adcd-753d94eeffa1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120064670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.120064670
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.1969695436
Short name T192
Test name
Test status
Simulation time 555339312 ps
CPU time 4.98 seconds
Started Jul 09 05:39:00 PM PDT 24
Finished Jul 09 05:39:06 PM PDT 24
Peak memory 224452 kb
Host smart-32270614-7454-4318-9be6-6c4853157c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969695436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.1969695436
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.853959071
Short name T622
Test name
Test status
Simulation time 26224766 ps
CPU time 0.83 seconds
Started Jul 09 05:38:54 PM PDT 24
Finished Jul 09 05:38:56 PM PDT 24
Peak memory 206588 kb
Host smart-3b5077a4-1013-41f7-a9cd-32c286279d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853959071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.853959071
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.2215518550
Short name T234
Test name
Test status
Simulation time 4233565647 ps
CPU time 31.37 seconds
Started Jul 09 05:38:56 PM PDT 24
Finished Jul 09 05:39:28 PM PDT 24
Peak memory 249172 kb
Host smart-3ba1a8cc-0e14-4641-93a7-adba6ed32304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215518550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.2215518550
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.3196111501
Short name T235
Test name
Test status
Simulation time 964462399464 ps
CPU time 548.59 seconds
Started Jul 09 05:38:55 PM PDT 24
Finished Jul 09 05:48:05 PM PDT 24
Peak memory 255172 kb
Host smart-4b079d44-21d4-443c-84fb-31fad2a6306c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196111501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.3196111501
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.431095999
Short name T993
Test name
Test status
Simulation time 28419528749 ps
CPU time 39.08 seconds
Started Jul 09 05:39:01 PM PDT 24
Finished Jul 09 05:39:41 PM PDT 24
Peak memory 224556 kb
Host smart-4d3299fc-d71a-4ef7-ae70-3cd7e6d04851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431095999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle.
431095999
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.71834489
Short name T348
Test name
Test status
Simulation time 7224833974 ps
CPU time 29.54 seconds
Started Jul 09 05:38:56 PM PDT 24
Finished Jul 09 05:39:27 PM PDT 24
Peak memory 240972 kb
Host smart-344fe751-11be-4927-8c6b-60f79fe7d17a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71834489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.71834489
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.652890563
Short name T507
Test name
Test status
Simulation time 485137027 ps
CPU time 8.97 seconds
Started Jul 09 05:38:58 PM PDT 24
Finished Jul 09 05:39:07 PM PDT 24
Peak memory 234204 kb
Host smart-2ed58c1c-9ae6-4f1e-bf0c-f4c08a865621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652890563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds.
652890563
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.314166576
Short name T722
Test name
Test status
Simulation time 38188818533 ps
CPU time 52.51 seconds
Started Jul 09 05:38:56 PM PDT 24
Finished Jul 09 05:39:49 PM PDT 24
Peak memory 224624 kb
Host smart-e4b4077d-b6ce-421c-a3e1-a662c6d42bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314166576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.314166576
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.3250557621
Short name T802
Test name
Test status
Simulation time 1030475769 ps
CPU time 10.93 seconds
Started Jul 09 05:38:55 PM PDT 24
Finished Jul 09 05:39:07 PM PDT 24
Peak memory 240708 kb
Host smart-fd05358b-ab1b-48fd-be8f-d0705e407430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250557621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.3250557621
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.383983800
Short name T249
Test name
Test status
Simulation time 452658534 ps
CPU time 4.66 seconds
Started Jul 09 05:38:58 PM PDT 24
Finished Jul 09 05:39:04 PM PDT 24
Peak memory 224492 kb
Host smart-eede363f-7858-41fe-87f0-a8bfe30ddd6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383983800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap.
383983800
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.3940410574
Short name T612
Test name
Test status
Simulation time 2331616710 ps
CPU time 7.99 seconds
Started Jul 09 05:38:56 PM PDT 24
Finished Jul 09 05:39:05 PM PDT 24
Peak memory 239700 kb
Host smart-80d617d4-086b-44d8-9108-94e31f90b60e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940410574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.3940410574
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.1662241310
Short name T78
Test name
Test status
Simulation time 158463526 ps
CPU time 3.64 seconds
Started Jul 09 05:38:58 PM PDT 24
Finished Jul 09 05:39:02 PM PDT 24
Peak memory 223224 kb
Host smart-1189bbd6-6497-4ebc-b51e-1a49217fd8d9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1662241310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.1662241310
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.558552044
Short name T389
Test name
Test status
Simulation time 154480524 ps
CPU time 0.9 seconds
Started Jul 09 05:38:59 PM PDT 24
Finished Jul 09 05:39:01 PM PDT 24
Peak memory 206748 kb
Host smart-864d9aa0-8aa0-4fc4-a406-51d1de187bcc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558552044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stress
_all.558552044
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.2877672042
Short name T610
Test name
Test status
Simulation time 14706567 ps
CPU time 0.72 seconds
Started Jul 09 05:38:57 PM PDT 24
Finished Jul 09 05:38:59 PM PDT 24
Peak memory 205712 kb
Host smart-8c3b8fd8-3edf-4449-8a17-80b96c4d1f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877672042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.2877672042
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.222441862
Short name T888
Test name
Test status
Simulation time 1671912526 ps
CPU time 5.26 seconds
Started Jul 09 05:38:55 PM PDT 24
Finished Jul 09 05:39:02 PM PDT 24
Peak memory 216256 kb
Host smart-23029c28-1e7a-49fc-ab10-0ff46be93235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222441862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.222441862
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.2928040369
Short name T416
Test name
Test status
Simulation time 22525423 ps
CPU time 0.91 seconds
Started Jul 09 05:38:57 PM PDT 24
Finished Jul 09 05:38:59 PM PDT 24
Peak memory 207460 kb
Host smart-70fe740f-e9e7-4895-a973-1bb8408341a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928040369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.2928040369
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.1368710169
Short name T822
Test name
Test status
Simulation time 80989175 ps
CPU time 0.75 seconds
Started Jul 09 05:38:54 PM PDT 24
Finished Jul 09 05:38:56 PM PDT 24
Peak memory 205928 kb
Host smart-10d37495-61b5-474b-a77b-9c7dfbf37e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368710169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.1368710169
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.3787566757
Short name T493
Test name
Test status
Simulation time 31657110471 ps
CPU time 14.34 seconds
Started Jul 09 05:38:56 PM PDT 24
Finished Jul 09 05:39:11 PM PDT 24
Peak memory 240992 kb
Host smart-14509b57-ef82-4133-bc50-65ebced33429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787566757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.3787566757
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.2598815639
Short name T555
Test name
Test status
Simulation time 16784229 ps
CPU time 0.81 seconds
Started Jul 09 05:39:07 PM PDT 24
Finished Jul 09 05:39:09 PM PDT 24
Peak memory 204988 kb
Host smart-fa4feb88-b329-414d-801d-b2b69b07b331
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598815639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.2
598815639
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.1627095244
Short name T952
Test name
Test status
Simulation time 1467518923 ps
CPU time 6.57 seconds
Started Jul 09 05:39:00 PM PDT 24
Finished Jul 09 05:39:07 PM PDT 24
Peak memory 224504 kb
Host smart-cdcf4b67-a1d2-4633-8e57-415b43124ce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627095244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.1627095244
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.1789433507
Short name T360
Test name
Test status
Simulation time 37885903 ps
CPU time 0.78 seconds
Started Jul 09 05:38:58 PM PDT 24
Finished Jul 09 05:38:59 PM PDT 24
Peak memory 205536 kb
Host smart-ac9ddc3a-6b35-4fcf-a2e0-4a438d77e1dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789433507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.1789433507
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.3401310071
Short name T914
Test name
Test status
Simulation time 490371880603 ps
CPU time 336.89 seconds
Started Jul 09 05:38:59 PM PDT 24
Finished Jul 09 05:44:37 PM PDT 24
Peak memory 250724 kb
Host smart-5f7f5d6a-319e-4fbe-8466-9235f3e75d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401310071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.3401310071
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.1928196336
Short name T53
Test name
Test status
Simulation time 62693765786 ps
CPU time 297.68 seconds
Started Jul 09 05:38:59 PM PDT 24
Finished Jul 09 05:43:57 PM PDT 24
Peak memory 249372 kb
Host smart-30a725e9-5261-4871-87e4-1e0a367a409e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928196336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.1928196336
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.1897580461
Short name T29
Test name
Test status
Simulation time 3574222561 ps
CPU time 74.4 seconds
Started Jul 09 05:39:02 PM PDT 24
Finished Jul 09 05:40:17 PM PDT 24
Peak memory 249248 kb
Host smart-223c7294-011b-494e-a956-ccbb6cd4c79a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897580461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.1897580461
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.63300122
Short name T747
Test name
Test status
Simulation time 255270665 ps
CPU time 3.39 seconds
Started Jul 09 05:38:59 PM PDT 24
Finished Jul 09 05:39:03 PM PDT 24
Peak memory 232672 kb
Host smart-5242fd07-0bc5-4656-a2fc-86b4ce863ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63300122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.63300122
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.2383238272
Short name T216
Test name
Test status
Simulation time 831316121384 ps
CPU time 361.62 seconds
Started Jul 09 05:39:00 PM PDT 24
Finished Jul 09 05:45:03 PM PDT 24
Peak memory 273696 kb
Host smart-a643969c-501c-42d7-8eb3-43df0e6d597b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383238272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds
.2383238272
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.2315591822
Short name T266
Test name
Test status
Simulation time 1785270131 ps
CPU time 14.7 seconds
Started Jul 09 05:39:00 PM PDT 24
Finished Jul 09 05:39:15 PM PDT 24
Peak memory 224380 kb
Host smart-a37a09f4-14e9-4e23-a4f9-31f1b1fabdfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315591822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.2315591822
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.1468903398
Short name T961
Test name
Test status
Simulation time 1467924531 ps
CPU time 6.37 seconds
Started Jul 09 05:39:02 PM PDT 24
Finished Jul 09 05:39:09 PM PDT 24
Peak memory 224432 kb
Host smart-3d8f8373-f2a7-409e-be3a-4b73ca468dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468903398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.1468903398
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.1644790545
Short name T62
Test name
Test status
Simulation time 142307022 ps
CPU time 3.01 seconds
Started Jul 09 05:39:00 PM PDT 24
Finished Jul 09 05:39:04 PM PDT 24
Peak memory 232696 kb
Host smart-16bdc149-9198-4c6a-b991-46fa77cdf9b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644790545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.1644790545
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.3724244230
Short name T371
Test name
Test status
Simulation time 4371875221 ps
CPU time 8.15 seconds
Started Jul 09 05:38:59 PM PDT 24
Finished Jul 09 05:39:07 PM PDT 24
Peak memory 232808 kb
Host smart-18e5802f-3237-4461-8721-73744fd5c0ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724244230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.3724244230
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.3471105125
Short name T518
Test name
Test status
Simulation time 253805066 ps
CPU time 5.13 seconds
Started Jul 09 05:39:03 PM PDT 24
Finished Jul 09 05:39:09 PM PDT 24
Peak memory 222120 kb
Host smart-87c1dd11-020a-415a-82a5-957ed23f2a48
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3471105125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.3471105125
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.3472020668
Short name T233
Test name
Test status
Simulation time 42463660338 ps
CPU time 364.59 seconds
Started Jul 09 05:39:06 PM PDT 24
Finished Jul 09 05:45:11 PM PDT 24
Peak memory 250632 kb
Host smart-ca358375-356d-40a8-9270-cc5f22341ec9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472020668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.3472020668
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.107917203
Short name T896
Test name
Test status
Simulation time 575782775 ps
CPU time 9.83 seconds
Started Jul 09 05:39:00 PM PDT 24
Finished Jul 09 05:39:11 PM PDT 24
Peak memory 219076 kb
Host smart-2afa6fe4-1f53-400a-a7a8-24aa0af76234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107917203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.107917203
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.941206238
Short name T691
Test name
Test status
Simulation time 10482456121 ps
CPU time 4.22 seconds
Started Jul 09 05:39:01 PM PDT 24
Finished Jul 09 05:39:06 PM PDT 24
Peak memory 216360 kb
Host smart-ffba74cc-a9aa-48e1-b2bf-eaf61a90db5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941206238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.941206238
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.3630280776
Short name T432
Test name
Test status
Simulation time 288502765 ps
CPU time 1.67 seconds
Started Jul 09 05:39:01 PM PDT 24
Finished Jul 09 05:39:03 PM PDT 24
Peak memory 216228 kb
Host smart-8fe228c7-ea1f-40cd-baa0-a5434a4395bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630280776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.3630280776
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.2067135759
Short name T542
Test name
Test status
Simulation time 120198824 ps
CPU time 0.88 seconds
Started Jul 09 05:39:01 PM PDT 24
Finished Jul 09 05:39:03 PM PDT 24
Peak memory 205976 kb
Host smart-e8fa6582-f9f4-4521-9a8b-df0628ef957e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067135759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.2067135759
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.1384285554
Short name T176
Test name
Test status
Simulation time 1038383037 ps
CPU time 3.81 seconds
Started Jul 09 05:39:00 PM PDT 24
Finished Jul 09 05:39:05 PM PDT 24
Peak memory 232656 kb
Host smart-a4564a7e-9771-48a4-b33c-fd05abbb9daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384285554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.1384285554
Directory /workspace/9.spi_device_upload/latest
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