Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2717580	1			T1	266		T2	1		T3	2768
all_values[1]	2717580	1			T1	266		T2	1		T3	2768
all_values[2]	2717580	1			T1	266		T2	1		T3	2768
all_values[3]	2717580	1			T1	266		T2	1		T3	2768
all_values[4]	2717580	1			T1	266		T2	1		T3	2768
all_values[5]	2717580	1			T1	266		T2	1		T3	2768
all_values[6]	2717580	1			T1	266		T2	1		T3	2768
all_values[7]	2717580	1			T1	266		T2	1		T3	2768

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21145455

1

T1

2128

T2

8

T3

22144

auto[1]

595185

1

T16

47

T17

107

T72

104

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21717209

1

T1

2128

T2

8

T3

22144

auto[1]

23431

1

T30

669

T31

16

T16

32

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2655348	1			T1	266		T2	1		T3	2768
all_values[0]	auto[0]	auto[1]	10245	1			T30	273		T31	15		T16	2
all_values[0]	auto[1]	auto[0]	51347	1			T16	2		T17	8		T72	12
all_values[0]	auto[1]	auto[1]	640	1			T16	3		T17	12		T72	4
all_values[1]	auto[0]	auto[0]	2569866	1			T1	266		T2	1		T3	2768
all_values[1]	auto[0]	auto[1]	6752	1			T30	209		T31	1		T16	1
all_values[1]	auto[1]	auto[0]	140359	1			T16	7		T17	11		T72	5
all_values[1]	auto[1]	auto[1]	603	1			T16	2		T17	4		T72	4
all_values[2]	auto[0]	auto[0]	2683785	1			T1	266		T2	1		T3	2768
all_values[2]	auto[0]	auto[1]	2873	1			T30	187		T16	3		T35	20
all_values[2]	auto[1]	auto[0]	30570	1			T16	1		T17	11		T72	7
all_values[2]	auto[1]	auto[1]	352	1			T16	2		T17	2		T72	9
all_values[3]	auto[0]	auto[0]	2672175	1			T1	266		T2	1		T3	2768
all_values[3]	auto[0]	auto[1]	210	1			T16	1		T17	4		T72	4
all_values[3]	auto[1]	auto[0]	45007	1			T16	4		T17	8		T72	5
all_values[3]	auto[1]	auto[1]	188	1			T16	2		T17	7		T72	10
all_values[4]	auto[0]	auto[0]	2593620	1			T1	266		T2	1		T3	2768
all_values[4]	auto[0]	auto[1]	209	1			T16	3		T17	9		T72	2
all_values[4]	auto[1]	auto[0]	123540	1			T16	2		T17	5		T72	8
all_values[4]	auto[1]	auto[1]	211	1			T16	5		T17	6		T72	7
all_values[5]	auto[0]	auto[0]	2680181	1			T1	266		T2	1		T3	2768
all_values[5]	auto[0]	auto[1]	191	1			T17	4		T72	5		T18	8
all_values[5]	auto[1]	auto[0]	37036	1			T16	4		T17	7		T72	7
all_values[5]	auto[1]	auto[1]	172	1			T16	2		T17	4		T72	5
all_values[6]	auto[0]	auto[0]	2677237	1			T1	266		T2	1		T3	2768
all_values[6]	auto[0]	auto[1]	214	1			T17	9		T72	8		T18	4
all_values[6]	auto[1]	auto[0]	39945	1			T16	4		T17	4		T72	4
all_values[6]	auto[1]	auto[1]	184	1			T16	2		T17	3		T72	2
all_values[7]	auto[0]	auto[0]	2592340	1			T1	266		T2	1		T3	2768
all_values[7]	auto[0]	auto[1]	209	1			T16	4		T17	4		T72	7
all_values[7]	auto[1]	auto[0]	124853	1			T16	5		T17	10		T72	11
all_values[7]	auto[1]	auto[1]	178	1			T17	5		T72	4		T18	4