Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	36456	1			T1	51		T3	112		T6	117
auto[SpiFlashAddrCfg]	7604	1			T1	22		T3	41		T6	52
auto[SpiFlashAddr3b]	9089	1			T1	17		T3	47		T6	63
auto[SpiFlashAddr4b]	7375	1			T1	10		T3	40		T6	48

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34826

1

T1

60

T3

135

T6

151

auto[1]

25698

1

T1

40

T3

105

T6

129

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32461

1

T1

58

T3

141

T6

168

auto[1]

28063

1

T1

42

T3

99

T6

112

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	40964	1			T1	44		T3	130		T6	163
values[1]	1091	1			T1	5		T3	17		T6	6
values[2]	1542	1			T1	4		T3	11		T6	6
values[3]	1431	1			T1	5		T3	7		T6	8
values[4]	1434	1			T1	10		T3	1		T6	9
values[5]	1459	1			T1	5		T3	13		T6	8
values[6]	1459	1			T1	6		T3	5		T6	8
values[7]	1440	1			T1	1		T3	5		T6	9
values[8]	9704	1			T1	20		T3	51		T6	63

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31003

1

T8

8

T9

6

T10

2

auto[1]

29521

1

T1

100

T3

240

T6

280

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

57377

1

T1

96

T3

216

T6

256

write

3147

1

T1

4

T3

24

T6

24

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

19054

1

T1

51

T3

99

T6

140

valids[0x1]

41470

1

T1

49

T3

141

T6

140

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1615	1			T1	5		T3	16		T6	11
internal_process_ops[0x5a]	1568	1			T1	3		T3	10		T6	15
internal_process_ops[0x05]	22520	1			T3	15		T6	15		T7	569
internal_process_ops[0x35]	1565	1			T1	6		T3	11		T6	8
internal_process_ops[0x15]	1642	1			T1	5		T3	5		T6	10
internal_process_ops[0x03]	1031	1			T3	2		T6	4		T7	1
internal_process_ops[0x0b]	988	1			T1	1		T3	1		T6	5
internal_process_ops[0x3b]	981	1			T1	1		T6	1		T7	5
internal_process_ops[0x6b]	1001	1			T1	2		T3	3		T6	7
internal_process_ops[0xbb]	1034	1			T3	4		T6	4		T7	2
internal_process_ops[0xeb]	1027	1			T1	1		T3	2		T6	1

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

58984

1

T1

98

T3

229

T6

267

auto[1]

1540

1

T1

2

T3

11

T6

13

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

58224

1

T1

96

T3

227

T6

255

auto[1]

2300

1

T1

4

T3

13

T6

25

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10266

1

T9

6

T10

2

T11

18

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7495

1

T11

10

T25

12

T30

94

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2038

1

T8

2

T11

11

T14

4

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1617

1

T11

6

T25

8

T30

19

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2422

1

T8

2

T11

1

T14

14

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2029

1

T11

2

T30

20

T177

6

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1928

1

T8

4

T11

3

T14

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1788

1

T11

8

T30

23

T31

10

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

110

1

T43

3

T178

1

T179

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

69

1

T30

1

T43

4

T17

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

83

1

T30

1

T64

2

T17

4

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

83

1

T31

1

T46

4

T45

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

138

1

T31

1

T64

1

T17

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

64

1

T45

1

T17

1

T178

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

67

1

T31

1

T45

2

T43

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

91

1

T31

1

T17

1

T47

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

83

1

T30

1

T64

1

T180

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

83

1

T30

4

T17

3

T47

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

72

1

T30

3

T17

2

T49

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

114

1

T30

1

T45

4

T43

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

101

1

T45

1

T43

1

T17

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

90

1

T11

1

T30

5

T31

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

92

1

T30

2

T43

4

T49

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

80

1

T31

2

T47

1

T178

1

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

11491

1

T1

32

T3

70

T6

88

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6420

1

T1

18

T3

38

T6

26

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1574

1

T1

15

T3

19

T6

16

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1547

1

T1

7

T3

14

T6

28

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1918

1

T1

8

T3

20

T6

19

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1942

1

T1

8

T3

24

T6

39

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1535

1

T1

2

T3

23

T6

13

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1367

1

T1

6

T3

8

T6

27

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

105

1

T1

1

T7

5

T78

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

106

1

T6

1

T7

2

T40

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

104

1

T3

1

T6

2

T7

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

124

1

T3

3

T7

1

T28

6

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

128

1

T6

2

T7

4

T28

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

125

1

T6

2

T7

1

T28

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

95

1

T3

5

T6

2

T7

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

120

1

T3

3

T6

2

T7

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

118

1

T6

3

T7

1

T40

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

114

1

T1

1

T6

1

T40

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

102

1

T28

1

T40

1

T78

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

92

1

T3

3

T6

1

T7

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

125

1

T1

1

T3

1

T6

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

95

1

T3

2

T6

4

T28

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

84

1

T3

6

T7

2

T78

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

90

1

T1

1

T6

2

T40

2

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3681	1			T9	6		T10	2		T11	13
auto[0]	values[0]	valids[0x1]	16644	1			T8	2		T11	13		T25	10
auto[0]	values[1]	valids[0x1]	558	1			T11	3		T14	2		T30	2
auto[0]	values[2]	valids[0x0]	516	1			T14	2		T30	2		T31	3
auto[0]	values[2]	valids[0x1]	334	1			T11	1		T30	1		T31	2
auto[0]	values[3]	valids[0x0]	499	1			T11	2		T30	5		T31	2
auto[0]	values[3]	valids[0x1]	271	1			T11	3		T30	1		T31	2
auto[0]	values[4]	valids[0x0]	584	1			T14	2		T30	2		T31	2
auto[0]	values[4]	valids[0x1]	265	1			T14	2		T30	4		T31	2
auto[0]	values[5]	valids[0x0]	488	1			T30	3		T177	2		T31	2
auto[0]	values[5]	valids[0x1]	252	1			T30	5		T31	2		T89	4
auto[0]	values[6]	valids[0x0]	492	1			T30	11		T31	2		T45	1
auto[0]	values[6]	valids[0x1]	279	1			T8	4		T30	2		T43	7
auto[0]	values[7]	valids[0x0]	534	1			T8	2		T11	2		T30	3
auto[0]	values[7]	valids[0x1]	258	1			T30	2		T46	4		T64	6
auto[0]	values[8]	valids[0x0]	3356	1			T11	12		T14	12		T25	6
auto[0]	values[8]	valids[0x1]	1992	1			T11	11		T25	2		T30	20
auto[1]	values[0]	valids[0x0]	4026	1			T1	22		T3	51		T6	71
auto[1]	values[0]	valids[0x1]	16613	1			T1	22		T3	79		T6	92
auto[1]	values[1]	valids[0x1]	533	1			T1	5		T3	17		T6	6
auto[1]	values[2]	valids[0x0]	397	1			T1	2		T3	3		T6	3
auto[1]	values[2]	valids[0x1]	295	1			T1	2		T3	8		T6	3
auto[1]	values[3]	valids[0x0]	408	1			T1	2		T3	6		T6	5
auto[1]	values[3]	valids[0x1]	253	1			T1	3		T3	1		T6	3
auto[1]	values[4]	valids[0x0]	322	1			T1	3		T3	1		T6	7
auto[1]	values[4]	valids[0x1]	263	1			T1	7		T6	2		T7	1
auto[1]	values[5]	valids[0x0]	418	1			T1	3		T3	7		T6	4
auto[1]	values[5]	valids[0x1]	301	1			T1	2		T3	6		T6	4
auto[1]	values[6]	valids[0x0]	410	1			T1	4		T3	4		T6	3
auto[1]	values[6]	valids[0x1]	278	1			T1	2		T3	1		T6	5
auto[1]	values[7]	valids[0x0]	356	1			T3	1		T6	7		T7	3
auto[1]	values[7]	valids[0x1]	292	1			T1	1		T3	4		T6	2
auto[1]	values[8]	valids[0x0]	2567	1			T1	15		T3	26		T6	40
auto[1]	values[8]	valids[0x1]	1789	1			T1	5		T3	25		T6	23