Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3271535

1

T1

3363

T3

11224

T6

9240

auto[1]

33089

1

T1

31

T3

93

T6

1120

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

882887

1

T1

231

T3

557

T6

653

auto[1]

2421737

1

T1

3163

T3

10760

T6

9707

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	604657	1			T1	4		T3	3491		T6	3417
auto[524288:1048575]	411087	1			T1	49		T3	4837		T6	1173
auto[1048576:1572863]	357299	1			T1	60		T3	7		T6	1182
auto[1572864:2097151]	386897	1			T1	13		T3	304		T6	1795
auto[2097152:2621439]	392764	1			T1	538		T3	697		T6	1488
auto[2621440:3145727]	370142	1			T1	786		T3	367		T6	455
auto[3145728:3670015]	404192	1			T1	32		T3	1561		T6	412
auto[3670016:4194303]	377586	1			T1	1912		T3	53		T6	438

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2454512

1

T1

3391

T3

11306

T6

10349

auto[1]

850112

1

T1

3

T3

11

T6

11

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2832084

1

T1

3347

T3

11102

T6

9713

auto[1]

472540

1

T1

47

T3

215

T6

647

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	183722	1			T1	4		T3	79		T6	35
auto[0]	auto[0]	auto[0:524287]	auto[1]	349066	1			T3	3392		T6	3235		T7	690
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	107072	1			T1	17		T3	84		T6	33
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	247973	1			T3	4747		T6	695		T11	128
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	89844	1			T1	21		T3	5		T6	65
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	212959	1			T1	15		T6	897		T28	775
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	72272	1			T1	11		T3	45		T6	38
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	244088	1			T3	259		T6	1700		T7	2350
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	82012	1			T1	17		T3	74		T6	103
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	262817	1			T1	517		T3	568		T6	1066
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	105912	1			T1	17		T3	24		T6	59
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	187807	1			T1	769		T3	152		T6	385
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	105393	1			T1	16		T3	58		T6	24
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	230973	1			T3	1481		T6	128		T7	808
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	123700	1			T1	52		T3	44		T6	43
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	199446	1			T1	1860		T6	384		T7	603
auto[0]	auto[1]	auto[0:524287]	auto[0]	1254	1			T3	3		T6	4		T30	3
auto[0]	auto[1]	auto[0:524287]	auto[1]	65750	1			T43	2539		T224	431		T209	577
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	1109	1			T1	17		T6	14		T9	410
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	51298	1			T6	256		T28	2899		T40	132
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	767	1			T1	12		T3	2		T6	16
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	49294	1			T7	7		T224	128		T17	2604
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	880	1			T1	2		T6	27		T7	4
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	66772	1			T7	2		T45	3219		T35	2607
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	1738	1			T3	8		T6	22		T9	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	41945	1			T6	3		T50	128		T51	287
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	1640	1			T3	52		T7	1		T28	3
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	69638	1			T3	131		T7	256		T28	175
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	784	1			T1	16		T3	7		T7	4
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	63133	1			T7	130		T11	512		T28	129
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	979	1			T3	9		T6	8		T28	5
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	49498	1			T28	768		T40	3012		T30	1
auto[1]	auto[0]	auto[0:524287]	auto[0]	492	1			T3	17		T6	15		T7	1
auto[1]	auto[0]	auto[0:524287]	auto[1]	3688	1			T6	128		T7	41		T30	22
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	389	1			T1	15		T3	6		T6	27
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	2848	1			T6	143		T28	24		T35	29
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	397	1			T1	10		T6	27		T11	7
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	3397	1			T1	2		T6	175		T28	10
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	310	1			T6	5		T7	2		T28	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	2014	1			T7	81		T28	20		T31	2
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	411	1			T1	4		T3	18		T6	33
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	3132	1			T3	29		T6	256		T7	105
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	386	1			T3	5		T6	11		T7	5
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	3873	1			T7	168		T28	15		T40	84
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	400	1			T3	14		T7	2		T28	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2627	1			T3	1		T7	61		T28	38
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	319	1			T6	3		T7	1		T11	9
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2345	1			T7	9		T11	14		T28	15
auto[1]	auto[1]	auto[0:524287]	auto[0]	105	1			T49	12		T231	4		T140	2
auto[1]	auto[1]	auto[0:524287]	auto[1]	580	1			T140	29		T18	6		T204	20
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	72	1			T6	5		T28	1		T40	3
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	326	1			T28	7		T209	25		T18	3
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	73	1			T6	2		T17	1		T49	2
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	568	1			T17	59		T248	12		T163	11
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	111	1			T6	25		T7	2		T209	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	450	1			T7	19		T209	22		T18	2
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	81	1			T6	5		T79	1		T21	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	628	1			T79	6		T21	1		T36	57
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	94	1			T3	3		T224	6		T180	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	792	1			T180	36		T133	3		T140	19
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	84	1			T6	4		T7	2		T28	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	798	1			T6	256		T7	59		T28	37
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	85	1			T30	1		T50	1		T224	6
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	1214	1			T30	18		T50	1		T209	1

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1959439	1			T1	3316		T3	11012		T6	8890
auto[0]	auto[0]	auto[1]	845617	1			T7	6		T8	19301		T9	1294
auto[0]	auto[1]	auto[0]	462611	1			T1	47		T3	212		T6	350
auto[0]	auto[1]	auto[1]	3868	1			T7	4		T9	402		T28	2
auto[1]	auto[0]	auto[0]	26520	1			T1	28		T3	80		T6	812
auto[1]	auto[0]	auto[1]	508	1			T1	3		T3	10		T6	11
auto[1]	auto[1]	auto[0]	5942	1			T3	2		T6	297		T7	82
auto[1]	auto[1]	auto[1]	119	1			T3	1		T40	2		T30	1