Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2717580	1			T1	266		T2	1		T3	2768
all_pins[1]	2717580	1			T1	266		T2	1		T3	2768
all_pins[2]	2717580	1			T1	266		T2	1		T3	2768
all_pins[3]	2717580	1			T1	266		T2	1		T3	2768
all_pins[4]	2717580	1			T1	266		T2	1		T3	2768
all_pins[5]	2717580	1			T1	266		T2	1		T3	2768
all_pins[6]	2717580	1			T1	266		T2	1		T3	2768
all_pins[7]	2717580	1			T1	266		T2	1		T3	2768

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	21696839	1			T1	2128		T2	8		T3	22144
values[0x1]	43801	1			T16	18		T17	43		T72	45
transitions[0x0=>0x1]	42141	1			T16	12		T17	28		T72	32
transitions[0x1=>0x0]	42151	1			T16	12		T17	28		T72	32

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2716895	1			T1	266		T2	1		T3	2768
all_pins[0]	values[0x1]	685	1			T16	3		T17	12		T72	4
all_pins[0]	transitions[0x0=>0x1]	410	1			T16	1		T17	8		T72	4
all_pins[0]	transitions[0x1=>0x0]	366	1			T72	4		T18	3		T36	121
all_pins[1]	values[0x0]	2716939	1			T1	266		T2	1		T3	2768
all_pins[1]	values[0x1]	641	1			T16	2		T17	4		T72	4
all_pins[1]	transitions[0x0=>0x1]	414	1			T16	2		T17	2		T72	4
all_pins[1]	transitions[0x1=>0x0]	135	1			T16	2		T72	9		T18	7
all_pins[2]	values[0x0]	2717218	1			T1	266		T2	1		T3	2768
all_pins[2]	values[0x1]	362	1			T16	2		T17	2		T72	9
all_pins[2]	transitions[0x0=>0x1]	320	1			T16	2		T17	2		T72	4
all_pins[2]	transitions[0x1=>0x0]	146	1			T16	2		T17	7		T72	5
all_pins[3]	values[0x0]	2717392	1			T1	266		T2	1		T3	2768
all_pins[3]	values[0x1]	188	1			T16	2		T17	7		T72	10
all_pins[3]	transitions[0x0=>0x1]	140	1			T17	4		T72	6		T18	8
all_pins[3]	transitions[0x1=>0x0]	163	1			T16	3		T17	3		T72	3
all_pins[4]	values[0x0]	2717369	1			T1	266		T2	1		T3	2768
all_pins[4]	values[0x1]	211	1			T16	5		T17	6		T72	7
all_pins[4]	transitions[0x0=>0x1]	158	1			T16	3		T17	4		T72	5
all_pins[4]	transitions[0x1=>0x0]	1757	1			T17	2		T72	3		T18	5
all_pins[5]	values[0x0]	2715770	1			T1	266		T2	1		T3	2768
all_pins[5]	values[0x1]	1810	1			T16	2		T17	4		T72	5
all_pins[5]	transitions[0x0=>0x1]	888	1			T16	2		T17	4		T72	5
all_pins[5]	transitions[0x1=>0x0]	38804	1			T16	2		T17	3		T72	2
all_pins[6]	values[0x0]	2677854	1			T1	266		T2	1		T3	2768
all_pins[6]	values[0x1]	39726	1			T16	2		T17	3		T72	2
all_pins[6]	transitions[0x0=>0x1]	39678	1			T16	2		T17	2		T72	1
all_pins[6]	transitions[0x1=>0x0]	130	1			T17	4		T72	3		T18	2
all_pins[7]	values[0x0]	2717402	1			T1	266		T2	1		T3	2768
all_pins[7]	values[0x1]	178	1			T17	5		T72	4		T18	4
all_pins[7]	transitions[0x0=>0x1]	133	1			T17	2		T72	3		T18	3
all_pins[7]	transitions[0x1=>0x0]	650	1			T16	3		T17	9		T72	3