Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17392

1

T8

8

T9

6

T10

2

auto[1]

13611

1

T11

26

T25

20

T30

163

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3584	1			T25	20		T31	20		T42	4
values[1]	3588	1			T9	6		T11	20		T31	40
values[2]	4055	1			T27	8		T30	47		T31	32
values[3]	3639	1			T11	20		T30	49		T89	18
values[4]	4170	1			T10	2		T11	20		T14	20
values[5]	3413	1			T30	91		T45	20		T251	6
values[6]	4458	1			T30	62		T177	6		T64	20
values[7]	4096	1			T8	8		T252	2		T64	20

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4111	1			T8	8		T11	40		T14	20
values[1]	4073	1			T10	2		T30	27		T177	6
values[2]	3917	1			T30	66		T64	20		T43	32
values[3]	4183	1			T9	6		T25	20		T30	43
values[4]	4059	1			T30	68		T31	20		T89	18
values[5]	3674	1			T42	4		T251	6		T253	4
values[6]	3122	1			T64	40		T211	2		T43	58
values[7]	3864	1			T11	20		T27	8		T30	74

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	273	1			T47	13		T254	2		T230	7
auto[0]	values[0]	values[1]	313	1			T18	11		T201	14		T204	12
auto[0]	values[0]	values[2]	249	1			T47	12		T231	17		T179	12
auto[0]	values[0]	values[3]	380	1			T31	8		T255	6		T256	4
auto[0]	values[0]	values[4]	331	1			T17	13		T140	33		T243	10
auto[0]	values[0]	values[5]	175	1			T42	4		T253	4		T36	55
auto[0]	values[0]	values[6]	228	1			T211	2		T212	21		T204	7
auto[0]	values[0]	values[7]	185	1			T180	12		T231	14		T226	11
auto[0]	values[1]	values[0]	360	1			T11	14		T212	84		T139	12
auto[0]	values[1]	values[1]	256	1			T257	4		T219	16		T258	12
auto[0]	values[1]	values[2]	166	1			T49	12		T18	13		T203	29
auto[0]	values[1]	values[3]	111	1			T9	6		T31	9		T203	15
auto[0]	values[1]	values[4]	271	1			T31	15		T17	65		T47	8
auto[0]	values[1]	values[5]	334	1			T17	13		T47	12		T180	14
auto[0]	values[1]	values[6]	160	1			T17	9		T98	8		T49	10
auto[0]	values[1]	values[7]	254	1			T43	12		T17	43		T204	16
auto[0]	values[2]	values[0]	357	1			T31	18		T180	13		T231	12
auto[0]	values[2]	values[1]	250	1			T47	12		T178	12		T231	6
auto[0]	values[2]	values[2]	233	1			T47	15		T19	13		T226	49
auto[0]	values[2]	values[3]	307	1			T242	14		T259	10		T260	8
auto[0]	values[2]	values[4]	293	1			T30	19		T43	29		T17	8
auto[0]	values[2]	values[5]	142	1			T261	6		T178	12		T135	16
auto[0]	values[2]	values[6]	345	1			T64	15		T43	28		T49	17
auto[0]	values[2]	values[7]	417	1			T27	8		T30	10		T204	136
auto[0]	values[3]	values[0]	262	1			T11	10		T195	4		T17	10
auto[0]	values[3]	values[1]	291	1			T30	16		T87	24		T43	6
auto[0]	values[3]	values[2]	256	1			T64	11		T17	11		T229	12
auto[0]	values[3]	values[3]	154	1			T231	11		T38	25		T203	9
auto[0]	values[3]	values[4]	301	1			T89	18		T262	2		T140	36
auto[0]	values[3]	values[5]	484	1			T18	11		T19	10		T223	108
auto[0]	values[3]	values[6]	271	1			T263	14		T36	13		T37	17
auto[0]	values[3]	values[7]	209	1			T30	10		T204	35		T144	14
auto[0]	values[4]	values[0]	443	1			T14	20		T17	14		T140	86
auto[0]	values[4]	values[1]	255	1			T10	2		T180	15		T179	12
auto[0]	values[4]	values[2]	296	1			T18	23		T218	24		T264	16
auto[0]	values[4]	values[3]	243	1			T45	15		T47	15		T49	26
auto[0]	values[4]	values[4]	326	1			T43	14		T17	8		T212	93
auto[0]	values[4]	values[5]	133	1			T180	5		T265	2		T199	8
auto[0]	values[4]	values[6]	296	1			T180	82		T204	8		T266	12
auto[0]	values[4]	values[7]	407	1			T11	10		T30	9		T49	12
auto[0]	values[5]	values[0]	260	1			T43	18		T17	13		T47	11
auto[0]	values[5]	values[1]	184	1			T45	13		T47	9		T180	17
auto[0]	values[5]	values[2]	222	1			T30	12		T18	27		T223	15
auto[0]	values[5]	values[3]	208	1			T30	9		T18	15		T267	2
auto[0]	values[5]	values[4]	225	1			T30	15		T43	12		T47	14
auto[0]	values[5]	values[5]	204	1			T251	6		T47	12		T180	6
auto[0]	values[5]	values[6]	226	1			T180	11		T237	11		T228	8
auto[0]	values[5]	values[7]	214	1			T142	8		T18	18		T268	12
auto[0]	values[6]	values[0]	252	1			T269	4		T219	15		T161	13
auto[0]	values[6]	values[1]	234	1			T45	13		T97	2		T231	14
auto[0]	values[6]	values[2]	377	1			T30	8		T43	24		T49	6
auto[0]	values[6]	values[3]	376	1			T30	7		T47	7		T238	7
auto[0]	values[6]	values[4]	462	1			T43	56		T17	8		T227	71
auto[0]	values[6]	values[5]	152	1			T270	4		T18	13		T204	20
auto[0]	values[6]	values[6]	265	1			T64	12		T231	12		T18	13
auto[0]	values[6]	values[7]	208	1			T180	10		T18	28		T271	6
auto[0]	values[7]	values[0]	262	1			T8	8		T64	13		T43	6
auto[0]	values[7]	values[1]	321	1			T17	16		T49	24		T272	47
auto[0]	values[7]	values[2]	327	1			T212	39		T18	21		T273	14
auto[0]	values[7]	values[3]	277	1			T252	2		T210	4		T274	16
auto[0]	values[7]	values[4]	296	1			T236	10		T179	16		T18	15
auto[0]	values[7]	values[5]	225	1			T178	12		T179	6		T204	6
auto[0]	values[7]	values[6]	209	1			T43	10		T140	55		T275	16
auto[0]	values[7]	values[7]	389	1			T276	10		T19	12		T277	10
auto[1]	values[0]	values[0]	158	1			T47	7		T230	13		T278	9
auto[1]	values[0]	values[1]	232	1			T18	9		T204	92		T279	6
auto[1]	values[0]	values[2]	307	1			T47	8		T231	3		T179	8
auto[1]	values[0]	values[3]	193	1			T25	20		T31	12		T38	8
auto[1]	values[0]	values[4]	112	1			T17	10		T140	8		T227	46
auto[1]	values[0]	values[5]	94	1			T36	6		T203	12		T220	6
auto[1]	values[0]	values[6]	211	1			T212	59		T204	13		T203	15
auto[1]	values[0]	values[7]	143	1			T180	8		T231	6		T226	32
auto[1]	values[1]	values[0]	150	1			T11	6		T212	4		T179	10
auto[1]	values[1]	values[1]	145	1			T214	14		T219	11		T258	15
auto[1]	values[1]	values[2]	188	1			T49	8		T18	7		T203	11
auto[1]	values[1]	values[3]	130	1			T31	11		T203	5		T280	14
auto[1]	values[1]	values[4]	239	1			T31	5		T17	15		T47	12
auto[1]	values[1]	values[5]	460	1			T17	7		T47	8		T180	6
auto[1]	values[1]	values[6]	182	1			T17	11		T49	10		T178	7
auto[1]	values[1]	values[7]	182	1			T43	8		T17	3		T204	4
auto[1]	values[2]	values[0]	354	1			T31	14		T180	7		T231	8
auto[1]	values[2]	values[1]	296	1			T47	8		T178	11		T231	14
auto[1]	values[2]	values[2]	82	1			T47	5		T19	13		T226	15
auto[1]	values[2]	values[3]	200	1			T18	18		T281	4		T238	9
auto[1]	values[2]	values[4]	298	1			T30	5		T43	6		T17	16
auto[1]	values[2]	values[5]	127	1			T178	8		T18	12		T19	14
auto[1]	values[2]	values[6]	107	1			T64	5		T43	10		T49	3
auto[1]	values[2]	values[7]	247	1			T30	13		T46	20		T204	12
auto[1]	values[3]	values[0]	126	1			T11	10		T17	10		T231	7
auto[1]	values[3]	values[1]	241	1			T30	11		T43	14		T17	9
auto[1]	values[3]	values[2]	204	1			T64	9		T17	9		T238	9
auto[1]	values[3]	values[3]	172	1			T231	9		T38	28		T203	24
auto[1]	values[3]	values[4]	120	1			T140	4		T18	4		T238	4
auto[1]	values[3]	values[5]	374	1			T282	2		T18	9		T19	10
auto[1]	values[3]	values[6]	36	1			T36	12		T37	5		T283	9
auto[1]	values[3]	values[7]	138	1			T30	12		T204	10		T144	6
auto[1]	values[4]	values[0]	246	1			T17	6		T140	11		T18	33
auto[1]	values[4]	values[1]	340	1			T180	5		T179	8		T223	10
auto[1]	values[4]	values[2]	142	1			T18	22		T264	4		T213	33
auto[1]	values[4]	values[3]	217	1			T45	5		T47	8		T49	14
auto[1]	values[4]	values[4]	225	1			T43	31		T17	13		T212	20
auto[1]	values[4]	values[5]	99	1			T180	15		T284	16		T220	16
auto[1]	values[4]	values[6]	180	1			T180	13		T204	71		T285	18
auto[1]	values[4]	values[7]	322	1			T11	10		T30	20		T49	8
auto[1]	values[5]	values[0]	138	1			T43	2		T17	8		T47	9
auto[1]	values[5]	values[1]	204	1			T45	7		T47	11		T180	3
auto[1]	values[5]	values[2]	278	1			T30	12		T18	18		T223	5
auto[1]	values[5]	values[3]	302	1			T30	14		T18	5		T204	83
auto[1]	values[5]	values[4]	202	1			T30	29		T43	8		T47	6
auto[1]	values[5]	values[5]	224	1			T47	9		T180	110		T212	9
auto[1]	values[5]	values[6]	201	1			T180	36		T237	9		T228	34
auto[1]	values[5]	values[7]	121	1			T18	9		T286	16		T227	9
auto[1]	values[6]	values[0]	202	1			T219	5		T161	10		T208	4
auto[1]	values[6]	values[1]	409	1			T177	6		T45	7		T231	6
auto[1]	values[6]	values[2]	347	1			T30	34		T43	8		T49	14
auto[1]	values[6]	values[3]	522	1			T30	13		T47	13		T238	72
auto[1]	values[6]	values[4]	142	1			T43	6		T17	47		T227	8
auto[1]	values[6]	values[5]	233	1			T18	7		T204	20		T36	25
auto[1]	values[6]	values[6]	103	1			T64	8		T231	8		T18	15
auto[1]	values[6]	values[7]	174	1			T180	10		T18	18		T219	30
auto[1]	values[7]	values[0]	268	1			T64	7		T43	14		T48	8
auto[1]	values[7]	values[1]	102	1			T17	9		T49	16		T18	11
auto[1]	values[7]	values[2]	243	1			T212	11		T18	8		T36	54
auto[1]	values[7]	values[3]	391	1			T41	5		T287	4		T228	16
auto[1]	values[7]	values[4]	216	1			T179	4		T18	5		T223	9
auto[1]	values[7]	values[5]	214	1			T178	12		T179	14		T204	14
auto[1]	values[7]	values[6]	102	1			T43	10		T140	6		T288	72
auto[1]	values[7]	values[7]	254	1			T19	48		T228	4		T162	14