Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	416	1			T11	2		T30	9		T31	1
auto[ReadAddrCrossIntoMailbox]	267	1			T11	2		T30	1		T64	2
auto[ReadAddrCrossOutOfMailbox]	301	1			T8	2		T11	1		T30	5
auto[ReadAddrCrossAllMailbox]	194	1			T30	2		T64	2		T253	2
auto[ReadAddrOutsideMailbox]	3311	1			T8	6		T11	11		T14	8

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2223

1

T8

4

T11

2

T14

4

auto[1]

2266

1

T8

4

T11

14

T14

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	756	1			T8	2		T11	4		T14	2
read_ops[0x0b]	726	1			T8	4		T14	2		T30	7
read_ops[0x3b]	728	1			T11	1		T30	5		T31	2
read_ops[0x6b]	740	1			T8	2		T11	1		T14	2
read_ops[0xbb]	782	1			T11	6		T14	2		T30	4
read_ops[0xeb]	757	1			T11	4		T30	11		T31	1

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	37	1			T30	1		T64	1		T98	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	35	1			T17	1		T98	1		T47	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	16	1			T64	1		T49	1		T18	2
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	12	1			T11	1		T47	2		T204	2
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T30	1		T236	1		T204	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	23	1			T43	1		T47	1		T49	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T212	1		T37	1		T41	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T30	1		T180	1		T287	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	275	1			T8	1		T11	1		T14	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	303	1			T8	1		T11	2		T14	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	28	1			T30	1		T43	1		T17	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	36	1			T30	2		T64	1		T49	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	23	1			T17	1		T47	2		T204	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	29	1			T43	1		T47	1		T237	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	24	1			T8	1		T17	2		T180	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	24	1			T8	1		T43	1		T47	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T43	1		T17	3		T49	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	13	1			T231	1		T18	1		T38	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	273	1			T8	1		T14	1		T30	4
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	259	1			T8	1		T14	1		T64	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	34	1			T30	1		T47	2		T140	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	38	1			T43	1		T47	1		T180	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	25	1			T97	1		T47	1		T212	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	16	1			T64	1		T43	1		T97	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	15	1			T30	1		T253	1		T17	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	33	1			T64	2		T45	1		T253	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	11	1			T18	1		T19	1		T227	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T64	1		T212	1		T36	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	262	1			T11	1		T30	3		T31	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	280	1			T31	1		T42	1		T43	9
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	29	1			T18	1		T237	1		T204	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	32	1			T64	1		T43	1		T17	2
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	21	1			T47	3		T179	1		T36	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	20	1			T30	1		T49	1		T180	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	16	1			T180	1		T237	1		T287	2
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	19	1			T30	1		T49	2		T180	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	20	1			T47	1		T180	4		T178	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	23	1			T49	1		T180	2		T18	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	263	1			T8	1		T14	1		T30	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	297	1			T8	1		T11	1		T14	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	41	1			T30	1		T43	1		T17	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	33	1			T11	2		T45	1		T47	2
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	23	1			T17	1		T142	1		T18	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	21	1			T11	1		T17	1		T47	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	39	1			T17	2		T47	1		T180	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	24	1			T47	1		T37	1		T38	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T212	1		T179	1		T36	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	12	1			T18	1		T204	1		T289	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	285	1			T14	1		T30	2		T31	4
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	286	1			T11	3		T14	1		T30	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	39	1			T30	1		T17	1		T47	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	34	1			T30	2		T31	1		T43	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	36	1			T255	1		T236	2		T140	2
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	25	1			T43	1		T255	1		T180	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	32	1			T43	1		T47	1		T180	2
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	31	1			T11	1		T30	2		T43	2
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T30	1		T64	1		T253	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T253	1		T204	1		T217	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	265	1			T30	5		T89	1		T64	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	263	1			T11	3		T89	1		T45	1