Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3444	1			T30	24		T42	4		T46	20
values[1]	4557	1			T30	44		T262	2		T43	149
values[2]	3626	1			T11	20		T30	29		T31	20
values[3]	3978	1			T10	2		T11	20		T30	22
values[4]	3614	1			T9	6		T25	20		T31	32
values[5]	3679	1			T11	20		T27	8		T30	23
values[6]	4455	1			T14	20		T64	20		T45	20
values[7]	3650	1			T8	8		T30	136		T177	6

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4053	1			T30	52		T177	6		T43	20
values[1]	3341	1			T9	6		T11	60		T14	20
values[2]	3770	1			T25	20		T30	48		T89	18
values[3]	3534	1			T10	2		T30	64		T31	32
values[4]	4252	1			T8	8		T30	42		T64	20
values[5]	4432	1			T27	8		T31	40		T42	4
values[6]	4028	1			T30	23		T31	20		T64	20
values[7]	3593	1			T30	49		T252	2		T46	20

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30329

1

T8

8

T9

6

T10

2

auto[1]

674

1

T11

1

T30

11

T31

6

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	443	1			T236	10		T212	56		T18	20
auto[0]	values[0]	values[1]	453	1			T210	4		T253	4		T17	20
auto[0]	values[0]	values[2]	301	1			T30	22		T195	4		T47	20
auto[0]	values[0]	values[3]	509	1			T64	20		T98	8		T180	20
auto[0]	values[0]	values[4]	483	1			T246	4		T49	20		T18	20
auto[0]	values[0]	values[5]	359	1			T42	4		T242	14		T140	97
auto[0]	values[0]	values[6]	558	1			T97	2		T17	20		T41	24
auto[0]	values[0]	values[7]	270	1			T46	16		T284	16		T203	40
auto[0]	values[1]	values[0]	535	1			T180	20		T231	20		T18	24
auto[0]	values[1]	values[1]	515	1			T17	22		T178	23		T265	2
auto[0]	values[1]	values[2]	613	1			T30	23		T290	12		T268	12
auto[0]	values[1]	values[3]	588	1			T30	20		T47	20		T212	20
auto[0]	values[1]	values[4]	521	1			T17	23		T231	19		T212	20
auto[0]	values[1]	values[5]	589	1			T43	93		T47	39		T180	20
auto[0]	values[1]	values[6]	719	1			T262	2		T43	50		T231	19
auto[0]	values[1]	values[7]	371	1			T17	19		T49	20		T141	10
auto[0]	values[2]	values[0]	485	1			T30	26		T18	45		T267	2
auto[0]	values[2]	values[1]	578	1			T11	20		T231	20		T204	43
auto[0]	values[2]	values[2]	383	1			T87	24		T49	17		T179	20
auto[0]	values[2]	values[3]	576	1			T19	19		T238	78		T204	19
auto[0]	values[2]	values[4]	457	1			T17	25		T231	20		T19	57
auto[0]	values[2]	values[5]	372	1			T17	20		T36	57		T226	16
auto[0]	values[2]	values[6]	454	1			T31	17		T47	20		T180	46
auto[0]	values[2]	values[7]	225	1			T231	20		T272	47		T140	20
auto[0]	values[3]	values[0]	566	1			T291	4		T49	20		T178	27
auto[0]	values[3]	values[1]	394	1			T11	19		T179	19		T18	52
auto[0]	values[3]	values[2]	311	1			T89	18		T88	6		T277	10
auto[0]	values[3]	values[3]	203	1			T10	2		T64	20		T180	19
auto[0]	values[3]	values[4]	599	1			T45	19		T17	55		T180	92
auto[0]	values[3]	values[5]	550	1			T31	18		T17	99		T18	20
auto[0]	values[3]	values[6]	554	1			T17	20		T282	2		T223	69
auto[0]	values[3]	values[7]	729	1			T30	22		T47	20		T49	18
auto[0]	values[4]	values[0]	272	1			T231	20		T256	4		T238	22
auto[0]	values[4]	values[1]	302	1			T9	6		T47	20		T276	10
auto[0]	values[4]	values[2]	554	1			T25	20		T292	16		T41	20
auto[0]	values[4]	values[3]	471	1			T31	31		T180	20		T140	40
auto[0]	values[4]	values[4]	450	1			T254	2		T18	19		T293	16
auto[0]	values[4]	values[5]	711	1			T43	44		T212	84		T18	19
auto[0]	values[4]	values[6]	330	1			T18	20		T36	69		T217	21
auto[0]	values[4]	values[7]	426	1			T43	20		T263	14		T18	38
auto[0]	values[5]	values[0]	469	1			T294	10		T18	25		T171	14
auto[0]	values[5]	values[1]	486	1			T11	20		T211	2		T43	38
auto[0]	values[5]	values[2]	291	1			T48	6		T49	20		T179	20
auto[0]	values[5]	values[3]	250	1			T180	20		T295	18		T203	20
auto[0]	values[5]	values[4]	566	1			T180	20		T139	12		T18	29
auto[0]	values[5]	values[5]	733	1			T27	8		T180	20		T212	55
auto[0]	values[5]	values[6]	524	1			T30	23		T64	20		T45	16
auto[0]	values[5]	values[7]	287	1			T252	2		T18	38		T36	20
auto[0]	values[6]	values[0]	645	1			T49	20		T180	116		T142	8
auto[0]	values[6]	values[1]	401	1			T14	20		T261	6		T203	20
auto[0]	values[6]	values[2]	851	1			T17	20		T47	42		T49	20
auto[0]	values[6]	values[3]	477	1			T212	68		T179	20		T228	54
auto[0]	values[6]	values[4]	539	1			T64	20		T251	6		T230	20
auto[0]	values[6]	values[5]	484	1			T17	46		T255	6		T212	60
auto[0]	values[6]	values[6]	366	1			T45	19		T231	18		T36	66
auto[0]	values[6]	values[7]	619	1			T43	40		T47	38		T178	20
auto[0]	values[7]	values[0]	555	1			T30	20		T177	6		T43	19
auto[0]	values[7]	values[1]	143	1			T47	20		T223	20		T36	20
auto[0]	values[7]	values[2]	385	1			T231	20		T243	10		T270	4
auto[0]	values[7]	values[3]	381	1			T30	44		T17	26		T178	22
auto[0]	values[7]	values[4]	564	1			T8	8		T30	41		T260	8
auto[0]	values[7]	values[5]	533	1			T31	20		T259	10		T135	16
auto[0]	values[7]	values[6]	420	1			T179	19		T296	2		T18	23
auto[0]	values[7]	values[7]	581	1			T30	26		T19	20		T38	21
auto[1]	values[0]	values[0]	6	1			T212	1		T19	1		T38	2
auto[1]	values[0]	values[1]	11	1			T49	3		T223	1		T38	1
auto[1]	values[0]	values[2]	10	1			T30	2		T47	1		T178	1
auto[1]	values[0]	values[3]	12	1			T297	5		T298	2		T299	2
auto[1]	values[0]	values[4]	7	1			T164	1		T206	1		T283	2
auto[1]	values[0]	values[5]	3	1			T217	1		T300	1		T52	1
auto[1]	values[0]	values[6]	13	1			T17	1		T41	1		T203	1
auto[1]	values[0]	values[7]	6	1			T46	4		T301	2		-	-
auto[1]	values[1]	values[0]	11	1			T18	1		T280	1		T301	1
auto[1]	values[1]	values[1]	18	1			T17	2		T178	1		T227	1
auto[1]	values[1]	values[2]	4	1			T30	1		T221	2		T302	1
auto[1]	values[1]	values[3]	9	1			T287	3		T80	1		T258	2
auto[1]	values[1]	values[4]	10	1			T231	1		T140	1		T19	1
auto[1]	values[1]	values[5]	16	1			T43	4		T47	1		T231	3
auto[1]	values[1]	values[6]	30	1			T43	2		T231	1		T179	4
auto[1]	values[1]	values[7]	8	1			T17	2		T217	3		T303	2
auto[1]	values[2]	values[0]	21	1			T30	3		T37	3		T80	2
auto[1]	values[2]	values[1]	17	1			T204	2		T233	2		T161	1
auto[1]	values[2]	values[2]	11	1			T49	3		T235	1		T280	1
auto[1]	values[2]	values[3]	21	1			T19	2		T238	1		T204	1
auto[1]	values[2]	values[4]	8	1			T19	3		T288	2		T166	1
auto[1]	values[2]	values[5]	7	1			T226	4		T206	1		T304	1
auto[1]	values[2]	values[6]	9	1			T31	3		T180	1		T145	2
auto[1]	values[2]	values[7]	2	1			T217	1		T161	1		-	-
auto[1]	values[3]	values[0]	8	1			T178	1		T140	1		T37	1
auto[1]	values[3]	values[1]	5	1			T11	1		T179	1		T18	1
auto[1]	values[3]	values[2]	6	1			T80	2		T162	1		T206	2
auto[1]	values[3]	values[3]	2	1			T180	1		T305	1		-	-
auto[1]	values[3]	values[4]	10	1			T45	1		T180	3		T18	3
auto[1]	values[3]	values[5]	14	1			T31	2		T17	1		T223	4
auto[1]	values[3]	values[6]	15	1			T223	1		T164	3		T206	1
auto[1]	values[3]	values[7]	12	1			T49	2		T19	2		T219	2
auto[1]	values[4]	values[0]	5	1			T306	2		T52	1		T60	2
auto[1]	values[4]	values[1]	2	1			T18	1		T166	1		-	-
auto[1]	values[4]	values[2]	24	1			T292	2		T41	2		T38	1
auto[1]	values[4]	values[3]	15	1			T31	1		T18	1		T161	1
auto[1]	values[4]	values[4]	10	1			T18	1		T36	1		T168	1
auto[1]	values[4]	values[5]	17	1			T43	1		T212	4		T18	1
auto[1]	values[4]	values[6]	6	1			T217	2		T307	1		T308	1
auto[1]	values[4]	values[7]	19	1			T18	2		T204	3		T38	3
auto[1]	values[5]	values[0]	10	1			T18	3		T303	4		T309	1
auto[1]	values[5]	values[1]	6	1			T144	2		T310	1		T62	2
auto[1]	values[5]	values[2]	6	1			T48	2		T207	1		T222	3
auto[1]	values[5]	values[3]	3	1			T300	1		T311	1		T312	1
auto[1]	values[5]	values[4]	9	1			T204	2		T226	1		T313	1
auto[1]	values[5]	values[5]	19	1			T212	1		T289	1		T37	1
auto[1]	values[5]	values[6]	13	1			T45	4		T38	1		T80	4
auto[1]	values[5]	values[7]	7	1			T18	2		T286	2		T287	3
auto[1]	values[6]	values[0]	7	1			T287	2		T203	1		T206	1
auto[1]	values[6]	values[1]	3	1			T205	2		T300	1		-	-
auto[1]	values[6]	values[2]	7	1			T47	1		T238	1		T226	1
auto[1]	values[6]	values[3]	7	1			T212	2		T164	2		T314	1
auto[1]	values[6]	values[4]	7	1			T227	2		T315	2		T62	2
auto[1]	values[6]	values[5]	14	1			T316	4		T18	2		T164	1
auto[1]	values[6]	values[6]	11	1			T45	1		T231	2		T162	3
auto[1]	values[6]	values[7]	17	1			T47	2		T178	1		T214	4
auto[1]	values[7]	values[0]	15	1			T30	3		T43	1		T204	3
auto[1]	values[7]	values[1]	7	1			T228	1		T80	4		T317	2
auto[1]	values[7]	values[2]	13	1			T219	3		T203	2		T205	1
auto[1]	values[7]	values[3]	10	1			T17	2		T178	1		T38	2
auto[1]	values[7]	values[4]	12	1			T30	1		T288	1		T308	2
auto[1]	values[7]	values[5]	11	1			T311	2		T305	1		T298	2
auto[1]	values[7]	values[6]	6	1			T179	1		T18	1		T19	1
auto[1]	values[7]	values[7]	14	1			T30	1		T19	1		T227	1