Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	823	1			T16	8		T17	21		T72	24
all_values[1]	823	1			T16	8		T17	21		T72	24
all_values[2]	823	1			T16	8		T17	21		T72	24
all_values[3]	823	1			T16	8		T17	21		T72	24
all_values[4]	823	1			T16	8		T17	21		T72	24
all_values[5]	823	1			T16	8		T17	21		T72	24
all_values[6]	823	1			T16	8		T17	21		T72	24
all_values[7]	823	1			T16	8		T17	21		T72	24

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3652

1

T16

40

T17

96

T72

113

auto[1]

2932

1

T16

24

T17

72

T72

79

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2666

1

T16

23

T17

64

T72

77

auto[1]

3918

1

T16

41

T17

104

T72

115

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3804

1

T16

37

T17

96

T72

113

auto[1]

2780

1

T16

27

T17

72

T72

79

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	192	1			T16	2		T17	1		T72	9
all_values[0]	auto[0]	auto[0]	auto[1]	65	1			T16	2		T72	1		T18	3
all_values[0]	auto[0]	auto[1]	auto[0]	150	1			T17	6		T72	4		T20	4
all_values[0]	auto[0]	auto[1]	auto[1]	80	1			T16	1		T17	3		T72	2
all_values[0]	auto[1]	auto[0]	auto[1]	168	1			T16	3		T17	4		T72	5
all_values[0]	auto[1]	auto[1]	auto[1]	168	1			T17	7		T72	3		T18	8
all_values[1]	auto[0]	auto[0]	auto[0]	193	1			T17	5		T72	6		T18	7
all_values[1]	auto[0]	auto[0]	auto[1]	79	1			T16	1		T17	2		T72	5
all_values[1]	auto[0]	auto[1]	auto[0]	131	1			T16	4		T17	2		T72	1
all_values[1]	auto[0]	auto[1]	auto[1]	76	1			T16	1		T17	2		T72	2
all_values[1]	auto[1]	auto[0]	auto[1]	187	1			T16	2		T17	5		T72	6
all_values[1]	auto[1]	auto[1]	auto[1]	157	1			T17	5		T72	4		T18	5
all_values[2]	auto[0]	auto[0]	auto[0]	185	1			T16	1		T17	3		T72	8
all_values[2]	auto[0]	auto[0]	auto[1]	92	1			T16	2		T17	2		T72	2
all_values[2]	auto[0]	auto[1]	auto[0]	121	1			T17	5		T72	1		T18	5
all_values[2]	auto[0]	auto[1]	auto[1]	82	1			T16	1		T17	1		T72	5
all_values[2]	auto[1]	auto[0]	auto[1]	185	1			T16	2		T17	8		T72	3
all_values[2]	auto[1]	auto[1]	auto[1]	158	1			T16	2		T17	2		T72	5
all_values[3]	auto[0]	auto[0]	auto[0]	190	1			T16	4		T17	4		T72	2
all_values[3]	auto[0]	auto[0]	auto[1]	95	1			T16	1		T17	2		T72	2
all_values[3]	auto[0]	auto[1]	auto[0]	125	1			T17	5		T72	2		T18	3
all_values[3]	auto[0]	auto[1]	auto[1]	73	1			T16	1		T17	3		T72	4
all_values[3]	auto[1]	auto[0]	auto[1]	191	1			T16	1		T17	4		T72	7
all_values[3]	auto[1]	auto[1]	auto[1]	149	1			T16	1		T17	3		T72	7
all_values[4]	auto[0]	auto[0]	auto[0]	173	1			T17	3		T72	8		T18	4
all_values[4]	auto[0]	auto[0]	auto[1]	93	1			T16	1		T17	5		T72	3
all_values[4]	auto[0]	auto[1]	auto[0]	118	1			T17	2		T72	2		T18	5
all_values[4]	auto[0]	auto[1]	auto[1]	97	1			T16	2		T17	2		T72	2
all_values[4]	auto[1]	auto[0]	auto[1]	186	1			T16	4		T17	6		T72	4
all_values[4]	auto[1]	auto[1]	auto[1]	156	1			T16	1		T17	3		T72	5
all_values[5]	auto[0]	auto[0]	auto[0]	231	1			T16	5		T17	11		T72	7
all_values[5]	auto[0]	auto[1]	auto[0]	229	1			T16	1		T17	2		T72	7
all_values[5]	auto[1]	auto[0]	auto[1]	219	1			T16	1		T17	3		T72	7
all_values[5]	auto[1]	auto[1]	auto[1]	144	1			T16	1		T17	5		T72	3
all_values[6]	auto[0]	auto[0]	auto[0]	182	1			T16	1		T17	4		T72	9
all_values[6]	auto[0]	auto[0]	auto[1]	91	1			T17	6		T72	2		T18	2
all_values[6]	auto[0]	auto[1]	auto[0]	132	1			T16	2		T17	2		T72	2
all_values[6]	auto[0]	auto[1]	auto[1]	70	1			T17	1		T18	1		T38	1
all_values[6]	auto[1]	auto[0]	auto[1]	209	1			T16	1		T17	7		T72	8
all_values[6]	auto[1]	auto[1]	auto[1]	139	1			T16	4		T17	1		T72	3
all_values[7]	auto[0]	auto[0]	auto[0]	173	1			T16	2		T17	5		T72	3
all_values[7]	auto[0]	auto[0]	auto[1]	72	1			T16	1		T17	2		T72	3
all_values[7]	auto[0]	auto[1]	auto[0]	141	1			T16	1		T17	4		T72	6
all_values[7]	auto[0]	auto[1]	auto[1]	73	1			T17	1		T72	3		T18	1
all_values[7]	auto[1]	auto[0]	auto[1]	201	1			T16	3		T17	4		T72	3
all_values[7]	auto[1]	auto[1]	auto[1]	163	1			T16	1		T17	5		T72	6

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal