Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1760

1

T29

2

T22

2

T23

4

auto[1]

1835

1

T29

1

T22

1

T23

1

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2003

1

T30

6

T31

20

T33

5

auto[1]

1592

1

T29

3

T22

3

T23

5

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2839

1

T29

3

T22

3

T23

5

auto[1]

756

1

T30

3

T31

2

T33

1

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	696	1			T30	1		T31	6		T32	4
valid[1]	705	1			T29	1		T22	2		T23	1
valid[2]	736	1			T29	1		T22	1		T30	1
valid[3]	700	1			T29	1		T23	2		T30	3
valid[4]	758	1			T23	2		T31	3		T32	2

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	126	1			T31	5		T35	1		T50	1
auto[0]	auto[0]	valid[0]	auto[1]	163	1			T34	3		T50	1		T85	1
auto[0]	auto[0]	valid[1]	auto[0]	116	1			T33	1		T35	1		T47	3
auto[0]	auto[0]	valid[1]	auto[1]	158	1			T29	1		T22	1		T23	1
auto[0]	auto[0]	valid[2]	auto[0]	127	1			T30	1		T31	1		T35	1
auto[0]	auto[0]	valid[2]	auto[1]	152	1			T22	1		T32	2		T85	2
auto[0]	auto[0]	valid[3]	auto[0]	111	1			T30	1		T31	3		T47	2
auto[0]	auto[0]	valid[3]	auto[1]	155	1			T29	1		T23	1		T32	1
auto[0]	auto[0]	valid[4]	auto[0]	133	1			T31	1		T35	1		T43	1
auto[0]	auto[0]	valid[4]	auto[1]	165	1			T23	2		T32	2		T34	2
auto[0]	auto[1]	valid[0]	auto[0]	128	1			T31	1		T50	2		T43	1
auto[0]	auto[1]	valid[0]	auto[1]	134	1			T32	4		T34	1		T85	1
auto[0]	auto[1]	valid[1]	auto[0]	125	1			T31	2		T33	1		T35	2
auto[0]	auto[1]	valid[1]	auto[1]	168	1			T22	1		T34	3		T85	1
auto[0]	auto[1]	valid[2]	auto[0]	137	1			T31	1		T33	1		T35	2
auto[0]	auto[1]	valid[2]	auto[1]	166	1			T29	1		T32	1		T34	1
auto[0]	auto[1]	valid[3]	auto[0]	125	1			T30	1		T31	2		T33	1
auto[0]	auto[1]	valid[3]	auto[1]	161	1			T23	1		T34	3		T86	3
auto[0]	auto[1]	valid[4]	auto[0]	119	1			T31	2		T35	1		T50	2
auto[0]	auto[1]	valid[4]	auto[1]	170	1			T34	4		T85	2		T86	6
auto[1]	auto[0]	valid[0]	auto[0]	74	1			T50	1		T47	2		T18	1
auto[1]	auto[0]	valid[1]	auto[0]	65	1			T30	1		T50	1		T47	1
auto[1]	auto[0]	valid[2]	auto[0]	68	1			T31	2		T50	2		T84	1
auto[1]	auto[0]	valid[3]	auto[0]	63	1			T30	1		T50	1		T47	2
auto[1]	auto[0]	valid[4]	auto[0]	84	1			T35	1		T50	1		T17	1
auto[1]	auto[1]	valid[0]	auto[0]	71	1			T30	1		T50	2		T47	1
auto[1]	auto[1]	valid[1]	auto[0]	73	1			T33	1		T50	1		T84	1
auto[1]	auto[1]	valid[2]	auto[0]	86	1			T47	1		T327	1		T18	3
auto[1]	auto[1]	valid[3]	auto[0]	85	1			T35	1		T50	1		T17	1
auto[1]	auto[1]	valid[4]	auto[0]	87	1			T250	1		T18	1		T237	2

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal