Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

50670

1

T4

14

T30

125

T31

385

auto[1]

16530

1

T29

3

T22

3

T23

5

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48609

1

T4

5

T29

3

T22

3

auto[1]

18591

1

T4

9

T30

61

T31

142

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	34532	1			T4	5		T29	3		T22	3
others[1]	5734	1			T4	1		T30	11		T31	27
others[2]	5630	1			T4	2		T30	13		T31	30
others[3]	6448	1			T4	1		T30	12		T31	48
interest[1]	3713	1			T4	1		T30	14		T31	25
interest[4]	22548	1			T4	3		T29	3		T22	3
interest[64]	11143	1			T4	4		T30	19		T31	56

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	16420	1			T4	1		T30	33		T31	119
auto[0]	auto[0]	others[1]	2761	1			T30	8		T31	17		T33	10
auto[0]	auto[0]	others[2]	2671	1			T4	1		T30	4		T31	19
auto[0]	auto[0]	others[3]	3077	1			T30	4		T31	26		T33	10
auto[0]	auto[0]	interest[1]	1760	1			T30	4		T31	16		T33	11
auto[0]	auto[0]	interest[4]	10615	1			T30	22		T31	87		T33	32
auto[0]	auto[0]	interest[64]	5390	1			T4	3		T30	11		T31	46
auto[0]	auto[1]	others[0]	8561	1			T29	3		T22	3		T23	5
auto[0]	auto[1]	others[1]	1389	1			T32	17		T34	33		T50	4
auto[0]	auto[1]	others[2]	1352	1			T30	4		T32	17		T34	26
auto[0]	auto[1]	others[3]	1595	1			T30	1		T32	12		T34	43
auto[0]	auto[1]	interest[1]	912	1			T30	4		T32	6		T34	14
auto[0]	auto[1]	interest[4]	5715	1			T29	3		T22	3		T23	5
auto[0]	auto[1]	interest[64]	2721	1			T30	3		T32	30		T34	50
auto[1]	auto[0]	others[0]	9551	1			T4	4		T30	35		T31	80
auto[1]	auto[0]	others[1]	1584	1			T4	1		T30	3		T31	10
auto[1]	auto[0]	others[2]	1607	1			T4	1		T30	5		T31	11
auto[1]	auto[0]	others[3]	1776	1			T4	1		T30	7		T31	22
auto[1]	auto[0]	interest[1]	1041	1			T4	1		T30	6		T31	9
auto[1]	auto[0]	interest[4]	6218	1			T4	3		T30	25		T31	51
auto[1]	auto[0]	interest[64]	3032	1			T4	1		T30	5		T31	10

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal