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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.04 98.38 93.99 98.62 89.36 97.19 95.45 99.26


Total test records in report: 1131
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html
T120 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.488611490 Jul 10 06:29:54 PM PDT 24 Jul 10 06:29:58 PM PDT 24 99738554 ps
T159 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.313079260 Jul 10 06:29:47 PM PDT 24 Jul 10 06:29:53 PM PDT 24 214201941 ps
T1045 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.2272236712 Jul 10 06:30:07 PM PDT 24 Jul 10 06:30:13 PM PDT 24 12521942 ps
T121 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.4143324277 Jul 10 06:29:48 PM PDT 24 Jul 10 06:30:28 PM PDT 24 2762734679 ps
T160 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.731645526 Jul 10 06:29:51 PM PDT 24 Jul 10 06:29:57 PM PDT 24 193914227 ps
T1046 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.1101232642 Jul 10 06:29:48 PM PDT 24 Jul 10 06:29:51 PM PDT 24 11516436 ps
T95 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2435970111 Jul 10 06:30:04 PM PDT 24 Jul 10 06:30:10 PM PDT 24 48527647 ps
T1047 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2512834416 Jul 10 06:30:10 PM PDT 24 Jul 10 06:30:15 PM PDT 24 29055029 ps
T113 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1308242544 Jul 10 06:29:47 PM PDT 24 Jul 10 06:29:52 PM PDT 24 127834772 ps
T122 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1472653729 Jul 10 06:30:06 PM PDT 24 Jul 10 06:30:14 PM PDT 24 86932082 ps
T1048 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2460100816 Jul 10 06:30:03 PM PDT 24 Jul 10 06:30:11 PM PDT 24 64194468 ps
T1049 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2392442647 Jul 10 06:30:06 PM PDT 24 Jul 10 06:30:15 PM PDT 24 204013828 ps
T1050 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.652678727 Jul 10 06:29:45 PM PDT 24 Jul 10 06:29:50 PM PDT 24 151946596 ps
T1051 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.593618455 Jul 10 06:30:09 PM PDT 24 Jul 10 06:30:14 PM PDT 24 22210690 ps
T99 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2430361671 Jul 10 06:30:03 PM PDT 24 Jul 10 06:30:08 PM PDT 24 172271874 ps
T1052 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2071821399 Jul 10 06:30:17 PM PDT 24 Jul 10 06:30:19 PM PDT 24 14639169 ps
T1053 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.2718421441 Jul 10 06:30:10 PM PDT 24 Jul 10 06:30:15 PM PDT 24 39850974 ps
T1054 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1256909905 Jul 10 06:29:57 PM PDT 24 Jul 10 06:30:01 PM PDT 24 44142214 ps
T182 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1692168842 Jul 10 06:29:59 PM PDT 24 Jul 10 06:30:08 PM PDT 24 106496152 ps
T1055 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.4244856129 Jul 10 06:30:08 PM PDT 24 Jul 10 06:30:14 PM PDT 24 13677923 ps
T102 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.208813962 Jul 10 06:29:41 PM PDT 24 Jul 10 06:29:47 PM PDT 24 46212326 ps
T1056 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1340946328 Jul 10 06:29:50 PM PDT 24 Jul 10 06:30:05 PM PDT 24 1226253299 ps
T186 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1017045968 Jul 10 06:30:06 PM PDT 24 Jul 10 06:30:19 PM PDT 24 410138680 ps
T123 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2368685342 Jul 10 06:29:48 PM PDT 24 Jul 10 06:29:52 PM PDT 24 29597094 ps
T190 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2363654434 Jul 10 06:29:58 PM PDT 24 Jul 10 06:30:07 PM PDT 24 108301930 ps
T1057 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1644626286 Jul 10 06:30:07 PM PDT 24 Jul 10 06:30:14 PM PDT 24 106289408 ps
T1058 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.419321623 Jul 10 06:29:47 PM PDT 24 Jul 10 06:29:49 PM PDT 24 16622724 ps
T1059 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.534526796 Jul 10 06:29:50 PM PDT 24 Jul 10 06:29:54 PM PDT 24 46334607 ps
T112 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.177486501 Jul 10 06:30:04 PM PDT 24 Jul 10 06:30:10 PM PDT 24 71642116 ps
T1060 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.2355594361 Jul 10 06:29:42 PM PDT 24 Jul 10 06:29:45 PM PDT 24 12695105 ps
T1061 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3467995218 Jul 10 06:30:04 PM PDT 24 Jul 10 06:30:09 PM PDT 24 25600563 ps
T1062 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2706942737 Jul 10 06:30:02 PM PDT 24 Jul 10 06:30:04 PM PDT 24 10736855 ps
T100 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2550961684 Jul 10 06:29:58 PM PDT 24 Jul 10 06:30:03 PM PDT 24 100145933 ps
T124 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.2263239579 Jul 10 06:29:49 PM PDT 24 Jul 10 06:29:52 PM PDT 24 31684018 ps
T1063 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3832324253 Jul 10 06:29:52 PM PDT 24 Jul 10 06:29:58 PM PDT 24 64622325 ps
T1064 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1560323388 Jul 10 06:29:46 PM PDT 24 Jul 10 06:29:48 PM PDT 24 17265322 ps
T125 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.456129248 Jul 10 06:29:41 PM PDT 24 Jul 10 06:29:45 PM PDT 24 60511436 ps
T1065 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.3352651437 Jul 10 06:30:08 PM PDT 24 Jul 10 06:30:14 PM PDT 24 64475355 ps
T1066 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.3770763496 Jul 10 06:30:06 PM PDT 24 Jul 10 06:30:12 PM PDT 24 34535193 ps
T1067 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.2203775494 Jul 10 06:30:09 PM PDT 24 Jul 10 06:30:15 PM PDT 24 47285133 ps
T1068 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.327392267 Jul 10 06:30:09 PM PDT 24 Jul 10 06:30:15 PM PDT 24 40484401 ps
T1069 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3136715602 Jul 10 06:30:04 PM PDT 24 Jul 10 06:30:12 PM PDT 24 432507569 ps
T111 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3638764714 Jul 10 06:30:02 PM PDT 24 Jul 10 06:30:09 PM PDT 24 334536519 ps
T104 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.278698883 Jul 10 06:30:05 PM PDT 24 Jul 10 06:30:12 PM PDT 24 285655604 ps
T126 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.532151937 Jul 10 06:29:57 PM PDT 24 Jul 10 06:30:01 PM PDT 24 338590049 ps
T127 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2377970591 Jul 10 06:29:40 PM PDT 24 Jul 10 06:29:45 PM PDT 24 140456356 ps
T128 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.2090937087 Jul 10 06:29:50 PM PDT 24 Jul 10 06:29:54 PM PDT 24 96277627 ps
T1070 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.4253008412 Jul 10 06:30:09 PM PDT 24 Jul 10 06:30:15 PM PDT 24 25132254 ps
T1071 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.36186852 Jul 10 06:30:03 PM PDT 24 Jul 10 06:30:10 PM PDT 24 139008334 ps
T183 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1014858234 Jul 10 06:29:57 PM PDT 24 Jul 10 06:30:15 PM PDT 24 732783530 ps
T1072 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.2584184349 Jul 10 06:30:08 PM PDT 24 Jul 10 06:30:14 PM PDT 24 45180790 ps
T1073 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.3145734718 Jul 10 06:30:10 PM PDT 24 Jul 10 06:30:15 PM PDT 24 28796269 ps
T1074 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.143528387 Jul 10 06:30:06 PM PDT 24 Jul 10 06:30:11 PM PDT 24 16557463 ps
T1075 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1734219410 Jul 10 06:30:01 PM PDT 24 Jul 10 06:30:05 PM PDT 24 122790376 ps
T1076 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3116828097 Jul 10 06:29:51 PM PDT 24 Jul 10 06:29:57 PM PDT 24 364519206 ps
T1077 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3505979039 Jul 10 06:29:48 PM PDT 24 Jul 10 06:29:58 PM PDT 24 2412241343 ps
T129 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.519476364 Jul 10 06:29:53 PM PDT 24 Jul 10 06:29:57 PM PDT 24 69157789 ps
T188 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2280152167 Jul 10 06:29:39 PM PDT 24 Jul 10 06:30:01 PM PDT 24 3351947740 ps
T184 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.2959379179 Jul 10 06:30:05 PM PDT 24 Jul 10 06:30:17 PM PDT 24 1255612787 ps
T1078 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.1596732581 Jul 10 06:30:09 PM PDT 24 Jul 10 06:30:15 PM PDT 24 40337435 ps
T1079 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2137990303 Jul 10 06:30:06 PM PDT 24 Jul 10 06:30:12 PM PDT 24 20998178 ps
T185 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2783751189 Jul 10 06:29:48 PM PDT 24 Jul 10 06:29:56 PM PDT 24 109636109 ps
T1080 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1734789825 Jul 10 06:30:05 PM PDT 24 Jul 10 06:30:10 PM PDT 24 35311322 ps
T1081 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1087468102 Jul 10 06:30:05 PM PDT 24 Jul 10 06:30:12 PM PDT 24 52803999 ps
T1082 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2830735637 Jul 10 06:30:03 PM PDT 24 Jul 10 06:30:10 PM PDT 24 176562696 ps
T130 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.593153064 Jul 10 06:29:39 PM PDT 24 Jul 10 06:29:41 PM PDT 24 271366833 ps
T101 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.2649370863 Jul 10 06:30:03 PM PDT 24 Jul 10 06:30:08 PM PDT 24 90711359 ps
T1083 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.1941478895 Jul 10 06:30:15 PM PDT 24 Jul 10 06:30:18 PM PDT 24 95377723 ps
T1084 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3942080166 Jul 10 06:30:09 PM PDT 24 Jul 10 06:30:15 PM PDT 24 21993609 ps
T1085 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.2135951273 Jul 10 06:29:39 PM PDT 24 Jul 10 06:29:55 PM PDT 24 841193849 ps
T181 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.367239674 Jul 10 06:29:40 PM PDT 24 Jul 10 06:29:44 PM PDT 24 779921899 ps
T1086 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.2608217321 Jul 10 06:30:04 PM PDT 24 Jul 10 06:30:08 PM PDT 24 13428889 ps
T187 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.3108519438 Jul 10 06:29:52 PM PDT 24 Jul 10 06:30:16 PM PDT 24 1724751449 ps
T1087 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.362574124 Jul 10 06:29:47 PM PDT 24 Jul 10 06:29:56 PM PDT 24 1377957101 ps
T1088 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.822934060 Jul 10 06:29:45 PM PDT 24 Jul 10 06:29:48 PM PDT 24 36967119 ps
T1089 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.2356267219 Jul 10 06:29:51 PM PDT 24 Jul 10 06:30:08 PM PDT 24 2894358499 ps
T1090 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2042208358 Jul 10 06:29:51 PM PDT 24 Jul 10 06:29:54 PM PDT 24 26271713 ps
T189 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1708652195 Jul 10 06:29:59 PM PDT 24 Jul 10 06:30:09 PM PDT 24 934502196 ps
T108 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3460173046 Jul 10 06:29:46 PM PDT 24 Jul 10 06:29:51 PM PDT 24 138198774 ps
T1091 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1826486465 Jul 10 06:30:03 PM PDT 24 Jul 10 06:30:09 PM PDT 24 495282909 ps
T1092 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1417807508 Jul 10 06:29:45 PM PDT 24 Jul 10 06:29:50 PM PDT 24 2048928423 ps
T131 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.230889090 Jul 10 06:30:05 PM PDT 24 Jul 10 06:30:11 PM PDT 24 346828634 ps
T107 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.2239524689 Jul 10 06:29:51 PM PDT 24 Jul 10 06:29:55 PM PDT 24 89819488 ps
T1093 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.711556309 Jul 10 06:29:58 PM PDT 24 Jul 10 06:30:01 PM PDT 24 64892511 ps
T1094 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.656436895 Jul 10 06:30:07 PM PDT 24 Jul 10 06:30:13 PM PDT 24 14528333 ps
T1095 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1762275458 Jul 10 06:30:11 PM PDT 24 Jul 10 06:30:16 PM PDT 24 11718946 ps
T109 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.3732065777 Jul 10 06:29:38 PM PDT 24 Jul 10 06:29:41 PM PDT 24 56417600 ps
T132 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.1566653483 Jul 10 06:29:48 PM PDT 24 Jul 10 06:30:04 PM PDT 24 1288839449 ps
T1096 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.1794347769 Jul 10 06:30:05 PM PDT 24 Jul 10 06:30:10 PM PDT 24 13103689 ps
T1097 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.2417381059 Jul 10 06:29:56 PM PDT 24 Jul 10 06:30:00 PM PDT 24 33038717 ps
T1098 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1719135885 Jul 10 06:30:04 PM PDT 24 Jul 10 06:30:10 PM PDT 24 282527510 ps
T193 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3591590728 Jul 10 06:29:50 PM PDT 24 Jul 10 06:30:12 PM PDT 24 3604691517 ps
T194 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1965840605 Jul 10 06:29:53 PM PDT 24 Jul 10 06:30:07 PM PDT 24 876015459 ps
T191 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.448202175 Jul 10 06:29:57 PM PDT 24 Jul 10 06:30:21 PM PDT 24 1092013918 ps
T1099 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3194693597 Jul 10 06:29:45 PM PDT 24 Jul 10 06:30:24 PM PDT 24 2807547318 ps
T1100 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.261231732 Jul 10 06:29:56 PM PDT 24 Jul 10 06:30:01 PM PDT 24 192673915 ps
T1101 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.769261635 Jul 10 06:29:48 PM PDT 24 Jul 10 06:29:54 PM PDT 24 577975597 ps
T1102 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.244729575 Jul 10 06:29:48 PM PDT 24 Jul 10 06:29:52 PM PDT 24 41981768 ps
T1103 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2575320867 Jul 10 06:30:09 PM PDT 24 Jul 10 06:30:15 PM PDT 24 23210924 ps
T1104 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2086163522 Jul 10 06:29:52 PM PDT 24 Jul 10 06:29:57 PM PDT 24 130146476 ps
T1105 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.627950151 Jul 10 06:30:06 PM PDT 24 Jul 10 06:30:14 PM PDT 24 264549402 ps
T1106 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.666528218 Jul 10 06:30:08 PM PDT 24 Jul 10 06:30:14 PM PDT 24 13569999 ps
T1107 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1016799980 Jul 10 06:29:41 PM PDT 24 Jul 10 06:29:57 PM PDT 24 8680030997 ps
T1108 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1052929299 Jul 10 06:29:44 PM PDT 24 Jul 10 06:29:48 PM PDT 24 105197259 ps
T1109 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2565023965 Jul 10 06:29:46 PM PDT 24 Jul 10 06:29:48 PM PDT 24 41528429 ps
T192 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.4158318492 Jul 10 06:29:45 PM PDT 24 Jul 10 06:30:06 PM PDT 24 692951064 ps
T110 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.3637128861 Jul 10 06:30:06 PM PDT 24 Jul 10 06:30:15 PM PDT 24 97952400 ps
T82 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.4151736945 Jul 10 06:29:47 PM PDT 24 Jul 10 06:29:50 PM PDT 24 29759603 ps
T1110 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.2441520140 Jul 10 06:29:58 PM PDT 24 Jul 10 06:30:07 PM PDT 24 1149185860 ps
T1111 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.863826657 Jul 10 06:29:55 PM PDT 24 Jul 10 06:30:00 PM PDT 24 585097597 ps
T1112 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.254552217 Jul 10 06:29:40 PM PDT 24 Jul 10 06:30:01 PM PDT 24 1169009219 ps
T1113 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.1636391929 Jul 10 06:29:42 PM PDT 24 Jul 10 06:29:45 PM PDT 24 11834176 ps
T1114 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3788442989 Jul 10 06:29:55 PM PDT 24 Jul 10 06:29:59 PM PDT 24 61323500 ps
T1115 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.1362895884 Jul 10 06:29:51 PM PDT 24 Jul 10 06:29:54 PM PDT 24 198069922 ps
T1116 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1858690691 Jul 10 06:29:47 PM PDT 24 Jul 10 06:30:23 PM PDT 24 1087988761 ps
T1117 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.4211319386 Jul 10 06:30:06 PM PDT 24 Jul 10 06:30:12 PM PDT 24 211638117 ps
T83 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1032778651 Jul 10 06:29:47 PM PDT 24 Jul 10 06:29:50 PM PDT 24 127034596 ps
T1118 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2116330679 Jul 10 06:30:04 PM PDT 24 Jul 10 06:30:11 PM PDT 24 112460119 ps
T1119 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.1946463 Jul 10 06:30:06 PM PDT 24 Jul 10 06:30:12 PM PDT 24 379649749 ps
T1120 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.2447543524 Jul 10 06:29:47 PM PDT 24 Jul 10 06:29:50 PM PDT 24 25268895 ps
T1121 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3425657548 Jul 10 06:30:03 PM PDT 24 Jul 10 06:30:15 PM PDT 24 349027573 ps
T1122 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.1301043191 Jul 10 06:29:57 PM PDT 24 Jul 10 06:30:01 PM PDT 24 116792360 ps
T1123 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2213109446 Jul 10 06:30:06 PM PDT 24 Jul 10 06:30:16 PM PDT 24 2115894158 ps
T1124 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1498479617 Jul 10 06:29:44 PM PDT 24 Jul 10 06:29:53 PM PDT 24 464987942 ps
T1125 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.429861533 Jul 10 06:29:59 PM PDT 24 Jul 10 06:30:01 PM PDT 24 53650803 ps
T1126 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.992516428 Jul 10 06:29:40 PM PDT 24 Jul 10 06:29:43 PM PDT 24 37007861 ps
T1127 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1125025973 Jul 10 06:29:57 PM PDT 24 Jul 10 06:30:03 PM PDT 24 646783037 ps
T1128 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.4187847635 Jul 10 06:30:04 PM PDT 24 Jul 10 06:30:10 PM PDT 24 271773693 ps
T1129 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.1811514623 Jul 10 06:30:03 PM PDT 24 Jul 10 06:30:08 PM PDT 24 36623519 ps
T1130 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1972577215 Jul 10 06:30:06 PM PDT 24 Jul 10 06:30:13 PM PDT 24 330397177 ps
T1131 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.353766836 Jul 10 06:29:58 PM PDT 24 Jul 10 06:30:02 PM PDT 24 85830156 ps

Test location /workspace/coverage/default/36.spi_device_flash_all.1904474347
Short name T7
Test name
Test status
Simulation time 3520829535 ps
CPU time 39.32 seconds
Started Jul 10 06:00:23 PM PDT 24
Finished Jul 10 06:01:04 PM PDT 24
Peak memory 249384 kb
Host smart-0112904e-c5ea-4667-a21d-c65de965b4c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904474347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.1904474347
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.126288393
Short name T30
Test name
Test status
Simulation time 71785963021 ps
CPU time 643.71 seconds
Started Jul 10 06:01:08 PM PDT 24
Finished Jul 10 06:11:53 PM PDT 24
Peak memory 268880 kb
Host smart-d951ce66-a9cb-4845-a608-c8e15bdcfa8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126288393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idle
.126288393
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.1753301389
Short name T18
Test name
Test status
Simulation time 134917355022 ps
CPU time 765.05 seconds
Started Jul 10 05:59:00 PM PDT 24
Finished Jul 10 06:11:48 PM PDT 24
Peak memory 283060 kb
Host smart-46ec59e4-3c17-41bc-ac32-3c53c707147d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753301389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.1753301389
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.3757997749
Short name T47
Test name
Test status
Simulation time 59018489303 ps
CPU time 542.52 seconds
Started Jul 10 05:58:49 PM PDT 24
Finished Jul 10 06:07:52 PM PDT 24
Peak memory 256312 kb
Host smart-c18b9685-ba27-4b0f-98f1-63ceccaa52af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757997749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.3757997749
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.3304196646
Short name T70
Test name
Test status
Simulation time 116884745 ps
CPU time 2.99 seconds
Started Jul 10 06:29:50 PM PDT 24
Finished Jul 10 06:29:55 PM PDT 24
Peak memory 216936 kb
Host smart-9e2f5988-49f6-48eb-b152-4c36f307eceb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304196646 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.3304196646
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.1821320314
Short name T19
Test name
Test status
Simulation time 258536366559 ps
CPU time 613.17 seconds
Started Jul 10 05:59:24 PM PDT 24
Finished Jul 10 06:09:38 PM PDT 24
Peak memory 265800 kb
Host smart-c00fb638-e7d7-4d90-9175-3538e9125cca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821320314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.1821320314
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.1088194157
Short name T73
Test name
Test status
Simulation time 47374108 ps
CPU time 0.75 seconds
Started Jul 10 05:57:22 PM PDT 24
Finished Jul 10 05:57:24 PM PDT 24
Peak memory 216080 kb
Host smart-482904cb-8fa5-468b-b5c1-70aa3b37b247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088194157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.1088194157
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.323241449
Short name T50
Test name
Test status
Simulation time 8167427186 ps
CPU time 97.28 seconds
Started Jul 10 05:59:02 PM PDT 24
Finished Jul 10 06:00:41 PM PDT 24
Peak memory 251504 kb
Host smart-a13da3c5-600e-4767-948e-44d8c25c941f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323241449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idle
.323241449
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.545307252
Short name T227
Test name
Test status
Simulation time 17967590045 ps
CPU time 258.91 seconds
Started Jul 10 06:00:37 PM PDT 24
Finished Jul 10 06:04:59 PM PDT 24
Peak memory 265668 kb
Host smart-d5395e3a-5307-4343-bc4a-3e44c807cab6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545307252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stres
s_all.545307252
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.1308100337
Short name T15
Test name
Test status
Simulation time 312143518 ps
CPU time 1.14 seconds
Started Jul 10 05:57:47 PM PDT 24
Finished Jul 10 05:57:50 PM PDT 24
Peak memory 236564 kb
Host smart-11805209-fc03-4cda-b435-3f0ae5a463f4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308100337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.1308100337
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.2487472829
Short name T13
Test name
Test status
Simulation time 247241618 ps
CPU time 11.68 seconds
Started Jul 10 05:57:55 PM PDT 24
Finished Jul 10 05:58:08 PM PDT 24
Peak memory 249064 kb
Host smart-b9c7f773-db84-49af-80d6-bbb7a28fd325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487472829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.2487472829
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.3325700430
Short name T203
Test name
Test status
Simulation time 394150540675 ps
CPU time 696.76 seconds
Started Jul 10 05:58:06 PM PDT 24
Finished Jul 10 06:09:44 PM PDT 24
Peak memory 263324 kb
Host smart-4f2b7101-a864-4bdb-ab55-81666bfd4231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325700430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.3325700430
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.1259733427
Short name T217
Test name
Test status
Simulation time 167390744451 ps
CPU time 871.98 seconds
Started Jul 10 06:00:47 PM PDT 24
Finished Jul 10 06:15:21 PM PDT 24
Peak memory 284452 kb
Host smart-05eb9438-4d30-4022-b28c-186c70fee6cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259733427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.1259733427
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.1027298740
Short name T231
Test name
Test status
Simulation time 205487972187 ps
CPU time 268.58 seconds
Started Jul 10 06:00:22 PM PDT 24
Finished Jul 10 06:04:53 PM PDT 24
Peak memory 265464 kb
Host smart-efbef307-393d-434a-99ef-cbf3de80d0a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027298740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmd
s.1027298740
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1267482455
Short name T94
Test name
Test status
Simulation time 1029521300 ps
CPU time 12.93 seconds
Started Jul 10 06:30:03 PM PDT 24
Finished Jul 10 06:30:20 PM PDT 24
Peak memory 216528 kb
Host smart-1d3a905b-6366-415e-b3ab-c83491912c85
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267482455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.1267482455
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2872942311
Short name T119
Test name
Test status
Simulation time 35976852 ps
CPU time 0.96 seconds
Started Jul 10 06:29:40 PM PDT 24
Finished Jul 10 06:29:43 PM PDT 24
Peak memory 207232 kb
Host smart-a0caccf3-340a-4f63-8b07-64cb44875df3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872942311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.2872942311
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.2508296576
Short name T180
Test name
Test status
Simulation time 48674611309 ps
CPU time 206.19 seconds
Started Jul 10 05:59:28 PM PDT 24
Finished Jul 10 06:02:56 PM PDT 24
Peak memory 249220 kb
Host smart-fdf8c17a-1ffb-4ffb-bbc2-8519b30f27a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508296576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.2508296576
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2589887502
Short name T93
Test name
Test status
Simulation time 186210444 ps
CPU time 4.41 seconds
Started Jul 10 06:29:59 PM PDT 24
Finished Jul 10 06:30:06 PM PDT 24
Peak memory 217004 kb
Host smart-7ad31587-4585-43dd-b7e3-8e1ea28e547d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589887502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.2
589887502
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.2725495650
Short name T305
Test name
Test status
Simulation time 11640675488 ps
CPU time 235.26 seconds
Started Jul 10 05:57:53 PM PDT 24
Finished Jul 10 06:01:50 PM PDT 24
Peak memory 273696 kb
Host smart-e54b15de-0023-4db0-b6e4-d6bbb4f0198d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725495650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.2725495650
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.3110562957
Short name T164
Test name
Test status
Simulation time 351959882227 ps
CPU time 199.73 seconds
Started Jul 10 05:58:39 PM PDT 24
Finished Jul 10 06:02:00 PM PDT 24
Peak memory 266556 kb
Host smart-215642ca-8ed5-4053-aa2c-1e3d6208aa4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110562957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.3110562957
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.1402363678
Short name T6
Test name
Test status
Simulation time 2696317293 ps
CPU time 60.36 seconds
Started Jul 10 05:58:41 PM PDT 24
Finished Jul 10 05:59:42 PM PDT 24
Peak memory 255016 kb
Host smart-a4933c9f-4f81-4db3-acc9-5b0f279a3736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402363678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmd
s.1402363678
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.2419186886
Short name T80
Test name
Test status
Simulation time 37102128871 ps
CPU time 498.25 seconds
Started Jul 10 05:57:30 PM PDT 24
Finished Jul 10 06:05:49 PM PDT 24
Peak memory 287696 kb
Host smart-df70ca53-0eb3-413e-af14-1b26830a75a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419186886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.2419186886
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.2690313480
Short name T207
Test name
Test status
Simulation time 11610991520 ps
CPU time 150.7 seconds
Started Jul 10 05:57:39 PM PDT 24
Finished Jul 10 06:00:10 PM PDT 24
Peak memory 257456 kb
Host smart-4ff79980-37be-4425-8f09-40c44caf2f67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690313480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.2690313480
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.3534095895
Short name T36
Test name
Test status
Simulation time 22377908488 ps
CPU time 271.89 seconds
Started Jul 10 05:58:00 PM PDT 24
Finished Jul 10 06:02:33 PM PDT 24
Peak memory 273192 kb
Host smart-879aa05b-1fb8-4a6b-b42f-fdac593cc038
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534095895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.3534095895
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.911206392
Short name T349
Test name
Test status
Simulation time 22028966 ps
CPU time 0.78 seconds
Started Jul 10 05:59:14 PM PDT 24
Finished Jul 10 05:59:16 PM PDT 24
Peak memory 205888 kb
Host smart-b6ed31f9-ab16-4c2e-b3f7-4c21802bf818
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911206392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.911206392
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.2427741542
Short name T49
Test name
Test status
Simulation time 5397292183 ps
CPU time 75.08 seconds
Started Jul 10 05:59:04 PM PDT 24
Finished Jul 10 06:00:20 PM PDT 24
Peak memory 253456 kb
Host smart-494f006e-ef45-4f47-8286-2ee4db1ce135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427741542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.2427741542
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.3839932933
Short name T340
Test name
Test status
Simulation time 4012998597 ps
CPU time 5.77 seconds
Started Jul 10 05:59:05 PM PDT 24
Finished Jul 10 05:59:12 PM PDT 24
Peak memory 216312 kb
Host smart-ed225b8f-ab73-4e50-9c91-1404b02e9854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839932933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.3839932933
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.278698883
Short name T104
Test name
Test status
Simulation time 285655604 ps
CPU time 2.88 seconds
Started Jul 10 06:30:05 PM PDT 24
Finished Jul 10 06:30:12 PM PDT 24
Peak memory 215832 kb
Host smart-07e76298-7082-451a-b866-f1aa049eb5ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278698883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.278698883
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.560627847
Short name T52
Test name
Test status
Simulation time 76926505356 ps
CPU time 739.04 seconds
Started Jul 10 05:59:11 PM PDT 24
Finished Jul 10 06:11:31 PM PDT 24
Peak memory 267056 kb
Host smart-e7117291-f252-40dc-832b-70c0fd248819
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560627847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stres
s_all.560627847
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.4032351236
Short name T115
Test name
Test status
Simulation time 1229430010 ps
CPU time 13.23 seconds
Started Jul 10 05:59:44 PM PDT 24
Finished Jul 10 05:59:58 PM PDT 24
Peak memory 224488 kb
Host smart-424f22ea-8b4e-4ab7-af3a-c86891fef7a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032351236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.4032351236
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.2666110551
Short name T62
Test name
Test status
Simulation time 8851787895 ps
CPU time 127.56 seconds
Started Jul 10 05:58:24 PM PDT 24
Finished Jul 10 06:00:33 PM PDT 24
Peak memory 254736 kb
Host smart-468da3cc-375a-4aca-a242-1e47e00f5906
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666110551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.2666110551
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.448202175
Short name T191
Test name
Test status
Simulation time 1092013918 ps
CPU time 22.45 seconds
Started Jul 10 06:29:57 PM PDT 24
Finished Jul 10 06:30:21 PM PDT 24
Peak memory 216084 kb
Host smart-509fe437-82ce-4d50-9754-1a912903af8e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448202175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device
_tl_intg_err.448202175
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.3108519438
Short name T187
Test name
Test status
Simulation time 1724751449 ps
CPU time 22.02 seconds
Started Jul 10 06:29:52 PM PDT 24
Finished Jul 10 06:30:16 PM PDT 24
Peak memory 215768 kb
Host smart-8c00a306-e17d-44eb-ae6f-dcbf7d145be5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108519438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.3108519438
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.3541326661
Short name T31
Test name
Test status
Simulation time 2557617529 ps
CPU time 62.21 seconds
Started Jul 10 05:58:21 PM PDT 24
Finished Jul 10 05:59:25 PM PDT 24
Peak memory 257032 kb
Host smart-6adcac35-fb9b-423e-bbce-6fc535c00dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541326661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.3541326661
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.2198066621
Short name T43
Test name
Test status
Simulation time 73651096539 ps
CPU time 214.11 seconds
Started Jul 10 05:58:41 PM PDT 24
Finished Jul 10 06:02:17 PM PDT 24
Peak memory 267200 kb
Host smart-c035b176-847b-484e-b44b-9b157575ca98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198066621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.2198066621
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.2892189411
Short name T205
Test name
Test status
Simulation time 85018135863 ps
CPU time 345.04 seconds
Started Jul 10 05:59:18 PM PDT 24
Finished Jul 10 06:05:04 PM PDT 24
Peak memory 255584 kb
Host smart-beb5ed38-3b03-4e34-9939-be847d2b0e35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892189411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.2892189411
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.2291958380
Short name T312
Test name
Test status
Simulation time 170447778324 ps
CPU time 1145.44 seconds
Started Jul 10 06:00:06 PM PDT 24
Finished Jul 10 06:19:13 PM PDT 24
Peak memory 284344 kb
Host smart-a29480c0-39a2-49b3-b103-f83da8746027
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291958380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.2291958380
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.2052503849
Short name T318
Test name
Test status
Simulation time 1090714050 ps
CPU time 14.94 seconds
Started Jul 10 06:00:53 PM PDT 24
Finished Jul 10 06:01:10 PM PDT 24
Peak memory 233324 kb
Host smart-4b831a57-3964-4cee-9213-cf74915e6b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052503849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.2052503849
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.1433069853
Short name T25
Test name
Test status
Simulation time 8956383110 ps
CPU time 24.71 seconds
Started Jul 10 05:59:57 PM PDT 24
Finished Jul 10 06:00:23 PM PDT 24
Peak memory 240240 kb
Host smart-27a6e1fa-597b-4529-87c4-7fb81ebad559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433069853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.1433069853
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.367239674
Short name T181
Test name
Test status
Simulation time 779921899 ps
CPU time 2.04 seconds
Started Jul 10 06:29:40 PM PDT 24
Finished Jul 10 06:29:44 PM PDT 24
Peak memory 216020 kb
Host smart-7076265e-f4d5-4ebf-9181-523e8d3cb19f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367239674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.367239674
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.2441520140
Short name T1110
Test name
Test status
Simulation time 1149185860 ps
CPU time 7.62 seconds
Started Jul 10 06:29:58 PM PDT 24
Finished Jul 10 06:30:07 PM PDT 24
Peak memory 216340 kb
Host smart-d76c92cf-f325-44d7-a25f-3aa941770d18
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441520140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.2441520140
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1014858234
Short name T183
Test name
Test status
Simulation time 732783530 ps
CPU time 15.91 seconds
Started Jul 10 06:29:57 PM PDT 24
Finished Jul 10 06:30:15 PM PDT 24
Peak memory 215872 kb
Host smart-6ccd5a4e-f25d-4130-aaaf-0dfdc6d151f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014858234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.1014858234
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.4160546471
Short name T425
Test name
Test status
Simulation time 24211371378 ps
CPU time 83.14 seconds
Started Jul 10 05:57:32 PM PDT 24
Finished Jul 10 05:58:57 PM PDT 24
Peak memory 250108 kb
Host smart-fb44aebb-dbd1-441f-889a-f592de2c55be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160546471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.4160546471
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.3926953791
Short name T700
Test name
Test status
Simulation time 456032398 ps
CPU time 2.78 seconds
Started Jul 10 05:58:25 PM PDT 24
Finished Jul 10 05:58:28 PM PDT 24
Peak memory 224496 kb
Host smart-6ec27867-8468-46a1-b36b-52113a39901b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926953791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.3926953791
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.1798081368
Short name T451
Test name
Test status
Simulation time 18398553139 ps
CPU time 125.51 seconds
Started Jul 10 05:58:42 PM PDT 24
Finished Jul 10 06:00:51 PM PDT 24
Peak memory 253100 kb
Host smart-2c514650-a6c0-4520-a58e-6ff597a20487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798081368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.1798081368
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.2462697682
Short name T961
Test name
Test status
Simulation time 3730088271 ps
CPU time 89.7 seconds
Started Jul 10 05:59:17 PM PDT 24
Finished Jul 10 06:00:48 PM PDT 24
Peak memory 264760 kb
Host smart-a6b931f0-1fbb-426e-8d63-8a8b7eee4eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462697682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.2462697682
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.3098580284
Short name T301
Test name
Test status
Simulation time 20632142030 ps
CPU time 214.64 seconds
Started Jul 10 05:59:35 PM PDT 24
Finished Jul 10 06:03:10 PM PDT 24
Peak memory 241024 kb
Host smart-a5ab707c-be20-4ff3-9131-17a9fb0b4cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098580284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.3098580284
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.2315431559
Short name T344
Test name
Test status
Simulation time 43083967 ps
CPU time 0.76 seconds
Started Jul 10 05:58:24 PM PDT 24
Finished Jul 10 05:58:25 PM PDT 24
Peak memory 206660 kb
Host smart-c43c0769-dae9-4a32-95be-2e13187e9d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315431559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.2315431559
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.2605939838
Short name T4
Test name
Test status
Simulation time 105169666 ps
CPU time 1.41 seconds
Started Jul 10 06:00:03 PM PDT 24
Finished Jul 10 06:00:05 PM PDT 24
Peak memory 215816 kb
Host smart-a5a07344-591c-4cb3-989d-55a9b569560d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605939838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.2605939838
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1125025973
Short name T1127
Test name
Test status
Simulation time 646783037 ps
CPU time 4.67 seconds
Started Jul 10 06:29:57 PM PDT 24
Finished Jul 10 06:30:03 PM PDT 24
Peak memory 215944 kb
Host smart-301fa50f-0a06-4533-a8ba-284f3b7f6d1f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125025973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
1125025973
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1032778651
Short name T83
Test name
Test status
Simulation time 127034596 ps
CPU time 1.36 seconds
Started Jul 10 06:29:47 PM PDT 24
Finished Jul 10 06:29:50 PM PDT 24
Peak memory 207408 kb
Host smart-bcad2fe3-d833-4e05-958d-1cc6f62f78ca
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032778651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.1032778651
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.2135951273
Short name T1085
Test name
Test status
Simulation time 841193849 ps
CPU time 13.67 seconds
Started Jul 10 06:29:39 PM PDT 24
Finished Jul 10 06:29:55 PM PDT 24
Peak memory 215684 kb
Host smart-baab95fa-8db1-47ef-bf0a-76306e79cf4b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135951273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.2135951273
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1016799980
Short name T1107
Test name
Test status
Simulation time 8680030997 ps
CPU time 13.26 seconds
Started Jul 10 06:29:41 PM PDT 24
Finished Jul 10 06:29:57 PM PDT 24
Peak memory 215744 kb
Host smart-65108a75-8f28-410b-9ac1-00a5c67fbee1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016799980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.1016799980
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2858449909
Short name T81
Test name
Test status
Simulation time 30219317 ps
CPU time 1.19 seconds
Started Jul 10 06:29:39 PM PDT 24
Finished Jul 10 06:29:42 PM PDT 24
Peak memory 207496 kb
Host smart-b92ee140-a6f0-48a4-8225-c0684a7c5dc2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858449909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.2858449909
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1417807508
Short name T1092
Test name
Test status
Simulation time 2048928423 ps
CPU time 3.75 seconds
Started Jul 10 06:29:45 PM PDT 24
Finished Jul 10 06:29:50 PM PDT 24
Peak memory 217508 kb
Host smart-55491f49-2059-46b6-b974-6daa3c508c41
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417807508 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.1417807508
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2377970591
Short name T127
Test name
Test status
Simulation time 140456356 ps
CPU time 2.74 seconds
Started Jul 10 06:29:40 PM PDT 24
Finished Jul 10 06:29:45 PM PDT 24
Peak memory 215724 kb
Host smart-d0c6230d-3eb1-4903-91b1-0dda7bc9b00e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377970591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.2
377970591
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.1636391929
Short name T1113
Test name
Test status
Simulation time 11834176 ps
CPU time 0.78 seconds
Started Jul 10 06:29:42 PM PDT 24
Finished Jul 10 06:29:45 PM PDT 24
Peak memory 204296 kb
Host smart-a309057b-9b9c-4bfc-985d-81cb0100e3b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636391929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.1
636391929
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.456129248
Short name T125
Test name
Test status
Simulation time 60511436 ps
CPU time 2.19 seconds
Started Jul 10 06:29:41 PM PDT 24
Finished Jul 10 06:29:45 PM PDT 24
Peak memory 215752 kb
Host smart-6e4d525b-679a-4349-bb1e-2981ec1318c7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456129248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_
device_mem_partial_access.456129248
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.491519966
Short name T1041
Test name
Test status
Simulation time 23992165 ps
CPU time 0.67 seconds
Started Jul 10 06:29:40 PM PDT 24
Finished Jul 10 06:29:43 PM PDT 24
Peak memory 204424 kb
Host smart-baae7f90-7c28-486a-960d-dc3e57f345b2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491519966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem
_walk.491519966
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1794688171
Short name T157
Test name
Test status
Simulation time 311781171 ps
CPU time 1.99 seconds
Started Jul 10 06:29:39 PM PDT 24
Finished Jul 10 06:29:43 PM PDT 24
Peak memory 215748 kb
Host smart-f5a11670-0223-48fc-b19f-c175a489531a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794688171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.1794688171
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2280152167
Short name T188
Test name
Test status
Simulation time 3351947740 ps
CPU time 19.87 seconds
Started Jul 10 06:29:39 PM PDT 24
Finished Jul 10 06:30:01 PM PDT 24
Peak memory 215944 kb
Host smart-d0b0c35a-07cb-46c5-8592-b69c6c1fccc2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280152167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.2280152167
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1498479617
Short name T1124
Test name
Test status
Simulation time 464987942 ps
CPU time 7.74 seconds
Started Jul 10 06:29:44 PM PDT 24
Finished Jul 10 06:29:53 PM PDT 24
Peak memory 215756 kb
Host smart-70e556eb-9b1f-4ce9-bfda-24e79bf00265
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498479617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.1498479617
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3194693597
Short name T1099
Test name
Test status
Simulation time 2807547318 ps
CPU time 38.46 seconds
Started Jul 10 06:29:45 PM PDT 24
Finished Jul 10 06:30:24 PM PDT 24
Peak memory 207572 kb
Host smart-53e688d8-0c05-4b45-835c-55e84d73945f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194693597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.3194693597
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1052929299
Short name T1108
Test name
Test status
Simulation time 105197259 ps
CPU time 2.72 seconds
Started Jul 10 06:29:44 PM PDT 24
Finished Jul 10 06:29:48 PM PDT 24
Peak memory 216892 kb
Host smart-fc201770-dfbd-4901-9927-f824966354d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052929299 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.1052929299
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1139450486
Short name T1030
Test name
Test status
Simulation time 319998170 ps
CPU time 2.44 seconds
Started Jul 10 06:29:40 PM PDT 24
Finished Jul 10 06:29:45 PM PDT 24
Peak memory 215648 kb
Host smart-05c5e6f4-4179-4848-9896-46d38c401785
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139450486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.1
139450486
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.2355594361
Short name T1060
Test name
Test status
Simulation time 12695105 ps
CPU time 0.76 seconds
Started Jul 10 06:29:42 PM PDT 24
Finished Jul 10 06:29:45 PM PDT 24
Peak memory 204316 kb
Host smart-45435918-96a6-4873-a8fc-9dc4aa23f2e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355594361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.2
355594361
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.593153064
Short name T130
Test name
Test status
Simulation time 271366833 ps
CPU time 1.27 seconds
Started Jul 10 06:29:39 PM PDT 24
Finished Jul 10 06:29:41 PM PDT 24
Peak memory 215792 kb
Host smart-313bd7aa-3909-467d-b54d-8e49393966ca
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593153064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_
device_mem_partial_access.593153064
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.992516428
Short name T1126
Test name
Test status
Simulation time 37007861 ps
CPU time 0.67 seconds
Started Jul 10 06:29:40 PM PDT 24
Finished Jul 10 06:29:43 PM PDT 24
Peak memory 204408 kb
Host smart-8db3986f-8a39-4964-ae75-0fd85ca8324e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992516428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem
_walk.992516428
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2786976421
Short name T1044
Test name
Test status
Simulation time 50534236 ps
CPU time 1.6 seconds
Started Jul 10 06:29:41 PM PDT 24
Finished Jul 10 06:29:45 PM PDT 24
Peak memory 215668 kb
Host smart-e87fb1bf-93b7-4f70-8f81-95364675b900
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786976421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.2786976421
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.3732065777
Short name T109
Test name
Test status
Simulation time 56417600 ps
CPU time 1.8 seconds
Started Jul 10 06:29:38 PM PDT 24
Finished Jul 10 06:29:41 PM PDT 24
Peak memory 217032 kb
Host smart-3fa0e5fe-071d-4dc3-941c-d300bb1bc21f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732065777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.3
732065777
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.254552217
Short name T1112
Test name
Test status
Simulation time 1169009219 ps
CPU time 18.27 seconds
Started Jul 10 06:29:40 PM PDT 24
Finished Jul 10 06:30:01 PM PDT 24
Peak memory 216332 kb
Host smart-0cc1a274-54dd-49a9-8b93-619a51385371
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254552217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_
tl_intg_err.254552217
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1256909905
Short name T1054
Test name
Test status
Simulation time 44142214 ps
CPU time 1.75 seconds
Started Jul 10 06:29:57 PM PDT 24
Finished Jul 10 06:30:01 PM PDT 24
Peak memory 216880 kb
Host smart-f78b75c2-17b2-4b10-b435-686d7c7dc102
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256909905 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.1256909905
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.532151937
Short name T126
Test name
Test status
Simulation time 338590049 ps
CPU time 2.61 seconds
Started Jul 10 06:29:57 PM PDT 24
Finished Jul 10 06:30:01 PM PDT 24
Peak memory 215624 kb
Host smart-55d97baa-bef0-48e6-8c9b-8dc00da76b69
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532151937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.532151937
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.429861533
Short name T1125
Test name
Test status
Simulation time 53650803 ps
CPU time 0.72 seconds
Started Jul 10 06:29:59 PM PDT 24
Finished Jul 10 06:30:01 PM PDT 24
Peak memory 204228 kb
Host smart-6648d75e-6df3-4362-a606-c0bb89aac6d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429861533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.429861533
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.863826657
Short name T1111
Test name
Test status
Simulation time 585097597 ps
CPU time 3.16 seconds
Started Jul 10 06:29:55 PM PDT 24
Finished Jul 10 06:30:00 PM PDT 24
Peak memory 215824 kb
Host smart-8f0fe29e-911f-4474-8243-329f81bfbdd9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863826657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.s
pi_device_same_csr_outstanding.863826657
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1708652195
Short name T189
Test name
Test status
Simulation time 934502196 ps
CPU time 7.7 seconds
Started Jul 10 06:29:59 PM PDT 24
Finished Jul 10 06:30:09 PM PDT 24
Peak memory 215768 kb
Host smart-1c9cca28-9b03-45f3-ab63-02aae9cbd841
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708652195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.1708652195
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.36186852
Short name T1071
Test name
Test status
Simulation time 139008334 ps
CPU time 2.59 seconds
Started Jul 10 06:30:03 PM PDT 24
Finished Jul 10 06:30:10 PM PDT 24
Peak memory 217408 kb
Host smart-77beb7e7-1554-4e6b-960e-67902388ee86
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36186852 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.36186852
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.1190295640
Short name T116
Test name
Test status
Simulation time 102747248 ps
CPU time 2.61 seconds
Started Jul 10 06:30:02 PM PDT 24
Finished Jul 10 06:30:06 PM PDT 24
Peak memory 215728 kb
Host smart-a44dce08-afad-4a95-9892-145ade392c7e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190295640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
1190295640
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2706942737
Short name T1062
Test name
Test status
Simulation time 10736855 ps
CPU time 0.72 seconds
Started Jul 10 06:30:02 PM PDT 24
Finished Jul 10 06:30:04 PM PDT 24
Peak memory 204284 kb
Host smart-c7e40d6d-94d5-4a05-ac2e-396cd5b471f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706942737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
2706942737
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2875733881
Short name T156
Test name
Test status
Simulation time 3969780561 ps
CPU time 4.33 seconds
Started Jul 10 06:29:58 PM PDT 24
Finished Jul 10 06:30:04 PM PDT 24
Peak memory 215816 kb
Host smart-17eb2e9a-4cc0-4814-a620-5cc0bf0ea940
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875733881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.2875733881
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3638764714
Short name T111
Test name
Test status
Simulation time 334536519 ps
CPU time 4.77 seconds
Started Jul 10 06:30:02 PM PDT 24
Finished Jul 10 06:30:09 PM PDT 24
Peak memory 215996 kb
Host smart-54961507-3f58-470c-8f1a-b9d279a6a732
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638764714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
3638764714
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2363654434
Short name T190
Test name
Test status
Simulation time 108301930 ps
CPU time 6.9 seconds
Started Jul 10 06:29:58 PM PDT 24
Finished Jul 10 06:30:07 PM PDT 24
Peak memory 215796 kb
Host smart-fa838249-1b21-4770-bf2e-fabd23a572b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363654434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.2363654434
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1088621746
Short name T103
Test name
Test status
Simulation time 95982770 ps
CPU time 3.78 seconds
Started Jul 10 06:29:59 PM PDT 24
Finished Jul 10 06:30:04 PM PDT 24
Peak memory 217948 kb
Host smart-5b183a35-eeee-482e-a6c5-d0f236482778
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088621746 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.1088621746
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1309360559
Short name T117
Test name
Test status
Simulation time 63713427 ps
CPU time 1.25 seconds
Started Jul 10 06:29:58 PM PDT 24
Finished Jul 10 06:30:01 PM PDT 24
Peak memory 215732 kb
Host smart-3fb49734-5e9e-4c6b-bbac-f2f497a2b6e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309360559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
1309360559
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.1811514623
Short name T1129
Test name
Test status
Simulation time 36623519 ps
CPU time 0.74 seconds
Started Jul 10 06:30:03 PM PDT 24
Finished Jul 10 06:30:08 PM PDT 24
Peak memory 204300 kb
Host smart-0df9cef2-388e-4740-8f9e-7ccf12bac4dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811514623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
1811514623
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1734219410
Short name T1075
Test name
Test status
Simulation time 122790376 ps
CPU time 1.96 seconds
Started Jul 10 06:30:01 PM PDT 24
Finished Jul 10 06:30:05 PM PDT 24
Peak memory 215760 kb
Host smart-0e5c5f8f-5133-4483-9d11-74f7981214a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734219410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.1734219410
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.353766836
Short name T1131
Test name
Test status
Simulation time 85830156 ps
CPU time 2.07 seconds
Started Jul 10 06:29:58 PM PDT 24
Finished Jul 10 06:30:02 PM PDT 24
Peak memory 215944 kb
Host smart-a3119d41-e313-42b0-b06e-b13f4c686ac3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353766836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.353766836
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1087468102
Short name T1081
Test name
Test status
Simulation time 52803999 ps
CPU time 3.34 seconds
Started Jul 10 06:30:05 PM PDT 24
Finished Jul 10 06:30:12 PM PDT 24
Peak memory 217624 kb
Host smart-d03d4990-62e1-45de-a4d1-78c8c8f6aee4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087468102 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.1087468102
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.230889090
Short name T131
Test name
Test status
Simulation time 346828634 ps
CPU time 2.11 seconds
Started Jul 10 06:30:05 PM PDT 24
Finished Jul 10 06:30:11 PM PDT 24
Peak memory 215536 kb
Host smart-f5c3da5c-01ae-49f4-b657-b741036eb166
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230889090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.230889090
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.94484341
Short name T1043
Test name
Test status
Simulation time 41562915 ps
CPU time 0.76 seconds
Started Jul 10 06:29:58 PM PDT 24
Finished Jul 10 06:30:01 PM PDT 24
Peak memory 204632 kb
Host smart-fd3904b6-e228-4aa0-8ada-af3f2618647d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94484341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.94484341
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1719135885
Short name T1098
Test name
Test status
Simulation time 282527510 ps
CPU time 2.76 seconds
Started Jul 10 06:30:04 PM PDT 24
Finished Jul 10 06:30:10 PM PDT 24
Peak memory 215740 kb
Host smart-a8b8aa42-8d6e-48d1-aa56-b7d4a5fd67cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719135885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.1719135885
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3467995218
Short name T1061
Test name
Test status
Simulation time 25600563 ps
CPU time 1.45 seconds
Started Jul 10 06:30:04 PM PDT 24
Finished Jul 10 06:30:09 PM PDT 24
Peak memory 216028 kb
Host smart-cfe1c5d9-fc64-4b94-af8d-c179173c9980
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467995218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
3467995218
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.4171374689
Short name T114
Test name
Test status
Simulation time 88950743 ps
CPU time 1.6 seconds
Started Jul 10 06:30:06 PM PDT 24
Finished Jul 10 06:30:12 PM PDT 24
Peak memory 215956 kb
Host smart-ead7302a-4cbd-455d-b270-d6d8900d2a06
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171374689 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.4171374689
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1472653729
Short name T122
Test name
Test status
Simulation time 86932082 ps
CPU time 2.69 seconds
Started Jul 10 06:30:06 PM PDT 24
Finished Jul 10 06:30:14 PM PDT 24
Peak memory 215728 kb
Host smart-cfa43eae-6faf-4068-9acd-3ea6ba9c7ea1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472653729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
1472653729
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.143528387
Short name T1074
Test name
Test status
Simulation time 16557463 ps
CPU time 0.75 seconds
Started Jul 10 06:30:06 PM PDT 24
Finished Jul 10 06:30:11 PM PDT 24
Peak memory 204284 kb
Host smart-be4dc5f2-ca2e-45ae-a292-0167a5fd69c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143528387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.143528387
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2392442647
Short name T1049
Test name
Test status
Simulation time 204013828 ps
CPU time 3.69 seconds
Started Jul 10 06:30:06 PM PDT 24
Finished Jul 10 06:30:15 PM PDT 24
Peak memory 215700 kb
Host smart-7a678a6c-a45b-400f-8d04-77efcd9fa9ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392442647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.2392442647
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2435970111
Short name T95
Test name
Test status
Simulation time 48527647 ps
CPU time 1.45 seconds
Started Jul 10 06:30:04 PM PDT 24
Finished Jul 10 06:30:10 PM PDT 24
Peak memory 215996 kb
Host smart-3dfdba9d-dbe4-4848-bdc2-c21fc2c11d9e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435970111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
2435970111
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.623230437
Short name T71
Test name
Test status
Simulation time 462586464 ps
CPU time 8.36 seconds
Started Jul 10 06:30:04 PM PDT 24
Finished Jul 10 06:30:16 PM PDT 24
Peak memory 215768 kb
Host smart-9cca1277-86d6-4fb0-8dfd-7e23bf7fd375
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623230437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device
_tl_intg_err.623230437
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3136715602
Short name T1069
Test name
Test status
Simulation time 432507569 ps
CPU time 3.67 seconds
Started Jul 10 06:30:04 PM PDT 24
Finished Jul 10 06:30:12 PM PDT 24
Peak memory 218032 kb
Host smart-97fa083c-4712-4a93-885d-b2544488c6e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136715602 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.3136715602
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1734789825
Short name T1080
Test name
Test status
Simulation time 35311322 ps
CPU time 1.39 seconds
Started Jul 10 06:30:05 PM PDT 24
Finished Jul 10 06:30:10 PM PDT 24
Peak memory 215628 kb
Host smart-d274eb85-68a1-4d16-bd49-0f58d86273e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734789825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
1734789825
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.2608217321
Short name T1086
Test name
Test status
Simulation time 13428889 ps
CPU time 0.7 seconds
Started Jul 10 06:30:04 PM PDT 24
Finished Jul 10 06:30:08 PM PDT 24
Peak memory 204296 kb
Host smart-90905316-8840-4c40-b2e9-31da6e8f7c56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608217321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
2608217321
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.4211319386
Short name T1117
Test name
Test status
Simulation time 211638117 ps
CPU time 1.81 seconds
Started Jul 10 06:30:06 PM PDT 24
Finished Jul 10 06:30:12 PM PDT 24
Peak memory 207604 kb
Host smart-92c1748c-d01e-41dc-9369-112608cdd1f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211319386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.4211319386
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3425657548
Short name T1121
Test name
Test status
Simulation time 349027573 ps
CPU time 8.33 seconds
Started Jul 10 06:30:03 PM PDT 24
Finished Jul 10 06:30:15 PM PDT 24
Peak memory 215864 kb
Host smart-ab404045-b5e8-43b8-8162-b7f54c96f3c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425657548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.3425657548
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.866018529
Short name T91
Test name
Test status
Simulation time 390615813 ps
CPU time 2.92 seconds
Started Jul 10 06:30:03 PM PDT 24
Finished Jul 10 06:30:09 PM PDT 24
Peak memory 217624 kb
Host smart-70ef551f-2123-45bb-b488-483ae198d94b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866018529 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.866018529
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2137990303
Short name T1079
Test name
Test status
Simulation time 20998178 ps
CPU time 1.37 seconds
Started Jul 10 06:30:06 PM PDT 24
Finished Jul 10 06:30:12 PM PDT 24
Peak memory 207536 kb
Host smart-251e4f17-3cb4-42ca-88e4-0092f189ddaa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137990303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
2137990303
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.1794347769
Short name T1096
Test name
Test status
Simulation time 13103689 ps
CPU time 0.72 seconds
Started Jul 10 06:30:05 PM PDT 24
Finished Jul 10 06:30:10 PM PDT 24
Peak memory 204612 kb
Host smart-9e25f251-03f6-4f5b-8dac-bdbda6d99e9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794347769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
1794347769
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1826486465
Short name T1091
Test name
Test status
Simulation time 495282909 ps
CPU time 3.06 seconds
Started Jul 10 06:30:03 PM PDT 24
Finished Jul 10 06:30:09 PM PDT 24
Peak memory 215684 kb
Host smart-0f199d17-48c8-4442-8fda-3ebf54aa294c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826486465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.1826486465
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.1946463
Short name T1119
Test name
Test status
Simulation time 379649749 ps
CPU time 2.62 seconds
Started Jul 10 06:30:06 PM PDT 24
Finished Jul 10 06:30:12 PM PDT 24
Peak memory 217032 kb
Host smart-a963b0f0-4b4c-42a5-9f68-e4172715052b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.1946463
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1702009453
Short name T69
Test name
Test status
Simulation time 5252190721 ps
CPU time 12.47 seconds
Started Jul 10 06:30:03 PM PDT 24
Finished Jul 10 06:30:19 PM PDT 24
Peak memory 215844 kb
Host smart-b095d92d-43da-4ecb-b20e-2cd2faed8330
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702009453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.1702009453
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.177486501
Short name T112
Test name
Test status
Simulation time 71642116 ps
CPU time 2.56 seconds
Started Jul 10 06:30:04 PM PDT 24
Finished Jul 10 06:30:10 PM PDT 24
Peak memory 216800 kb
Host smart-c5d48d1e-1f38-4222-85b2-12e60fec3104
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177486501 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.177486501
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.4187847635
Short name T1128
Test name
Test status
Simulation time 271773693 ps
CPU time 2.39 seconds
Started Jul 10 06:30:04 PM PDT 24
Finished Jul 10 06:30:10 PM PDT 24
Peak memory 215628 kb
Host smart-e6b3d743-7a19-48f8-8443-b32f8a4e1945
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187847635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
4187847635
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.3770763496
Short name T1066
Test name
Test status
Simulation time 34535193 ps
CPU time 0.74 seconds
Started Jul 10 06:30:06 PM PDT 24
Finished Jul 10 06:30:12 PM PDT 24
Peak memory 204296 kb
Host smart-c6de0d81-5648-49eb-a15d-32c049eea52b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770763496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
3770763496
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2830735637
Short name T1082
Test name
Test status
Simulation time 176562696 ps
CPU time 3.09 seconds
Started Jul 10 06:30:03 PM PDT 24
Finished Jul 10 06:30:10 PM PDT 24
Peak memory 215700 kb
Host smart-714b5fc3-e290-4694-905c-f058cd80bef2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830735637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.2830735637
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.2649370863
Short name T101
Test name
Test status
Simulation time 90711359 ps
CPU time 1.51 seconds
Started Jul 10 06:30:03 PM PDT 24
Finished Jul 10 06:30:08 PM PDT 24
Peak memory 216016 kb
Host smart-3ad22792-9f45-4c2c-b349-c9746edfa430
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649370863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
2649370863
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.2959379179
Short name T184
Test name
Test status
Simulation time 1255612787 ps
CPU time 7.6 seconds
Started Jul 10 06:30:05 PM PDT 24
Finished Jul 10 06:30:17 PM PDT 24
Peak memory 215812 kb
Host smart-cde99a73-b2e8-47f8-880f-1cec608fe0d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959379179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.2959379179
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2116330679
Short name T1118
Test name
Test status
Simulation time 112460119 ps
CPU time 3.73 seconds
Started Jul 10 06:30:04 PM PDT 24
Finished Jul 10 06:30:11 PM PDT 24
Peak memory 218844 kb
Host smart-56ae55f7-6fa1-49c3-a1ca-4eef6807a6fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116330679 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.2116330679
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.627950151
Short name T1105
Test name
Test status
Simulation time 264549402 ps
CPU time 2.2 seconds
Started Jul 10 06:30:06 PM PDT 24
Finished Jul 10 06:30:14 PM PDT 24
Peak memory 215728 kb
Host smart-a9f7b970-9fae-4490-b037-7277779d7c09
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627950151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.627950151
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.136839450
Short name T1027
Test name
Test status
Simulation time 27268537 ps
CPU time 0.71 seconds
Started Jul 10 06:30:06 PM PDT 24
Finished Jul 10 06:30:11 PM PDT 24
Peak memory 204636 kb
Host smart-7fd9dc02-204e-4746-9518-1deaa4a7f713
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136839450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.136839450
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2213109446
Short name T1123
Test name
Test status
Simulation time 2115894158 ps
CPU time 4.26 seconds
Started Jul 10 06:30:06 PM PDT 24
Finished Jul 10 06:30:16 PM PDT 24
Peak memory 215728 kb
Host smart-07959b24-61d5-4de0-b60d-84a91a313dae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213109446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.2213109446
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2430361671
Short name T99
Test name
Test status
Simulation time 172271874 ps
CPU time 2.82 seconds
Started Jul 10 06:30:03 PM PDT 24
Finished Jul 10 06:30:08 PM PDT 24
Peak memory 215924 kb
Host smart-83aa256b-fbbe-4d79-b38a-84ccb7930dd7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430361671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
2430361671
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1972577215
Short name T1130
Test name
Test status
Simulation time 330397177 ps
CPU time 2.52 seconds
Started Jul 10 06:30:06 PM PDT 24
Finished Jul 10 06:30:13 PM PDT 24
Peak memory 216952 kb
Host smart-dc05b7cb-4667-4205-9b8f-321ca49b9119
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972577215 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.1972577215
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1644626286
Short name T1057
Test name
Test status
Simulation time 106289408 ps
CPU time 1.41 seconds
Started Jul 10 06:30:07 PM PDT 24
Finished Jul 10 06:30:14 PM PDT 24
Peak memory 207444 kb
Host smart-052ba088-c9b2-4579-b8d6-e5ae14489f1a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644626286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
1644626286
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.656436895
Short name T1094
Test name
Test status
Simulation time 14528333 ps
CPU time 0.72 seconds
Started Jul 10 06:30:07 PM PDT 24
Finished Jul 10 06:30:13 PM PDT 24
Peak memory 204632 kb
Host smart-3d157f66-49af-4f21-8aa3-e5eae662921c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656436895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.656436895
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.3763832831
Short name T148
Test name
Test status
Simulation time 61105426 ps
CPU time 3.72 seconds
Started Jul 10 06:30:05 PM PDT 24
Finished Jul 10 06:30:13 PM PDT 24
Peak memory 215764 kb
Host smart-51919d2b-2407-4ed3-a33d-dcbd95c3ce56
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763832831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.3763832831
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.3637128861
Short name T110
Test name
Test status
Simulation time 97952400 ps
CPU time 3.13 seconds
Started Jul 10 06:30:06 PM PDT 24
Finished Jul 10 06:30:15 PM PDT 24
Peak memory 216020 kb
Host smart-32f11bc8-77be-4a9a-9f8c-35be2b7bc16b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637128861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
3637128861
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1017045968
Short name T186
Test name
Test status
Simulation time 410138680 ps
CPU time 6.86 seconds
Started Jul 10 06:30:06 PM PDT 24
Finished Jul 10 06:30:19 PM PDT 24
Peak memory 217104 kb
Host smart-634ee4a9-f83d-4d41-9195-c568a32470be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017045968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.1017045968
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.1566653483
Short name T132
Test name
Test status
Simulation time 1288839449 ps
CPU time 15.03 seconds
Started Jul 10 06:29:48 PM PDT 24
Finished Jul 10 06:30:04 PM PDT 24
Peak memory 215728 kb
Host smart-7007542f-7a12-436e-9faa-38f52e69b2de
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566653483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.1566653483
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1858690691
Short name T1116
Test name
Test status
Simulation time 1087988761 ps
CPU time 34.85 seconds
Started Jul 10 06:29:47 PM PDT 24
Finished Jul 10 06:30:23 PM PDT 24
Peak memory 207340 kb
Host smart-50d5c91a-383e-4c12-af7e-86a4ca7ae3a2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858690691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.1858690691
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2368685342
Short name T123
Test name
Test status
Simulation time 29597094 ps
CPU time 1.24 seconds
Started Jul 10 06:29:48 PM PDT 24
Finished Jul 10 06:29:52 PM PDT 24
Peak memory 207432 kb
Host smart-687c7764-339b-4332-91ed-af95b693b351
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368685342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.2368685342
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.769261635
Short name T1101
Test name
Test status
Simulation time 577975597 ps
CPU time 3.45 seconds
Started Jul 10 06:29:48 PM PDT 24
Finished Jul 10 06:29:54 PM PDT 24
Peak memory 218740 kb
Host smart-a72b54b3-ffe0-42d8-a112-02d608158e33
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769261635 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.769261635
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.822934060
Short name T1088
Test name
Test status
Simulation time 36967119 ps
CPU time 2.33 seconds
Started Jul 10 06:29:45 PM PDT 24
Finished Jul 10 06:29:48 PM PDT 24
Peak memory 215712 kb
Host smart-7b5c93a6-ea59-47da-a1e2-cbe8b46bc03a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822934060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.822934060
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.2447543524
Short name T1120
Test name
Test status
Simulation time 25268895 ps
CPU time 0.77 seconds
Started Jul 10 06:29:47 PM PDT 24
Finished Jul 10 06:29:50 PM PDT 24
Peak memory 204264 kb
Host smart-db4a69cb-e90e-4726-bdc2-e1527a704ddb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447543524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.2
447543524
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.230496314
Short name T118
Test name
Test status
Simulation time 49327492 ps
CPU time 1.73 seconds
Started Jul 10 06:29:46 PM PDT 24
Finished Jul 10 06:29:49 PM PDT 24
Peak memory 215768 kb
Host smart-04d573f5-627b-463c-8633-4f885ca371b4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230496314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_
device_mem_partial_access.230496314
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2279293449
Short name T1033
Test name
Test status
Simulation time 29293220 ps
CPU time 0.69 seconds
Started Jul 10 06:29:48 PM PDT 24
Finished Jul 10 06:29:50 PM PDT 24
Peak memory 204088 kb
Host smart-2380588b-3da6-4e71-94a8-979db7ebace4
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279293449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.2279293449
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.652678727
Short name T1050
Test name
Test status
Simulation time 151946596 ps
CPU time 3.91 seconds
Started Jul 10 06:29:45 PM PDT 24
Finished Jul 10 06:29:50 PM PDT 24
Peak memory 207460 kb
Host smart-6798fce2-7f42-4d3c-b558-5864b02f1f40
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652678727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sp
i_device_same_csr_outstanding.652678727
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.208813962
Short name T102
Test name
Test status
Simulation time 46212326 ps
CPU time 2.87 seconds
Started Jul 10 06:29:41 PM PDT 24
Finished Jul 10 06:29:47 PM PDT 24
Peak memory 215996 kb
Host smart-164c9f3a-2434-4fd4-b094-f8003992b0b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208813962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.208813962
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.4158318492
Short name T192
Test name
Test status
Simulation time 692951064 ps
CPU time 19.43 seconds
Started Jul 10 06:29:45 PM PDT 24
Finished Jul 10 06:30:06 PM PDT 24
Peak memory 215792 kb
Host smart-2d5035db-b1fa-48a8-961d-265b76effb50
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158318492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.4158318492
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.1485727654
Short name T1031
Test name
Test status
Simulation time 30322526 ps
CPU time 0.72 seconds
Started Jul 10 06:30:08 PM PDT 24
Finished Jul 10 06:30:13 PM PDT 24
Peak memory 204196 kb
Host smart-6a33f68e-82d3-478d-9bf9-d0587b17fb17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485727654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
1485727654
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.1766869182
Short name T1038
Test name
Test status
Simulation time 134848067 ps
CPU time 0.69 seconds
Started Jul 10 06:30:10 PM PDT 24
Finished Jul 10 06:30:15 PM PDT 24
Peak memory 204308 kb
Host smart-651fc796-d98a-4206-8ded-6bfcd55125c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766869182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
1766869182
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.593618455
Short name T1051
Test name
Test status
Simulation time 22210690 ps
CPU time 0.73 seconds
Started Jul 10 06:30:09 PM PDT 24
Finished Jul 10 06:30:14 PM PDT 24
Peak memory 204304 kb
Host smart-a35bd8ff-2c87-490a-a2bd-01d0375021ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593618455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.593618455
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2590964472
Short name T1032
Test name
Test status
Simulation time 86797444 ps
CPU time 0.74 seconds
Started Jul 10 06:30:11 PM PDT 24
Finished Jul 10 06:30:16 PM PDT 24
Peak memory 204288 kb
Host smart-85767f78-ab51-40bc-a45a-8fb64753384d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590964472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
2590964472
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.3145734718
Short name T1073
Test name
Test status
Simulation time 28796269 ps
CPU time 0.76 seconds
Started Jul 10 06:30:10 PM PDT 24
Finished Jul 10 06:30:15 PM PDT 24
Peak memory 204616 kb
Host smart-3f4d629c-445f-4683-9eae-9e60911595d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145734718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
3145734718
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.2718421441
Short name T1053
Test name
Test status
Simulation time 39850974 ps
CPU time 0.75 seconds
Started Jul 10 06:30:10 PM PDT 24
Finished Jul 10 06:30:15 PM PDT 24
Peak memory 204284 kb
Host smart-5728d577-ba36-4024-87d7-66262be09ee4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718421441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
2718421441
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.3707202360
Short name T1022
Test name
Test status
Simulation time 39255536 ps
CPU time 0.81 seconds
Started Jul 10 06:30:10 PM PDT 24
Finished Jul 10 06:30:15 PM PDT 24
Peak memory 204304 kb
Host smart-747e0e99-0576-4d78-87a6-1625878efc9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707202360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
3707202360
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.2584184349
Short name T1072
Test name
Test status
Simulation time 45180790 ps
CPU time 0.76 seconds
Started Jul 10 06:30:08 PM PDT 24
Finished Jul 10 06:30:14 PM PDT 24
Peak memory 204296 kb
Host smart-c2a4df4b-e044-41d3-8782-3d4324faca2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584184349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
2584184349
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.3352651437
Short name T1065
Test name
Test status
Simulation time 64475355 ps
CPU time 0.75 seconds
Started Jul 10 06:30:08 PM PDT 24
Finished Jul 10 06:30:14 PM PDT 24
Peak memory 204324 kb
Host smart-9cf23f8b-3bd7-452d-8772-4dc7208d4a86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352651437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
3352651437
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2512834416
Short name T1047
Test name
Test status
Simulation time 29055029 ps
CPU time 0.72 seconds
Started Jul 10 06:30:10 PM PDT 24
Finished Jul 10 06:30:15 PM PDT 24
Peak memory 204624 kb
Host smart-6a8f488e-74ac-4323-9f08-e573d55d3eae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512834416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
2512834416
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3505979039
Short name T1077
Test name
Test status
Simulation time 2412241343 ps
CPU time 8.16 seconds
Started Jul 10 06:29:48 PM PDT 24
Finished Jul 10 06:29:58 PM PDT 24
Peak memory 215772 kb
Host smart-946a93af-b4f8-4ae3-b127-6a40eb2a7a10
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505979039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.3505979039
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.4143324277
Short name T121
Test name
Test status
Simulation time 2762734679 ps
CPU time 38.6 seconds
Started Jul 10 06:29:48 PM PDT 24
Finished Jul 10 06:30:28 PM PDT 24
Peak memory 207608 kb
Host smart-cc3753e7-9a8b-470a-a147-f469ee48e2c3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143324277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.4143324277
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1308242544
Short name T113
Test name
Test status
Simulation time 127834772 ps
CPU time 2.53 seconds
Started Jul 10 06:29:47 PM PDT 24
Finished Jul 10 06:29:52 PM PDT 24
Peak memory 215832 kb
Host smart-afceda09-f751-4285-8841-33dc372dc901
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308242544 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.1308242544
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.752401291
Short name T1042
Test name
Test status
Simulation time 94153915 ps
CPU time 1.93 seconds
Started Jul 10 06:29:46 PM PDT 24
Finished Jul 10 06:29:49 PM PDT 24
Peak memory 215704 kb
Host smart-5902945e-a656-42dd-a2bc-229a615f285e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752401291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.752401291
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.419321623
Short name T1058
Test name
Test status
Simulation time 16622724 ps
CPU time 0.76 seconds
Started Jul 10 06:29:47 PM PDT 24
Finished Jul 10 06:29:49 PM PDT 24
Peak memory 204196 kb
Host smart-7b5f5b1b-a7dc-4e6f-b9da-527c126d61c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419321623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.419321623
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.244729575
Short name T1102
Test name
Test status
Simulation time 41981768 ps
CPU time 1.66 seconds
Started Jul 10 06:29:48 PM PDT 24
Finished Jul 10 06:29:52 PM PDT 24
Peak memory 215728 kb
Host smart-6ab277ea-7144-4a35-8bf8-7ea72e60f33f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244729575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_
device_mem_partial_access.244729575
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1560323388
Short name T1064
Test name
Test status
Simulation time 17265322 ps
CPU time 0.64 seconds
Started Jul 10 06:29:46 PM PDT 24
Finished Jul 10 06:29:48 PM PDT 24
Peak memory 204108 kb
Host smart-5ac8d749-9514-4139-a86a-9c2c08ed16b5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560323388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.1560323388
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.313079260
Short name T159
Test name
Test status
Simulation time 214201941 ps
CPU time 4.57 seconds
Started Jul 10 06:29:47 PM PDT 24
Finished Jul 10 06:29:53 PM PDT 24
Peak memory 215788 kb
Host smart-8387e620-9e2d-4be2-a233-8014ab65f82c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313079260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sp
i_device_same_csr_outstanding.313079260
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1703275262
Short name T92
Test name
Test status
Simulation time 41890045 ps
CPU time 2.81 seconds
Started Jul 10 06:29:46 PM PDT 24
Finished Jul 10 06:29:50 PM PDT 24
Peak memory 217504 kb
Host smart-82d56dcd-dd62-45e1-83ab-24dfa08fc105
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703275262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.1
703275262
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.362574124
Short name T1087
Test name
Test status
Simulation time 1377957101 ps
CPU time 7.68 seconds
Started Jul 10 06:29:47 PM PDT 24
Finished Jul 10 06:29:56 PM PDT 24
Peak memory 215692 kb
Host smart-b73aafec-d6cc-4ca2-a51c-2fb16d2365d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362574124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_
tl_intg_err.362574124
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.3423727833
Short name T1040
Test name
Test status
Simulation time 14604883 ps
CPU time 0.76 seconds
Started Jul 10 06:30:09 PM PDT 24
Finished Jul 10 06:30:15 PM PDT 24
Peak memory 204248 kb
Host smart-58d73bbc-63a6-416e-900f-1f51bdfb25f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423727833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
3423727833
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.4244856129
Short name T1055
Test name
Test status
Simulation time 13677923 ps
CPU time 0.69 seconds
Started Jul 10 06:30:08 PM PDT 24
Finished Jul 10 06:30:14 PM PDT 24
Peak memory 204328 kb
Host smart-fe96b191-a4da-4c0e-9f29-b52dfd21321b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244856129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
4244856129
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3942080166
Short name T1084
Test name
Test status
Simulation time 21993609 ps
CPU time 0.71 seconds
Started Jul 10 06:30:09 PM PDT 24
Finished Jul 10 06:30:15 PM PDT 24
Peak memory 204272 kb
Host smart-1c0a2fe6-b48d-492b-b2fb-6e5bceacc09b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942080166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
3942080166
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.2272236712
Short name T1045
Test name
Test status
Simulation time 12521942 ps
CPU time 0.7 seconds
Started Jul 10 06:30:07 PM PDT 24
Finished Jul 10 06:30:13 PM PDT 24
Peak memory 204300 kb
Host smart-f75d5115-a6cc-49ff-8bb8-896c952923ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272236712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
2272236712
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3673406168
Short name T1028
Test name
Test status
Simulation time 19601044 ps
CPU time 0.77 seconds
Started Jul 10 06:30:09 PM PDT 24
Finished Jul 10 06:30:15 PM PDT 24
Peak memory 204296 kb
Host smart-15e027e7-9be7-48b2-b2ab-c993da1eb65a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673406168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
3673406168
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1762275458
Short name T1095
Test name
Test status
Simulation time 11718946 ps
CPU time 0.72 seconds
Started Jul 10 06:30:11 PM PDT 24
Finished Jul 10 06:30:16 PM PDT 24
Peak memory 204604 kb
Host smart-91a11962-a853-4e46-9272-f42949add7f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762275458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
1762275458
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.3549338453
Short name T1024
Test name
Test status
Simulation time 48098594 ps
CPU time 0.72 seconds
Started Jul 10 06:30:08 PM PDT 24
Finished Jul 10 06:30:14 PM PDT 24
Peak memory 204552 kb
Host smart-0fd740e4-4061-48ec-9046-aa818469853b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549338453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
3549338453
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.1941478895
Short name T1083
Test name
Test status
Simulation time 95377723 ps
CPU time 0.69 seconds
Started Jul 10 06:30:15 PM PDT 24
Finished Jul 10 06:30:18 PM PDT 24
Peak memory 204304 kb
Host smart-a06d167f-ddd4-41c5-9919-3875494c3176
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941478895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
1941478895
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.1596732581
Short name T1078
Test name
Test status
Simulation time 40337435 ps
CPU time 0.7 seconds
Started Jul 10 06:30:09 PM PDT 24
Finished Jul 10 06:30:15 PM PDT 24
Peak memory 204236 kb
Host smart-3ce3e4da-8b93-475e-b6b6-feb6d491d104
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596732581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
1596732581
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.666528218
Short name T1106
Test name
Test status
Simulation time 13569999 ps
CPU time 0.7 seconds
Started Jul 10 06:30:08 PM PDT 24
Finished Jul 10 06:30:14 PM PDT 24
Peak memory 204296 kb
Host smart-76789a36-13ba-4c84-bd24-bf23b98dde57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666528218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.666528218
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.2356267219
Short name T1089
Test name
Test status
Simulation time 2894358499 ps
CPU time 14.73 seconds
Started Jul 10 06:29:51 PM PDT 24
Finished Jul 10 06:30:08 PM PDT 24
Peak memory 207516 kb
Host smart-0c67df79-6784-4d34-80e9-8609aee6ba44
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356267219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.2356267219
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1340946328
Short name T1056
Test name
Test status
Simulation time 1226253299 ps
CPU time 13.19 seconds
Started Jul 10 06:29:50 PM PDT 24
Finished Jul 10 06:30:05 PM PDT 24
Peak memory 207444 kb
Host smart-20de8a77-5558-464f-8924-2ef84bec81e4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340946328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.1340946328
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.4151736945
Short name T82
Test name
Test status
Simulation time 29759603 ps
CPU time 1.23 seconds
Started Jul 10 06:29:47 PM PDT 24
Finished Jul 10 06:29:50 PM PDT 24
Peak memory 216700 kb
Host smart-c635c911-cf6d-4320-9618-b334c57d51ed
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151736945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.4151736945
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3116828097
Short name T1076
Test name
Test status
Simulation time 364519206 ps
CPU time 3.29 seconds
Started Jul 10 06:29:51 PM PDT 24
Finished Jul 10 06:29:57 PM PDT 24
Peak memory 217600 kb
Host smart-e5b4fbe4-e557-4ba6-b04f-195cce177e55
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116828097 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.3116828097
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.488611490
Short name T120
Test name
Test status
Simulation time 99738554 ps
CPU time 1.79 seconds
Started Jul 10 06:29:54 PM PDT 24
Finished Jul 10 06:29:58 PM PDT 24
Peak memory 207524 kb
Host smart-bba20a1b-382d-4019-aaed-244f9d5334f4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488611490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.488611490
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.1101232642
Short name T1046
Test name
Test status
Simulation time 11516436 ps
CPU time 0.7 seconds
Started Jul 10 06:29:48 PM PDT 24
Finished Jul 10 06:29:51 PM PDT 24
Peak memory 204632 kb
Host smart-bc402644-1228-4699-8535-7b5e9b13a2ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101232642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.1
101232642
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.2263239579
Short name T124
Test name
Test status
Simulation time 31684018 ps
CPU time 1.35 seconds
Started Jul 10 06:29:49 PM PDT 24
Finished Jul 10 06:29:52 PM PDT 24
Peak memory 215808 kb
Host smart-00ee6ff1-9b8a-48af-9895-14642c4dea1e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263239579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.2263239579
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2565023965
Short name T1109
Test name
Test status
Simulation time 41528429 ps
CPU time 0.73 seconds
Started Jul 10 06:29:46 PM PDT 24
Finished Jul 10 06:29:48 PM PDT 24
Peak memory 204432 kb
Host smart-c6a7f536-3c74-47ff-818a-d8d8c0c35328
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565023965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.2565023965
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.3995934015
Short name T1029
Test name
Test status
Simulation time 122619427 ps
CPU time 1.85 seconds
Started Jul 10 06:29:51 PM PDT 24
Finished Jul 10 06:29:55 PM PDT 24
Peak memory 217052 kb
Host smart-e24815f1-3768-466e-8b63-033c2ea76663
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995934015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.3995934015
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3460173046
Short name T108
Test name
Test status
Simulation time 138198774 ps
CPU time 3.25 seconds
Started Jul 10 06:29:46 PM PDT 24
Finished Jul 10 06:29:51 PM PDT 24
Peak memory 216016 kb
Host smart-519b6133-50f9-4286-9df3-214b6f006198
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460173046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.3
460173046
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2783751189
Short name T185
Test name
Test status
Simulation time 109636109 ps
CPU time 6.56 seconds
Started Jul 10 06:29:48 PM PDT 24
Finished Jul 10 06:29:56 PM PDT 24
Peak memory 215772 kb
Host smart-93480838-5e3b-4baf-82a7-eb4213f350b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783751189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.2783751189
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2575320867
Short name T1103
Test name
Test status
Simulation time 23210924 ps
CPU time 0.71 seconds
Started Jul 10 06:30:09 PM PDT 24
Finished Jul 10 06:30:15 PM PDT 24
Peak memory 204288 kb
Host smart-6fd04d99-674f-49cb-8e89-d4f2aaab3d7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575320867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
2575320867
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.2203775494
Short name T1067
Test name
Test status
Simulation time 47285133 ps
CPU time 0.72 seconds
Started Jul 10 06:30:09 PM PDT 24
Finished Jul 10 06:30:15 PM PDT 24
Peak memory 204252 kb
Host smart-8cdf3781-10f8-4eed-81cf-5e1aff89b8b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203775494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
2203775494
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.4092023848
Short name T1039
Test name
Test status
Simulation time 13319858 ps
CPU time 0.69 seconds
Started Jul 10 06:30:10 PM PDT 24
Finished Jul 10 06:30:16 PM PDT 24
Peak memory 204296 kb
Host smart-61781830-1552-4633-90bc-93a71201d072
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092023848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
4092023848
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.1693168054
Short name T1026
Test name
Test status
Simulation time 269490333 ps
CPU time 0.78 seconds
Started Jul 10 06:30:08 PM PDT 24
Finished Jul 10 06:30:13 PM PDT 24
Peak memory 204588 kb
Host smart-b90970ee-66ef-4b6e-b941-07655455a4a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693168054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
1693168054
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.248817709
Short name T1037
Test name
Test status
Simulation time 12585791 ps
CPU time 0.73 seconds
Started Jul 10 06:30:09 PM PDT 24
Finished Jul 10 06:30:14 PM PDT 24
Peak memory 204284 kb
Host smart-e1c26d33-ce35-42cd-8606-e9e2fa99612f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248817709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.248817709
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.223290823
Short name T1035
Test name
Test status
Simulation time 15527134 ps
CPU time 0.72 seconds
Started Jul 10 06:30:08 PM PDT 24
Finished Jul 10 06:30:14 PM PDT 24
Peak memory 204664 kb
Host smart-e73dee10-798b-4eaf-8efe-63a87f0ef66b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223290823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.223290823
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.4253008412
Short name T1070
Test name
Test status
Simulation time 25132254 ps
CPU time 0.7 seconds
Started Jul 10 06:30:09 PM PDT 24
Finished Jul 10 06:30:15 PM PDT 24
Peak memory 204284 kb
Host smart-3c3f0d82-9976-4bfa-b97e-09a942ba9176
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253008412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
4253008412
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.327392267
Short name T1068
Test name
Test status
Simulation time 40484401 ps
CPU time 0.69 seconds
Started Jul 10 06:30:09 PM PDT 24
Finished Jul 10 06:30:15 PM PDT 24
Peak memory 204252 kb
Host smart-fe2c8342-7bac-4c43-9eb3-300d96725b88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327392267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.327392267
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2071821399
Short name T1052
Test name
Test status
Simulation time 14639169 ps
CPU time 0.72 seconds
Started Jul 10 06:30:17 PM PDT 24
Finished Jul 10 06:30:19 PM PDT 24
Peak memory 204296 kb
Host smart-a9bfbe7c-1c24-48f4-b70c-df30d7e3e9f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071821399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
2071821399
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.2011355131
Short name T1023
Test name
Test status
Simulation time 17193853 ps
CPU time 0.72 seconds
Started Jul 10 06:30:16 PM PDT 24
Finished Jul 10 06:30:19 PM PDT 24
Peak memory 204296 kb
Host smart-b50e423a-437e-406f-9831-8835c179a8af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011355131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
2011355131
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.731645526
Short name T160
Test name
Test status
Simulation time 193914227 ps
CPU time 2.78 seconds
Started Jul 10 06:29:51 PM PDT 24
Finished Jul 10 06:29:57 PM PDT 24
Peak memory 215660 kb
Host smart-7a3c4ee1-5619-4033-be98-29c6c1d2cc91
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731645526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.731645526
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.1362895884
Short name T1115
Test name
Test status
Simulation time 198069922 ps
CPU time 0.74 seconds
Started Jul 10 06:29:51 PM PDT 24
Finished Jul 10 06:29:54 PM PDT 24
Peak memory 204612 kb
Host smart-57c67cf1-cf18-4e95-a059-9b2f6d3734ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362895884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.1
362895884
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3832324253
Short name T1063
Test name
Test status
Simulation time 64622325 ps
CPU time 3.99 seconds
Started Jul 10 06:29:52 PM PDT 24
Finished Jul 10 06:29:58 PM PDT 24
Peak memory 215760 kb
Host smart-95dd75ca-90cc-471b-85c4-0bd236f95695
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832324253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.3832324253
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.2239524689
Short name T107
Test name
Test status
Simulation time 89819488 ps
CPU time 2.38 seconds
Started Jul 10 06:29:51 PM PDT 24
Finished Jul 10 06:29:55 PM PDT 24
Peak memory 216188 kb
Host smart-1c886505-fcaf-4b74-b5c7-bb48ed91fe6f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239524689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.2
239524689
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3591590728
Short name T193
Test name
Test status
Simulation time 3604691517 ps
CPU time 19.87 seconds
Started Jul 10 06:29:50 PM PDT 24
Finished Jul 10 06:30:12 PM PDT 24
Peak memory 215760 kb
Host smart-0be75385-5e42-45c4-84fc-92700f5bb8d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591590728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.3591590728
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3705185799
Short name T106
Test name
Test status
Simulation time 60684854 ps
CPU time 3.84 seconds
Started Jul 10 06:29:55 PM PDT 24
Finished Jul 10 06:30:00 PM PDT 24
Peak memory 218900 kb
Host smart-dbc2c9b3-8cee-4a27-908d-0717bf83eac3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705185799 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.3705185799
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.519476364
Short name T129
Test name
Test status
Simulation time 69157789 ps
CPU time 2.28 seconds
Started Jul 10 06:29:53 PM PDT 24
Finished Jul 10 06:29:57 PM PDT 24
Peak memory 215736 kb
Host smart-d4d19f5c-e02d-4229-80a0-a2e2019d5065
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519476364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.519476364
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2042208358
Short name T1090
Test name
Test status
Simulation time 26271713 ps
CPU time 0.75 seconds
Started Jul 10 06:29:51 PM PDT 24
Finished Jul 10 06:29:54 PM PDT 24
Peak memory 204296 kb
Host smart-21073643-6ff5-46c7-bf4c-e440794f16a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042208358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.2
042208358
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2641255820
Short name T158
Test name
Test status
Simulation time 179589830 ps
CPU time 1.92 seconds
Started Jul 10 06:29:51 PM PDT 24
Finished Jul 10 06:29:56 PM PDT 24
Peak memory 215780 kb
Host smart-4191879c-7c4c-47e8-96fe-e05206c9e882
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641255820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.2641255820
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2086163522
Short name T1104
Test name
Test status
Simulation time 130146476 ps
CPU time 2.53 seconds
Started Jul 10 06:29:52 PM PDT 24
Finished Jul 10 06:29:57 PM PDT 24
Peak memory 216020 kb
Host smart-f2c75271-5727-47c9-a67d-acf377592ee9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086163522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.2
086163522
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1965840605
Short name T194
Test name
Test status
Simulation time 876015459 ps
CPU time 11.74 seconds
Started Jul 10 06:29:53 PM PDT 24
Finished Jul 10 06:30:07 PM PDT 24
Peak memory 215920 kb
Host smart-ac338352-88c3-4a97-aef6-6ac3895fdc54
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965840605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.1965840605
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3461739994
Short name T105
Test name
Test status
Simulation time 233265644 ps
CPU time 3.63 seconds
Started Jul 10 06:29:59 PM PDT 24
Finished Jul 10 06:30:05 PM PDT 24
Peak memory 219000 kb
Host smart-6eafd431-f723-404c-ae74-86274ac45ec3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461739994 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.3461739994
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.2090937087
Short name T128
Test name
Test status
Simulation time 96277627 ps
CPU time 1.81 seconds
Started Jul 10 06:29:50 PM PDT 24
Finished Jul 10 06:29:54 PM PDT 24
Peak memory 207496 kb
Host smart-98b1d132-eecc-409a-ad91-e12ca1ae8729
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090937087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.2
090937087
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.534526796
Short name T1059
Test name
Test status
Simulation time 46334607 ps
CPU time 0.69 seconds
Started Jul 10 06:29:50 PM PDT 24
Finished Jul 10 06:29:54 PM PDT 24
Peak memory 204304 kb
Host smart-1a6c1632-7aed-4789-8427-f0bd7ddbe980
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534526796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.534526796
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3788442989
Short name T1114
Test name
Test status
Simulation time 61323500 ps
CPU time 1.9 seconds
Started Jul 10 06:29:55 PM PDT 24
Finished Jul 10 06:29:59 PM PDT 24
Peak memory 215704 kb
Host smart-9cf05682-9985-4184-b5be-1cc7582433ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788442989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.3788442989
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2371076095
Short name T90
Test name
Test status
Simulation time 80961518 ps
CPU time 1.3 seconds
Started Jul 10 06:29:53 PM PDT 24
Finished Jul 10 06:29:56 PM PDT 24
Peak memory 217072 kb
Host smart-d90e354c-b502-4fac-94e6-ebed56b3a62b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371076095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.2
371076095
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.1301043191
Short name T1122
Test name
Test status
Simulation time 116792360 ps
CPU time 2.41 seconds
Started Jul 10 06:29:57 PM PDT 24
Finished Jul 10 06:30:01 PM PDT 24
Peak memory 218428 kb
Host smart-3182fe64-4ca0-4cb1-973b-5e3a37ff5490
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301043191 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.1301043191
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.2417381059
Short name T1097
Test name
Test status
Simulation time 33038717 ps
CPU time 2.15 seconds
Started Jul 10 06:29:56 PM PDT 24
Finished Jul 10 06:30:00 PM PDT 24
Peak memory 215652 kb
Host smart-6ca61c42-66d7-4b8d-a3ed-d4e0aea8b12e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417381059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.2
417381059
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.711556309
Short name T1093
Test name
Test status
Simulation time 64892511 ps
CPU time 0.82 seconds
Started Jul 10 06:29:58 PM PDT 24
Finished Jul 10 06:30:01 PM PDT 24
Peak memory 204296 kb
Host smart-0c1c5686-33ef-478f-b621-579d05a06fce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711556309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.711556309
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.539969012
Short name T1036
Test name
Test status
Simulation time 155696174 ps
CPU time 4.38 seconds
Started Jul 10 06:30:02 PM PDT 24
Finished Jul 10 06:30:08 PM PDT 24
Peak memory 215756 kb
Host smart-edf6bce0-ca9e-421f-a31b-f82051bdac81
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539969012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sp
i_device_same_csr_outstanding.539969012
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2550961684
Short name T100
Test name
Test status
Simulation time 100145933 ps
CPU time 3.07 seconds
Started Jul 10 06:29:58 PM PDT 24
Finished Jul 10 06:30:03 PM PDT 24
Peak memory 217352 kb
Host smart-b10e2ce9-6cde-45a7-891a-f83af74b2046
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550961684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.2
550961684
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1692168842
Short name T182
Test name
Test status
Simulation time 106496152 ps
CPU time 6.96 seconds
Started Jul 10 06:29:59 PM PDT 24
Finished Jul 10 06:30:08 PM PDT 24
Peak memory 215712 kb
Host smart-4f0c4497-61b5-495a-aca8-dcd185638249
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692168842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.1692168842
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.261231732
Short name T1100
Test name
Test status
Simulation time 192673915 ps
CPU time 2.46 seconds
Started Jul 10 06:29:56 PM PDT 24
Finished Jul 10 06:30:01 PM PDT 24
Peak memory 217172 kb
Host smart-66054301-4bdb-415c-bc9e-9086a74563b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261231732 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.261231732
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.1801600266
Short name T1025
Test name
Test status
Simulation time 144844923 ps
CPU time 1.46 seconds
Started Jul 10 06:30:00 PM PDT 24
Finished Jul 10 06:30:03 PM PDT 24
Peak memory 207536 kb
Host smart-ce9f682d-a649-4d5c-9538-5787bed2aec0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801600266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.1
801600266
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.512072949
Short name T1034
Test name
Test status
Simulation time 18840943 ps
CPU time 0.76 seconds
Started Jul 10 06:30:02 PM PDT 24
Finished Jul 10 06:30:05 PM PDT 24
Peak memory 204308 kb
Host smart-609b95fc-a3a6-4f37-a4f0-9cb22ba47aef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512072949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.512072949
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2460100816
Short name T1048
Test name
Test status
Simulation time 64194468 ps
CPU time 3.77 seconds
Started Jul 10 06:30:03 PM PDT 24
Finished Jul 10 06:30:11 PM PDT 24
Peak memory 215768 kb
Host smart-774d2710-049f-4c30-9f59-f2982cdb1314
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460100816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.2460100816
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.1616164530
Short name T827
Test name
Test status
Simulation time 43300115 ps
CPU time 0.73 seconds
Started Jul 10 05:57:26 PM PDT 24
Finished Jul 10 05:57:28 PM PDT 24
Peak memory 205728 kb
Host smart-d8ec3375-b345-4b61-a72a-120481b3c44a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616164530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.1
616164530
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.4103704043
Short name T661
Test name
Test status
Simulation time 3322604681 ps
CPU time 25.75 seconds
Started Jul 10 05:57:20 PM PDT 24
Finished Jul 10 05:57:46 PM PDT 24
Peak memory 224608 kb
Host smart-cac8132a-07fd-4a53-bfeb-58b719ed44ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103704043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.4103704043
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.3143089181
Short name T883
Test name
Test status
Simulation time 50019030 ps
CPU time 0.75 seconds
Started Jul 10 05:57:23 PM PDT 24
Finished Jul 10 05:57:24 PM PDT 24
Peak memory 205632 kb
Host smart-3e44cb9a-3509-4f1d-a136-53e5c395b254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143089181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.3143089181
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.4148667502
Short name T995
Test name
Test status
Simulation time 10025756122 ps
CPU time 78.36 seconds
Started Jul 10 05:57:26 PM PDT 24
Finished Jul 10 05:58:46 PM PDT 24
Peak memory 237804 kb
Host smart-5b82f0df-f07b-4d04-8693-a0c5365d270b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148667502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.4148667502
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.1970740370
Short name T808
Test name
Test status
Simulation time 71113401503 ps
CPU time 170.02 seconds
Started Jul 10 05:57:25 PM PDT 24
Finished Jul 10 06:00:16 PM PDT 24
Peak memory 232872 kb
Host smart-748a2408-fc89-4e92-8604-c5141d9f5600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970740370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.1970740370
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.222897329
Short name T41
Test name
Test status
Simulation time 21598111720 ps
CPU time 79.01 seconds
Started Jul 10 05:57:27 PM PDT 24
Finished Jul 10 05:58:48 PM PDT 24
Peak memory 253880 kb
Host smart-430e9920-821b-4ea0-81da-228484344c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222897329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle.
222897329
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.2893070921
Short name T860
Test name
Test status
Simulation time 739360008 ps
CPU time 7.03 seconds
Started Jul 10 05:57:20 PM PDT 24
Finished Jul 10 05:57:28 PM PDT 24
Peak memory 249100 kb
Host smart-8b6bb355-4a2c-4fd2-9cf2-b5bdf5b38806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893070921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.2893070921
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.94424004
Short name T1
Test name
Test status
Simulation time 3950448815 ps
CPU time 27.05 seconds
Started Jul 10 05:57:27 PM PDT 24
Finished Jul 10 05:57:56 PM PDT 24
Peak memory 240996 kb
Host smart-1ce53e3c-2ddc-436b-847d-46931124f670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94424004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds.94424004
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_intercept.2020600068
Short name T346
Test name
Test status
Simulation time 1003103182 ps
CPU time 4.48 seconds
Started Jul 10 05:57:19 PM PDT 24
Finished Jul 10 05:57:25 PM PDT 24
Peak memory 232636 kb
Host smart-7ac1e14e-fa68-4661-ab30-cbbd4ca5ce69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020600068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.2020600068
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.3890931796
Short name T542
Test name
Test status
Simulation time 3438349976 ps
CPU time 12.32 seconds
Started Jul 10 05:57:21 PM PDT 24
Finished Jul 10 05:57:34 PM PDT 24
Peak memory 240760 kb
Host smart-9b6c34b9-f221-48e9-b42d-d69b96a23a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890931796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.3890931796
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.2298943276
Short name T810
Test name
Test status
Simulation time 693686422 ps
CPU time 4.89 seconds
Started Jul 10 05:57:23 PM PDT 24
Finished Jul 10 05:57:28 PM PDT 24
Peak memory 235576 kb
Host smart-6b53998e-e592-4504-9798-150848cea779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298943276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.2298943276
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.2379757244
Short name T931
Test name
Test status
Simulation time 1057792723 ps
CPU time 8.18 seconds
Started Jul 10 05:57:21 PM PDT 24
Finished Jul 10 05:57:31 PM PDT 24
Peak memory 232628 kb
Host smart-e555d009-647c-40b8-8049-f609db62a4fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379757244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.2379757244
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.457465565
Short name T379
Test name
Test status
Simulation time 546642248 ps
CPU time 4.57 seconds
Started Jul 10 05:57:26 PM PDT 24
Finished Jul 10 05:57:32 PM PDT 24
Peak memory 222516 kb
Host smart-c98d9169-70c5-4fdf-bb67-a5349aa3a9d0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=457465565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_direc
t.457465565
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.2637638923
Short name T77
Test name
Test status
Simulation time 40682856 ps
CPU time 1.06 seconds
Started Jul 10 05:57:26 PM PDT 24
Finished Jul 10 05:57:29 PM PDT 24
Peak memory 235940 kb
Host smart-dd2a6dab-0dd8-4093-b374-4c7f0be5b0ca
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637638923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.2637638923
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.2437895110
Short name T283
Test name
Test status
Simulation time 43003432111 ps
CPU time 447.93 seconds
Started Jul 10 05:57:26 PM PDT 24
Finished Jul 10 06:04:56 PM PDT 24
Peak memory 266368 kb
Host smart-d145044b-6f62-4aee-bdfc-1b9168913d43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437895110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.2437895110
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.2832964379
Short name T949
Test name
Test status
Simulation time 15640807485 ps
CPU time 31.86 seconds
Started Jul 10 05:57:21 PM PDT 24
Finished Jul 10 05:57:54 PM PDT 24
Peak memory 216520 kb
Host smart-068dc4e9-4085-4997-8d83-fb210955f245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832964379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.2832964379
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.59813431
Short name T962
Test name
Test status
Simulation time 2158322771 ps
CPU time 10.75 seconds
Started Jul 10 05:57:21 PM PDT 24
Finished Jul 10 05:57:32 PM PDT 24
Peak memory 216228 kb
Host smart-d598cd15-fc90-46ca-8545-30d01472d50d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59813431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.59813431
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.3716846017
Short name T938
Test name
Test status
Simulation time 22117787 ps
CPU time 0.82 seconds
Started Jul 10 05:57:23 PM PDT 24
Finished Jul 10 05:57:25 PM PDT 24
Peak memory 205980 kb
Host smart-c8743364-ba5c-4086-8adc-dd04fa9e642e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716846017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.3716846017
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.4230943295
Short name T406
Test name
Test status
Simulation time 92927932 ps
CPU time 0.74 seconds
Started Jul 10 05:57:20 PM PDT 24
Finished Jul 10 05:57:22 PM PDT 24
Peak memory 205980 kb
Host smart-6897dca7-a508-4ffa-b5bb-c80956fda142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230943295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.4230943295
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.1965093076
Short name T923
Test name
Test status
Simulation time 1940597836 ps
CPU time 8.12 seconds
Started Jul 10 05:57:24 PM PDT 24
Finished Jul 10 05:57:34 PM PDT 24
Peak memory 232692 kb
Host smart-7f81bf5f-9918-4191-afc9-12de5592fc39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965093076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.1965093076
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.1185087278
Short name T567
Test name
Test status
Simulation time 20017285 ps
CPU time 0.73 seconds
Started Jul 10 05:57:31 PM PDT 24
Finished Jul 10 05:57:33 PM PDT 24
Peak memory 205556 kb
Host smart-b9fece3a-f93b-4616-9a37-a344882e86c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185087278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.1
185087278
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.3585870822
Short name T745
Test name
Test status
Simulation time 682169889 ps
CPU time 4.59 seconds
Started Jul 10 05:57:25 PM PDT 24
Finished Jul 10 05:57:31 PM PDT 24
Peak memory 232672 kb
Host smart-94b0b887-c4b0-49cc-b663-a1bff2192245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585870822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.3585870822
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.1857403078
Short name T1017
Test name
Test status
Simulation time 24707293 ps
CPU time 0.76 seconds
Started Jul 10 05:57:26 PM PDT 24
Finished Jul 10 05:57:28 PM PDT 24
Peak memory 205576 kb
Host smart-2a6e2786-505c-481e-b63e-aaa010310c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857403078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.1857403078
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.178606141
Short name T788
Test name
Test status
Simulation time 3732180641 ps
CPU time 25.95 seconds
Started Jul 10 05:57:31 PM PDT 24
Finished Jul 10 05:57:59 PM PDT 24
Peak memory 249812 kb
Host smart-0ea023e3-8e14-4555-a81c-445689caa255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178606141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.178606141
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.1506402490
Short name T701
Test name
Test status
Simulation time 2271925180 ps
CPU time 41.83 seconds
Started Jul 10 05:57:32 PM PDT 24
Finished Jul 10 05:58:15 PM PDT 24
Peak memory 240608 kb
Host smart-5791b103-5f45-4c3a-aeb0-5e5919ba5ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506402490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.1506402490
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.906484091
Short name T320
Test name
Test status
Simulation time 17373997169 ps
CPU time 66.15 seconds
Started Jul 10 05:57:27 PM PDT 24
Finished Jul 10 05:58:35 PM PDT 24
Peak memory 241192 kb
Host smart-d71d1994-56c4-4125-b2c6-cd41ec8a0858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906484091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.906484091
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.3841682458
Short name T460
Test name
Test status
Simulation time 22868506525 ps
CPU time 99.79 seconds
Started Jul 10 05:57:27 PM PDT 24
Finished Jul 10 05:59:08 PM PDT 24
Peak memory 240948 kb
Host smart-955f81f6-2e88-4ae1-8b2c-379578b94fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841682458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds
.3841682458
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_intercept.2539484925
Short name T366
Test name
Test status
Simulation time 312037589 ps
CPU time 4.46 seconds
Started Jul 10 05:57:33 PM PDT 24
Finished Jul 10 05:57:39 PM PDT 24
Peak memory 224436 kb
Host smart-13f8b300-bee2-4fcf-89ad-fd15a571614c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539484925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.2539484925
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.303580555
Short name T654
Test name
Test status
Simulation time 3518427709 ps
CPU time 34.06 seconds
Started Jul 10 05:57:28 PM PDT 24
Finished Jul 10 05:58:03 PM PDT 24
Peak memory 240816 kb
Host smart-b11aa226-0c53-45a2-af05-c2639576b3cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303580555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.303580555
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.1781483636
Short name T282
Test name
Test status
Simulation time 32087316 ps
CPU time 2.33 seconds
Started Jul 10 05:57:29 PM PDT 24
Finished Jul 10 05:57:32 PM PDT 24
Peak memory 224660 kb
Host smart-fb1b4242-b678-45e6-a2ff-25283cb4b6ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781483636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.1781483636
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.1662322340
Short name T622
Test name
Test status
Simulation time 23117477394 ps
CPU time 16.06 seconds
Started Jul 10 05:57:32 PM PDT 24
Finished Jul 10 05:57:49 PM PDT 24
Peak memory 232852 kb
Host smart-3d7d81f7-2e03-43bb-b1a9-99f053808130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662322340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.1662322340
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.3766609502
Short name T896
Test name
Test status
Simulation time 174615279 ps
CPU time 4.28 seconds
Started Jul 10 05:57:32 PM PDT 24
Finished Jul 10 05:57:38 PM PDT 24
Peak memory 223016 kb
Host smart-958381d1-8100-42dd-b5a8-319b840124f0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3766609502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.3766609502
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.965930168
Short name T74
Test name
Test status
Simulation time 273445546 ps
CPU time 1.07 seconds
Started Jul 10 05:57:30 PM PDT 24
Finished Jul 10 05:57:32 PM PDT 24
Peak memory 236544 kb
Host smart-97ab4d59-6d18-4cef-800f-fdc6f6fff632
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965930168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.965930168
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.1192376711
Short name T750
Test name
Test status
Simulation time 3157620519 ps
CPU time 21.38 seconds
Started Jul 10 05:57:33 PM PDT 24
Finished Jul 10 05:57:55 PM PDT 24
Peak memory 216320 kb
Host smart-13b333fe-d6b8-44e0-9340-480581553392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192376711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.1192376711
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.1989911553
Short name T385
Test name
Test status
Simulation time 39217542917 ps
CPU time 22.69 seconds
Started Jul 10 05:57:25 PM PDT 24
Finished Jul 10 05:57:49 PM PDT 24
Peak memory 217300 kb
Host smart-58e0361e-f167-4f78-96d8-6e505e39f74e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989911553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.1989911553
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.614578077
Short name T570
Test name
Test status
Simulation time 261767287 ps
CPU time 2.63 seconds
Started Jul 10 05:57:33 PM PDT 24
Finished Jul 10 05:57:37 PM PDT 24
Peak memory 216244 kb
Host smart-32bfba9f-4620-4eac-8ad4-3be948c31bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614578077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.614578077
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.3168301496
Short name T716
Test name
Test status
Simulation time 388818264 ps
CPU time 0.93 seconds
Started Jul 10 05:57:24 PM PDT 24
Finished Jul 10 05:57:25 PM PDT 24
Peak memory 206992 kb
Host smart-57590346-f492-4878-a0b0-574db962e531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168301496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.3168301496
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.420868020
Short name T753
Test name
Test status
Simulation time 292300158 ps
CPU time 3.49 seconds
Started Jul 10 05:57:27 PM PDT 24
Finished Jul 10 05:57:32 PM PDT 24
Peak memory 224420 kb
Host smart-a9270b24-c5f9-4980-bc27-779b3cb5e9a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420868020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.420868020
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.1687778797
Short name T851
Test name
Test status
Simulation time 24727777 ps
CPU time 0.72 seconds
Started Jul 10 05:58:24 PM PDT 24
Finished Jul 10 05:58:25 PM PDT 24
Peak memory 204980 kb
Host smart-ffe72c6d-7e4b-4714-8b54-ea332f1fbbee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687778797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
1687778797
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.549504536
Short name T852
Test name
Test status
Simulation time 317920887 ps
CPU time 5.85 seconds
Started Jul 10 05:58:15 PM PDT 24
Finished Jul 10 05:58:22 PM PDT 24
Peak memory 224412 kb
Host smart-c869a563-38db-416f-bab9-73b107999dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549504536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.549504536
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.2180495911
Short name T392
Test name
Test status
Simulation time 69235925 ps
CPU time 0.81 seconds
Started Jul 10 05:58:19 PM PDT 24
Finished Jul 10 05:58:21 PM PDT 24
Peak memory 206588 kb
Host smart-f5618acf-ab07-452d-b2a2-e7504a11a14d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180495911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.2180495911
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.2942502554
Short name T511
Test name
Test status
Simulation time 208154725017 ps
CPU time 90.27 seconds
Started Jul 10 05:58:17 PM PDT 24
Finished Jul 10 05:59:49 PM PDT 24
Peak memory 240996 kb
Host smart-45f9ad32-c1aa-4ada-8c66-c5490adbce7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942502554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.2942502554
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.1786563337
Short name T816
Test name
Test status
Simulation time 12252693838 ps
CPU time 27.35 seconds
Started Jul 10 05:58:21 PM PDT 24
Finished Jul 10 05:58:49 PM PDT 24
Peak memory 224668 kb
Host smart-6bf6fe30-a17d-492c-9241-4ab580991f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786563337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.1786563337
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.2370818924
Short name T347
Test name
Test status
Simulation time 3221812180 ps
CPU time 11.01 seconds
Started Jul 10 05:58:21 PM PDT 24
Finished Jul 10 05:58:33 PM PDT 24
Peak memory 232816 kb
Host smart-b82a8b3c-26ed-42d7-8cb6-55364b756f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370818924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.2370818924
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.2628338305
Short name T882
Test name
Test status
Simulation time 28922780118 ps
CPU time 71 seconds
Started Jul 10 05:58:17 PM PDT 24
Finished Jul 10 05:59:30 PM PDT 24
Peak memory 253920 kb
Host smart-8ddb0199-99f9-435c-9fd3-2cfec4acf6ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628338305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmd
s.2628338305
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.3038664154
Short name T475
Test name
Test status
Simulation time 498668636 ps
CPU time 2.44 seconds
Started Jul 10 05:58:19 PM PDT 24
Finished Jul 10 05:58:23 PM PDT 24
Peak memory 224432 kb
Host smart-59abaae7-7d7f-421e-b0a1-4d55998040cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038664154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.3038664154
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.3823097841
Short name T617
Test name
Test status
Simulation time 196620010 ps
CPU time 5.89 seconds
Started Jul 10 05:58:16 PM PDT 24
Finished Jul 10 05:58:25 PM PDT 24
Peak memory 232644 kb
Host smart-f167e317-647e-4662-b83c-8901ed57ee11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823097841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.3823097841
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.2957798432
Short name T401
Test name
Test status
Simulation time 751166143 ps
CPU time 4.12 seconds
Started Jul 10 05:58:17 PM PDT 24
Finished Jul 10 05:58:24 PM PDT 24
Peak memory 224412 kb
Host smart-9eee8c33-d93b-4bdf-89d5-a1973a9e4532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957798432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.2957798432
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.892854197
Short name T624
Test name
Test status
Simulation time 4250443137 ps
CPU time 7.55 seconds
Started Jul 10 05:58:18 PM PDT 24
Finished Jul 10 05:58:27 PM PDT 24
Peak memory 224592 kb
Host smart-62db0e5a-0b53-4420-ae5f-0fa768b3e2fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892854197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.892854197
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.1749017996
Short name T404
Test name
Test status
Simulation time 2271735074 ps
CPU time 8.24 seconds
Started Jul 10 05:58:21 PM PDT 24
Finished Jul 10 05:58:30 PM PDT 24
Peak memory 223152 kb
Host smart-a1131c15-8178-49c5-901f-3af2d3efeb83
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1749017996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.1749017996
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.3675783091
Short name T744
Test name
Test status
Simulation time 4178520795 ps
CPU time 22.27 seconds
Started Jul 10 05:58:16 PM PDT 24
Finished Jul 10 05:58:40 PM PDT 24
Peak memory 216340 kb
Host smart-1473955d-8a32-407b-8f34-fe296c4985dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675783091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.3675783091
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.2709840597
Short name T985
Test name
Test status
Simulation time 1456348629 ps
CPU time 2.86 seconds
Started Jul 10 05:58:17 PM PDT 24
Finished Jul 10 05:58:22 PM PDT 24
Peak memory 207896 kb
Host smart-c4979d75-d9b7-499e-9a4a-7dff6f0fd09a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709840597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.2709840597
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.3162432901
Short name T749
Test name
Test status
Simulation time 37030426 ps
CPU time 1.06 seconds
Started Jul 10 05:58:16 PM PDT 24
Finished Jul 10 05:58:19 PM PDT 24
Peak memory 206992 kb
Host smart-9f92e49d-a0cc-4431-9d93-c3eca59165c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162432901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.3162432901
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.857504923
Short name T342
Test name
Test status
Simulation time 66130771 ps
CPU time 0.88 seconds
Started Jul 10 05:58:16 PM PDT 24
Finished Jul 10 05:58:20 PM PDT 24
Peak memory 205984 kb
Host smart-6d206b6b-250d-4da6-8026-f6da9a5c87b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857504923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.857504923
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.395145372
Short name T780
Test name
Test status
Simulation time 662085060 ps
CPU time 6.27 seconds
Started Jul 10 05:58:21 PM PDT 24
Finished Jul 10 05:58:28 PM PDT 24
Peak memory 232764 kb
Host smart-3045b509-0667-4bab-a422-f2d03139d39c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395145372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.395145372
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.2753997558
Short name T448
Test name
Test status
Simulation time 11726633 ps
CPU time 0.74 seconds
Started Jul 10 05:58:31 PM PDT 24
Finished Jul 10 05:58:32 PM PDT 24
Peak memory 204964 kb
Host smart-d1dfa4fb-9863-48eb-9fc7-4cdcaff3e8ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753997558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
2753997558
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.2058758278
Short name T28
Test name
Test status
Simulation time 3954460270 ps
CPU time 50.35 seconds
Started Jul 10 05:58:26 PM PDT 24
Finished Jul 10 05:59:17 PM PDT 24
Peak memory 257004 kb
Host smart-24201ae3-1c79-4278-89fc-dc15d3f7d6dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058758278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.2058758278
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.1539796327
Short name T1009
Test name
Test status
Simulation time 1247571330 ps
CPU time 25.15 seconds
Started Jul 10 05:58:42 PM PDT 24
Finished Jul 10 05:59:10 PM PDT 24
Peak memory 232768 kb
Host smart-b2b974ab-48f1-493a-82b0-d16e60a784d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539796327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.1539796327
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.2876905511
Short name T278
Test name
Test status
Simulation time 3199916743 ps
CPU time 33.99 seconds
Started Jul 10 05:58:37 PM PDT 24
Finished Jul 10 05:59:13 PM PDT 24
Peak memory 241116 kb
Host smart-6e047215-d80e-47ff-b91f-d5e3af4d4faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876905511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.2876905511
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.793548478
Short name T739
Test name
Test status
Simulation time 12658248497 ps
CPU time 43.28 seconds
Started Jul 10 05:58:23 PM PDT 24
Finished Jul 10 05:59:07 PM PDT 24
Peak memory 241008 kb
Host smart-8724e481-e80f-460f-9ad2-04c665b7139d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793548478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.793548478
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.759142531
Short name T659
Test name
Test status
Simulation time 137134824559 ps
CPU time 216.2 seconds
Started Jul 10 05:58:23 PM PDT 24
Finished Jul 10 06:02:00 PM PDT 24
Peak memory 257360 kb
Host smart-ebf431a1-09df-4383-b114-2819bdacc90a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759142531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmds
.759142531
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.2242105228
Short name T989
Test name
Test status
Simulation time 350940974 ps
CPU time 4.41 seconds
Started Jul 10 05:58:25 PM PDT 24
Finished Jul 10 05:58:31 PM PDT 24
Peak memory 232676 kb
Host smart-3508ea19-8ade-4014-86db-833d3143ec8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242105228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.2242105228
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.1543886633
Short name T473
Test name
Test status
Simulation time 7269691560 ps
CPU time 40.25 seconds
Started Jul 10 05:58:22 PM PDT 24
Finished Jul 10 05:59:03 PM PDT 24
Peak memory 237920 kb
Host smart-e517465f-cf35-4e5e-b1b1-e314e54b5cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543886633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.1543886633
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.3012082283
Short name T279
Test name
Test status
Simulation time 312667687 ps
CPU time 2.99 seconds
Started Jul 10 05:58:24 PM PDT 24
Finished Jul 10 05:58:28 PM PDT 24
Peak memory 224388 kb
Host smart-8b437130-9fa3-4ab1-b3ac-cf1113d16f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012082283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.3012082283
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.755471111
Short name T407
Test name
Test status
Simulation time 1433040864 ps
CPU time 3.47 seconds
Started Jul 10 05:58:24 PM PDT 24
Finished Jul 10 05:58:29 PM PDT 24
Peak memory 232652 kb
Host smart-8b8e2deb-4462-430c-a7bb-666a73828b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755471111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.755471111
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.4199778590
Short name T382
Test name
Test status
Simulation time 667893363 ps
CPU time 8.52 seconds
Started Jul 10 05:58:25 PM PDT 24
Finished Jul 10 05:58:34 PM PDT 24
Peak memory 223056 kb
Host smart-fb1576e2-c588-4332-bed7-cde2431d86ac
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4199778590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.4199778590
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.3581658072
Short name T743
Test name
Test status
Simulation time 15892739676 ps
CPU time 137.22 seconds
Started Jul 10 05:58:32 PM PDT 24
Finished Jul 10 06:00:51 PM PDT 24
Peak memory 254816 kb
Host smart-c0ca4788-3b9d-46d5-aae5-aadb8318a8ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581658072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.3581658072
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.493221483
Short name T709
Test name
Test status
Simulation time 954563997 ps
CPU time 4.92 seconds
Started Jul 10 05:58:26 PM PDT 24
Finished Jul 10 05:58:32 PM PDT 24
Peak memory 216248 kb
Host smart-719bc802-b364-4fdc-97a1-e82a44da4514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493221483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.493221483
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.806768691
Short name T994
Test name
Test status
Simulation time 539802920 ps
CPU time 4.82 seconds
Started Jul 10 05:58:27 PM PDT 24
Finished Jul 10 05:58:32 PM PDT 24
Peak memory 216240 kb
Host smart-93d6af09-0599-474c-9438-458b9767574e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806768691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.806768691
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.2006505801
Short name T557
Test name
Test status
Simulation time 171670559 ps
CPU time 2.79 seconds
Started Jul 10 05:58:23 PM PDT 24
Finished Jul 10 05:58:26 PM PDT 24
Peak memory 216164 kb
Host smart-71edbe0e-08df-4ff8-b701-e303db5f5a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006505801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.2006505801
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.1747045182
Short name T673
Test name
Test status
Simulation time 27955773 ps
CPU time 0.77 seconds
Started Jul 10 05:58:27 PM PDT 24
Finished Jul 10 05:58:29 PM PDT 24
Peak memory 206164 kb
Host smart-d1ad2faf-7a81-48de-aafc-9a58a8d7c873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747045182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.1747045182
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.140677297
Short name T919
Test name
Test status
Simulation time 29637124010 ps
CPU time 30.64 seconds
Started Jul 10 05:58:26 PM PDT 24
Finished Jul 10 05:58:57 PM PDT 24
Peak memory 224568 kb
Host smart-bc02657e-96c7-41ce-8194-f2ca8d3fa45b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140677297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.140677297
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.2812284536
Short name T434
Test name
Test status
Simulation time 20462709 ps
CPU time 0.73 seconds
Started Jul 10 05:58:31 PM PDT 24
Finished Jul 10 05:58:33 PM PDT 24
Peak memory 205532 kb
Host smart-58e49ba2-1969-4f24-9633-6af96ba172ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812284536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
2812284536
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.1058336243
Short name T268
Test name
Test status
Simulation time 908825364 ps
CPU time 9.68 seconds
Started Jul 10 05:58:35 PM PDT 24
Finished Jul 10 05:58:45 PM PDT 24
Peak memory 224440 kb
Host smart-e382bcc3-9765-435d-b84b-338284fd8f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058336243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.1058336243
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.538087783
Short name T345
Test name
Test status
Simulation time 28658723 ps
CPU time 0.83 seconds
Started Jul 10 05:58:37 PM PDT 24
Finished Jul 10 05:58:39 PM PDT 24
Peak memory 206612 kb
Host smart-f7ed98e1-3026-4f9d-814f-e5cfcbf3ef3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538087783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.538087783
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.3616432837
Short name T500
Test name
Test status
Simulation time 12851610 ps
CPU time 0.78 seconds
Started Jul 10 05:58:35 PM PDT 24
Finished Jul 10 05:58:37 PM PDT 24
Peak memory 215772 kb
Host smart-16c5c41a-e749-4600-b270-097d26a76734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616432837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.3616432837
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.395678240
Short name T920
Test name
Test status
Simulation time 2122018886 ps
CPU time 34.61 seconds
Started Jul 10 05:58:35 PM PDT 24
Finished Jul 10 05:59:11 PM PDT 24
Peak memory 224560 kb
Host smart-ae39fe0c-3b88-46c5-bb8d-e3238f320b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395678240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.395678240
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.2779310157
Short name T760
Test name
Test status
Simulation time 10326312690 ps
CPU time 87.86 seconds
Started Jul 10 05:58:33 PM PDT 24
Finished Jul 10 06:00:01 PM PDT 24
Peak memory 249216 kb
Host smart-9f9cf920-aebe-4088-bd05-ac53fe253116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779310157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.2779310157
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.1930695317
Short name T438
Test name
Test status
Simulation time 319756004 ps
CPU time 8.2 seconds
Started Jul 10 05:58:35 PM PDT 24
Finished Jul 10 05:58:44 PM PDT 24
Peak memory 250312 kb
Host smart-af79d92b-a1f9-4ebf-a31f-72fd7c7a4bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930695317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.1930695317
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.2733655449
Short name T64
Test name
Test status
Simulation time 16675633027 ps
CPU time 112.91 seconds
Started Jul 10 05:58:41 PM PDT 24
Finished Jul 10 06:00:35 PM PDT 24
Peak memory 235848 kb
Host smart-d644e069-222a-48c2-bbe8-321047128af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733655449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmd
s.2733655449
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_intercept.1042048258
Short name T874
Test name
Test status
Simulation time 2043610961 ps
CPU time 6.7 seconds
Started Jul 10 05:58:36 PM PDT 24
Finished Jul 10 05:58:43 PM PDT 24
Peak memory 224424 kb
Host smart-eb32bfda-450c-47cc-b298-4850e3015500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042048258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.1042048258
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.2775590001
Short name T761
Test name
Test status
Simulation time 147216457 ps
CPU time 5.64 seconds
Started Jul 10 05:58:31 PM PDT 24
Finished Jul 10 05:58:38 PM PDT 24
Peak memory 239504 kb
Host smart-e8b5c71f-ffb0-4279-9f01-51426b15288d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775590001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.2775590001
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.1470577522
Short name T650
Test name
Test status
Simulation time 2637798950 ps
CPU time 10.8 seconds
Started Jul 10 05:58:33 PM PDT 24
Finished Jul 10 05:58:44 PM PDT 24
Peak memory 232752 kb
Host smart-b2537e63-575a-456a-9859-8b0bb65d263d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470577522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.1470577522
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.32946205
Short name T562
Test name
Test status
Simulation time 52540654 ps
CPU time 2.85 seconds
Started Jul 10 05:58:32 PM PDT 24
Finished Jul 10 05:58:36 PM PDT 24
Peak memory 232652 kb
Host smart-3fba49c3-755d-4c4b-bccd-dc6b98fc5b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32946205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.32946205
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.2768597322
Short name T980
Test name
Test status
Simulation time 404755601 ps
CPU time 4.12 seconds
Started Jul 10 05:58:36 PM PDT 24
Finished Jul 10 05:58:41 PM PDT 24
Peak memory 222584 kb
Host smart-512ec37d-322c-4b5b-8fe8-fe0ef8f3b7d9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2768597322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.2768597322
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.1520433576
Short name T929
Test name
Test status
Simulation time 22151685621 ps
CPU time 86.09 seconds
Started Jul 10 05:58:37 PM PDT 24
Finished Jul 10 06:00:04 PM PDT 24
Peak memory 269460 kb
Host smart-38563ee5-d8ff-4195-a59e-ebcf38bb0c2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520433576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.1520433576
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.3734427937
Short name T775
Test name
Test status
Simulation time 336149980 ps
CPU time 2.06 seconds
Started Jul 10 05:58:32 PM PDT 24
Finished Jul 10 05:58:35 PM PDT 24
Peak memory 216248 kb
Host smart-ca0531df-5adc-4a4f-bec0-370d9a882e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734427937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.3734427937
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.2785088576
Short name T405
Test name
Test status
Simulation time 7136173885 ps
CPU time 20.75 seconds
Started Jul 10 05:58:32 PM PDT 24
Finished Jul 10 05:58:53 PM PDT 24
Peak memory 216332 kb
Host smart-c39a7c99-32dd-4863-b48d-ce1da2a4087f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785088576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.2785088576
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.708082313
Short name T359
Test name
Test status
Simulation time 48861948 ps
CPU time 0.76 seconds
Started Jul 10 05:58:31 PM PDT 24
Finished Jul 10 05:58:33 PM PDT 24
Peak memory 205988 kb
Host smart-c9c7d4ad-2513-4fad-8f0b-344407e76020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708082313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.708082313
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.1744485962
Short name T765
Test name
Test status
Simulation time 170358196 ps
CPU time 0.8 seconds
Started Jul 10 05:58:32 PM PDT 24
Finished Jul 10 05:58:34 PM PDT 24
Peak memory 205980 kb
Host smart-600b4d1b-a513-4d8a-b9d7-6d71b596d2c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744485962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.1744485962
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.1941573697
Short name T604
Test name
Test status
Simulation time 1141142517 ps
CPU time 2.59 seconds
Started Jul 10 05:58:32 PM PDT 24
Finished Jul 10 05:58:35 PM PDT 24
Peak memory 224436 kb
Host smart-e5b9052d-7ddb-4a2f-9eb7-585cfb277e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941573697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.1941573697
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.674793471
Short name T517
Test name
Test status
Simulation time 37088681 ps
CPU time 0.76 seconds
Started Jul 10 05:58:39 PM PDT 24
Finished Jul 10 05:58:41 PM PDT 24
Peak memory 204972 kb
Host smart-fae5f9f9-3a48-42d3-864b-8a9cbddb9f5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674793471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.674793471
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.2372737965
Short name T767
Test name
Test status
Simulation time 1294993871 ps
CPU time 3.81 seconds
Started Jul 10 05:58:38 PM PDT 24
Finished Jul 10 05:58:43 PM PDT 24
Peak memory 232684 kb
Host smart-f7ccf3fe-9cb0-4a3d-98d5-0651247b4c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372737965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.2372737965
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.767291378
Short name T502
Test name
Test status
Simulation time 24509506 ps
CPU time 0.85 seconds
Started Jul 10 05:58:32 PM PDT 24
Finished Jul 10 05:58:34 PM PDT 24
Peak memory 206796 kb
Host smart-6466a51e-be74-48d1-b0f5-e6aee8cb2685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767291378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.767291378
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.4010634103
Short name T799
Test name
Test status
Simulation time 11393549439 ps
CPU time 52.59 seconds
Started Jul 10 05:58:40 PM PDT 24
Finished Jul 10 05:59:34 PM PDT 24
Peak memory 249212 kb
Host smart-e400e1ef-c250-4f02-9d83-66e42b9a503c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010634103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.4010634103
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.3039692101
Short name T53
Test name
Test status
Simulation time 57681534591 ps
CPU time 287.61 seconds
Started Jul 10 05:58:42 PM PDT 24
Finished Jul 10 06:03:32 PM PDT 24
Peak memory 251168 kb
Host smart-f6942a44-72bf-47fa-8dfa-13b424d491ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039692101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.3039692101
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.800305336
Short name T924
Test name
Test status
Simulation time 701854643 ps
CPU time 3.3 seconds
Started Jul 10 05:58:37 PM PDT 24
Finished Jul 10 05:58:41 PM PDT 24
Peak memory 224488 kb
Host smart-59e965bc-b280-495c-b62b-320efffe6e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800305336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.800305336
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.231189377
Short name T545
Test name
Test status
Simulation time 134102877156 ps
CPU time 215.78 seconds
Started Jul 10 05:58:42 PM PDT 24
Finished Jul 10 06:02:20 PM PDT 24
Peak memory 251192 kb
Host smart-c2414d67-43d8-4334-997f-776ec14f6eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231189377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmds
.231189377
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_intercept.2118905525
Short name T201
Test name
Test status
Simulation time 4343149995 ps
CPU time 21.77 seconds
Started Jul 10 05:58:37 PM PDT 24
Finished Jul 10 05:58:59 PM PDT 24
Peak memory 224608 kb
Host smart-55a8bf13-9edc-494f-8e2c-423dd01466ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118905525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.2118905525
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.1497120545
Short name T679
Test name
Test status
Simulation time 3957774838 ps
CPU time 11.48 seconds
Started Jul 10 05:58:38 PM PDT 24
Finished Jul 10 05:58:50 PM PDT 24
Peak memory 232740 kb
Host smart-8c76f77c-4bff-43c8-8bc8-5fe31efe4ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497120545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.1497120545
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.1054825125
Short name T284
Test name
Test status
Simulation time 8753833530 ps
CPU time 9.44 seconds
Started Jul 10 05:58:42 PM PDT 24
Finished Jul 10 05:58:54 PM PDT 24
Peak memory 240540 kb
Host smart-a663c865-6d7e-412e-b352-9d92cd6529f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054825125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.1054825125
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.3712257215
Short name T778
Test name
Test status
Simulation time 2044449952 ps
CPU time 9.7 seconds
Started Jul 10 05:58:42 PM PDT 24
Finished Jul 10 05:58:54 PM PDT 24
Peak memory 224504 kb
Host smart-7f5fc622-ace5-4a93-89cc-26b4ad97ddad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712257215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.3712257215
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.3621510886
Short name T490
Test name
Test status
Simulation time 3587258562 ps
CPU time 10.96 seconds
Started Jul 10 05:58:42 PM PDT 24
Finished Jul 10 05:58:56 PM PDT 24
Peak memory 218812 kb
Host smart-083fea17-a24b-4348-b5c3-201e576cb456
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3621510886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.3621510886
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.54183740
Short name T861
Test name
Test status
Simulation time 374339002 ps
CPU time 3.29 seconds
Started Jul 10 05:58:39 PM PDT 24
Finished Jul 10 05:58:44 PM PDT 24
Peak memory 216180 kb
Host smart-1c31bbf8-3649-4260-bdd1-6bf498e0e8a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54183740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.54183740
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.2862494219
Short name T974
Test name
Test status
Simulation time 845703957 ps
CPU time 2.75 seconds
Started Jul 10 05:58:37 PM PDT 24
Finished Jul 10 05:58:41 PM PDT 24
Peak memory 216208 kb
Host smart-919f93af-43af-459a-af5f-7421c0889bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862494219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.2862494219
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.710309250
Short name T354
Test name
Test status
Simulation time 283404471 ps
CPU time 1.6 seconds
Started Jul 10 05:58:35 PM PDT 24
Finished Jul 10 05:58:37 PM PDT 24
Peak memory 216172 kb
Host smart-a18919a4-d05f-46c8-a3c2-357283a56e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710309250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.710309250
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.1343788783
Short name T352
Test name
Test status
Simulation time 15761371 ps
CPU time 0.72 seconds
Started Jul 10 05:58:42 PM PDT 24
Finished Jul 10 05:58:46 PM PDT 24
Peak memory 205972 kb
Host smart-92bf4c66-4c34-4037-8797-40222dcb671c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343788783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.1343788783
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.2889656206
Short name T707
Test name
Test status
Simulation time 423719077 ps
CPU time 6.1 seconds
Started Jul 10 05:58:33 PM PDT 24
Finished Jul 10 05:58:40 PM PDT 24
Peak memory 232692 kb
Host smart-1e724a59-11b8-41a4-96a3-c3b66dea2350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889656206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.2889656206
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.1894248509
Short name T952
Test name
Test status
Simulation time 41742878 ps
CPU time 0.68 seconds
Started Jul 10 05:58:42 PM PDT 24
Finished Jul 10 05:58:45 PM PDT 24
Peak memory 205872 kb
Host smart-e2459280-9506-4f66-a042-82b8abe5ee45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894248509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
1894248509
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.4065132152
Short name T953
Test name
Test status
Simulation time 1598519076 ps
CPU time 4.65 seconds
Started Jul 10 05:58:38 PM PDT 24
Finished Jul 10 05:58:44 PM PDT 24
Peak memory 224516 kb
Host smart-455d609d-d800-497a-9e9e-afcbb61ad468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065132152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.4065132152
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.1148518284
Short name T738
Test name
Test status
Simulation time 16023975 ps
CPU time 0.8 seconds
Started Jul 10 05:58:43 PM PDT 24
Finished Jul 10 05:58:47 PM PDT 24
Peak memory 205556 kb
Host smart-5246addf-e876-444a-aee8-3db21e0164af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148518284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.1148518284
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.1216865892
Short name T697
Test name
Test status
Simulation time 15003353772 ps
CPU time 102.83 seconds
Started Jul 10 05:58:44 PM PDT 24
Finished Jul 10 06:00:29 PM PDT 24
Peak memory 256056 kb
Host smart-f500f17f-24b5-426a-84ec-998338f86fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216865892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.1216865892
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.1245126197
Short name T237
Test name
Test status
Simulation time 9190763880 ps
CPU time 55.93 seconds
Started Jul 10 05:58:43 PM PDT 24
Finished Jul 10 05:59:42 PM PDT 24
Peak memory 237224 kb
Host smart-72067071-80c3-43af-b99c-d687099bf35f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245126197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.1245126197
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.190849623
Short name T445
Test name
Test status
Simulation time 60663575 ps
CPU time 3.65 seconds
Started Jul 10 05:58:42 PM PDT 24
Finished Jul 10 05:58:47 PM PDT 24
Peak memory 224492 kb
Host smart-b85482fa-62f6-4735-834d-fc5301f5cc35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190849623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.190849623
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_intercept.3431319917
Short name T492
Test name
Test status
Simulation time 91525316 ps
CPU time 2.74 seconds
Started Jul 10 05:58:40 PM PDT 24
Finished Jul 10 05:58:44 PM PDT 24
Peak memory 224456 kb
Host smart-c19f1165-2b1b-4e11-b99f-3fdedc7382ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431319917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.3431319917
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.1129237102
Short name T805
Test name
Test status
Simulation time 4162309270 ps
CPU time 4.23 seconds
Started Jul 10 05:58:41 PM PDT 24
Finished Jul 10 05:58:47 PM PDT 24
Peak memory 224544 kb
Host smart-97bf26ee-303e-416c-9cdf-fb2479714a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129237102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.1129237102
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.3604611036
Short name T911
Test name
Test status
Simulation time 58479099 ps
CPU time 2.52 seconds
Started Jul 10 05:58:37 PM PDT 24
Finished Jul 10 05:58:41 PM PDT 24
Peak memory 232364 kb
Host smart-fc75f204-973c-4f7e-9266-c97ea86424cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604611036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.3604611036
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.2257252470
Short name T913
Test name
Test status
Simulation time 28111063492 ps
CPU time 9.05 seconds
Started Jul 10 05:58:39 PM PDT 24
Finished Jul 10 05:58:49 PM PDT 24
Peak memory 224628 kb
Host smart-bfe1ce67-ea2b-4151-a759-5d88597bb97e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257252470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.2257252470
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.3242312843
Short name T486
Test name
Test status
Simulation time 2208350141 ps
CPU time 10.79 seconds
Started Jul 10 05:58:43 PM PDT 24
Finished Jul 10 05:58:56 PM PDT 24
Peak memory 223228 kb
Host smart-96870217-1d68-45b7-99ca-6c9ff2ecf04f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3242312843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.3242312843
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.3892966074
Short name T166
Test name
Test status
Simulation time 6342951137 ps
CPU time 105.16 seconds
Started Jul 10 05:58:43 PM PDT 24
Finished Jul 10 06:00:31 PM PDT 24
Peak memory 255568 kb
Host smart-a4f50e2d-54ab-4eb5-8beb-9ac3f744781f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892966074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.3892966074
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.537649627
Short name T704
Test name
Test status
Simulation time 4836826499 ps
CPU time 8.8 seconds
Started Jul 10 05:58:42 PM PDT 24
Finished Jul 10 05:58:53 PM PDT 24
Peak memory 219800 kb
Host smart-181cd406-bba3-4816-aa92-805d34bc0f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537649627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.537649627
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.1096325317
Short name T889
Test name
Test status
Simulation time 4913089727 ps
CPU time 5.08 seconds
Started Jul 10 05:58:42 PM PDT 24
Finished Jul 10 05:58:49 PM PDT 24
Peak memory 216312 kb
Host smart-d0b6a02b-f881-40de-a688-0997921a89aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096325317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.1096325317
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.767452063
Short name T529
Test name
Test status
Simulation time 105923067 ps
CPU time 2.35 seconds
Started Jul 10 05:58:38 PM PDT 24
Finished Jul 10 05:58:41 PM PDT 24
Peak memory 216172 kb
Host smart-ef517f1b-de3c-4d2c-8512-f6584bcb77e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767452063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.767452063
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.449410937
Short name T561
Test name
Test status
Simulation time 56413057 ps
CPU time 0.86 seconds
Started Jul 10 05:58:41 PM PDT 24
Finished Jul 10 05:58:44 PM PDT 24
Peak memory 205976 kb
Host smart-46081927-cddc-40d5-90f4-1dbc2944d45f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449410937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.449410937
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.2202073208
Short name T1013
Test name
Test status
Simulation time 4230417612 ps
CPU time 14.1 seconds
Started Jul 10 05:58:43 PM PDT 24
Finished Jul 10 05:59:00 PM PDT 24
Peak memory 224612 kb
Host smart-ae88b189-7280-45a6-8a59-2f20d794a322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202073208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.2202073208
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.2980857359
Short name T628
Test name
Test status
Simulation time 31918077 ps
CPU time 0.75 seconds
Started Jul 10 05:58:45 PM PDT 24
Finished Jul 10 05:58:48 PM PDT 24
Peak memory 205556 kb
Host smart-9e9dacf4-8fda-4ff6-aa1c-19f97f426435
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980857359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
2980857359
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.1659879822
Short name T553
Test name
Test status
Simulation time 909526929 ps
CPU time 3.63 seconds
Started Jul 10 05:58:40 PM PDT 24
Finished Jul 10 05:58:45 PM PDT 24
Peak memory 224504 kb
Host smart-5233eb42-79e6-4825-8990-de87dac258b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659879822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.1659879822
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.216765428
Short name T843
Test name
Test status
Simulation time 59225143 ps
CPU time 0.84 seconds
Started Jul 10 05:58:43 PM PDT 24
Finished Jul 10 05:58:47 PM PDT 24
Peak memory 206792 kb
Host smart-8cc27d9f-9523-41fa-ab27-47b3429fb39f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216765428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.216765428
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.3509622061
Short name T1012
Test name
Test status
Simulation time 10266215192 ps
CPU time 23.54 seconds
Started Jul 10 05:58:43 PM PDT 24
Finished Jul 10 05:59:10 PM PDT 24
Peak memory 234296 kb
Host smart-98a2eee0-8fda-4be2-b005-deb85558650a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509622061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.3509622061
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.1472662460
Short name T598
Test name
Test status
Simulation time 5492122983 ps
CPU time 49.31 seconds
Started Jul 10 05:58:44 PM PDT 24
Finished Jul 10 05:59:36 PM PDT 24
Peak memory 232856 kb
Host smart-650c552e-13a2-49fb-93ab-b226428703b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472662460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.1472662460
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.2829425481
Short name T325
Test name
Test status
Simulation time 1394179752 ps
CPU time 7.41 seconds
Started Jul 10 05:58:43 PM PDT 24
Finished Jul 10 05:58:54 PM PDT 24
Peak memory 240892 kb
Host smart-31d8ba63-47dc-44ce-a641-110d7c72c210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829425481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.2829425481
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.2671503294
Short name T569
Test name
Test status
Simulation time 16415717991 ps
CPU time 58.69 seconds
Started Jul 10 05:58:42 PM PDT 24
Finished Jul 10 05:59:44 PM PDT 24
Peak memory 249404 kb
Host smart-49c76795-bc66-4c52-9198-1d95480eaafc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671503294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmd
s.2671503294
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.3012199685
Short name T690
Test name
Test status
Simulation time 836979496 ps
CPU time 4.56 seconds
Started Jul 10 05:58:43 PM PDT 24
Finished Jul 10 05:58:51 PM PDT 24
Peak memory 232628 kb
Host smart-1571ef55-2cee-4857-91ec-a902d83cd2c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012199685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.3012199685
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.3763766724
Short name T245
Test name
Test status
Simulation time 696915745 ps
CPU time 15.36 seconds
Started Jul 10 05:58:42 PM PDT 24
Finished Jul 10 05:59:00 PM PDT 24
Peak memory 249108 kb
Host smart-15633f5b-f431-4814-9861-063c93bcbc9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763766724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.3763766724
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.1065020644
Short name T812
Test name
Test status
Simulation time 1306506793 ps
CPU time 6.8 seconds
Started Jul 10 05:58:44 PM PDT 24
Finished Jul 10 05:58:53 PM PDT 24
Peak memory 232588 kb
Host smart-16174207-eaf5-4001-9e86-0ceb4de5c38e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065020644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.1065020644
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.4276522822
Short name T733
Test name
Test status
Simulation time 1060065967 ps
CPU time 9.03 seconds
Started Jul 10 05:58:45 PM PDT 24
Finished Jul 10 05:58:56 PM PDT 24
Peak memory 232724 kb
Host smart-946fd638-55f5-46c1-a9c7-11050bb631f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276522822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.4276522822
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.1302596009
Short name T731
Test name
Test status
Simulation time 198557333 ps
CPU time 3.83 seconds
Started Jul 10 05:58:45 PM PDT 24
Finished Jul 10 05:58:51 PM PDT 24
Peak memory 219288 kb
Host smart-773f7d43-8848-43f6-9a45-1b39751a3129
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1302596009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.1302596009
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.3710905101
Short name T934
Test name
Test status
Simulation time 14396324133 ps
CPU time 43.79 seconds
Started Jul 10 05:58:45 PM PDT 24
Finished Jul 10 05:59:31 PM PDT 24
Peak memory 241100 kb
Host smart-0b379675-72a3-4a43-9ae2-17724ce92e87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710905101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.3710905101
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.1721058349
Short name T504
Test name
Test status
Simulation time 6778427746 ps
CPU time 36.96 seconds
Started Jul 10 05:58:44 PM PDT 24
Finished Jul 10 05:59:24 PM PDT 24
Peak memory 216364 kb
Host smart-ffca13dd-018a-4c70-94b3-f482a1c3465c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721058349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.1721058349
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.2762524363
Short name T416
Test name
Test status
Simulation time 18170225957 ps
CPU time 5.72 seconds
Started Jul 10 05:58:42 PM PDT 24
Finished Jul 10 05:58:49 PM PDT 24
Peak memory 216464 kb
Host smart-e91acce7-e7c8-4c63-8d75-820223b0cc4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762524363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.2762524363
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.1270533638
Short name T769
Test name
Test status
Simulation time 175778195 ps
CPU time 2.19 seconds
Started Jul 10 05:58:44 PM PDT 24
Finished Jul 10 05:58:49 PM PDT 24
Peak memory 216252 kb
Host smart-b1d1082c-2dfb-4284-a635-329a3bb047fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270533638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.1270533638
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.2071614773
Short name T900
Test name
Test status
Simulation time 73727436 ps
CPU time 0.78 seconds
Started Jul 10 05:58:41 PM PDT 24
Finished Jul 10 05:58:43 PM PDT 24
Peak memory 205976 kb
Host smart-2d4c9e30-bbb1-4306-b55d-44b610bc2a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071614773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.2071614773
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.3502459747
Short name T850
Test name
Test status
Simulation time 3214625719 ps
CPU time 16.34 seconds
Started Jul 10 05:58:41 PM PDT 24
Finished Jul 10 05:58:59 PM PDT 24
Peak memory 232756 kb
Host smart-077a6f77-41d6-438d-91c7-a6585b088183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502459747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.3502459747
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.1643990199
Short name T811
Test name
Test status
Simulation time 40859853 ps
CPU time 0.78 seconds
Started Jul 10 05:58:58 PM PDT 24
Finished Jul 10 05:59:01 PM PDT 24
Peak memory 205512 kb
Host smart-f7e28f08-b35d-496e-b27b-7ad876397699
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643990199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
1643990199
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.2375921496
Short name T251
Test name
Test status
Simulation time 138018667 ps
CPU time 2.93 seconds
Started Jul 10 05:58:51 PM PDT 24
Finished Jul 10 05:58:54 PM PDT 24
Peak memory 224452 kb
Host smart-4576c980-4bc3-4d2a-be96-54ba39891813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375921496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.2375921496
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.413402749
Short name T510
Test name
Test status
Simulation time 39820463 ps
CPU time 0.77 seconds
Started Jul 10 05:58:47 PM PDT 24
Finished Jul 10 05:58:49 PM PDT 24
Peak memory 206596 kb
Host smart-ce890283-4c03-4490-8624-f83e0885ecc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413402749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.413402749
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.2246480604
Short name T280
Test name
Test status
Simulation time 9584643396 ps
CPU time 82.59 seconds
Started Jul 10 05:58:57 PM PDT 24
Finished Jul 10 06:00:21 PM PDT 24
Peak memory 252496 kb
Host smart-16778940-4664-456e-84a9-7ed0c1652c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246480604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.2246480604
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.1774935815
Short name T307
Test name
Test status
Simulation time 9144455068 ps
CPU time 64.72 seconds
Started Jul 10 05:58:52 PM PDT 24
Finished Jul 10 05:59:57 PM PDT 24
Peak memory 255932 kb
Host smart-1c98b93c-f0d9-4e5d-b070-3755026fe36b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774935815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.1774935815
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.177827523
Short name T946
Test name
Test status
Simulation time 78214612263 ps
CPU time 175.56 seconds
Started Jul 10 05:58:53 PM PDT 24
Finished Jul 10 06:01:50 PM PDT 24
Peak memory 249280 kb
Host smart-8b05066e-df86-41c3-9221-801865077ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177827523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idle
.177827523
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.2790917614
Short name T150
Test name
Test status
Simulation time 2769280118 ps
CPU time 12.08 seconds
Started Jul 10 05:58:56 PM PDT 24
Finished Jul 10 05:59:08 PM PDT 24
Peak memory 232752 kb
Host smart-710c2ba6-d7f5-442f-9ad1-810c08f324ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790917614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.2790917614
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.120376454
Short name T942
Test name
Test status
Simulation time 1906650218 ps
CPU time 17.02 seconds
Started Jul 10 05:58:52 PM PDT 24
Finished Jul 10 05:59:10 PM PDT 24
Peak memory 224504 kb
Host smart-ce63eebc-b58e-453e-9272-2fad3109d9d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120376454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmds
.120376454
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.3764274651
Short name T627
Test name
Test status
Simulation time 2163422437 ps
CPU time 7.74 seconds
Started Jul 10 05:58:45 PM PDT 24
Finished Jul 10 05:58:55 PM PDT 24
Peak memory 232708 kb
Host smart-e1bb68da-29c5-4a1f-a79c-ab9990a54187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764274651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.3764274651
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.734817074
Short name T471
Test name
Test status
Simulation time 3235688321 ps
CPU time 15.83 seconds
Started Jul 10 05:58:52 PM PDT 24
Finished Jul 10 05:59:09 PM PDT 24
Peak memory 224624 kb
Host smart-31e483f7-3f23-4dc1-8bcc-a8cb6b2355e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734817074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.734817074
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.891919861
Short name T281
Test name
Test status
Simulation time 819216054 ps
CPU time 3.36 seconds
Started Jul 10 05:58:45 PM PDT 24
Finished Jul 10 05:58:51 PM PDT 24
Peak memory 227444 kb
Host smart-66d1c066-16b2-4459-a568-7af041a4e99c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891919861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swap
.891919861
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.417888692
Short name T541
Test name
Test status
Simulation time 39070372161 ps
CPU time 30.02 seconds
Started Jul 10 05:58:49 PM PDT 24
Finished Jul 10 05:59:20 PM PDT 24
Peak memory 224612 kb
Host smart-f92b8652-5626-46aa-9fc1-cf58e9497aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417888692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.417888692
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.3888089562
Short name T735
Test name
Test status
Simulation time 182657137 ps
CPU time 4.19 seconds
Started Jul 10 05:58:53 PM PDT 24
Finished Jul 10 05:58:58 PM PDT 24
Peak memory 219492 kb
Host smart-eb35d700-328f-4eb7-8a0b-79aded16c4ba
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3888089562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.3888089562
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.2154994515
Short name T221
Test name
Test status
Simulation time 960319269540 ps
CPU time 635.6 seconds
Started Jul 10 05:58:53 PM PDT 24
Finished Jul 10 06:09:30 PM PDT 24
Peak memory 263936 kb
Host smart-8960782b-b0cc-413e-b196-e5d5894442bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154994515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.2154994515
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.361059551
Short name T968
Test name
Test status
Simulation time 290069962 ps
CPU time 2.94 seconds
Started Jul 10 05:58:46 PM PDT 24
Finished Jul 10 05:58:50 PM PDT 24
Peak memory 216316 kb
Host smart-5f83d692-3b53-4672-8a4c-400726d9fb34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361059551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.361059551
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.1105267638
Short name T951
Test name
Test status
Simulation time 2213566001 ps
CPU time 10.95 seconds
Started Jul 10 05:58:45 PM PDT 24
Finished Jul 10 05:58:58 PM PDT 24
Peak memory 216316 kb
Host smart-0fc6a2d6-1bba-48ff-9fc0-3ef2a28d6f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105267638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.1105267638
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.423559652
Short name T960
Test name
Test status
Simulation time 175997240 ps
CPU time 1 seconds
Started Jul 10 05:58:46 PM PDT 24
Finished Jul 10 05:58:49 PM PDT 24
Peak memory 206876 kb
Host smart-a8d02c34-9b32-470f-808b-5c8c18a45cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423559652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.423559652
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.318722546
Short name T670
Test name
Test status
Simulation time 44687041 ps
CPU time 0.83 seconds
Started Jul 10 05:58:48 PM PDT 24
Finished Jul 10 05:58:49 PM PDT 24
Peak memory 205976 kb
Host smart-666f2fd8-c185-4e0b-8332-791b9c185e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318722546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.318722546
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.1727715738
Short name T872
Test name
Test status
Simulation time 6405571125 ps
CPU time 9.15 seconds
Started Jul 10 05:58:57 PM PDT 24
Finished Jul 10 05:59:08 PM PDT 24
Peak memory 229572 kb
Host smart-f38674a9-7523-44b0-9a1d-36cdbaa75c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727715738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.1727715738
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.1930267364
Short name T577
Test name
Test status
Simulation time 14494471 ps
CPU time 0.73 seconds
Started Jul 10 05:58:59 PM PDT 24
Finished Jul 10 05:59:02 PM PDT 24
Peak memory 204976 kb
Host smart-9fd16415-6d30-4a43-9846-cb188519e03e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930267364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
1930267364
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.3183172812
Short name T549
Test name
Test status
Simulation time 66244401 ps
CPU time 2.59 seconds
Started Jul 10 05:58:57 PM PDT 24
Finished Jul 10 05:59:00 PM PDT 24
Peak memory 232668 kb
Host smart-075d505c-441a-4155-a886-e49324bdec56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183172812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.3183172812
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.1973282813
Short name T768
Test name
Test status
Simulation time 16567973 ps
CPU time 0.79 seconds
Started Jul 10 05:58:52 PM PDT 24
Finished Jul 10 05:58:53 PM PDT 24
Peak memory 206608 kb
Host smart-50c868bd-25e4-480a-a1c5-aada1165657a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973282813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.1973282813
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.3109902390
Short name T524
Test name
Test status
Simulation time 67067214709 ps
CPU time 83.24 seconds
Started Jul 10 05:58:58 PM PDT 24
Finished Jul 10 06:00:23 PM PDT 24
Peak memory 249204 kb
Host smart-cf967165-41b0-4d15-bbc3-88584045fcae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109902390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.3109902390
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.1486019349
Short name T369
Test name
Test status
Simulation time 1377462993 ps
CPU time 8.92 seconds
Started Jul 10 05:58:58 PM PDT 24
Finished Jul 10 05:59:09 PM PDT 24
Peak memory 224356 kb
Host smart-921eaf7e-eacc-4a51-a1ab-2e6517b66fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486019349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.1486019349
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.3738764356
Short name T133
Test name
Test status
Simulation time 9378666932 ps
CPU time 56.22 seconds
Started Jul 10 05:58:58 PM PDT 24
Finished Jul 10 05:59:57 PM PDT 24
Peak memory 249680 kb
Host smart-9de50be9-2888-4a85-941c-fc5f624a169b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738764356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.3738764356
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.116622053
Short name T322
Test name
Test status
Simulation time 329977481 ps
CPU time 8.69 seconds
Started Jul 10 05:58:58 PM PDT 24
Finished Jul 10 05:59:09 PM PDT 24
Peak memory 233728 kb
Host smart-0ebcafaf-f950-406a-81a0-f39a7f13b3f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116622053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.116622053
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.1097273246
Short name T240
Test name
Test status
Simulation time 31701295544 ps
CPU time 97.99 seconds
Started Jul 10 05:58:51 PM PDT 24
Finished Jul 10 06:00:30 PM PDT 24
Peak memory 249216 kb
Host smart-e0f9c197-7f00-4d34-a4a5-2c924d7ff4ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097273246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmd
s.1097273246
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_intercept.1256545860
Short name T584
Test name
Test status
Simulation time 337019014 ps
CPU time 2.92 seconds
Started Jul 10 05:58:53 PM PDT 24
Finished Jul 10 05:58:57 PM PDT 24
Peak memory 232680 kb
Host smart-ce2413e4-aa6d-4981-b500-0426eeca94ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256545860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.1256545860
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.1560940680
Short name T981
Test name
Test status
Simulation time 29200809114 ps
CPU time 43.23 seconds
Started Jul 10 05:58:57 PM PDT 24
Finished Jul 10 05:59:43 PM PDT 24
Peak memory 232760 kb
Host smart-8a926db4-59ef-4bcf-8397-7f42ca1000fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560940680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.1560940680
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.530220282
Short name T285
Test name
Test status
Simulation time 1670072731 ps
CPU time 9.22 seconds
Started Jul 10 05:58:52 PM PDT 24
Finished Jul 10 05:59:02 PM PDT 24
Peak memory 232676 kb
Host smart-70c1d5ac-6aee-4dcb-9e54-3d395d26eb8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530220282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swap
.530220282
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.1315936010
Short name T269
Test name
Test status
Simulation time 12661661721 ps
CPU time 9.48 seconds
Started Jul 10 05:58:56 PM PDT 24
Finished Jul 10 05:59:06 PM PDT 24
Peak memory 232772 kb
Host smart-4390d3ac-322f-4b62-9242-dfee076b8e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315936010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.1315936010
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.800666075
Short name T734
Test name
Test status
Simulation time 1595904380 ps
CPU time 5.67 seconds
Started Jul 10 05:58:52 PM PDT 24
Finished Jul 10 05:58:59 PM PDT 24
Peak memory 222564 kb
Host smart-e7e747fa-111f-4c1c-98d5-0565afcece3e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=800666075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dire
ct.800666075
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.2867178217
Short name T908
Test name
Test status
Simulation time 76151394 ps
CPU time 1 seconds
Started Jul 10 05:58:57 PM PDT 24
Finished Jul 10 05:59:00 PM PDT 24
Peak memory 206964 kb
Host smart-6c09c3e5-bbbf-4856-8072-bf176c0d66fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867178217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.2867178217
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.1386202067
Short name T173
Test name
Test status
Simulation time 4329531084 ps
CPU time 26.8 seconds
Started Jul 10 05:58:57 PM PDT 24
Finished Jul 10 05:59:25 PM PDT 24
Peak memory 216396 kb
Host smart-09f8e27d-892f-4b43-9695-f2cbde402eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386202067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.1386202067
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.531806122
Short name T341
Test name
Test status
Simulation time 82168837 ps
CPU time 1.18 seconds
Started Jul 10 05:58:54 PM PDT 24
Finished Jul 10 05:58:56 PM PDT 24
Peak memory 207868 kb
Host smart-0f48b15a-c90f-4b7e-8323-bef2e705df34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531806122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.531806122
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.312795896
Short name T605
Test name
Test status
Simulation time 186084672 ps
CPU time 1.13 seconds
Started Jul 10 05:58:53 PM PDT 24
Finished Jul 10 05:58:55 PM PDT 24
Peak memory 207732 kb
Host smart-b932bc31-a435-4f3c-97d0-bf3d03ad3e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312795896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.312795896
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.2333003295
Short name T459
Test name
Test status
Simulation time 20684912 ps
CPU time 0.78 seconds
Started Jul 10 05:58:53 PM PDT 24
Finished Jul 10 05:58:54 PM PDT 24
Peak memory 205976 kb
Host smart-53f4a0af-7e77-454d-8a83-d5162efbe76c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333003295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.2333003295
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.2090448792
Short name T751
Test name
Test status
Simulation time 377590147 ps
CPU time 3.4 seconds
Started Jul 10 05:58:57 PM PDT 24
Finished Jul 10 05:59:03 PM PDT 24
Peak memory 232644 kb
Host smart-1d863457-d4f7-40b5-bc9f-26ea1c575e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090448792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.2090448792
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.3552046491
Short name T886
Test name
Test status
Simulation time 12794027 ps
CPU time 0.74 seconds
Started Jul 10 05:58:58 PM PDT 24
Finished Jul 10 05:59:01 PM PDT 24
Peak memory 204848 kb
Host smart-2e135c08-23cb-4ae8-ba71-e9ce7eacac43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552046491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
3552046491
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.2289259149
Short name T261
Test name
Test status
Simulation time 115271534 ps
CPU time 3.54 seconds
Started Jul 10 05:58:57 PM PDT 24
Finished Jul 10 05:59:02 PM PDT 24
Peak memory 232668 kb
Host smart-a8ad93be-f8b1-44e8-b649-96403b19ed05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289259149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.2289259149
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.880539927
Short name T879
Test name
Test status
Simulation time 43114711 ps
CPU time 0.84 seconds
Started Jul 10 05:58:59 PM PDT 24
Finished Jul 10 05:59:02 PM PDT 24
Peak memory 206916 kb
Host smart-48de98e5-70fa-41e6-a2ae-a8a76ac2ac8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880539927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.880539927
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.1627119538
Short name T877
Test name
Test status
Simulation time 472649139 ps
CPU time 6.12 seconds
Started Jul 10 05:58:58 PM PDT 24
Finished Jul 10 05:59:07 PM PDT 24
Peak memory 240728 kb
Host smart-79a71b77-d1db-4c65-867a-eab854c117ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627119538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.1627119538
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.1834038753
Short name T144
Test name
Test status
Simulation time 13203780693 ps
CPU time 100.71 seconds
Started Jul 10 05:58:59 PM PDT 24
Finished Jul 10 06:00:42 PM PDT 24
Peak memory 250492 kb
Host smart-e1d7351a-f76c-48ac-a25c-ffb7db0b2c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834038753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.1834038753
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.1236141720
Short name T548
Test name
Test status
Simulation time 8706363999 ps
CPU time 50.91 seconds
Started Jul 10 05:58:59 PM PDT 24
Finished Jul 10 05:59:53 PM PDT 24
Peak memory 249420 kb
Host smart-acef388e-5d6f-4cf5-bacd-d363dc3bbe93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236141720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.1236141720
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.1470430917
Short name T1007
Test name
Test status
Simulation time 1621524504 ps
CPU time 13.73 seconds
Started Jul 10 05:59:01 PM PDT 24
Finished Jul 10 05:59:17 PM PDT 24
Peak memory 224496 kb
Host smart-256d3495-6c99-473e-8956-5d3f5fb295a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470430917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.1470430917
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.546317408
Short name T631
Test name
Test status
Simulation time 30198409475 ps
CPU time 215.86 seconds
Started Jul 10 05:58:57 PM PDT 24
Finished Jul 10 06:02:35 PM PDT 24
Peak memory 256728 kb
Host smart-894833ae-13bc-4b28-84b3-5636e178525b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546317408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmds
.546317408
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_intercept.1511044649
Short name T232
Test name
Test status
Simulation time 169306702 ps
CPU time 3.54 seconds
Started Jul 10 05:58:59 PM PDT 24
Finished Jul 10 05:59:05 PM PDT 24
Peak memory 224424 kb
Host smart-66b3ab28-5293-44a0-b959-efa73a615c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511044649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.1511044649
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.3438125499
Short name T798
Test name
Test status
Simulation time 31397107699 ps
CPU time 67.53 seconds
Started Jul 10 05:59:00 PM PDT 24
Finished Jul 10 06:00:10 PM PDT 24
Peak memory 237816 kb
Host smart-d25e405c-7e8f-4bd9-ad13-93e31232d5a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438125499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.3438125499
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.1904188244
Short name T172
Test name
Test status
Simulation time 39585921994 ps
CPU time 16.85 seconds
Started Jul 10 05:58:58 PM PDT 24
Finished Jul 10 05:59:17 PM PDT 24
Peak memory 232816 kb
Host smart-67d09fe1-5a8f-4b44-9cbe-6fabae0487e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904188244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.1904188244
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.1329371211
Short name T742
Test name
Test status
Simulation time 16349736918 ps
CPU time 24.34 seconds
Started Jul 10 05:58:56 PM PDT 24
Finished Jul 10 05:59:21 PM PDT 24
Peak memory 224648 kb
Host smart-d78e721b-b7d5-41d5-900a-8403e0cfe584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329371211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.1329371211
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.155690610
Short name T854
Test name
Test status
Simulation time 297984613 ps
CPU time 6.15 seconds
Started Jul 10 05:58:57 PM PDT 24
Finished Jul 10 05:59:06 PM PDT 24
Peak memory 218712 kb
Host smart-7413f9af-92dc-4aed-befa-aff1044339a6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=155690610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dire
ct.155690610
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.1699789837
Short name T975
Test name
Test status
Simulation time 133263991713 ps
CPU time 140.22 seconds
Started Jul 10 05:58:59 PM PDT 24
Finished Jul 10 06:01:22 PM PDT 24
Peak memory 237128 kb
Host smart-078ff598-81bc-409b-bc4a-205e371164a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699789837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.1699789837
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.2746820128
Short name T1011
Test name
Test status
Simulation time 2623426136 ps
CPU time 8.87 seconds
Started Jul 10 05:58:57 PM PDT 24
Finished Jul 10 05:59:08 PM PDT 24
Peak memory 216424 kb
Host smart-40aa33e1-7239-4fad-bbe0-c65178a7d138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746820128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.2746820128
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.3590121524
Short name T726
Test name
Test status
Simulation time 3538606374 ps
CPU time 11.44 seconds
Started Jul 10 05:58:59 PM PDT 24
Finished Jul 10 05:59:13 PM PDT 24
Peak memory 216296 kb
Host smart-f6eb520d-350e-49c6-8cd4-df13250eb52f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590121524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.3590121524
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.4191178522
Short name T711
Test name
Test status
Simulation time 76963410 ps
CPU time 0.98 seconds
Started Jul 10 05:58:59 PM PDT 24
Finished Jul 10 05:59:03 PM PDT 24
Peak memory 207464 kb
Host smart-c117c068-e634-4837-b140-c8d9d1bbbd70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191178522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.4191178522
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.3327468813
Short name T339
Test name
Test status
Simulation time 56454639 ps
CPU time 0.92 seconds
Started Jul 10 05:58:57 PM PDT 24
Finished Jul 10 05:59:01 PM PDT 24
Peak memory 205980 kb
Host smart-f572618b-7ba6-40bf-86db-ca36a9a804c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327468813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.3327468813
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.1314241948
Short name T89
Test name
Test status
Simulation time 973158019 ps
CPU time 10.07 seconds
Started Jul 10 05:59:00 PM PDT 24
Finished Jul 10 05:59:12 PM PDT 24
Peak memory 232576 kb
Host smart-487e3952-20ca-4d43-aa07-905ea388cd32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314241948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.1314241948
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.992940229
Short name T430
Test name
Test status
Simulation time 21745762 ps
CPU time 0.71 seconds
Started Jul 10 05:59:01 PM PDT 24
Finished Jul 10 05:59:04 PM PDT 24
Peak memory 204976 kb
Host smart-020b205c-ed45-419e-8f89-d664663e76b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992940229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.992940229
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.4113394998
Short name T487
Test name
Test status
Simulation time 36428513 ps
CPU time 2.69 seconds
Started Jul 10 05:59:05 PM PDT 24
Finished Jul 10 05:59:08 PM PDT 24
Peak memory 232692 kb
Host smart-ba4b5baf-d520-48f7-adf5-e438cdc7b74a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113394998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.4113394998
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.2565210397
Short name T804
Test name
Test status
Simulation time 45888615 ps
CPU time 0.75 seconds
Started Jul 10 05:58:57 PM PDT 24
Finished Jul 10 05:58:59 PM PDT 24
Peak memory 205588 kb
Host smart-4213b47c-0100-496a-9190-93c7fa8f0e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565210397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.2565210397
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.1622021408
Short name T140
Test name
Test status
Simulation time 1726120602 ps
CPU time 41.25 seconds
Started Jul 10 05:59:02 PM PDT 24
Finished Jul 10 05:59:45 PM PDT 24
Peak memory 249524 kb
Host smart-39f4ebe7-f6cd-4308-8637-6e36bd43beb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622021408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.1622021408
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.300688725
Short name T907
Test name
Test status
Simulation time 46399969760 ps
CPU time 434.99 seconds
Started Jul 10 05:59:03 PM PDT 24
Finished Jul 10 06:06:20 PM PDT 24
Peak memory 249240 kb
Host smart-267d7729-4002-4d05-953c-cb5d9524f6c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300688725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.300688725
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.1137773123
Short name T956
Test name
Test status
Simulation time 502437795 ps
CPU time 5.49 seconds
Started Jul 10 05:59:02 PM PDT 24
Finished Jul 10 05:59:09 PM PDT 24
Peak memory 236884 kb
Host smart-20a837a4-867d-4394-b030-1ccd0664cc7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137773123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.1137773123
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.1331305212
Short name T296
Test name
Test status
Simulation time 536719004 ps
CPU time 3.72 seconds
Started Jul 10 05:59:01 PM PDT 24
Finished Jul 10 05:59:07 PM PDT 24
Peak memory 224508 kb
Host smart-d0935bad-a081-44d8-b37c-424b4a1151f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331305212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.1331305212
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.3824353620
Short name T420
Test name
Test status
Simulation time 309071092 ps
CPU time 4.41 seconds
Started Jul 10 05:59:06 PM PDT 24
Finished Jul 10 05:59:11 PM PDT 24
Peak memory 224488 kb
Host smart-eb3f9b2f-eb62-4dee-be02-013c18de5fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824353620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.3824353620
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.223256306
Short name T547
Test name
Test status
Simulation time 46156925027 ps
CPU time 28.62 seconds
Started Jul 10 05:59:01 PM PDT 24
Finished Jul 10 05:59:31 PM PDT 24
Peak memory 232740 kb
Host smart-8c4c5a49-3cd7-4a07-adb6-49199ddd86e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223256306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swap
.223256306
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.256451535
Short name T455
Test name
Test status
Simulation time 261815860 ps
CPU time 4.25 seconds
Started Jul 10 05:59:02 PM PDT 24
Finished Jul 10 05:59:08 PM PDT 24
Peak memory 232632 kb
Host smart-e5bb8c3c-ccb5-4a1d-ba64-3812c121413b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256451535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.256451535
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.297039250
Short name T626
Test name
Test status
Simulation time 1139589673 ps
CPU time 9.27 seconds
Started Jul 10 05:59:00 PM PDT 24
Finished Jul 10 05:59:12 PM PDT 24
Peak memory 220260 kb
Host smart-ac9e1995-1f5a-46a5-8218-f68ecd61abc4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=297039250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dire
ct.297039250
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.3528924704
Short name T649
Test name
Test status
Simulation time 4756869853 ps
CPU time 26.01 seconds
Started Jul 10 05:59:03 PM PDT 24
Finished Jul 10 05:59:30 PM PDT 24
Peak memory 216408 kb
Host smart-313519b0-848a-4ce9-8c6a-0f217f0c6d48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528924704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.3528924704
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.3479843649
Short name T449
Test name
Test status
Simulation time 2070412160 ps
CPU time 6.41 seconds
Started Jul 10 05:58:58 PM PDT 24
Finished Jul 10 05:59:07 PM PDT 24
Peak memory 216180 kb
Host smart-28952b3e-f1b7-45f9-a2e3-915db7f1e913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479843649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.3479843649
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.3568034205
Short name T587
Test name
Test status
Simulation time 28851858 ps
CPU time 0.69 seconds
Started Jul 10 05:59:03 PM PDT 24
Finished Jul 10 05:59:05 PM PDT 24
Peak memory 205648 kb
Host smart-3b29f263-a718-4cb5-8329-7592d8233df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568034205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.3568034205
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.798643528
Short name T375
Test name
Test status
Simulation time 119282879 ps
CPU time 0.87 seconds
Started Jul 10 05:59:02 PM PDT 24
Finished Jul 10 05:59:05 PM PDT 24
Peak memory 206012 kb
Host smart-f84b6c86-3f78-4223-8a23-016b6729ff11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798643528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.798643528
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.1594103902
Short name T273
Test name
Test status
Simulation time 640017470 ps
CPU time 9.68 seconds
Started Jul 10 05:59:02 PM PDT 24
Finished Jul 10 05:59:13 PM PDT 24
Peak memory 229680 kb
Host smart-43c6e0f7-cd0f-4c60-a91a-d50b8e2cd3ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594103902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.1594103902
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.3871576759
Short name T996
Test name
Test status
Simulation time 54252372 ps
CPU time 0.79 seconds
Started Jul 10 05:57:35 PM PDT 24
Finished Jul 10 05:57:37 PM PDT 24
Peak memory 204976 kb
Host smart-7b6dd14b-a29d-4f0f-a0a9-6138aa7b3bbb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871576759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.3
871576759
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.1241345147
Short name T914
Test name
Test status
Simulation time 465311081 ps
CPU time 4.1 seconds
Started Jul 10 05:57:34 PM PDT 24
Finished Jul 10 05:57:39 PM PDT 24
Peak memory 232632 kb
Host smart-a6ac7d5f-4f5a-4684-b70b-ff6dd1085856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241345147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.1241345147
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.1275409594
Short name T5
Test name
Test status
Simulation time 44765225 ps
CPU time 0.81 seconds
Started Jul 10 05:57:32 PM PDT 24
Finished Jul 10 05:57:34 PM PDT 24
Peak memory 206600 kb
Host smart-1aeebbb2-b415-4eec-8ecd-b42c3842e8dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275409594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.1275409594
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.192544723
Short name T987
Test name
Test status
Simulation time 18541277337 ps
CPU time 85.48 seconds
Started Jul 10 05:57:37 PM PDT 24
Finished Jul 10 05:59:03 PM PDT 24
Peak memory 248996 kb
Host smart-5deb3ce6-56f6-4907-86e8-16ce3f8f7d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192544723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.192544723
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.1345839294
Short name T249
Test name
Test status
Simulation time 7551990783 ps
CPU time 70.22 seconds
Started Jul 10 05:57:48 PM PDT 24
Finished Jul 10 05:58:59 PM PDT 24
Peak memory 224676 kb
Host smart-ac943c18-a505-4fe3-afbe-3609e525db26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345839294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.1345839294
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.3027950
Short name T625
Test name
Test status
Simulation time 20428456670 ps
CPU time 26.93 seconds
Started Jul 10 05:57:35 PM PDT 24
Finished Jul 10 05:58:03 PM PDT 24
Peak memory 217768 kb
Host smart-8227a647-57d1-4d46-9c48-283b6b5d2f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle.3027950
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.3273058116
Short name T324
Test name
Test status
Simulation time 14606788727 ps
CPU time 28.72 seconds
Started Jul 10 05:57:37 PM PDT 24
Finished Jul 10 05:58:07 PM PDT 24
Peak memory 241004 kb
Host smart-eff178d7-03ee-4b77-9c72-c50c740dfe63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273058116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.3273058116
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.1036303208
Short name T566
Test name
Test status
Simulation time 12279758 ps
CPU time 0.76 seconds
Started Jul 10 05:57:36 PM PDT 24
Finished Jul 10 05:57:37 PM PDT 24
Peak memory 215788 kb
Host smart-b86ad3bd-958d-4d7d-8283-3c4dc54811ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036303208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds
.1036303208
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.2584550
Short name T817
Test name
Test status
Simulation time 943891813 ps
CPU time 6.81 seconds
Started Jul 10 05:57:36 PM PDT 24
Finished Jul 10 05:57:44 PM PDT 24
Peak memory 232640 kb
Host smart-e03f7d21-4fd2-4107-aab7-55096bf67b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.2584550
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.1114744995
Short name T590
Test name
Test status
Simulation time 407622027 ps
CPU time 3.86 seconds
Started Jul 10 05:57:34 PM PDT 24
Finished Jul 10 05:57:39 PM PDT 24
Peak memory 224496 kb
Host smart-97fbc3a8-1591-4af8-a3d6-fe26db6763a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114744995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.1114744995
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.858432543
Short name T915
Test name
Test status
Simulation time 441639267 ps
CPU time 2.85 seconds
Started Jul 10 05:57:36 PM PDT 24
Finished Jul 10 05:57:40 PM PDT 24
Peak memory 232612 kb
Host smart-42f55e16-30cf-4809-bd76-9b22e9e56e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858432543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap.
858432543
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.3169012739
Short name T614
Test name
Test status
Simulation time 73395363238 ps
CPU time 24.95 seconds
Started Jul 10 05:57:32 PM PDT 24
Finished Jul 10 05:57:58 PM PDT 24
Peak memory 232844 kb
Host smart-1a437a82-bab5-4198-bb8b-d8e05ce5d94e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169012739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.3169012739
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.915868537
Short name T154
Test name
Test status
Simulation time 506752994 ps
CPU time 8.79 seconds
Started Jul 10 05:57:34 PM PDT 24
Finished Jul 10 05:57:44 PM PDT 24
Peak memory 221592 kb
Host smart-720d86e0-d5d7-4835-b3d2-481b71b43a4f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=915868537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_direc
t.915868537
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.2932195056
Short name T1006
Test name
Test status
Simulation time 225614000 ps
CPU time 1.09 seconds
Started Jul 10 05:57:48 PM PDT 24
Finished Jul 10 05:57:50 PM PDT 24
Peak memory 206732 kb
Host smart-79f4c78b-7e3f-47f6-87bc-16ef68d7dcfd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932195056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.2932195056
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.3450944260
Short name T746
Test name
Test status
Simulation time 7047948215 ps
CPU time 47.19 seconds
Started Jul 10 05:57:28 PM PDT 24
Finished Jul 10 05:58:17 PM PDT 24
Peak memory 216356 kb
Host smart-4b49b191-014d-45ef-9b92-eb50f5f2405a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450944260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.3450944260
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.2344044724
Short name T777
Test name
Test status
Simulation time 590535954 ps
CPU time 2.91 seconds
Started Jul 10 05:57:29 PM PDT 24
Finished Jul 10 05:57:33 PM PDT 24
Peak memory 216184 kb
Host smart-35e2f288-d227-4d0e-917c-d95466f3b19c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344044724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.2344044724
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.4230665641
Short name T762
Test name
Test status
Simulation time 711026021 ps
CPU time 2.69 seconds
Started Jul 10 05:57:32 PM PDT 24
Finished Jul 10 05:57:36 PM PDT 24
Peak memory 216204 kb
Host smart-b90cb059-fec8-4101-a70c-e48eb6332409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230665641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.4230665641
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.3422122636
Short name T992
Test name
Test status
Simulation time 633014676 ps
CPU time 0.92 seconds
Started Jul 10 05:57:32 PM PDT 24
Finished Jul 10 05:57:34 PM PDT 24
Peak memory 206464 kb
Host smart-b24d725f-3438-4b1b-acde-bf1dd2cbb58f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422122636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.3422122636
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.2255462415
Short name T272
Test name
Test status
Simulation time 4901633769 ps
CPU time 7.38 seconds
Started Jul 10 05:57:33 PM PDT 24
Finished Jul 10 05:57:42 PM PDT 24
Peak memory 232824 kb
Host smart-ff346c25-0e39-4886-9f0e-d0b99a0934d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255462415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.2255462415
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.1851620028
Short name T467
Test name
Test status
Simulation time 33925191 ps
CPU time 0.73 seconds
Started Jul 10 05:59:07 PM PDT 24
Finished Jul 10 05:59:08 PM PDT 24
Peak memory 204976 kb
Host smart-cacdc97e-596b-4cb2-97c9-4a877a0441d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851620028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
1851620028
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.2000882796
Short name T695
Test name
Test status
Simulation time 1207523899 ps
CPU time 11.04 seconds
Started Jul 10 05:59:12 PM PDT 24
Finished Jul 10 05:59:23 PM PDT 24
Peak memory 224632 kb
Host smart-6c107da3-165b-4b17-96b3-445b209f0cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000882796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.2000882796
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.582424141
Short name T361
Test name
Test status
Simulation time 156217677 ps
CPU time 0.81 seconds
Started Jul 10 05:59:04 PM PDT 24
Finished Jul 10 05:59:06 PM PDT 24
Peak memory 206584 kb
Host smart-ab4b6a42-9aed-4419-8fed-dfe2fdb7a4ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582424141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.582424141
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.4071978731
Short name T298
Test name
Test status
Simulation time 260089746933 ps
CPU time 388.64 seconds
Started Jul 10 05:59:12 PM PDT 24
Finished Jul 10 06:05:42 PM PDT 24
Peak memory 252844 kb
Host smart-7c7ca062-b5cd-440d-9df0-9340394c3fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071978731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.4071978731
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.3958313996
Short name T801
Test name
Test status
Simulation time 59269315540 ps
CPU time 278.47 seconds
Started Jul 10 05:59:08 PM PDT 24
Finished Jul 10 06:03:48 PM PDT 24
Peak memory 257444 kb
Host smart-e8483d11-f275-444a-8a1c-ac823bc93c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958313996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.3958313996
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.882042605
Short name T501
Test name
Test status
Simulation time 1275095915 ps
CPU time 17.17 seconds
Started Jul 10 05:59:13 PM PDT 24
Finished Jul 10 05:59:32 PM PDT 24
Peak memory 219204 kb
Host smart-d976a4c5-867f-4797-affb-f3a38939a452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882042605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idle
.882042605
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.4186195947
Short name T776
Test name
Test status
Simulation time 1593791557 ps
CPU time 4.95 seconds
Started Jul 10 05:59:12 PM PDT 24
Finished Jul 10 05:59:17 PM PDT 24
Peak memory 232688 kb
Host smart-06bfa553-ac74-4918-9d7a-883d7b7291fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186195947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.4186195947
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.380972003
Short name T230
Test name
Test status
Simulation time 65883123214 ps
CPU time 116.47 seconds
Started Jul 10 05:59:07 PM PDT 24
Finished Jul 10 06:01:04 PM PDT 24
Peak memory 235112 kb
Host smart-5346bccc-c4bb-4318-bc4f-81eaebb6c41c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380972003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmds
.380972003
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_intercept.616385169
Short name T450
Test name
Test status
Simulation time 2749504139 ps
CPU time 37.46 seconds
Started Jul 10 05:59:07 PM PDT 24
Finished Jul 10 05:59:45 PM PDT 24
Peak memory 224560 kb
Host smart-af3390dd-e7e8-44b8-a97f-ec4f6112b3a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616385169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.616385169
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.2872933120
Short name T525
Test name
Test status
Simulation time 313077117 ps
CPU time 5.06 seconds
Started Jul 10 05:59:07 PM PDT 24
Finished Jul 10 05:59:13 PM PDT 24
Peak memory 224444 kb
Host smart-5df7cc86-3b75-4fc6-8ed3-7cc5bbc8eb90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872933120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.2872933120
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.3645156527
Short name T792
Test name
Test status
Simulation time 5131960082 ps
CPU time 8.53 seconds
Started Jul 10 05:59:10 PM PDT 24
Finished Jul 10 05:59:19 PM PDT 24
Peak memory 224612 kb
Host smart-3d283a9e-64e0-4553-83ef-2a82dc8536f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645156527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.3645156527
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.534987127
Short name T781
Test name
Test status
Simulation time 3518830012 ps
CPU time 5.56 seconds
Started Jul 10 05:59:01 PM PDT 24
Finished Jul 10 05:59:09 PM PDT 24
Peak memory 224596 kb
Host smart-92c11bb5-e5a8-46b5-b081-ff92093aae97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534987127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.534987127
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.3052586169
Short name T1002
Test name
Test status
Simulation time 1017486509 ps
CPU time 8.48 seconds
Started Jul 10 05:59:08 PM PDT 24
Finished Jul 10 05:59:17 PM PDT 24
Peak memory 222128 kb
Host smart-47799eae-67bf-429b-a3a3-eff07466e463
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3052586169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.3052586169
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.4165927233
Short name T17
Test name
Test status
Simulation time 13975284404 ps
CPU time 207.12 seconds
Started Jul 10 05:59:08 PM PDT 24
Finished Jul 10 06:02:36 PM PDT 24
Peak memory 266648 kb
Host smart-7366938b-4710-43b1-ad37-968c91a8150a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165927233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.4165927233
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.2772401956
Short name T837
Test name
Test status
Simulation time 64354168646 ps
CPU time 37.13 seconds
Started Jul 10 05:59:05 PM PDT 24
Finished Jul 10 05:59:44 PM PDT 24
Peak memory 216364 kb
Host smart-7f37351e-8f8a-4cd1-9c5b-09c7f99d9511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772401956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.2772401956
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.1064854184
Short name T772
Test name
Test status
Simulation time 125094557 ps
CPU time 2.51 seconds
Started Jul 10 05:59:01 PM PDT 24
Finished Jul 10 05:59:06 PM PDT 24
Peak memory 216228 kb
Host smart-e4b18f1a-74b1-4514-a2b8-ca53ddb9c11e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064854184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.1064854184
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.293714627
Short name T422
Test name
Test status
Simulation time 36623240 ps
CPU time 0.88 seconds
Started Jul 10 05:59:01 PM PDT 24
Finished Jul 10 05:59:04 PM PDT 24
Peak memory 206036 kb
Host smart-3aa98654-42ce-42bb-8682-f0a310590554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293714627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.293714627
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.1457202057
Short name T906
Test name
Test status
Simulation time 8371965713 ps
CPU time 6.43 seconds
Started Jul 10 05:59:06 PM PDT 24
Finished Jul 10 05:59:14 PM PDT 24
Peak memory 224576 kb
Host smart-1982feaa-1688-4c43-a176-b380d1b2bf9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457202057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.1457202057
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.3138166441
Short name T922
Test name
Test status
Simulation time 560521180 ps
CPU time 2.37 seconds
Started Jul 10 05:59:16 PM PDT 24
Finished Jul 10 05:59:19 PM PDT 24
Peak memory 224472 kb
Host smart-c4840a30-b2ee-471e-9ea1-99ab4f4806cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138166441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.3138166441
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.316591252
Short name T773
Test name
Test status
Simulation time 63212342 ps
CPU time 0.84 seconds
Started Jul 10 05:59:08 PM PDT 24
Finished Jul 10 05:59:09 PM PDT 24
Peak memory 206632 kb
Host smart-55d73ced-d596-49ed-8af6-a8aff04d2247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316591252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.316591252
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.1769188490
Short name T235
Test name
Test status
Simulation time 32311068649 ps
CPU time 62.95 seconds
Started Jul 10 05:59:12 PM PDT 24
Finished Jul 10 06:00:16 PM PDT 24
Peak memory 250668 kb
Host smart-33339f97-9ca6-4586-8cc6-56a8e6bfb95c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769188490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.1769188490
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.2294195006
Short name T206
Test name
Test status
Simulation time 68752778927 ps
CPU time 700.38 seconds
Started Jul 10 05:59:15 PM PDT 24
Finished Jul 10 06:10:56 PM PDT 24
Peak memory 262152 kb
Host smart-0b4b724a-a612-4a2c-9853-755b53797472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294195006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.2294195006
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.1741246892
Short name T250
Test name
Test status
Simulation time 19899468251 ps
CPU time 96.79 seconds
Started Jul 10 05:59:13 PM PDT 24
Finished Jul 10 06:00:51 PM PDT 24
Peak memory 240616 kb
Host smart-3f7b1d3d-ae7c-4a03-90a4-6b66351e59f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741246892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.1741246892
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.3402349909
Short name T983
Test name
Test status
Simulation time 754415199 ps
CPU time 11.8 seconds
Started Jul 10 05:59:13 PM PDT 24
Finished Jul 10 05:59:26 PM PDT 24
Peak memory 236384 kb
Host smart-7842933a-e4ba-439e-9e58-ea0465babe35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402349909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.3402349909
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.3408068485
Short name T11
Test name
Test status
Simulation time 12666561007 ps
CPU time 87.9 seconds
Started Jul 10 05:59:13 PM PDT 24
Finished Jul 10 06:00:42 PM PDT 24
Peak memory 235256 kb
Host smart-dd5a166f-bfa2-4498-840b-6f8129e07908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408068485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmd
s.3408068485
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.1012696432
Short name T821
Test name
Test status
Simulation time 759574686 ps
CPU time 4.52 seconds
Started Jul 10 05:59:16 PM PDT 24
Finished Jul 10 05:59:21 PM PDT 24
Peak memory 224436 kb
Host smart-dcd163e0-b28e-4999-8688-70e7c49153b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012696432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.1012696432
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.2786090390
Short name T698
Test name
Test status
Simulation time 35709796 ps
CPU time 2.14 seconds
Started Jul 10 05:59:13 PM PDT 24
Finished Jul 10 05:59:16 PM PDT 24
Peak memory 224620 kb
Host smart-62a39529-82ab-4496-bf3b-06dd590d14d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786090390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.2786090390
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.3078786356
Short name T177
Test name
Test status
Simulation time 3565693359 ps
CPU time 6.92 seconds
Started Jul 10 05:59:12 PM PDT 24
Finished Jul 10 05:59:20 PM PDT 24
Peak memory 224496 kb
Host smart-8c9b9b07-dc59-4ac6-8e5e-89ae19575554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078786356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.3078786356
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.1154713165
Short name T630
Test name
Test status
Simulation time 9527393124 ps
CPU time 21.76 seconds
Started Jul 10 05:59:14 PM PDT 24
Finished Jul 10 05:59:37 PM PDT 24
Peak memory 232784 kb
Host smart-0bb77682-095b-4790-be6d-41676b96fe49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154713165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.1154713165
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.1246913729
Short name T153
Test name
Test status
Simulation time 6408295042 ps
CPU time 22.67 seconds
Started Jul 10 05:59:15 PM PDT 24
Finished Jul 10 05:59:38 PM PDT 24
Peak memory 220128 kb
Host smart-fd7ccfa5-f22b-43b1-bbca-1f2f726eefd3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1246913729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.1246913729
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.1180494014
Short name T967
Test name
Test status
Simulation time 6648447288 ps
CPU time 21.85 seconds
Started Jul 10 05:59:15 PM PDT 24
Finished Jul 10 05:59:37 PM PDT 24
Peak memory 216436 kb
Host smart-7952d9de-7b61-4ee4-a313-df0980689f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180494014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.1180494014
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.987487315
Short name T656
Test name
Test status
Simulation time 30758422441 ps
CPU time 14.62 seconds
Started Jul 10 05:59:15 PM PDT 24
Finished Jul 10 05:59:30 PM PDT 24
Peak memory 216352 kb
Host smart-3852d7f9-44a7-4ee5-9581-ccb382cfd7ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987487315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.987487315
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.2323475760
Short name T842
Test name
Test status
Simulation time 49214665 ps
CPU time 1.47 seconds
Started Jul 10 05:59:11 PM PDT 24
Finished Jul 10 05:59:13 PM PDT 24
Peak memory 216240 kb
Host smart-ac5c5f33-f9aa-4e40-b727-8c7f847a97b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323475760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.2323475760
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.1746685232
Short name T918
Test name
Test status
Simulation time 124546447 ps
CPU time 0.82 seconds
Started Jul 10 05:59:12 PM PDT 24
Finished Jul 10 05:59:14 PM PDT 24
Peak memory 205988 kb
Host smart-db35e8fe-dbdf-4749-a8f1-ac1f37b0475f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746685232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.1746685232
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.1496967270
Short name T465
Test name
Test status
Simulation time 17300366574 ps
CPU time 7.79 seconds
Started Jul 10 05:59:13 PM PDT 24
Finished Jul 10 05:59:22 PM PDT 24
Peak memory 232816 kb
Host smart-7d98f8b4-6dc2-443f-a86d-a19ff98b1b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496967270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.1496967270
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.3226662530
Short name T429
Test name
Test status
Simulation time 11519113 ps
CPU time 0.74 seconds
Started Jul 10 05:59:20 PM PDT 24
Finished Jul 10 05:59:22 PM PDT 24
Peak memory 205540 kb
Host smart-e72424c7-e869-4874-b15c-103cc653db4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226662530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
3226662530
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.491714623
Short name T680
Test name
Test status
Simulation time 669624112 ps
CPU time 6.81 seconds
Started Jul 10 05:59:19 PM PDT 24
Finished Jul 10 05:59:27 PM PDT 24
Peak memory 232688 kb
Host smart-6ee0ca8e-7cd4-4632-a007-16d3f6290bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491714623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.491714623
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.1025137401
Short name T796
Test name
Test status
Simulation time 15911078 ps
CPU time 0.8 seconds
Started Jul 10 05:59:15 PM PDT 24
Finished Jul 10 05:59:16 PM PDT 24
Peak memory 206588 kb
Host smart-51516033-6f04-4538-b24a-96e4c749fe6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025137401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.1025137401
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.1519839528
Short name T304
Test name
Test status
Simulation time 8042780074 ps
CPU time 72.07 seconds
Started Jul 10 05:59:18 PM PDT 24
Finished Jul 10 06:00:31 PM PDT 24
Peak memory 249212 kb
Host smart-9518b8b8-e5d5-4ad4-8348-c40c0144b149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519839528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.1519839528
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.3583657688
Short name T615
Test name
Test status
Simulation time 6390427408 ps
CPU time 34.9 seconds
Started Jul 10 05:59:20 PM PDT 24
Finished Jul 10 05:59:56 PM PDT 24
Peak memory 240756 kb
Host smart-3a53f230-59eb-44bc-90b2-7d16d64acb6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583657688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.3583657688
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.2608599855
Short name T362
Test name
Test status
Simulation time 91274046 ps
CPU time 3.46 seconds
Started Jul 10 05:59:19 PM PDT 24
Finished Jul 10 05:59:24 PM PDT 24
Peak memory 235476 kb
Host smart-a266df7f-88ea-42da-8898-7079236ba685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608599855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.2608599855
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.3152934475
Short name T582
Test name
Test status
Simulation time 29432826468 ps
CPU time 226.61 seconds
Started Jul 10 05:59:20 PM PDT 24
Finished Jul 10 06:03:08 PM PDT 24
Peak memory 254320 kb
Host smart-0b0c9088-e863-438e-aa50-e8a58c7bae7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152934475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmd
s.3152934475
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.151184800
Short name T277
Test name
Test status
Simulation time 1785170794 ps
CPU time 17.43 seconds
Started Jul 10 05:59:18 PM PDT 24
Finished Jul 10 05:59:36 PM PDT 24
Peak memory 224452 kb
Host smart-cc357fef-70b9-4d40-8181-2d785f938841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151184800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.151184800
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.4279455131
Short name T276
Test name
Test status
Simulation time 2712730607 ps
CPU time 13.33 seconds
Started Jul 10 05:59:18 PM PDT 24
Finished Jul 10 05:59:32 PM PDT 24
Peak memory 232712 kb
Host smart-579cf59b-bf3e-49e4-8ef6-e74dcacb84fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279455131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.4279455131
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.1129507770
Short name T591
Test name
Test status
Simulation time 108362074 ps
CPU time 2.68 seconds
Started Jul 10 05:59:19 PM PDT 24
Finished Jul 10 05:59:22 PM PDT 24
Peak memory 232356 kb
Host smart-57daf6e1-e34c-4948-b189-61630553725c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129507770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.1129507770
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.2509350090
Short name T521
Test name
Test status
Simulation time 2972593624 ps
CPU time 11.08 seconds
Started Jul 10 05:59:19 PM PDT 24
Finished Jul 10 05:59:31 PM PDT 24
Peak memory 232768 kb
Host smart-58e04be8-cc2a-4c0e-874d-15fe6366ac18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509350090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.2509350090
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.1094326733
Short name T152
Test name
Test status
Simulation time 4306231083 ps
CPU time 8.66 seconds
Started Jul 10 05:59:20 PM PDT 24
Finished Jul 10 05:59:30 PM PDT 24
Peak memory 222688 kb
Host smart-bd0ca161-6805-48eb-a77b-d92126759392
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1094326733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.1094326733
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.4080052402
Short name T770
Test name
Test status
Simulation time 7304481816 ps
CPU time 19.96 seconds
Started Jul 10 05:59:13 PM PDT 24
Finished Jul 10 05:59:34 PM PDT 24
Peak memory 216372 kb
Host smart-7e52f456-b417-47cd-8f0d-ef19794fc74b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080052402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.4080052402
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.2366874721
Short name T830
Test name
Test status
Simulation time 1224410032 ps
CPU time 4.17 seconds
Started Jul 10 05:59:13 PM PDT 24
Finished Jul 10 05:59:19 PM PDT 24
Peak memory 216172 kb
Host smart-c99e7601-5591-4be2-9a3f-81bbe93e5d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366874721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.2366874721
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.1447152533
Short name T356
Test name
Test status
Simulation time 87372542 ps
CPU time 1.06 seconds
Started Jul 10 05:59:19 PM PDT 24
Finished Jul 10 05:59:21 PM PDT 24
Peak memory 207416 kb
Host smart-fa1ae3cd-add5-4a52-ad34-d03b3ca03ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447152533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.1447152533
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.559024010
Short name T370
Test name
Test status
Simulation time 31398495 ps
CPU time 0.8 seconds
Started Jul 10 05:59:13 PM PDT 24
Finished Jul 10 05:59:14 PM PDT 24
Peak memory 205948 kb
Host smart-7b59a570-879c-44d7-90ff-7941887c9a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559024010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.559024010
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.1201867989
Short name T782
Test name
Test status
Simulation time 2198693001 ps
CPU time 9.78 seconds
Started Jul 10 05:59:18 PM PDT 24
Finished Jul 10 05:59:28 PM PDT 24
Peak memory 232680 kb
Host smart-0445880a-e032-4f92-8f8d-49db86a37385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201867989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.1201867989
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.1635588256
Short name T718
Test name
Test status
Simulation time 23162191 ps
CPU time 0.74 seconds
Started Jul 10 05:59:29 PM PDT 24
Finished Jul 10 05:59:31 PM PDT 24
Peak memory 204944 kb
Host smart-f0784071-a686-4046-8fdc-a7e33dadf2b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635588256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
1635588256
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.2160259110
Short name T523
Test name
Test status
Simulation time 297689569 ps
CPU time 2.88 seconds
Started Jul 10 05:59:22 PM PDT 24
Finished Jul 10 05:59:26 PM PDT 24
Peak memory 232680 kb
Host smart-d6fd6542-978d-4e42-a49e-aef81f56c4ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160259110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.2160259110
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.1089546563
Short name T878
Test name
Test status
Simulation time 116363590 ps
CPU time 0.8 seconds
Started Jul 10 05:59:18 PM PDT 24
Finished Jul 10 05:59:20 PM PDT 24
Peak memory 206612 kb
Host smart-2f6a1cab-a158-4955-aa53-6d01546e4f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089546563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.1089546563
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.1239278896
Short name T223
Test name
Test status
Simulation time 30071527823 ps
CPU time 93.72 seconds
Started Jul 10 05:59:29 PM PDT 24
Finished Jul 10 06:01:04 PM PDT 24
Peak memory 255412 kb
Host smart-2cb2ea3c-68ee-4f92-b2f0-52d6a130ac64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239278896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.1239278896
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.1890224549
Short name T317
Test name
Test status
Simulation time 29958098680 ps
CPU time 147.81 seconds
Started Jul 10 05:59:26 PM PDT 24
Finished Jul 10 06:01:56 PM PDT 24
Peak memory 255268 kb
Host smart-2cbf458f-1192-4eaa-920e-4210287c34ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890224549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.1890224549
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.1644501
Short name T532
Test name
Test status
Simulation time 38968459343 ps
CPU time 60.36 seconds
Started Jul 10 05:59:23 PM PDT 24
Finished Jul 10 06:00:24 PM PDT 24
Peak memory 251472 kb
Host smart-64339e18-201d-4caa-9912-313efe44a9f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idle.1644501
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.1173219727
Short name T730
Test name
Test status
Simulation time 1428089839 ps
CPU time 26.65 seconds
Started Jul 10 05:59:27 PM PDT 24
Finished Jul 10 05:59:56 PM PDT 24
Peak memory 232688 kb
Host smart-19bcc8af-6318-497d-bb58-82c3867e4b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173219727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.1173219727
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.3173647562
Short name T819
Test name
Test status
Simulation time 14785909720 ps
CPU time 57.64 seconds
Started Jul 10 05:59:25 PM PDT 24
Finished Jul 10 06:00:25 PM PDT 24
Peak memory 249900 kb
Host smart-adef912e-6409-48f9-ad31-ce54b2d445b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173647562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmd
s.3173647562
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.3072370536
Short name T215
Test name
Test status
Simulation time 192118762 ps
CPU time 5.63 seconds
Started Jul 10 05:59:20 PM PDT 24
Finished Jul 10 05:59:26 PM PDT 24
Peak memory 227680 kb
Host smart-55d67359-b9f2-46f2-8606-7addc02f9d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072370536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.3072370536
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.3705086204
Short name T236
Test name
Test status
Simulation time 6979552991 ps
CPU time 65.39 seconds
Started Jul 10 05:59:19 PM PDT 24
Finished Jul 10 06:00:26 PM PDT 24
Peak memory 236796 kb
Host smart-28c6f8ab-5d89-4873-bc0d-300c52a596e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705086204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.3705086204
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.1146158466
Short name T702
Test name
Test status
Simulation time 79480201 ps
CPU time 2.61 seconds
Started Jul 10 05:59:20 PM PDT 24
Finished Jul 10 05:59:24 PM PDT 24
Peak memory 232368 kb
Host smart-08e46b09-03f6-48d4-8bac-e0c3555fa235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146158466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.1146158466
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.2341611983
Short name T441
Test name
Test status
Simulation time 3981937606 ps
CPU time 5.87 seconds
Started Jul 10 05:59:21 PM PDT 24
Finished Jul 10 05:59:28 PM PDT 24
Peak memory 224588 kb
Host smart-e378608f-3945-41fe-a9a3-24bb09e94664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341611983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.2341611983
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.677681150
Short name T174
Test name
Test status
Simulation time 482269036 ps
CPU time 4.82 seconds
Started Jul 10 05:59:26 PM PDT 24
Finished Jul 10 05:59:33 PM PDT 24
Peak memory 223140 kb
Host smart-ebc32734-3c2b-4ee8-8565-f6bb52fb7b9a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=677681150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dire
ct.677681150
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.3992095300
Short name T389
Test name
Test status
Simulation time 56855723 ps
CPU time 0.73 seconds
Started Jul 10 05:59:19 PM PDT 24
Finished Jul 10 05:59:21 PM PDT 24
Peak memory 205712 kb
Host smart-04b55c5d-1f67-499c-beb1-507e7013b0b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992095300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.3992095300
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.1831129332
Short name T732
Test name
Test status
Simulation time 379972651 ps
CPU time 1.57 seconds
Started Jul 10 05:59:20 PM PDT 24
Finished Jul 10 05:59:23 PM PDT 24
Peak memory 207908 kb
Host smart-6d6d7fac-7b1b-45c4-a138-7278de6ab374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831129332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.1831129332
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.1422165845
Short name T333
Test name
Test status
Simulation time 234580896 ps
CPU time 3.76 seconds
Started Jul 10 05:59:16 PM PDT 24
Finished Jul 10 05:59:21 PM PDT 24
Peak memory 216148 kb
Host smart-92b50c74-86ba-4479-a211-b3af7b3fc1eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422165845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.1422165845
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.92558139
Short name T390
Test name
Test status
Simulation time 95091469 ps
CPU time 1.07 seconds
Started Jul 10 05:59:17 PM PDT 24
Finished Jul 10 05:59:19 PM PDT 24
Peak memory 206996 kb
Host smart-10ae4e39-5674-4599-b693-8baff9bbc316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92558139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.92558139
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.1294535183
Short name T424
Test name
Test status
Simulation time 602566479 ps
CPU time 4.74 seconds
Started Jul 10 05:59:18 PM PDT 24
Finished Jul 10 05:59:23 PM PDT 24
Peak memory 240864 kb
Host smart-45b9d73f-27a6-451e-b55a-13ba368ee77a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294535183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.1294535183
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.1628447079
Short name T1019
Test name
Test status
Simulation time 11707105 ps
CPU time 0.74 seconds
Started Jul 10 05:59:29 PM PDT 24
Finished Jul 10 05:59:32 PM PDT 24
Peak memory 204944 kb
Host smart-c531011c-c83f-41f2-9f51-5dd13cb166c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628447079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
1628447079
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.259337565
Short name T856
Test name
Test status
Simulation time 5648455377 ps
CPU time 10.11 seconds
Started Jul 10 05:59:25 PM PDT 24
Finished Jul 10 05:59:36 PM PDT 24
Peak memory 232756 kb
Host smart-25ef0b0b-3be9-4b3d-b2b4-632352eee1df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259337565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.259337565
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.2074486651
Short name T715
Test name
Test status
Simulation time 51842626 ps
CPU time 0.78 seconds
Started Jul 10 05:59:26 PM PDT 24
Finished Jul 10 05:59:29 PM PDT 24
Peak memory 206612 kb
Host smart-e8046770-1c6e-4519-a93c-249ea6f2d3e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074486651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.2074486651
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.1572181045
Short name T204
Test name
Test status
Simulation time 9186672690 ps
CPU time 102.76 seconds
Started Jul 10 05:59:25 PM PDT 24
Finished Jul 10 06:01:09 PM PDT 24
Peak memory 272920 kb
Host smart-7fed5657-3984-4d74-b671-03db218225c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572181045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.1572181045
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.1462855737
Short name T706
Test name
Test status
Simulation time 36939117226 ps
CPU time 155.36 seconds
Started Jul 10 05:59:26 PM PDT 24
Finished Jul 10 06:02:04 PM PDT 24
Peak memory 256764 kb
Host smart-12564cf7-d346-4a76-9bdb-098baf2ccfed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462855737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.1462855737
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.2476251112
Short name T146
Test name
Test status
Simulation time 10636824736 ps
CPU time 81.78 seconds
Started Jul 10 05:59:26 PM PDT 24
Finished Jul 10 06:00:50 PM PDT 24
Peak memory 254492 kb
Host smart-6cef5d3e-c7a6-42a2-b3b6-69865ca0f71a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476251112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.2476251112
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.233194880
Short name T636
Test name
Test status
Simulation time 229221064 ps
CPU time 5.22 seconds
Started Jul 10 05:59:25 PM PDT 24
Finished Jul 10 05:59:31 PM PDT 24
Peak memory 232712 kb
Host smart-b7bee8dd-a77d-4c72-9523-8ad80da713ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233194880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.233194880
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.1100381189
Short name T208
Test name
Test status
Simulation time 21540900401 ps
CPU time 187.6 seconds
Started Jul 10 05:59:24 PM PDT 24
Finished Jul 10 06:02:33 PM PDT 24
Peak memory 257384 kb
Host smart-e8959859-7350-47ec-9ba5-29fc504d9f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100381189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmd
s.1100381189
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.2609491712
Short name T527
Test name
Test status
Simulation time 9834544252 ps
CPU time 25.9 seconds
Started Jul 10 05:59:26 PM PDT 24
Finished Jul 10 05:59:54 PM PDT 24
Peak memory 232756 kb
Host smart-10ae5631-2e4d-40e2-9725-ecf957f7fe3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609491712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.2609491712
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.3873350232
Short name T943
Test name
Test status
Simulation time 3747006119 ps
CPU time 14.47 seconds
Started Jul 10 05:59:27 PM PDT 24
Finished Jul 10 05:59:43 PM PDT 24
Peak memory 241208 kb
Host smart-f34f593f-19a7-4587-9c1d-29feb541b069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873350232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.3873350232
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.956007778
Short name T755
Test name
Test status
Simulation time 57538651 ps
CPU time 2.08 seconds
Started Jul 10 05:59:30 PM PDT 24
Finished Jul 10 05:59:34 PM PDT 24
Peak memory 222756 kb
Host smart-c3701caa-06dc-43df-aea9-73ccf3b1dbea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956007778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swap
.956007778
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.3285422009
Short name T386
Test name
Test status
Simulation time 1978587098 ps
CPU time 3.47 seconds
Started Jul 10 05:59:25 PM PDT 24
Finished Jul 10 05:59:29 PM PDT 24
Peak memory 224524 kb
Host smart-78a6a92b-6625-4913-a0e7-fbe671fe4b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285422009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.3285422009
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.2009585509
Short name T176
Test name
Test status
Simulation time 453606826 ps
CPU time 4.44 seconds
Started Jul 10 05:59:23 PM PDT 24
Finished Jul 10 05:59:29 PM PDT 24
Peak memory 219428 kb
Host smart-af153cd9-5810-4852-ab84-f8542b60e632
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2009585509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.2009585509
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.448948381
Short name T143
Test name
Test status
Simulation time 4176623469 ps
CPU time 53.88 seconds
Started Jul 10 05:59:26 PM PDT 24
Finished Jul 10 06:00:22 PM PDT 24
Peak memory 250764 kb
Host smart-365367dd-a38b-4bce-b45c-a68b37840642
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448948381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stres
s_all.448948381
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.2370854011
Short name T807
Test name
Test status
Simulation time 9695874959 ps
CPU time 24.38 seconds
Started Jul 10 05:59:26 PM PDT 24
Finished Jul 10 05:59:52 PM PDT 24
Peak memory 216524 kb
Host smart-7583fd57-d75d-4637-b19d-3cab41d63f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370854011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.2370854011
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.2069125638
Short name T901
Test name
Test status
Simulation time 6834107056 ps
CPU time 18.96 seconds
Started Jul 10 05:59:22 PM PDT 24
Finished Jul 10 05:59:41 PM PDT 24
Peak memory 216360 kb
Host smart-934fbe14-e8b3-4907-b32a-777af54494e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069125638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.2069125638
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.2266670655
Short name T583
Test name
Test status
Simulation time 171828308 ps
CPU time 1.39 seconds
Started Jul 10 05:59:24 PM PDT 24
Finished Jul 10 05:59:27 PM PDT 24
Peak memory 216204 kb
Host smart-a3c80f18-f708-4839-a5dc-a6e1ce55a4bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266670655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.2266670655
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.3761961491
Short name T351
Test name
Test status
Simulation time 89084507 ps
CPU time 0.96 seconds
Started Jul 10 05:59:23 PM PDT 24
Finished Jul 10 05:59:25 PM PDT 24
Peak memory 207004 kb
Host smart-b35cce9e-8e7d-4beb-b756-4a2824e51322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761961491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.3761961491
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.1840371295
Short name T135
Test name
Test status
Simulation time 9414069275 ps
CPU time 32.23 seconds
Started Jul 10 05:59:26 PM PDT 24
Finished Jul 10 06:00:00 PM PDT 24
Peak memory 240384 kb
Host smart-95a9139c-da69-4eae-af5d-5207b71f67a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840371295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.1840371295
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.3728054606
Short name T458
Test name
Test status
Simulation time 31334388 ps
CPU time 0.7 seconds
Started Jul 10 05:59:29 PM PDT 24
Finished Jul 10 05:59:31 PM PDT 24
Peak memory 205556 kb
Host smart-163bb2d9-1887-4f97-b399-3bf3e5c6b56d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728054606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
3728054606
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.607893658
Short name T479
Test name
Test status
Simulation time 423313195 ps
CPU time 4.34 seconds
Started Jul 10 05:59:28 PM PDT 24
Finished Jul 10 05:59:34 PM PDT 24
Peak memory 224468 kb
Host smart-d548c6df-81fb-4397-b61c-fed5ae3ab232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607893658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.607893658
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.2237775785
Short name T976
Test name
Test status
Simulation time 20884416 ps
CPU time 0.84 seconds
Started Jul 10 05:59:25 PM PDT 24
Finished Jul 10 05:59:28 PM PDT 24
Peak memory 206660 kb
Host smart-ab38ae18-5304-419a-b550-f307315ec0ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237775785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.2237775785
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.97272215
Short name T1020
Test name
Test status
Simulation time 13924614298 ps
CPU time 118.58 seconds
Started Jul 10 05:59:29 PM PDT 24
Finished Jul 10 06:01:29 PM PDT 24
Peak memory 239640 kb
Host smart-9df8b291-8944-4aa9-bbb2-9f82d15429b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97272215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.97272215
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.2221051266
Short name T308
Test name
Test status
Simulation time 10281324832 ps
CPU time 69.14 seconds
Started Jul 10 05:59:35 PM PDT 24
Finished Jul 10 06:00:46 PM PDT 24
Peak memory 265648 kb
Host smart-c2e52742-da2e-4855-949e-76b750c546be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221051266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.2221051266
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.3983552897
Short name T849
Test name
Test status
Simulation time 968047918 ps
CPU time 11.74 seconds
Started Jul 10 05:59:27 PM PDT 24
Finished Jul 10 05:59:41 PM PDT 24
Peak memory 240844 kb
Host smart-676778b4-4b5f-4a9d-9dc0-ac9a1280153c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983552897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.3983552897
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.1149899847
Short name T480
Test name
Test status
Simulation time 19606646817 ps
CPU time 38 seconds
Started Jul 10 05:59:37 PM PDT 24
Finished Jul 10 06:00:16 PM PDT 24
Peak memory 249204 kb
Host smart-29e329ad-fc43-4e5c-94e3-a08feff91022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149899847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmd
s.1149899847
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.2343739412
Short name T202
Test name
Test status
Simulation time 188895038 ps
CPU time 4.33 seconds
Started Jul 10 05:59:30 PM PDT 24
Finished Jul 10 05:59:36 PM PDT 24
Peak memory 232600 kb
Host smart-f4317144-932a-469d-8363-4f9266942b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343739412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.2343739412
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.100195602
Short name T257
Test name
Test status
Simulation time 4239765654 ps
CPU time 29.01 seconds
Started Jul 10 05:59:30 PM PDT 24
Finished Jul 10 06:00:01 PM PDT 24
Peak memory 232764 kb
Host smart-f48bbe14-8fbd-42ab-bc46-aab39cb29aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100195602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.100195602
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.697229468
Short name T513
Test name
Test status
Simulation time 6575422067 ps
CPU time 10.02 seconds
Started Jul 10 05:59:29 PM PDT 24
Finished Jul 10 05:59:41 PM PDT 24
Peak memory 232776 kb
Host smart-3e5e0494-7949-4169-a5dd-27b759519491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697229468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swap
.697229468
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.580987507
Short name T888
Test name
Test status
Simulation time 62294684 ps
CPU time 2.74 seconds
Started Jul 10 05:59:28 PM PDT 24
Finished Jul 10 05:59:33 PM PDT 24
Peak memory 232680 kb
Host smart-54002224-787d-4b24-b56f-2eec9dfdc54f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580987507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.580987507
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.2691702592
Short name T409
Test name
Test status
Simulation time 2645321976 ps
CPU time 10.14 seconds
Started Jul 10 05:59:31 PM PDT 24
Finished Jul 10 05:59:43 PM PDT 24
Peak memory 219476 kb
Host smart-ea613053-091e-4165-af7a-a5c170ef77d4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2691702592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.2691702592
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.3621721724
Short name T699
Test name
Test status
Simulation time 247161280 ps
CPU time 1.03 seconds
Started Jul 10 05:59:29 PM PDT 24
Finished Jul 10 05:59:31 PM PDT 24
Peak memory 206988 kb
Host smart-d7e60f25-690c-4c14-a477-525d3b2e023b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621721724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.3621721724
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.7654801
Short name T933
Test name
Test status
Simulation time 14899760482 ps
CPU time 23.71 seconds
Started Jul 10 05:59:26 PM PDT 24
Finished Jul 10 05:59:52 PM PDT 24
Peak memory 216416 kb
Host smart-46c666f2-116c-4f1e-9552-dcad61c5e9b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7654801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.7654801
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.3135920369
Short name T34
Test name
Test status
Simulation time 16299780161 ps
CPU time 10.62 seconds
Started Jul 10 05:59:26 PM PDT 24
Finished Jul 10 05:59:38 PM PDT 24
Peak memory 216360 kb
Host smart-27987218-1af7-4677-b1b4-4ce77ad22757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135920369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.3135920369
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.1693804817
Short name T905
Test name
Test status
Simulation time 320788335 ps
CPU time 2.77 seconds
Started Jul 10 05:59:29 PM PDT 24
Finished Jul 10 05:59:33 PM PDT 24
Peak memory 216448 kb
Host smart-c3abfbc2-0560-4f82-bdd8-3ad468bf1625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693804817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.1693804817
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.3813442189
Short name T613
Test name
Test status
Simulation time 23154033 ps
CPU time 0.89 seconds
Started Jul 10 05:59:24 PM PDT 24
Finished Jul 10 05:59:26 PM PDT 24
Peak memory 205980 kb
Host smart-f10dd496-3be4-4631-b670-3db43b7faf79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813442189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.3813442189
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.2969645161
Short name T55
Test name
Test status
Simulation time 12272391078 ps
CPU time 12.72 seconds
Started Jul 10 05:59:28 PM PDT 24
Finished Jul 10 05:59:42 PM PDT 24
Peak memory 232788 kb
Host smart-aa985321-8896-47a2-813c-227c221a16a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969645161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.2969645161
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.2574173343
Short name T65
Test name
Test status
Simulation time 16232361 ps
CPU time 0.72 seconds
Started Jul 10 05:59:34 PM PDT 24
Finished Jul 10 05:59:36 PM PDT 24
Peak memory 204976 kb
Host smart-ee894fb6-7f29-4082-81f3-fe584a76b2c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574173343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
2574173343
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.1519682189
Short name T9
Test name
Test status
Simulation time 2765762185 ps
CPU time 6.98 seconds
Started Jul 10 05:59:34 PM PDT 24
Finished Jul 10 05:59:42 PM PDT 24
Peak memory 224544 kb
Host smart-b7cf1c5b-e35f-420a-8e3d-c0558237d562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519682189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.1519682189
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.1588617274
Short name T684
Test name
Test status
Simulation time 51018528 ps
CPU time 0.74 seconds
Started Jul 10 05:59:30 PM PDT 24
Finished Jul 10 05:59:32 PM PDT 24
Peak memory 205564 kb
Host smart-492e7fbf-48a5-4b7e-90d6-a8ade8dda87a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588617274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.1588617274
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.2148761859
Short name T652
Test name
Test status
Simulation time 28892427875 ps
CPU time 91.66 seconds
Started Jul 10 05:59:38 PM PDT 24
Finished Jul 10 06:01:11 PM PDT 24
Peak memory 248880 kb
Host smart-b04e841d-f0c8-47e7-9d50-4b40496acb10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148761859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.2148761859
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.1906294144
Short name T79
Test name
Test status
Simulation time 4460633104 ps
CPU time 46.77 seconds
Started Jul 10 05:59:34 PM PDT 24
Finished Jul 10 06:00:22 PM PDT 24
Peak memory 250684 kb
Host smart-727513f1-fe73-4467-89ea-5ac9d229fd79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906294144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.1906294144
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.1770755740
Short name T556
Test name
Test status
Simulation time 1147869425 ps
CPU time 16.46 seconds
Started Jul 10 05:59:34 PM PDT 24
Finished Jul 10 05:59:52 PM PDT 24
Peak memory 232692 kb
Host smart-de7d0edd-9268-4e1e-a61e-1fe1a017e725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770755740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.1770755740
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.2172349113
Short name T892
Test name
Test status
Simulation time 1318826912 ps
CPU time 36.38 seconds
Started Jul 10 05:59:32 PM PDT 24
Finished Jul 10 06:00:09 PM PDT 24
Peak memory 256956 kb
Host smart-767ed46f-a694-4e28-b7fd-d3e838f385a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172349113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmd
s.2172349113
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.4113690859
Short name T244
Test name
Test status
Simulation time 1515541492 ps
CPU time 11.86 seconds
Started Jul 10 05:59:36 PM PDT 24
Finished Jul 10 05:59:48 PM PDT 24
Peak memory 224452 kb
Host smart-4c2f48bb-7755-4df4-888a-d77232ba2eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113690859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.4113690859
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.347695795
Short name T948
Test name
Test status
Simulation time 4470398752 ps
CPU time 51.75 seconds
Started Jul 10 05:59:33 PM PDT 24
Finished Jul 10 06:00:26 PM PDT 24
Peak memory 232760 kb
Host smart-df26d74a-388c-459a-a38a-6e5071feb5e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347695795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.347695795
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.2513945525
Short name T216
Test name
Test status
Simulation time 1700216331 ps
CPU time 9.83 seconds
Started Jul 10 05:59:40 PM PDT 24
Finished Jul 10 05:59:52 PM PDT 24
Peak memory 232636 kb
Host smart-fd3e5513-77f0-4aff-9af8-99bfd0a5f075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513945525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.2513945525
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.824823500
Short name T835
Test name
Test status
Simulation time 45543320252 ps
CPU time 13.67 seconds
Started Jul 10 05:59:32 PM PDT 24
Finished Jul 10 05:59:47 PM PDT 24
Peak memory 240588 kb
Host smart-6625ce2d-89b5-4486-b2aa-90eafd685383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824823500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.824823500
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.764306246
Short name T363
Test name
Test status
Simulation time 2696555875 ps
CPU time 7.89 seconds
Started Jul 10 05:59:34 PM PDT 24
Finished Jul 10 05:59:43 PM PDT 24
Peak memory 222080 kb
Host smart-aa1d1b94-81ff-412b-ab30-9ddb6259866a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=764306246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dire
ct.764306246
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.3728957509
Short name T864
Test name
Test status
Simulation time 95890338108 ps
CPU time 413.36 seconds
Started Jul 10 05:59:35 PM PDT 24
Finished Jul 10 06:06:29 PM PDT 24
Peak memory 282040 kb
Host smart-5d2b914f-7f25-4e78-be9b-690945ec1442
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728957509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.3728957509
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.128971864
Short name T710
Test name
Test status
Simulation time 2048991843 ps
CPU time 20.8 seconds
Started Jul 10 05:59:30 PM PDT 24
Finished Jul 10 05:59:52 PM PDT 24
Peak memory 216296 kb
Host smart-6c93c8e2-0030-440b-bc51-fccf86cdda23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128971864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.128971864
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.1118050266
Short name T433
Test name
Test status
Simulation time 4988780587 ps
CPU time 15.17 seconds
Started Jul 10 05:59:37 PM PDT 24
Finished Jul 10 05:59:53 PM PDT 24
Peak memory 216292 kb
Host smart-db5637fb-050b-4784-bc82-b917a7a1c7c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118050266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.1118050266
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.2144213953
Short name T809
Test name
Test status
Simulation time 238928803 ps
CPU time 3.38 seconds
Started Jul 10 05:59:38 PM PDT 24
Finished Jul 10 05:59:42 PM PDT 24
Peak memory 216252 kb
Host smart-de0df18d-9279-49d9-b9e7-f13ba568952f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144213953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.2144213953
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.662827688
Short name T461
Test name
Test status
Simulation time 107971557 ps
CPU time 1.04 seconds
Started Jul 10 05:59:29 PM PDT 24
Finished Jul 10 05:59:31 PM PDT 24
Peak memory 207008 kb
Host smart-3b73801e-59ee-4dd1-887b-43c00a653269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662827688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.662827688
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.261427738
Short name T294
Test name
Test status
Simulation time 19601920936 ps
CPU time 20.82 seconds
Started Jul 10 05:59:39 PM PDT 24
Finished Jul 10 06:00:00 PM PDT 24
Peak memory 232744 kb
Host smart-d6453c91-4cda-4bf5-9ccf-876961dd9a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261427738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.261427738
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.3016415024
Short name T686
Test name
Test status
Simulation time 77865398 ps
CPU time 0.74 seconds
Started Jul 10 05:59:41 PM PDT 24
Finished Jul 10 05:59:43 PM PDT 24
Peak memory 205548 kb
Host smart-5b0c1962-ca76-4701-b385-f9669c0c5386
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016415024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
3016415024
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.3802059132
Short name T846
Test name
Test status
Simulation time 225169703 ps
CPU time 4.74 seconds
Started Jul 10 05:59:41 PM PDT 24
Finished Jul 10 05:59:48 PM PDT 24
Peak memory 224444 kb
Host smart-196e9169-861b-49a0-a80f-0ea54b86dca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802059132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.3802059132
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.1033018097
Short name T453
Test name
Test status
Simulation time 83240612 ps
CPU time 0.8 seconds
Started Jul 10 05:59:39 PM PDT 24
Finished Jul 10 05:59:40 PM PDT 24
Peak memory 206620 kb
Host smart-b7a8e403-ea6f-4077-aae0-463b3dff4677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033018097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.1033018097
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.1837742017
Short name T815
Test name
Test status
Simulation time 16316847264 ps
CPU time 170.96 seconds
Started Jul 10 05:59:41 PM PDT 24
Finished Jul 10 06:02:34 PM PDT 24
Peak memory 254280 kb
Host smart-8b487b9f-3bc6-42ac-a587-c8c78cca981f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837742017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.1837742017
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.3182139445
Short name T898
Test name
Test status
Simulation time 52623317328 ps
CPU time 246.25 seconds
Started Jul 10 05:59:41 PM PDT 24
Finished Jul 10 06:03:48 PM PDT 24
Peak memory 255044 kb
Host smart-0668c5b6-08bd-47e9-9e19-b73451d491e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182139445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.3182139445
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.1027647954
Short name T528
Test name
Test status
Simulation time 26801120248 ps
CPU time 51.49 seconds
Started Jul 10 05:59:40 PM PDT 24
Finished Jul 10 06:00:33 PM PDT 24
Peak memory 224672 kb
Host smart-cb2f21e8-1a90-46fe-92fa-b79b07c7daf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027647954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.1027647954
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.4230666677
Short name T539
Test name
Test status
Simulation time 14022533966 ps
CPU time 41.27 seconds
Started Jul 10 05:59:39 PM PDT 24
Finished Jul 10 06:00:22 PM PDT 24
Peak memory 232740 kb
Host smart-fab1945f-62e2-4875-8909-b6427b9416ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230666677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.4230666677
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.2856311509
Short name T314
Test name
Test status
Simulation time 30112835826 ps
CPU time 53.8 seconds
Started Jul 10 05:59:39 PM PDT 24
Finished Jul 10 06:00:34 PM PDT 24
Peak memory 224576 kb
Host smart-e4749434-ba07-4444-9714-3df0aaf04578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856311509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmd
s.2856311509
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.2131962831
Short name T899
Test name
Test status
Simulation time 32053048 ps
CPU time 2.19 seconds
Started Jul 10 05:59:34 PM PDT 24
Finished Jul 10 05:59:37 PM PDT 24
Peak memory 232384 kb
Host smart-135ac661-58a6-4ba2-94a3-68c1bbecf93a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131962831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.2131962831
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.2307858087
Short name T291
Test name
Test status
Simulation time 19566496978 ps
CPU time 40.24 seconds
Started Jul 10 05:59:38 PM PDT 24
Finished Jul 10 06:00:19 PM PDT 24
Peak memory 240528 kb
Host smart-694afce6-9160-4976-9686-023169ef4f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307858087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.2307858087
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.2635704933
Short name T306
Test name
Test status
Simulation time 385306242 ps
CPU time 6.58 seconds
Started Jul 10 05:59:35 PM PDT 24
Finished Jul 10 05:59:43 PM PDT 24
Peak memory 240648 kb
Host smart-b8be01e3-f484-4757-b749-c44230f22eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635704933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.2635704933
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.2426223731
Short name T474
Test name
Test status
Simulation time 11600457622 ps
CPU time 5.11 seconds
Started Jul 10 05:59:35 PM PDT 24
Finished Jul 10 05:59:42 PM PDT 24
Peak memory 224520 kb
Host smart-6ac434a8-5951-4bf0-84dd-1e7a06221898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426223731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.2426223731
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.2313786806
Short name T26
Test name
Test status
Simulation time 1818994146 ps
CPU time 6.61 seconds
Started Jul 10 05:59:39 PM PDT 24
Finished Jul 10 05:59:46 PM PDT 24
Peak memory 220484 kb
Host smart-18bf8cc1-4fc6-45da-9a18-c15859ea0423
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2313786806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.2313786806
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.2867660374
Short name T16
Test name
Test status
Simulation time 101972523 ps
CPU time 1.1 seconds
Started Jul 10 05:59:40 PM PDT 24
Finished Jul 10 05:59:42 PM PDT 24
Peak memory 206880 kb
Host smart-139020e1-4663-4004-a106-00934e034af1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867660374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.2867660374
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.1096759473
Short name T169
Test name
Test status
Simulation time 13767743654 ps
CPU time 24.68 seconds
Started Jul 10 05:59:37 PM PDT 24
Finished Jul 10 06:00:02 PM PDT 24
Peak memory 220656 kb
Host smart-ee232dc4-4d91-4cc4-8d50-ceb225b8ca6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096759473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.1096759473
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.3445088924
Short name T633
Test name
Test status
Simulation time 11267275228 ps
CPU time 18.51 seconds
Started Jul 10 05:59:36 PM PDT 24
Finished Jul 10 05:59:56 PM PDT 24
Peak memory 216348 kb
Host smart-aab519e7-161b-4d59-9efb-ffe20d70158c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445088924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.3445088924
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.4011326312
Short name T374
Test name
Test status
Simulation time 701482340 ps
CPU time 1.43 seconds
Started Jul 10 05:59:35 PM PDT 24
Finished Jul 10 05:59:37 PM PDT 24
Peak memory 217544 kb
Host smart-d3588251-034f-4b09-a765-a09338dc7825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011326312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.4011326312
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.1045553034
Short name T384
Test name
Test status
Simulation time 60140226 ps
CPU time 0.91 seconds
Started Jul 10 05:59:41 PM PDT 24
Finished Jul 10 05:59:44 PM PDT 24
Peak memory 206436 kb
Host smart-6bd36feb-f9ee-4ffa-8c97-aff59f962c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045553034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.1045553034
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.3780000210
Short name T42
Test name
Test status
Simulation time 535673615 ps
CPU time 4.21 seconds
Started Jul 10 05:59:34 PM PDT 24
Finished Jul 10 05:59:39 PM PDT 24
Peak memory 232704 kb
Host smart-58321379-1c5d-47fa-9e0d-5798326a80f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780000210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.3780000210
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.2963089075
Short name T979
Test name
Test status
Simulation time 16904656 ps
CPU time 0.71 seconds
Started Jul 10 05:59:45 PM PDT 24
Finished Jul 10 05:59:47 PM PDT 24
Peak memory 205524 kb
Host smart-e3e88e27-b1d2-4fe1-9601-8864188f9fb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963089075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
2963089075
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.3400235305
Short name T265
Test name
Test status
Simulation time 1194229327 ps
CPU time 12.8 seconds
Started Jul 10 05:59:52 PM PDT 24
Finished Jul 10 06:00:06 PM PDT 24
Peak memory 232620 kb
Host smart-b53cdc06-8500-48ce-8b6e-62f16535fec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400235305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.3400235305
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.1654230650
Short name T639
Test name
Test status
Simulation time 67400891 ps
CPU time 0.73 seconds
Started Jul 10 05:59:40 PM PDT 24
Finished Jul 10 05:59:41 PM PDT 24
Peak memory 205584 kb
Host smart-555d3fcd-5573-4e1f-af54-d9b0038fa131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654230650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.1654230650
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.535089843
Short name T723
Test name
Test status
Simulation time 4149412992 ps
CPU time 50.39 seconds
Started Jul 10 05:59:40 PM PDT 24
Finished Jul 10 06:00:32 PM PDT 24
Peak memory 249452 kb
Host smart-55491786-188d-4535-abc2-bcf47aec0bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535089843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.535089843
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.1522484688
Short name T327
Test name
Test status
Simulation time 17241054628 ps
CPU time 39.52 seconds
Started Jul 10 05:59:41 PM PDT 24
Finished Jul 10 06:00:22 PM PDT 24
Peak memory 239624 kb
Host smart-9e411ade-e838-4887-8495-a930bdce829c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522484688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.1522484688
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.989321332
Short name T313
Test name
Test status
Simulation time 2501919211 ps
CPU time 55.92 seconds
Started Jul 10 05:59:40 PM PDT 24
Finished Jul 10 06:00:37 PM PDT 24
Peak memory 252996 kb
Host smart-aaafe492-6a21-4d85-bab0-99ed80c055a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989321332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idle
.989321332
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.553026186
Short name T225
Test name
Test status
Simulation time 2324642108 ps
CPU time 14.5 seconds
Started Jul 10 05:59:40 PM PDT 24
Finished Jul 10 05:59:56 PM PDT 24
Peak memory 232820 kb
Host smart-91004c61-4784-446f-9282-6cbe27815e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553026186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.553026186
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.696234391
Short name T3
Test name
Test status
Simulation time 45548295645 ps
CPU time 177.6 seconds
Started Jul 10 05:59:49 PM PDT 24
Finished Jul 10 06:02:47 PM PDT 24
Peak memory 259468 kb
Host smart-efa83664-d537-4ba2-886a-0de9fdb5ac3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696234391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmds
.696234391
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.3527431624
Short name T98
Test name
Test status
Simulation time 13004849168 ps
CPU time 30.67 seconds
Started Jul 10 05:59:40 PM PDT 24
Finished Jul 10 06:00:12 PM PDT 24
Peak memory 232800 kb
Host smart-97817455-36db-4f50-ac50-774483285233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527431624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.3527431624
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.1561296922
Short name T585
Test name
Test status
Simulation time 2318726199 ps
CPU time 7.9 seconds
Started Jul 10 05:59:40 PM PDT 24
Finished Jul 10 05:59:49 PM PDT 24
Peak memory 232736 kb
Host smart-0085774d-fcac-4bf9-ad9c-841cfd4c720b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561296922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.1561296922
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.1575330226
Short name T426
Test name
Test status
Simulation time 984423853 ps
CPU time 2.52 seconds
Started Jul 10 05:59:40 PM PDT 24
Finished Jul 10 05:59:43 PM PDT 24
Peak memory 224408 kb
Host smart-e4f2e9d1-2443-4e1c-b8a7-9807e7274a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575330226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.1575330226
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.698199168
Short name T1016
Test name
Test status
Simulation time 3332467047 ps
CPU time 10.43 seconds
Started Jul 10 05:59:40 PM PDT 24
Finished Jul 10 05:59:52 PM PDT 24
Peak memory 240244 kb
Host smart-9e6bb44c-739d-4ba4-aa0a-48fd50cc8389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698199168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.698199168
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.93859316
Short name T599
Test name
Test status
Simulation time 365954583 ps
CPU time 4.75 seconds
Started Jul 10 05:59:40 PM PDT 24
Finished Jul 10 05:59:46 PM PDT 24
Peak memory 222692 kb
Host smart-8804613e-613d-4fb6-b403-5572efb9cb39
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=93859316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_direc
t.93859316
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.3573797453
Short name T200
Test name
Test status
Simulation time 9218442679 ps
CPU time 28.23 seconds
Started Jul 10 05:59:39 PM PDT 24
Finished Jul 10 06:00:08 PM PDT 24
Peak memory 224692 kb
Host smart-7efb7c0f-6541-484f-a932-618429e6e5f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573797453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.3573797453
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.3944300701
Short name T377
Test name
Test status
Simulation time 3158088018 ps
CPU time 15.72 seconds
Started Jul 10 05:59:41 PM PDT 24
Finished Jul 10 05:59:58 PM PDT 24
Peak memory 216376 kb
Host smart-c3422c34-5f55-43d7-afaa-eac591502534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944300701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.3944300701
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.610989503
Short name T610
Test name
Test status
Simulation time 1904799716 ps
CPU time 7.53 seconds
Started Jul 10 05:59:41 PM PDT 24
Finished Jul 10 05:59:51 PM PDT 24
Peak memory 216248 kb
Host smart-5f769fa1-2c7c-449a-af84-0b845f71b37f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610989503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.610989503
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.4027639372
Short name T134
Test name
Test status
Simulation time 14716378 ps
CPU time 0.92 seconds
Started Jul 10 05:59:40 PM PDT 24
Finished Jul 10 05:59:42 PM PDT 24
Peak memory 207320 kb
Host smart-4dce6a64-8579-453d-8de6-155b4d2a5ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027639372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.4027639372
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.1832121026
Short name T648
Test name
Test status
Simulation time 239548232 ps
CPU time 0.8 seconds
Started Jul 10 05:59:43 PM PDT 24
Finished Jul 10 05:59:44 PM PDT 24
Peak memory 206000 kb
Host smart-b925b5fd-9ac8-4da5-92b4-7ea87d531a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832121026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.1832121026
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.2561091665
Short name T800
Test name
Test status
Simulation time 14526398156 ps
CPU time 13.93 seconds
Started Jul 10 05:59:40 PM PDT 24
Finished Jul 10 05:59:56 PM PDT 24
Peak memory 232836 kb
Host smart-abba9b9f-634f-445f-a2f6-e48ee4489100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561091665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.2561091665
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.1956923105
Short name T741
Test name
Test status
Simulation time 14354823 ps
CPU time 0.73 seconds
Started Jul 10 05:59:44 PM PDT 24
Finished Jul 10 05:59:47 PM PDT 24
Peak memory 205568 kb
Host smart-194fdc4a-62ea-41a0-9247-b2edd5acdff9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956923105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
1956923105
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.1851863222
Short name T795
Test name
Test status
Simulation time 298476304 ps
CPU time 5.09 seconds
Started Jul 10 05:59:45 PM PDT 24
Finished Jul 10 05:59:51 PM PDT 24
Peak memory 224424 kb
Host smart-ead25b68-fdc0-4645-b8b9-74634ac78ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851863222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.1851863222
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.2048467993
Short name T876
Test name
Test status
Simulation time 24027450 ps
CPU time 0.89 seconds
Started Jul 10 05:59:44 PM PDT 24
Finished Jul 10 05:59:47 PM PDT 24
Peak memory 206604 kb
Host smart-0b2c3c7d-5726-4e06-954d-84df33aa5e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048467993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.2048467993
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.446100028
Short name T428
Test name
Test status
Simulation time 15167302012 ps
CPU time 65.91 seconds
Started Jul 10 05:59:44 PM PDT 24
Finished Jul 10 06:00:51 PM PDT 24
Peak memory 264824 kb
Host smart-c0e1fea0-1ffd-4b40-8497-c2b775bb4223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446100028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.446100028
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.3829527216
Short name T786
Test name
Test status
Simulation time 74172538882 ps
CPU time 175.37 seconds
Started Jul 10 05:59:46 PM PDT 24
Finished Jul 10 06:02:42 PM PDT 24
Peak memory 255832 kb
Host smart-828ec20b-14cd-4519-abd4-2e53c3902105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829527216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.3829527216
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.2377203440
Short name T220
Test name
Test status
Simulation time 58223446759 ps
CPU time 394.75 seconds
Started Jul 10 05:59:44 PM PDT 24
Finished Jul 10 06:06:20 PM PDT 24
Peak memory 265148 kb
Host smart-3d653544-2cdd-46b0-8a68-0db0fd191c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377203440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.2377203440
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.2460854356
Short name T413
Test name
Test status
Simulation time 1229343716 ps
CPU time 27.87 seconds
Started Jul 10 05:59:46 PM PDT 24
Finished Jul 10 06:00:15 PM PDT 24
Peak memory 241444 kb
Host smart-8ff3dec5-4650-4839-bb7c-c80d47419e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460854356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmd
s.2460854356
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.4162341169
Short name T394
Test name
Test status
Simulation time 140051891 ps
CPU time 5.56 seconds
Started Jul 10 05:59:46 PM PDT 24
Finished Jul 10 05:59:53 PM PDT 24
Peak memory 232420 kb
Host smart-a2881bcc-2056-4249-a418-83fe7d711e50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162341169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.4162341169
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.3107260569
Short name T927
Test name
Test status
Simulation time 498985155 ps
CPU time 9.43 seconds
Started Jul 10 05:59:54 PM PDT 24
Finished Jul 10 06:00:05 PM PDT 24
Peak memory 239948 kb
Host smart-cb260af8-2fc7-4252-bad9-2a4d2ef3f263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107260569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.3107260569
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.2386501471
Short name T611
Test name
Test status
Simulation time 283818070 ps
CPU time 3.1 seconds
Started Jul 10 05:59:44 PM PDT 24
Finished Jul 10 05:59:49 PM PDT 24
Peak memory 224476 kb
Host smart-796fdcd7-59d2-4261-ad48-fc4c6c19e0c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386501471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.2386501471
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.3809588711
Short name T935
Test name
Test status
Simulation time 12503409757 ps
CPU time 11.96 seconds
Started Jul 10 05:59:44 PM PDT 24
Finished Jul 10 05:59:57 PM PDT 24
Peak memory 224548 kb
Host smart-0e384c57-1584-44b4-9628-2da27292875e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809588711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.3809588711
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.1833231343
Short name T999
Test name
Test status
Simulation time 1250534248 ps
CPU time 5.15 seconds
Started Jul 10 05:59:44 PM PDT 24
Finished Jul 10 05:59:50 PM PDT 24
Peak memory 222784 kb
Host smart-e172a3fe-4c97-404b-9a05-abc6a17f764e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1833231343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.1833231343
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.3157074451
Short name T38
Test name
Test status
Simulation time 34170404267 ps
CPU time 390.61 seconds
Started Jul 10 05:59:55 PM PDT 24
Finished Jul 10 06:06:27 PM PDT 24
Peak memory 273176 kb
Host smart-07d5c0a9-b0a0-4b76-9a5c-0ab8391c0657
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157074451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.3157074451
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.2933565490
Short name T977
Test name
Test status
Simulation time 15251509 ps
CPU time 0.73 seconds
Started Jul 10 05:59:45 PM PDT 24
Finished Jul 10 05:59:47 PM PDT 24
Peak memory 205696 kb
Host smart-d5fa887f-ba02-4b2a-946b-34c980bd8f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933565490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.2933565490
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.2979792734
Short name T1001
Test name
Test status
Simulation time 394029940 ps
CPU time 2.88 seconds
Started Jul 10 05:59:46 PM PDT 24
Finished Jul 10 05:59:50 PM PDT 24
Peak memory 216200 kb
Host smart-25457bcf-619d-47e0-af8d-3df0aa6accd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979792734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.2979792734
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.3898260913
Short name T982
Test name
Test status
Simulation time 258595182 ps
CPU time 1.44 seconds
Started Jul 10 05:59:46 PM PDT 24
Finished Jul 10 05:59:49 PM PDT 24
Peak memory 216240 kb
Host smart-b550ee6f-ba57-4f55-8231-69fa253870d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898260913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.3898260913
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.1751637927
Short name T572
Test name
Test status
Simulation time 20009274 ps
CPU time 0.72 seconds
Started Jul 10 05:59:55 PM PDT 24
Finished Jul 10 05:59:57 PM PDT 24
Peak memory 205628 kb
Host smart-0819a68d-7ce1-4c8a-b4d0-c4653c6942cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751637927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.1751637927
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.1173829528
Short name T616
Test name
Test status
Simulation time 1599141082 ps
CPU time 6.81 seconds
Started Jul 10 05:59:55 PM PDT 24
Finished Jul 10 06:00:03 PM PDT 24
Peak memory 224492 kb
Host smart-d0b28bd5-3234-4856-865d-fb66a0fce26e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173829528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.1173829528
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.912429493
Short name T721
Test name
Test status
Simulation time 16282205 ps
CPU time 0.75 seconds
Started Jul 10 05:57:42 PM PDT 24
Finished Jul 10 05:57:43 PM PDT 24
Peak memory 206060 kb
Host smart-40c500ae-1e38-4ec9-b81a-78c206aa77a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912429493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.912429493
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.1406388030
Short name T195
Test name
Test status
Simulation time 199235322 ps
CPU time 4.67 seconds
Started Jul 10 05:57:36 PM PDT 24
Finished Jul 10 05:57:42 PM PDT 24
Peak memory 224404 kb
Host smart-ac4fce99-1c08-426a-a0c2-c09a6c5489f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406388030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.1406388030
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.1907968872
Short name T507
Test name
Test status
Simulation time 14612317 ps
CPU time 0.78 seconds
Started Jul 10 05:57:36 PM PDT 24
Finished Jul 10 05:57:38 PM PDT 24
Peak memory 206608 kb
Host smart-b06d7392-9ac8-4296-90e3-e3284d4e5234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907968872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.1907968872
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.2989715518
Short name T228
Test name
Test status
Simulation time 119371320950 ps
CPU time 189.27 seconds
Started Jul 10 05:57:41 PM PDT 24
Finished Jul 10 06:00:51 PM PDT 24
Peak memory 250216 kb
Host smart-f5f90f15-0922-405d-9064-f601a438aac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989715518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.2989715518
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.1059427798
Short name T35
Test name
Test status
Simulation time 13726611070 ps
CPU time 63.1 seconds
Started Jul 10 05:57:40 PM PDT 24
Finished Jul 10 05:58:44 PM PDT 24
Peak memory 248812 kb
Host smart-074c2446-cbf2-40ce-bad2-87fdf3852922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059427798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.1059427798
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.453739528
Short name T412
Test name
Test status
Simulation time 4466373883 ps
CPU time 76.4 seconds
Started Jul 10 05:57:39 PM PDT 24
Finished Jul 10 05:58:56 PM PDT 24
Peak memory 249264 kb
Host smart-81ff79df-2ff0-4432-b27e-2364799f43bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453739528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle.
453739528
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.2768151590
Short name T823
Test name
Test status
Simulation time 99427966 ps
CPU time 2.7 seconds
Started Jul 10 05:57:35 PM PDT 24
Finished Jul 10 05:57:39 PM PDT 24
Peak memory 224460 kb
Host smart-39e5a07c-62e3-4e44-84b1-04b4c3f5fbb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768151590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.2768151590
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.1411626651
Short name T844
Test name
Test status
Simulation time 142106155099 ps
CPU time 89.21 seconds
Started Jul 10 05:57:39 PM PDT 24
Finished Jul 10 05:59:09 PM PDT 24
Peak memory 239164 kb
Host smart-e3248d4e-fe6a-4762-ad04-33ed89d4a69b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411626651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds
.1411626651
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.1666530313
Short name T271
Test name
Test status
Simulation time 1937592607 ps
CPU time 17.47 seconds
Started Jul 10 05:57:43 PM PDT 24
Finished Jul 10 05:58:02 PM PDT 24
Peak memory 224448 kb
Host smart-3047e65f-ea3d-4e37-9f03-3de4c3d382e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666530313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.1666530313
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.3652023978
Short name T667
Test name
Test status
Simulation time 1251907686 ps
CPU time 8.72 seconds
Started Jul 10 05:57:37 PM PDT 24
Finished Jul 10 05:57:47 PM PDT 24
Peak memory 240184 kb
Host smart-b8bb882b-e6d1-45f8-9fa6-54ff4ef19649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652023978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.3652023978
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.3367247865
Short name T672
Test name
Test status
Simulation time 46454599969 ps
CPU time 23.82 seconds
Started Jul 10 05:57:48 PM PDT 24
Finished Jul 10 05:58:13 PM PDT 24
Peak memory 233804 kb
Host smart-760770b2-3b38-49c8-a585-a44c8bac95df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367247865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.3367247865
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.398121227
Short name T14
Test name
Test status
Simulation time 5426678047 ps
CPU time 19.43 seconds
Started Jul 10 05:57:41 PM PDT 24
Finished Jul 10 05:58:01 PM PDT 24
Peak memory 232756 kb
Host smart-4857c4f5-896f-4461-ae9f-73ab36233510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398121227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.398121227
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.243164042
Short name T845
Test name
Test status
Simulation time 64099236 ps
CPU time 3.19 seconds
Started Jul 10 05:57:43 PM PDT 24
Finished Jul 10 05:57:47 PM PDT 24
Peak memory 218760 kb
Host smart-5281171d-a4b8-4f63-8580-a18ebae873f6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=243164042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_direc
t.243164042
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.2132443410
Short name T76
Test name
Test status
Simulation time 127923526 ps
CPU time 0.94 seconds
Started Jul 10 05:57:39 PM PDT 24
Finished Jul 10 05:57:40 PM PDT 24
Peak memory 235884 kb
Host smart-99f490e8-c691-4d4f-bd71-6da0e9c2e798
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132443410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.2132443410
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.2197381394
Short name T638
Test name
Test status
Simulation time 9010951624 ps
CPU time 41.29 seconds
Started Jul 10 05:57:35 PM PDT 24
Finished Jul 10 05:58:17 PM PDT 24
Peak memory 216316 kb
Host smart-0f634b16-aa50-4284-8a5f-616aa2db9de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197381394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.2197381394
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.3071992974
Short name T619
Test name
Test status
Simulation time 557997587 ps
CPU time 2.72 seconds
Started Jul 10 05:57:48 PM PDT 24
Finished Jul 10 05:57:52 PM PDT 24
Peak memory 216108 kb
Host smart-a3ac35af-4276-4c2e-bbf9-ed111c51b4e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071992974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.3071992974
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.1501621792
Short name T427
Test name
Test status
Simulation time 16785926 ps
CPU time 0.83 seconds
Started Jul 10 05:57:36 PM PDT 24
Finished Jul 10 05:57:37 PM PDT 24
Peak memory 205976 kb
Host smart-9af1aae9-6195-4c91-9f1d-b986cf7a352c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501621792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.1501621792
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.2239436263
Short name T970
Test name
Test status
Simulation time 181669115 ps
CPU time 0.9 seconds
Started Jul 10 05:57:47 PM PDT 24
Finished Jul 10 05:57:49 PM PDT 24
Peak memory 206996 kb
Host smart-bc2ebe5f-bd14-44fe-bfb4-4ef831fe4d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239436263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.2239436263
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.1657514657
Short name T880
Test name
Test status
Simulation time 1255500523 ps
CPU time 5.24 seconds
Started Jul 10 05:57:35 PM PDT 24
Finished Jul 10 05:57:42 PM PDT 24
Peak memory 232688 kb
Host smart-50936ecb-fad5-4233-bb6e-0ee52c028bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657514657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.1657514657
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.1785978750
Short name T506
Test name
Test status
Simulation time 39314729 ps
CPU time 0.7 seconds
Started Jul 10 05:59:50 PM PDT 24
Finished Jul 10 05:59:52 PM PDT 24
Peak memory 205872 kb
Host smart-cd460c48-4670-4029-a593-27ac508d4ccc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785978750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
1785978750
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.2871525049
Short name T664
Test name
Test status
Simulation time 358446538 ps
CPU time 6.73 seconds
Started Jul 10 05:59:46 PM PDT 24
Finished Jul 10 05:59:54 PM PDT 24
Peak memory 232668 kb
Host smart-5b391d6c-35c2-46e9-aaa6-ea4ff35944bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871525049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.2871525049
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.2071638754
Short name T671
Test name
Test status
Simulation time 31483855 ps
CPU time 0.81 seconds
Started Jul 10 05:59:46 PM PDT 24
Finished Jul 10 05:59:48 PM PDT 24
Peak memory 206848 kb
Host smart-24cbb32b-2fd8-4b55-93a5-2c67260c67ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071638754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.2071638754
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.1596861508
Short name T581
Test name
Test status
Simulation time 5718253414 ps
CPU time 76.36 seconds
Started Jul 10 05:59:50 PM PDT 24
Finished Jul 10 06:01:07 PM PDT 24
Peak memory 255532 kb
Host smart-47665150-65ab-4b3a-ae5e-34f174be2065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596861508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.1596861508
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.400268630
Short name T311
Test name
Test status
Simulation time 143513428877 ps
CPU time 268.9 seconds
Started Jul 10 05:59:49 PM PDT 24
Finished Jul 10 06:04:19 PM PDT 24
Peak memory 236556 kb
Host smart-53995273-cbb3-4f42-a860-4125ee9d2beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400268630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.400268630
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.1610757240
Short name T335
Test name
Test status
Simulation time 72687261740 ps
CPU time 131.27 seconds
Started Jul 10 05:59:54 PM PDT 24
Finished Jul 10 06:02:06 PM PDT 24
Peak memory 250224 kb
Host smart-59b66b58-8eb4-4ceb-a3f6-caa3f1dc3b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610757240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.1610757240
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.3696993900
Short name T826
Test name
Test status
Simulation time 1052861474 ps
CPU time 5.19 seconds
Started Jul 10 05:59:45 PM PDT 24
Finished Jul 10 05:59:51 PM PDT 24
Peak memory 233696 kb
Host smart-5aef5fbf-5737-4c53-90db-80cff72c5032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696993900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.3696993900
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.1704795670
Short name T653
Test name
Test status
Simulation time 7941610560 ps
CPU time 51.99 seconds
Started Jul 10 05:59:49 PM PDT 24
Finished Jul 10 06:00:42 PM PDT 24
Peak memory 269256 kb
Host smart-9742c05f-3a28-46b8-901e-a494839f4912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704795670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmd
s.1704795670
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.1016940249
Short name T867
Test name
Test status
Simulation time 231852002 ps
CPU time 4.2 seconds
Started Jul 10 05:59:43 PM PDT 24
Finished Jul 10 05:59:49 PM PDT 24
Peak memory 232648 kb
Host smart-448c3152-f61b-4698-af60-f6943d790a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016940249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.1016940249
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.992546457
Short name T457
Test name
Test status
Simulation time 146704024 ps
CPU time 2.52 seconds
Started Jul 10 05:59:44 PM PDT 24
Finished Jul 10 05:59:48 PM PDT 24
Peak memory 232324 kb
Host smart-ffa3a224-f48a-4ce6-a6d0-aa5961f51afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992546457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.992546457
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.3907924645
Short name T771
Test name
Test status
Simulation time 32469052 ps
CPU time 2.35 seconds
Started Jul 10 05:59:44 PM PDT 24
Finished Jul 10 05:59:48 PM PDT 24
Peak memory 232328 kb
Host smart-56fe0f66-46ee-4735-b0cf-ea79afb05bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907924645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.3907924645
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.66225610
Short name T824
Test name
Test status
Simulation time 3129515478 ps
CPU time 14.73 seconds
Started Jul 10 05:59:47 PM PDT 24
Finished Jul 10 06:00:03 PM PDT 24
Peak memory 232712 kb
Host smart-5f4353f7-e417-4779-b45a-fa5f3fd51388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66225610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.66225610
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.2695700232
Short name T820
Test name
Test status
Simulation time 3903778660 ps
CPU time 8.14 seconds
Started Jul 10 05:59:54 PM PDT 24
Finished Jul 10 06:00:03 PM PDT 24
Peak memory 223088 kb
Host smart-afc002ba-04dc-432b-b957-fa6f220632ba
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2695700232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.2695700232
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.1372511062
Short name T21
Test name
Test status
Simulation time 84532840080 ps
CPU time 399.36 seconds
Started Jul 10 05:59:52 PM PDT 24
Finished Jul 10 06:06:32 PM PDT 24
Peak memory 257412 kb
Host smart-0e85688b-fcc5-4d4b-b6db-6907993a9b21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372511062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.1372511062
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.1957365673
Short name T537
Test name
Test status
Simulation time 66894118068 ps
CPU time 22.44 seconds
Started Jul 10 05:59:46 PM PDT 24
Finished Jul 10 06:00:10 PM PDT 24
Peak memory 220576 kb
Host smart-cb997acb-d7fa-4e08-9b27-679cfeff022a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957365673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.1957365673
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.2984156509
Short name T609
Test name
Test status
Simulation time 1750536435 ps
CPU time 2.92 seconds
Started Jul 10 05:59:45 PM PDT 24
Finished Jul 10 05:59:49 PM PDT 24
Peak memory 216196 kb
Host smart-40b3683c-4bee-438f-a959-68f03fb24e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984156509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.2984156509
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.277669029
Short name T565
Test name
Test status
Simulation time 22111143 ps
CPU time 1.15 seconds
Started Jul 10 05:59:44 PM PDT 24
Finished Jul 10 05:59:46 PM PDT 24
Peak memory 207872 kb
Host smart-86bc2506-7a9d-4ab6-82ab-249c50c98770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277669029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.277669029
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.3771458164
Short name T917
Test name
Test status
Simulation time 190270705 ps
CPU time 0.89 seconds
Started Jul 10 05:59:56 PM PDT 24
Finished Jul 10 05:59:58 PM PDT 24
Peak memory 206984 kb
Host smart-475401dd-45c7-4e72-bd29-730eebfa83a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771458164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.3771458164
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.2444606198
Short name T787
Test name
Test status
Simulation time 7477225597 ps
CPU time 26.22 seconds
Started Jul 10 05:59:44 PM PDT 24
Finished Jul 10 06:00:12 PM PDT 24
Peak memory 232756 kb
Host smart-6c20a23e-5194-4295-8f62-0186946e421c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444606198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.2444606198
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.4190980855
Short name T57
Test name
Test status
Simulation time 11863776 ps
CPU time 0.75 seconds
Started Jul 10 05:59:55 PM PDT 24
Finished Jul 10 05:59:57 PM PDT 24
Peak memory 204964 kb
Host smart-5eaf6bd2-f567-4591-b50d-3b262a5fab0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190980855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
4190980855
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.769218200
Short name T688
Test name
Test status
Simulation time 1912689007 ps
CPU time 8.6 seconds
Started Jul 10 05:59:54 PM PDT 24
Finished Jul 10 06:00:03 PM PDT 24
Peak memory 232880 kb
Host smart-ee513b71-addf-45b8-bf54-ce16002c6d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769218200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.769218200
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.1269448705
Short name T724
Test name
Test status
Simulation time 17284211 ps
CPU time 0.8 seconds
Started Jul 10 05:59:51 PM PDT 24
Finished Jul 10 05:59:53 PM PDT 24
Peak memory 206604 kb
Host smart-b866bd97-d535-4e7d-87ae-be5dc6e10493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269448705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.1269448705
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.1248553098
Short name T226
Test name
Test status
Simulation time 38455714815 ps
CPU time 260.7 seconds
Started Jul 10 05:59:55 PM PDT 24
Finished Jul 10 06:04:16 PM PDT 24
Peak memory 254256 kb
Host smart-63187184-2e5d-4fcb-8d1b-0058e9189c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248553098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.1248553098
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.780805018
Short name T564
Test name
Test status
Simulation time 8495339064 ps
CPU time 46.02 seconds
Started Jul 10 05:59:56 PM PDT 24
Finished Jul 10 06:00:44 PM PDT 24
Peak memory 249848 kb
Host smart-5bfd0f33-61f5-4b03-b3a6-bb341a2fceb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780805018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.780805018
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.4010798404
Short name T63
Test name
Test status
Simulation time 4721186996 ps
CPU time 45.49 seconds
Started Jul 10 05:59:55 PM PDT 24
Finished Jul 10 06:00:42 PM PDT 24
Peak memory 232828 kb
Host smart-8e0446c6-75ed-40ac-8c12-8ad9ecdc9a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010798404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.4010798404
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.900586169
Short name T904
Test name
Test status
Simulation time 1418362683 ps
CPU time 8.81 seconds
Started Jul 10 05:59:58 PM PDT 24
Finished Jul 10 06:00:07 PM PDT 24
Peak memory 236736 kb
Host smart-f9f65542-8426-43b0-9b52-a61b0155b729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900586169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.900586169
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.2189238004
Short name T552
Test name
Test status
Simulation time 26861486 ps
CPU time 0.81 seconds
Started Jul 10 05:59:55 PM PDT 24
Finished Jul 10 05:59:57 PM PDT 24
Peak memory 215820 kb
Host smart-af21071a-5ebf-4bda-9b20-12829cd94460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189238004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmd
s.2189238004
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.3747820630
Short name T275
Test name
Test status
Simulation time 1053537273 ps
CPU time 12.13 seconds
Started Jul 10 05:59:50 PM PDT 24
Finished Jul 10 06:00:03 PM PDT 24
Peak memory 232720 kb
Host smart-26f69833-0cee-46d4-ac96-212ab29e8546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747820630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.3747820630
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.3951629219
Short name T791
Test name
Test status
Simulation time 362008527 ps
CPU time 3.32 seconds
Started Jul 10 05:59:50 PM PDT 24
Finished Jul 10 05:59:54 PM PDT 24
Peak memory 232680 kb
Host smart-41bb1a8b-4404-412c-bba4-9d0f51f052bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951629219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.3951629219
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.2293276262
Short name T635
Test name
Test status
Simulation time 1446703564 ps
CPU time 2.72 seconds
Started Jul 10 05:59:50 PM PDT 24
Finished Jul 10 05:59:53 PM PDT 24
Peak memory 224492 kb
Host smart-2cc44dab-95ff-4a2e-9967-eff46b1feecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293276262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.2293276262
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.3479280096
Short name T998
Test name
Test status
Simulation time 16282565210 ps
CPU time 12.38 seconds
Started Jul 10 05:59:55 PM PDT 24
Finished Jul 10 06:00:09 PM PDT 24
Peak memory 224576 kb
Host smart-2dd0bbc4-12fa-473c-8a22-854649e7b200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479280096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.3479280096
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.4162599557
Short name T797
Test name
Test status
Simulation time 226360856 ps
CPU time 4.16 seconds
Started Jul 10 05:59:56 PM PDT 24
Finished Jul 10 06:00:02 PM PDT 24
Peak memory 223012 kb
Host smart-888bafff-f6fe-492f-bb30-889f5a072278
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4162599557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.4162599557
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.507193085
Short name T696
Test name
Test status
Simulation time 6202868571 ps
CPU time 81.92 seconds
Started Jul 10 05:59:57 PM PDT 24
Finished Jul 10 06:01:20 PM PDT 24
Peak memory 257196 kb
Host smart-21c3b94e-684e-405e-aa7b-d1da0a201ee6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507193085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stres
s_all.507193085
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.4221468833
Short name T881
Test name
Test status
Simulation time 1703071300 ps
CPU time 3.78 seconds
Started Jul 10 05:59:51 PM PDT 24
Finished Jul 10 05:59:55 PM PDT 24
Peak memory 216248 kb
Host smart-4f02d8a7-241c-4d3f-9f75-22d75cef5af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221468833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.4221468833
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.1696550137
Short name T32
Test name
Test status
Simulation time 546823188 ps
CPU time 3.74 seconds
Started Jul 10 05:59:51 PM PDT 24
Finished Jul 10 05:59:55 PM PDT 24
Peak memory 216172 kb
Host smart-d5795cc4-10bd-4e48-be45-b481ceca33e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696550137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.1696550137
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.3584631828
Short name T637
Test name
Test status
Simulation time 629733952 ps
CPU time 2.3 seconds
Started Jul 10 05:59:52 PM PDT 24
Finished Jul 10 05:59:55 PM PDT 24
Peak memory 216212 kb
Host smart-2beb2bf1-ea4e-458f-9259-80a98518ca60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584631828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.3584631828
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.3539355120
Short name T367
Test name
Test status
Simulation time 11478807 ps
CPU time 0.71 seconds
Started Jul 10 05:59:50 PM PDT 24
Finished Jul 10 05:59:51 PM PDT 24
Peak memory 205616 kb
Host smart-d1d65541-1fd0-4099-b57d-565d2bd532b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539355120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.3539355120
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.1336094393
Short name T677
Test name
Test status
Simulation time 468959198 ps
CPU time 4.67 seconds
Started Jul 10 05:59:51 PM PDT 24
Finished Jul 10 05:59:56 PM PDT 24
Peak memory 232668 kb
Host smart-980a18e4-a1e1-43b8-9cdc-4748e8483c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336094393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.1336094393
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.4284238848
Short name T663
Test name
Test status
Simulation time 31446880 ps
CPU time 0.73 seconds
Started Jul 10 06:00:01 PM PDT 24
Finished Jul 10 06:00:02 PM PDT 24
Peak memory 205888 kb
Host smart-dc38c848-fc73-496a-a4da-ea0a07054957
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284238848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
4284238848
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.390037986
Short name T926
Test name
Test status
Simulation time 287767747 ps
CPU time 2.87 seconds
Started Jul 10 05:59:54 PM PDT 24
Finished Jul 10 05:59:58 PM PDT 24
Peak memory 232636 kb
Host smart-928f03fe-4bf6-4ba8-a411-5bdc47a5a075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390037986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.390037986
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.1965067168
Short name T470
Test name
Test status
Simulation time 185509529 ps
CPU time 0.76 seconds
Started Jul 10 05:59:56 PM PDT 24
Finished Jul 10 05:59:58 PM PDT 24
Peak memory 205832 kb
Host smart-085f602b-fdba-4ebe-accf-be9fb385972f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965067168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.1965067168
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.3757480728
Short name T713
Test name
Test status
Simulation time 13663232096 ps
CPU time 63.71 seconds
Started Jul 10 06:00:00 PM PDT 24
Finished Jul 10 06:01:05 PM PDT 24
Peak memory 256816 kb
Host smart-075e27e6-dfea-4dd1-8e7a-46c7e4ed755d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757480728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.3757480728
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.820283098
Short name T674
Test name
Test status
Simulation time 13665864696 ps
CPU time 48.21 seconds
Started Jul 10 06:00:05 PM PDT 24
Finished Jul 10 06:00:54 PM PDT 24
Peak memory 251384 kb
Host smart-72c33f40-5f2c-48bd-8b2b-da146855a924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820283098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.820283098
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.3944850418
Short name T197
Test name
Test status
Simulation time 25627581071 ps
CPU time 297.51 seconds
Started Jul 10 05:59:59 PM PDT 24
Finished Jul 10 06:04:57 PM PDT 24
Peak memory 249256 kb
Host smart-93a850ad-f6a9-4c8f-8b63-5637ea5f9795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944850418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.3944850418
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.1868948212
Short name T397
Test name
Test status
Simulation time 161617580 ps
CPU time 6.29 seconds
Started Jul 10 06:00:02 PM PDT 24
Finished Jul 10 06:00:09 PM PDT 24
Peak memory 249092 kb
Host smart-dcf1f182-de40-4ec5-8c46-b9a70acd7117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868948212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.1868948212
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.927684687
Short name T597
Test name
Test status
Simulation time 128668385362 ps
CPU time 218.85 seconds
Started Jul 10 05:59:59 PM PDT 24
Finished Jul 10 06:03:38 PM PDT 24
Peak memory 271180 kb
Host smart-dd8b12bf-91dc-4dc9-a000-ecf99e79f3f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927684687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmds
.927684687
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.799590553
Short name T601
Test name
Test status
Simulation time 11342752684 ps
CPU time 15.7 seconds
Started Jul 10 05:59:55 PM PDT 24
Finished Jul 10 06:00:13 PM PDT 24
Peak memory 232748 kb
Host smart-64d7da5e-e8b7-4c5a-9e8c-fa92cdb79dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799590553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.799590553
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.3109804669
Short name T676
Test name
Test status
Simulation time 56666870653 ps
CPU time 102.1 seconds
Started Jul 10 05:59:57 PM PDT 24
Finished Jul 10 06:01:40 PM PDT 24
Peak memory 248776 kb
Host smart-b79458ee-3463-4619-91c8-613836eb3e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109804669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.3109804669
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.3940108624
Short name T963
Test name
Test status
Simulation time 6062354033 ps
CPU time 18.98 seconds
Started Jul 10 05:59:54 PM PDT 24
Finished Jul 10 06:00:14 PM PDT 24
Peak memory 232864 kb
Host smart-b092720c-a8ee-4198-a7e0-6bca86d820a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940108624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.3940108624
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.754944168
Short name T44
Test name
Test status
Simulation time 426037423 ps
CPU time 4.19 seconds
Started Jul 10 06:00:00 PM PDT 24
Finished Jul 10 06:00:05 PM PDT 24
Peak memory 223064 kb
Host smart-85b47394-3750-4b9e-b761-fa8b70c44234
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=754944168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dire
ct.754944168
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.3042069832
Short name T198
Test name
Test status
Simulation time 3479750510 ps
CPU time 26.13 seconds
Started Jul 10 06:00:00 PM PDT 24
Finished Jul 10 06:00:27 PM PDT 24
Peak memory 224648 kb
Host smart-f7effc18-fc0b-4399-a70b-ceb3a60edb5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042069832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.3042069832
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.2849864408
Short name T563
Test name
Test status
Simulation time 13042088473 ps
CPU time 34.56 seconds
Started Jul 10 05:59:55 PM PDT 24
Finished Jul 10 06:00:31 PM PDT 24
Peak memory 216556 kb
Host smart-b34caaef-1968-46b2-b77e-fd31fdcf1dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849864408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.2849864408
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.2676580136
Short name T712
Test name
Test status
Simulation time 2268879438 ps
CPU time 6.07 seconds
Started Jul 10 05:59:57 PM PDT 24
Finished Jul 10 06:00:04 PM PDT 24
Peak memory 216272 kb
Host smart-28c23f24-64b7-43d1-aa1d-e3477c5a433e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676580136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.2676580136
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.2649130244
Short name T683
Test name
Test status
Simulation time 30208528 ps
CPU time 1.2 seconds
Started Jul 10 05:59:56 PM PDT 24
Finished Jul 10 05:59:59 PM PDT 24
Peak memory 216284 kb
Host smart-0ea62ee9-1322-447f-a6d1-8e6c1d5aa3f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649130244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.2649130244
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.960107803
Short name T22
Test name
Test status
Simulation time 41752629 ps
CPU time 0.78 seconds
Started Jul 10 05:59:55 PM PDT 24
Finished Jul 10 05:59:57 PM PDT 24
Peak memory 205956 kb
Host smart-f1a4058c-c66c-4923-91c2-94ff083215db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960107803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.960107803
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.2291709160
Short name T59
Test name
Test status
Simulation time 947719188 ps
CPU time 7.02 seconds
Started Jul 10 05:59:57 PM PDT 24
Finished Jul 10 06:00:05 PM PDT 24
Peak memory 224528 kb
Host smart-89c0a261-e60b-4aa3-9edb-8ad7ae4c938d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291709160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.2291709160
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.870916943
Short name T66
Test name
Test status
Simulation time 16188562 ps
CPU time 0.79 seconds
Started Jul 10 06:00:07 PM PDT 24
Finished Jul 10 06:00:08 PM PDT 24
Peak memory 205860 kb
Host smart-a3d5881c-d16f-428c-bcbb-4c8f26d09f8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870916943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.870916943
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.3948181354
Short name T509
Test name
Test status
Simulation time 14765231028 ps
CPU time 15.16 seconds
Started Jul 10 06:00:03 PM PDT 24
Finished Jul 10 06:00:19 PM PDT 24
Peak memory 232812 kb
Host smart-d5551915-ea88-4fb6-90f3-c28c2a396624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948181354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.3948181354
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.2263598602
Short name T555
Test name
Test status
Simulation time 23394802 ps
CPU time 0.85 seconds
Started Jul 10 06:00:01 PM PDT 24
Finished Jul 10 06:00:03 PM PDT 24
Peak memory 206604 kb
Host smart-abde65b3-5947-4bae-ab52-fa8a5cc9814d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263598602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.2263598602
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.2342161716
Short name T402
Test name
Test status
Simulation time 385823704 ps
CPU time 5.79 seconds
Started Jul 10 06:00:07 PM PDT 24
Finished Jul 10 06:00:13 PM PDT 24
Peak memory 236472 kb
Host smart-c730902e-c44a-4565-98b6-6da947c5d1c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342161716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.2342161716
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.197743332
Short name T222
Test name
Test status
Simulation time 30879302531 ps
CPU time 117.35 seconds
Started Jul 10 06:00:04 PM PDT 24
Finished Jul 10 06:02:02 PM PDT 24
Peak memory 249252 kb
Host smart-8beed795-11c7-4c41-b373-d321844a136c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197743332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.197743332
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.3876389810
Short name T522
Test name
Test status
Simulation time 111298393187 ps
CPU time 250.69 seconds
Started Jul 10 06:00:04 PM PDT 24
Finished Jul 10 06:04:16 PM PDT 24
Peak memory 255248 kb
Host smart-ee6d267c-35b9-4af9-8c48-f8fecc1463dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876389810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.3876389810
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.2339641610
Short name T531
Test name
Test status
Simulation time 2911852533 ps
CPU time 33.35 seconds
Started Jul 10 06:00:06 PM PDT 24
Finished Jul 10 06:00:40 PM PDT 24
Peak memory 233856 kb
Host smart-377ce397-23dd-4a66-99a8-b59cdb528bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339641610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.2339641610
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.1537455947
Short name T839
Test name
Test status
Simulation time 52741456858 ps
CPU time 26.92 seconds
Started Jul 10 06:00:09 PM PDT 24
Finished Jul 10 06:00:37 PM PDT 24
Peak memory 224612 kb
Host smart-345d6d2b-8b96-4906-abb6-79ff5222a368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537455947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmd
s.1537455947
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.371693063
Short name T940
Test name
Test status
Simulation time 1281269158 ps
CPU time 15.64 seconds
Started Jul 10 06:00:00 PM PDT 24
Finished Jul 10 06:00:16 PM PDT 24
Peak memory 232648 kb
Host smart-14c910fd-ee71-488e-b1f9-590751fae661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371693063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.371693063
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.604502439
Short name T576
Test name
Test status
Simulation time 37286141 ps
CPU time 2.36 seconds
Started Jul 10 06:00:04 PM PDT 24
Finished Jul 10 06:00:08 PM PDT 24
Peak memory 232640 kb
Host smart-0c54c5c4-25c8-41ee-8280-9b1f3b507c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604502439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.604502439
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.3400764176
Short name T607
Test name
Test status
Simulation time 3217551870 ps
CPU time 6.87 seconds
Started Jul 10 06:00:03 PM PDT 24
Finished Jul 10 06:00:11 PM PDT 24
Peak memory 232260 kb
Host smart-466fa8d3-b597-40aa-8d60-f44c9817238f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400764176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.3400764176
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.2308683282
Short name T469
Test name
Test status
Simulation time 908788811 ps
CPU time 7.82 seconds
Started Jul 10 06:00:04 PM PDT 24
Finished Jul 10 06:00:12 PM PDT 24
Peak memory 232616 kb
Host smart-806d494c-36da-4d25-8c37-57ee5f4e5862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308683282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.2308683282
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.696457782
Short name T863
Test name
Test status
Simulation time 252353568 ps
CPU time 5.26 seconds
Started Jul 10 06:00:05 PM PDT 24
Finished Jul 10 06:00:12 PM PDT 24
Peak memory 219260 kb
Host smart-1c26d9e6-f137-44dd-b27b-90f9e67cc90c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=696457782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dire
ct.696457782
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.100566993
Short name T544
Test name
Test status
Simulation time 3732163353 ps
CPU time 19.89 seconds
Started Jul 10 06:00:00 PM PDT 24
Finished Jul 10 06:00:21 PM PDT 24
Peak memory 216320 kb
Host smart-ada9fcad-2655-4b15-b6a4-ae280d42144a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100566993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.100566993
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.3334325587
Short name T403
Test name
Test status
Simulation time 492603251 ps
CPU time 2.51 seconds
Started Jul 10 06:00:01 PM PDT 24
Finished Jul 10 06:00:04 PM PDT 24
Peak memory 216092 kb
Host smart-baaa536d-88d0-4f17-b441-cf61f8738a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334325587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.3334325587
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.2664829143
Short name T373
Test name
Test status
Simulation time 74677680 ps
CPU time 0.99 seconds
Started Jul 10 06:00:01 PM PDT 24
Finished Jul 10 06:00:02 PM PDT 24
Peak memory 205980 kb
Host smart-8dc7dbf0-3b9c-41c9-97a3-df8be5fc114a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664829143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.2664829143
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.1928388625
Short name T971
Test name
Test status
Simulation time 4286150040 ps
CPU time 18.63 seconds
Started Jul 10 06:00:05 PM PDT 24
Finished Jul 10 06:00:24 PM PDT 24
Peak memory 241164 kb
Host smart-9d5411c1-0f47-4125-ad0e-99a240d3b526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928388625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.1928388625
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.1132354793
Short name T986
Test name
Test status
Simulation time 54688155 ps
CPU time 0.74 seconds
Started Jul 10 06:00:11 PM PDT 24
Finished Jul 10 06:00:13 PM PDT 24
Peak memory 205564 kb
Host smart-29c97776-4392-4127-90ed-7af2a0ca1c4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132354793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
1132354793
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.131081722
Short name T252
Test name
Test status
Simulation time 275276040 ps
CPU time 2.36 seconds
Started Jul 10 06:00:11 PM PDT 24
Finished Jul 10 06:00:14 PM PDT 24
Peak memory 224684 kb
Host smart-6b5a2267-df5d-4d7a-88c9-c94c841d64f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131081722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.131081722
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.2878852595
Short name T381
Test name
Test status
Simulation time 23621905 ps
CPU time 0.9 seconds
Started Jul 10 06:00:02 PM PDT 24
Finished Jul 10 06:00:04 PM PDT 24
Peak memory 206596 kb
Host smart-0090f79c-683f-44cf-aa40-d3a0004e6a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878852595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.2878852595
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.4092289725
Short name T212
Test name
Test status
Simulation time 6822760701 ps
CPU time 94.95 seconds
Started Jul 10 06:00:09 PM PDT 24
Finished Jul 10 06:01:46 PM PDT 24
Peak memory 251088 kb
Host smart-89bbc25f-6f6b-4d53-80aa-0d98d2bfec52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092289725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.4092289725
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.779030468
Short name T51
Test name
Test status
Simulation time 55256665820 ps
CPU time 228.68 seconds
Started Jul 10 06:00:10 PM PDT 24
Finished Jul 10 06:04:00 PM PDT 24
Peak memory 265656 kb
Host smart-b5b9047d-6cec-4f74-9668-e1252542d8a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779030468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.779030468
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.2984809417
Short name T297
Test name
Test status
Simulation time 12086853137 ps
CPU time 67.36 seconds
Started Jul 10 06:00:09 PM PDT 24
Finished Jul 10 06:01:17 PM PDT 24
Peak memory 257156 kb
Host smart-bf92b4dd-f70b-4724-b706-07316beed821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984809417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.2984809417
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.1803082391
Short name T96
Test name
Test status
Simulation time 6438758187 ps
CPU time 39.8 seconds
Started Jul 10 06:00:10 PM PDT 24
Finished Jul 10 06:00:51 PM PDT 24
Peak memory 241024 kb
Host smart-9447246f-646f-4e8b-a40c-42e231350714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803082391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.1803082391
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.4101926729
Short name T241
Test name
Test status
Simulation time 8019845559 ps
CPU time 62.76 seconds
Started Jul 10 06:00:10 PM PDT 24
Finished Jul 10 06:01:14 PM PDT 24
Peak memory 254044 kb
Host smart-795370fb-5905-4500-b63a-179178bb1ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101926729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmd
s.4101926729
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.4217922963
Short name T519
Test name
Test status
Simulation time 4269543600 ps
CPU time 19 seconds
Started Jul 10 06:00:09 PM PDT 24
Finished Jul 10 06:00:29 PM PDT 24
Peak memory 232824 kb
Host smart-df194bdd-6aa7-4137-aae0-65eb716cec3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217922963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.4217922963
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.2693653500
Short name T255
Test name
Test status
Simulation time 3262844035 ps
CPU time 32.94 seconds
Started Jul 10 06:00:11 PM PDT 24
Finished Jul 10 06:00:45 PM PDT 24
Peak memory 249168 kb
Host smart-58606f1b-ccc3-43c6-9c4a-ca865f91b954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693653500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.2693653500
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.1774738074
Short name T46
Test name
Test status
Simulation time 4248965760 ps
CPU time 7.46 seconds
Started Jul 10 06:00:05 PM PDT 24
Finished Jul 10 06:00:14 PM PDT 24
Peak memory 224472 kb
Host smart-c266c3b8-498c-4867-af93-198d0ec8c4e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774738074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.1774738074
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.732904258
Short name T645
Test name
Test status
Simulation time 164033985 ps
CPU time 2.88 seconds
Started Jul 10 06:00:09 PM PDT 24
Finished Jul 10 06:00:13 PM PDT 24
Peak memory 224504 kb
Host smart-472adbc3-5296-412f-9292-3af1ea50935b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732904258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.732904258
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.2653758371
Short name T520
Test name
Test status
Simulation time 785983750 ps
CPU time 5.2 seconds
Started Jul 10 06:00:09 PM PDT 24
Finished Jul 10 06:00:15 PM PDT 24
Peak memory 222044 kb
Host smart-1f9b72b0-2df0-46e4-bdda-bd054a1990db
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2653758371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.2653758371
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.2990659747
Short name T37
Test name
Test status
Simulation time 138009983111 ps
CPU time 323.77 seconds
Started Jul 10 06:00:10 PM PDT 24
Finished Jul 10 06:05:36 PM PDT 24
Peak memory 250892 kb
Host smart-4fedbb36-bb5a-4220-a8af-f523d98ebde0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990659747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.2990659747
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.861924499
Short name T832
Test name
Test status
Simulation time 36893230 ps
CPU time 0.76 seconds
Started Jul 10 06:00:05 PM PDT 24
Finished Jul 10 06:00:07 PM PDT 24
Peak memory 205728 kb
Host smart-5c13148e-54ff-48e8-84d3-df601a718ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861924499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.861924499
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.856566024
Short name T890
Test name
Test status
Simulation time 226813853 ps
CPU time 1.3 seconds
Started Jul 10 06:00:04 PM PDT 24
Finished Jul 10 06:00:06 PM PDT 24
Peak memory 207864 kb
Host smart-ffe1b012-5926-444b-92a0-91c88579f891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856566024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.856566024
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.1720690381
Short name T662
Test name
Test status
Simulation time 94256818 ps
CPU time 1.01 seconds
Started Jul 10 06:00:07 PM PDT 24
Finished Jul 10 06:00:09 PM PDT 24
Peak memory 207348 kb
Host smart-bfa057c4-c187-43ee-85a8-1a72622df649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720690381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.1720690381
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.4165342882
Short name T972
Test name
Test status
Simulation time 79071236 ps
CPU time 0.74 seconds
Started Jul 10 06:00:04 PM PDT 24
Finished Jul 10 06:00:06 PM PDT 24
Peak memory 205984 kb
Host smart-1d03be01-e090-4c97-99ce-f504b4500e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165342882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.4165342882
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.2873551682
Short name T260
Test name
Test status
Simulation time 771778590 ps
CPU time 4.49 seconds
Started Jul 10 06:00:10 PM PDT 24
Finished Jul 10 06:00:16 PM PDT 24
Peak memory 224448 kb
Host smart-8fa4d6ff-f19f-4af3-ad77-d3570fbba835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873551682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.2873551682
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.2501368539
Short name T825
Test name
Test status
Simulation time 221243885 ps
CPU time 0.76 seconds
Started Jul 10 06:00:14 PM PDT 24
Finished Jul 10 06:00:15 PM PDT 24
Peak memory 205868 kb
Host smart-70b4bc95-ffdf-49bd-908e-fc04cd9472f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501368539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
2501368539
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.3002242943
Short name T902
Test name
Test status
Simulation time 692876815 ps
CPU time 8.03 seconds
Started Jul 10 06:00:14 PM PDT 24
Finished Jul 10 06:00:23 PM PDT 24
Peak memory 232672 kb
Host smart-2c74d410-3c65-4a50-96f3-8ba739074db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002242943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.3002242943
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.3702918406
Short name T368
Test name
Test status
Simulation time 77421610 ps
CPU time 0.85 seconds
Started Jul 10 06:00:09 PM PDT 24
Finished Jul 10 06:00:12 PM PDT 24
Peak memory 206596 kb
Host smart-8dd5330f-9a83-449e-8f97-3a2eb06fe1eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702918406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.3702918406
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.2809017497
Short name T213
Test name
Test status
Simulation time 10675010823 ps
CPU time 87.58 seconds
Started Jul 10 06:00:15 PM PDT 24
Finished Jul 10 06:01:44 PM PDT 24
Peak memory 240996 kb
Host smart-b7b147c8-f8ba-4187-b299-383a2cf741a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809017497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.2809017497
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.2028035455
Short name T891
Test name
Test status
Simulation time 5689086031 ps
CPU time 78.39 seconds
Started Jul 10 06:00:16 PM PDT 24
Finished Jul 10 06:01:35 PM PDT 24
Peak memory 249268 kb
Host smart-0387f81e-ec93-44a6-b741-12dd1d73f7a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028035455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.2028035455
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.288088601
Short name T60
Test name
Test status
Simulation time 5788352208 ps
CPU time 52.8 seconds
Started Jul 10 06:00:15 PM PDT 24
Finished Jul 10 06:01:09 PM PDT 24
Peak memory 252644 kb
Host smart-88a9a97b-d153-4fc4-b744-ed1bf1e2fa91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288088601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idle
.288088601
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.355722600
Short name T495
Test name
Test status
Simulation time 47035222 ps
CPU time 3.06 seconds
Started Jul 10 06:00:18 PM PDT 24
Finished Jul 10 06:00:22 PM PDT 24
Peak memory 232640 kb
Host smart-a27f3ac5-344d-4bb4-ab8a-58b9188c0ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355722600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.355722600
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.3039815325
Short name T550
Test name
Test status
Simulation time 12960565951 ps
CPU time 86.28 seconds
Started Jul 10 06:00:16 PM PDT 24
Finished Jul 10 06:01:43 PM PDT 24
Peak memory 255336 kb
Host smart-995cc7ad-e3c9-4920-987d-a0dd6ecc959f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039815325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmd
s.3039815325
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.3537419080
Short name T400
Test name
Test status
Simulation time 87894721 ps
CPU time 2.12 seconds
Started Jul 10 06:00:13 PM PDT 24
Finished Jul 10 06:00:16 PM PDT 24
Peak memory 223092 kb
Host smart-dc086702-b9c1-4869-8c32-65da17a2eec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537419080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.3537419080
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.1053780384
Short name T991
Test name
Test status
Simulation time 79006863 ps
CPU time 2.3 seconds
Started Jul 10 06:00:18 PM PDT 24
Finished Jul 10 06:00:21 PM PDT 24
Peak memory 224088 kb
Host smart-4955a061-1c2a-4c85-acf2-7f57b2808c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053780384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.1053780384
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.758868783
Short name T632
Test name
Test status
Simulation time 4441832892 ps
CPU time 7.66 seconds
Started Jul 10 06:00:08 PM PDT 24
Finished Jul 10 06:00:17 PM PDT 24
Peak memory 232740 kb
Host smart-0e600ec6-0c13-46e0-9ecf-42e47701a2a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758868783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swap
.758868783
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.2559753825
Short name T139
Test name
Test status
Simulation time 10591345354 ps
CPU time 18.52 seconds
Started Jul 10 06:00:09 PM PDT 24
Finished Jul 10 06:00:28 PM PDT 24
Peak memory 232756 kb
Host smart-5466f6ca-6c09-49fa-9c8a-9065f0dcbf16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559753825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.2559753825
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.3395522282
Short name T481
Test name
Test status
Simulation time 4699872251 ps
CPU time 7.23 seconds
Started Jul 10 06:00:14 PM PDT 24
Finished Jul 10 06:00:22 PM PDT 24
Peak memory 223344 kb
Host smart-61fa705f-2d0e-480c-8151-80f3375a96ba
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3395522282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.3395522282
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.1614394404
Short name T72
Test name
Test status
Simulation time 192925273 ps
CPU time 0.98 seconds
Started Jul 10 06:00:16 PM PDT 24
Finished Jul 10 06:00:17 PM PDT 24
Peak memory 207400 kb
Host smart-04ca6a5b-aa80-4990-8d02-cd5a8091dc5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614394404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.1614394404
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.1917992862
Short name T84
Test name
Test status
Simulation time 3571271006 ps
CPU time 21.98 seconds
Started Jul 10 06:00:09 PM PDT 24
Finished Jul 10 06:00:32 PM PDT 24
Peak memory 220112 kb
Host smart-3fcb5357-e906-4e3e-8ab0-5d525af47f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917992862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.1917992862
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.1687849770
Short name T85
Test name
Test status
Simulation time 543401230 ps
CPU time 3.88 seconds
Started Jul 10 06:00:10 PM PDT 24
Finished Jul 10 06:00:15 PM PDT 24
Peak memory 216252 kb
Host smart-8c462cba-7849-4d04-9ff6-a7e28cbe6112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687849770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.1687849770
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.2872079637
Short name T586
Test name
Test status
Simulation time 20292804 ps
CPU time 0.86 seconds
Started Jul 10 06:00:08 PM PDT 24
Finished Jul 10 06:00:09 PM PDT 24
Peak memory 205988 kb
Host smart-9e51fd4c-3b54-4fb1-ace5-f92de1ea407c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872079637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.2872079637
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.2427203179
Short name T23
Test name
Test status
Simulation time 160789297 ps
CPU time 0.84 seconds
Started Jul 10 06:00:09 PM PDT 24
Finished Jul 10 06:00:12 PM PDT 24
Peak memory 205980 kb
Host smart-50c9da7e-f831-4ca2-a602-2348f1f75ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427203179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.2427203179
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.3166522302
Short name T897
Test name
Test status
Simulation time 2518798118 ps
CPU time 8.46 seconds
Started Jul 10 06:00:17 PM PDT 24
Finished Jul 10 06:00:26 PM PDT 24
Peak memory 224804 kb
Host smart-2dd53921-1c4f-4cd6-ae12-1a69c3f479fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166522302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.3166522302
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.2316524092
Short name T360
Test name
Test status
Simulation time 13219562 ps
CPU time 0.79 seconds
Started Jul 10 06:00:24 PM PDT 24
Finished Jul 10 06:00:27 PM PDT 24
Peak memory 205548 kb
Host smart-e48904ba-b904-466e-92c7-cf3c40035f87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316524092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
2316524092
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.1697350026
Short name T603
Test name
Test status
Simulation time 354138384 ps
CPU time 4.83 seconds
Started Jul 10 06:00:24 PM PDT 24
Finished Jul 10 06:00:30 PM PDT 24
Peak memory 232652 kb
Host smart-d47c3104-fb99-4749-ac1d-0ab7ae5e3a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697350026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.1697350026
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.1590644276
Short name T496
Test name
Test status
Simulation time 17721762 ps
CPU time 0.82 seconds
Started Jul 10 06:00:17 PM PDT 24
Finished Jul 10 06:00:19 PM PDT 24
Peak memory 205564 kb
Host smart-9c3dad62-10d7-4f06-a7f2-20b819de4795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590644276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.1590644276
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.1439214907
Short name T836
Test name
Test status
Simulation time 282879051368 ps
CPU time 387.28 seconds
Started Jul 10 06:00:22 PM PDT 24
Finished Jul 10 06:06:52 PM PDT 24
Peak memory 252076 kb
Host smart-694079b6-63ba-47ef-ad10-66395ce4877e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439214907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.1439214907
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.2280293930
Short name T596
Test name
Test status
Simulation time 7843270662 ps
CPU time 68.31 seconds
Started Jul 10 06:00:23 PM PDT 24
Finished Jul 10 06:01:33 PM PDT 24
Peak memory 249224 kb
Host smart-8ea4df44-5954-4578-b590-348db8e67feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280293930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.2280293930
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.1065095910
Short name T391
Test name
Test status
Simulation time 5193995948 ps
CPU time 8.56 seconds
Started Jul 10 06:00:24 PM PDT 24
Finished Jul 10 06:00:34 PM PDT 24
Peak memory 234384 kb
Host smart-cb5c1120-e151-4733-ae8b-ab4e26f70769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065095910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.1065095910
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.3250693655
Short name T302
Test name
Test status
Simulation time 23380195713 ps
CPU time 174.41 seconds
Started Jul 10 06:00:23 PM PDT 24
Finished Jul 10 06:03:19 PM PDT 24
Peak memory 249184 kb
Host smart-5c0fb778-2209-40f0-b263-5e75b489af9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250693655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.3250693655
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.477279022
Short name T641
Test name
Test status
Simulation time 1374665013 ps
CPU time 3.64 seconds
Started Jul 10 06:00:22 PM PDT 24
Finished Jul 10 06:00:27 PM PDT 24
Peak memory 232688 kb
Host smart-27c71ddf-1550-4444-be18-835ac8cf8085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477279022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.477279022
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.451590877
Short name T97
Test name
Test status
Simulation time 71956760969 ps
CPU time 57.96 seconds
Started Jul 10 06:00:23 PM PDT 24
Finished Jul 10 06:01:23 PM PDT 24
Peak memory 234044 kb
Host smart-99318799-1c63-4ef5-9f0b-1e2b27292465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451590877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.451590877
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.3532286712
Short name T646
Test name
Test status
Simulation time 2766098061 ps
CPU time 6.39 seconds
Started Jul 10 06:00:22 PM PDT 24
Finished Jul 10 06:00:31 PM PDT 24
Peak memory 232764 kb
Host smart-a16e9574-211e-4f84-bc6d-6bb75d929ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532286712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.3532286712
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.72884044
Short name T675
Test name
Test status
Simulation time 2826848197 ps
CPU time 7.34 seconds
Started Jul 10 06:00:22 PM PDT 24
Finished Jul 10 06:00:31 PM PDT 24
Peak memory 238424 kb
Host smart-0c43c98a-0374-4d3e-a232-3f6ac0f1ce55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72884044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.72884044
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.807618562
Short name T869
Test name
Test status
Simulation time 134663930 ps
CPU time 4.48 seconds
Started Jul 10 06:00:22 PM PDT 24
Finished Jul 10 06:00:29 PM PDT 24
Peak memory 223008 kb
Host smart-5ab954cb-83d1-43df-b8a5-ae9cfae7cbc4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=807618562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dire
ct.807618562
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.2898869099
Short name T165
Test name
Test status
Simulation time 518031858221 ps
CPU time 301.52 seconds
Started Jul 10 06:00:23 PM PDT 24
Finished Jul 10 06:05:27 PM PDT 24
Peak memory 257476 kb
Host smart-0b0285c9-2b70-46f6-9692-a905585da79c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898869099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.2898869099
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.3086363774
Short name T551
Test name
Test status
Simulation time 2127273142 ps
CPU time 18.55 seconds
Started Jul 10 06:00:18 PM PDT 24
Finished Jul 10 06:00:37 PM PDT 24
Peak memory 216268 kb
Host smart-d33acff4-840b-4aee-8e08-c9bd9f3252fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086363774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.3086363774
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.3485446728
Short name T439
Test name
Test status
Simulation time 6269890397 ps
CPU time 5.01 seconds
Started Jul 10 06:00:15 PM PDT 24
Finished Jul 10 06:00:21 PM PDT 24
Peak memory 216308 kb
Host smart-8ce8d0d6-da95-4bff-8aa8-b78b2f96fa41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485446728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.3485446728
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.4221657460
Short name T538
Test name
Test status
Simulation time 166277949 ps
CPU time 1.31 seconds
Started Jul 10 06:00:22 PM PDT 24
Finished Jul 10 06:00:25 PM PDT 24
Peak memory 216188 kb
Host smart-6fb52901-c36d-47c8-8fba-b71104ae97ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221657460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.4221657460
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.1578968212
Short name T417
Test name
Test status
Simulation time 144295559 ps
CPU time 0.86 seconds
Started Jul 10 06:00:18 PM PDT 24
Finished Jul 10 06:00:20 PM PDT 24
Peak memory 205980 kb
Host smart-092e6d29-8fc7-4d73-a131-399692637fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578968212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.1578968212
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.3406909315
Short name T910
Test name
Test status
Simulation time 13420921721 ps
CPU time 14.5 seconds
Started Jul 10 06:00:22 PM PDT 24
Finished Jul 10 06:00:37 PM PDT 24
Peak memory 239484 kb
Host smart-43e8e905-6060-47fb-80cb-d6e062cba131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406909315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.3406909315
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.1521607517
Short name T947
Test name
Test status
Simulation time 10279750 ps
CPU time 0.74 seconds
Started Jul 10 06:00:31 PM PDT 24
Finished Jul 10 06:00:34 PM PDT 24
Peak memory 205868 kb
Host smart-2a0f33a7-9eaa-48e0-b016-df3474a2ec35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521607517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
1521607517
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.178751003
Short name T256
Test name
Test status
Simulation time 766320523 ps
CPU time 5.61 seconds
Started Jul 10 06:00:22 PM PDT 24
Finished Jul 10 06:00:30 PM PDT 24
Peak memory 224492 kb
Host smart-0f91d263-123b-4db5-9f96-e2e5713eeb1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178751003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.178751003
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.1291807536
Short name T338
Test name
Test status
Simulation time 24463962 ps
CPU time 0.78 seconds
Started Jul 10 06:00:22 PM PDT 24
Finished Jul 10 06:00:24 PM PDT 24
Peak memory 205632 kb
Host smart-8dc97e7a-bcf0-4bc9-a546-0aa158d20bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291807536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.1291807536
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.666986766
Short name T691
Test name
Test status
Simulation time 6130038832 ps
CPU time 44.45 seconds
Started Jul 10 06:00:21 PM PDT 24
Finished Jul 10 06:01:06 PM PDT 24
Peak memory 253188 kb
Host smart-1a2e5eae-f360-4ab7-8b76-46b47170ffaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666986766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.666986766
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.3198833900
Short name T939
Test name
Test status
Simulation time 28075674946 ps
CPU time 41.02 seconds
Started Jul 10 06:00:24 PM PDT 24
Finished Jul 10 06:01:07 PM PDT 24
Peak memory 254268 kb
Host smart-a3e8f318-0012-443b-87e9-2b8206382bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198833900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.3198833900
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.3863558442
Short name T287
Test name
Test status
Simulation time 57184444053 ps
CPU time 293.98 seconds
Started Jul 10 06:00:30 PM PDT 24
Finished Jul 10 06:05:26 PM PDT 24
Peak memory 254644 kb
Host smart-70a8d79e-f8aa-4b01-a7ce-9f1d8989c34b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863558442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.3863558442
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.2173521918
Short name T175
Test name
Test status
Simulation time 10276366684 ps
CPU time 10.94 seconds
Started Jul 10 06:00:22 PM PDT 24
Finished Jul 10 06:00:35 PM PDT 24
Peak memory 241036 kb
Host smart-fb9a9ef3-f981-4070-9855-8d3b6edfe29b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173521918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.2173521918
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.593570095
Short name T210
Test name
Test status
Simulation time 242265740 ps
CPU time 3.27 seconds
Started Jul 10 06:00:22 PM PDT 24
Finished Jul 10 06:00:26 PM PDT 24
Peak memory 232656 kb
Host smart-f58c1f08-f78f-4ca5-932b-1554785c5e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593570095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.593570095
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.4246962583
Short name T560
Test name
Test status
Simulation time 825112639 ps
CPU time 13.68 seconds
Started Jul 10 06:00:23 PM PDT 24
Finished Jul 10 06:00:39 PM PDT 24
Peak memory 232696 kb
Host smart-652abae4-6a89-4ae9-b9d9-12e0ed739651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246962583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.4246962583
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.2539905933
Short name T476
Test name
Test status
Simulation time 114655494 ps
CPU time 2.34 seconds
Started Jul 10 06:00:22 PM PDT 24
Finished Jul 10 06:00:27 PM PDT 24
Peak memory 218392 kb
Host smart-d145425d-dddc-440c-bbf2-5846360e8a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539905933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.2539905933
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.396482114
Short name T594
Test name
Test status
Simulation time 3104732409 ps
CPU time 6.56 seconds
Started Jul 10 06:00:24 PM PDT 24
Finished Jul 10 06:00:32 PM PDT 24
Peak memory 224764 kb
Host smart-f70661ac-59c7-456c-8650-3ad135e5e760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396482114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.396482114
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.913493286
Short name T462
Test name
Test status
Simulation time 1012841423 ps
CPU time 4.85 seconds
Started Jul 10 06:00:23 PM PDT 24
Finished Jul 10 06:00:30 PM PDT 24
Peak memory 223052 kb
Host smart-3901b8e0-eae5-4850-ae28-46aabb21b34a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=913493286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dire
ct.913493286
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.71939013
Short name T162
Test name
Test status
Simulation time 52191167649 ps
CPU time 434.25 seconds
Started Jul 10 06:00:28 PM PDT 24
Finished Jul 10 06:07:44 PM PDT 24
Peak memory 253572 kb
Host smart-4474ef7a-44d3-4536-9bde-80c2ddf6c519
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71939013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stress
_all.71939013
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.1135956513
Short name T33
Test name
Test status
Simulation time 1430042184 ps
CPU time 10.98 seconds
Started Jul 10 06:00:21 PM PDT 24
Finished Jul 10 06:00:33 PM PDT 24
Peak memory 218884 kb
Host smart-75a54d9c-9b88-46b3-a1c7-daf85129fcb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135956513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.1135956513
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.337612432
Short name T357
Test name
Test status
Simulation time 8549308459 ps
CPU time 23.08 seconds
Started Jul 10 06:00:22 PM PDT 24
Finished Jul 10 06:00:48 PM PDT 24
Peak memory 216336 kb
Host smart-e0ff3cb7-dab0-4ce1-8a52-1ec3015d574b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337612432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.337612432
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.2723993808
Short name T355
Test name
Test status
Simulation time 11581038 ps
CPU time 0.73 seconds
Started Jul 10 06:00:22 PM PDT 24
Finished Jul 10 06:00:24 PM PDT 24
Peak memory 205612 kb
Host smart-e17ccafa-5bd8-4639-a87f-1fc1fb3f5f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723993808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.2723993808
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.1124869888
Short name T423
Test name
Test status
Simulation time 153632450 ps
CPU time 0.89 seconds
Started Jul 10 06:00:22 PM PDT 24
Finished Jul 10 06:00:25 PM PDT 24
Peak memory 205996 kb
Host smart-3b128b87-b4d9-42dc-b371-af9090c8e148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124869888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.1124869888
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.2069371482
Short name T763
Test name
Test status
Simulation time 638609009 ps
CPU time 3.91 seconds
Started Jul 10 06:00:21 PM PDT 24
Finished Jul 10 06:00:26 PM PDT 24
Peak memory 232728 kb
Host smart-a66cf406-1282-43cb-a890-842a58f6ad50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069371482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.2069371482
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.2851363163
Short name T665
Test name
Test status
Simulation time 16960433 ps
CPU time 0.7 seconds
Started Jul 10 06:00:29 PM PDT 24
Finished Jul 10 06:00:31 PM PDT 24
Peak memory 205560 kb
Host smart-ec445b32-2d49-4895-adfc-9db9e2b05725
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851363163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
2851363163
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.819332336
Short name T540
Test name
Test status
Simulation time 122118602 ps
CPU time 2.68 seconds
Started Jul 10 06:00:31 PM PDT 24
Finished Jul 10 06:00:36 PM PDT 24
Peak memory 224420 kb
Host smart-d88e0473-0650-41cf-9541-d9e9769fb7be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819332336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.819332336
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.3544825004
Short name T534
Test name
Test status
Simulation time 58907122 ps
CPU time 0.8 seconds
Started Jul 10 06:00:30 PM PDT 24
Finished Jul 10 06:00:33 PM PDT 24
Peak memory 206608 kb
Host smart-ed593e44-f3fc-4ad7-adb3-19bb0f801ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544825004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.3544825004
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.2555690191
Short name T234
Test name
Test status
Simulation time 3921706973 ps
CPU time 26.5 seconds
Started Jul 10 06:00:30 PM PDT 24
Finished Jul 10 06:00:58 PM PDT 24
Peak memory 233804 kb
Host smart-8c77a2e7-2817-43d7-a579-8d9909937ce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555690191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.2555690191
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.760806947
Short name T239
Test name
Test status
Simulation time 6811754972 ps
CPU time 91.75 seconds
Started Jul 10 06:00:29 PM PDT 24
Finished Jul 10 06:02:03 PM PDT 24
Peak memory 261896 kb
Host smart-ecd4a6e1-3f8c-475e-9adf-5868dd1350ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760806947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.760806947
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.1171786737
Short name T1010
Test name
Test status
Simulation time 46880663298 ps
CPU time 94.34 seconds
Started Jul 10 06:00:28 PM PDT 24
Finished Jul 10 06:02:04 PM PDT 24
Peak memory 249576 kb
Host smart-bb4e63c2-9197-49e7-bfbf-a83c07a095ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171786737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.1171786737
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.311333937
Short name T151
Test name
Test status
Simulation time 903493858 ps
CPU time 10.01 seconds
Started Jul 10 06:00:36 PM PDT 24
Finished Jul 10 06:00:48 PM PDT 24
Peak memory 250172 kb
Host smart-bbea7507-f0cc-46be-b3c0-566aed466f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311333937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.311333937
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.4163704245
Short name T533
Test name
Test status
Simulation time 12953584334 ps
CPU time 41.51 seconds
Started Jul 10 06:00:36 PM PDT 24
Finished Jul 10 06:01:19 PM PDT 24
Peak memory 232772 kb
Host smart-4728330e-3b41-4068-97f1-6423803c74a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163704245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmd
s.4163704245
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.2864763211
Short name T909
Test name
Test status
Simulation time 157574744 ps
CPU time 2.64 seconds
Started Jul 10 06:00:34 PM PDT 24
Finished Jul 10 06:00:38 PM PDT 24
Peak memory 232628 kb
Host smart-e942b9b9-5696-4451-a2b6-1a071e751be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864763211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.2864763211
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.4028510870
Short name T644
Test name
Test status
Simulation time 53330304 ps
CPU time 2.24 seconds
Started Jul 10 06:00:30 PM PDT 24
Finished Jul 10 06:00:34 PM PDT 24
Peak memory 223788 kb
Host smart-742c4ca1-398d-438d-9a62-5a54e857cbf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028510870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.4028510870
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.1698394043
Short name T512
Test name
Test status
Simulation time 1968395904 ps
CPU time 3.53 seconds
Started Jul 10 06:00:30 PM PDT 24
Finished Jul 10 06:00:35 PM PDT 24
Peak memory 224456 kb
Host smart-02f5feec-8111-4173-a373-ef69c8f64a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698394043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.1698394043
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.1263247996
Short name T141
Test name
Test status
Simulation time 3152519475 ps
CPU time 9.84 seconds
Started Jul 10 06:00:30 PM PDT 24
Finished Jul 10 06:00:41 PM PDT 24
Peak memory 232760 kb
Host smart-e4acdd75-26fc-423c-bb09-5709f74169dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263247996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.1263247996
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.1030364085
Short name T1015
Test name
Test status
Simulation time 190476502 ps
CPU time 3.66 seconds
Started Jul 10 06:00:36 PM PDT 24
Finished Jul 10 06:00:42 PM PDT 24
Peak memory 220080 kb
Host smart-374bd63d-aead-4888-9a82-8a6f1fa4ada5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1030364085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.1030364085
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.2573263949
Short name T518
Test name
Test status
Simulation time 27631308568 ps
CPU time 30.85 seconds
Started Jul 10 06:00:32 PM PDT 24
Finished Jul 10 06:01:05 PM PDT 24
Peak memory 249312 kb
Host smart-1c32a1cc-cf4e-401f-ae85-d48d82156691
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573263949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.2573263949
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.1019122435
Short name T61
Test name
Test status
Simulation time 13563300082 ps
CPU time 20.5 seconds
Started Jul 10 06:00:29 PM PDT 24
Finished Jul 10 06:00:51 PM PDT 24
Peak memory 216712 kb
Host smart-7b9f7b3c-f6ec-4293-b013-7677b75d455b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019122435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.1019122435
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.1786508872
Short name T870
Test name
Test status
Simulation time 613744524 ps
CPU time 2.05 seconds
Started Jul 10 06:00:30 PM PDT 24
Finished Jul 10 06:00:34 PM PDT 24
Peak memory 216132 kb
Host smart-5effbeed-0b51-40c3-8fe5-61fb90b122c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786508872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.1786508872
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.2529856024
Short name T388
Test name
Test status
Simulation time 37823025 ps
CPU time 1.99 seconds
Started Jul 10 06:00:30 PM PDT 24
Finished Jul 10 06:00:34 PM PDT 24
Peak memory 216232 kb
Host smart-4ba15d19-8336-4a1d-a5f2-5de75e097771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529856024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.2529856024
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.1475555356
Short name T895
Test name
Test status
Simulation time 66551355 ps
CPU time 0.94 seconds
Started Jul 10 06:00:36 PM PDT 24
Finished Jul 10 06:00:38 PM PDT 24
Peak memory 206000 kb
Host smart-d796e340-492b-4676-bbb1-310da5555a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475555356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.1475555356
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.1705915777
Short name T262
Test name
Test status
Simulation time 95362147 ps
CPU time 2.7 seconds
Started Jul 10 06:00:34 PM PDT 24
Finished Jul 10 06:00:38 PM PDT 24
Peak memory 232676 kb
Host smart-7e06602b-8b20-4bdd-8452-dda53b15315b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705915777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.1705915777
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.3327510677
Short name T387
Test name
Test status
Simulation time 35658690 ps
CPU time 0.76 seconds
Started Jul 10 06:00:39 PM PDT 24
Finished Jul 10 06:00:43 PM PDT 24
Peak memory 205572 kb
Host smart-b325bf76-ac77-4b29-ad73-2209707e22c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327510677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
3327510677
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.2550957197
Short name T608
Test name
Test status
Simulation time 5258710328 ps
CPU time 7.51 seconds
Started Jul 10 06:00:29 PM PDT 24
Finished Jul 10 06:00:38 PM PDT 24
Peak memory 232720 kb
Host smart-59aac411-1080-43ee-b388-bed965f00b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550957197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.2550957197
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.3771291914
Short name T350
Test name
Test status
Simulation time 34640515 ps
CPU time 0.8 seconds
Started Jul 10 06:00:31 PM PDT 24
Finished Jul 10 06:00:34 PM PDT 24
Peak memory 206592 kb
Host smart-627c55e9-2bf6-4cf3-9b5b-85c01969b0d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771291914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.3771291914
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.327473009
Short name T831
Test name
Test status
Simulation time 11296829091 ps
CPU time 60.98 seconds
Started Jul 10 06:00:38 PM PDT 24
Finished Jul 10 06:01:42 PM PDT 24
Peak memory 255536 kb
Host smart-0bb9739e-af9a-47af-9e3c-66b51486ec69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327473009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.327473009
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.3587859641
Short name T309
Test name
Test status
Simulation time 59273322958 ps
CPU time 132.88 seconds
Started Jul 10 06:00:37 PM PDT 24
Finished Jul 10 06:02:53 PM PDT 24
Peak memory 237868 kb
Host smart-a0599ac8-0547-4876-be2d-0fd677996985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587859641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.3587859641
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.927730266
Short name T219
Test name
Test status
Simulation time 23998927910 ps
CPU time 161.69 seconds
Started Jul 10 06:00:37 PM PDT 24
Finished Jul 10 06:03:21 PM PDT 24
Peak memory 265456 kb
Host smart-f1762c14-50ab-4f3b-8d0c-a4080d6f0e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927730266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idle
.927730266
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.1226926690
Short name T736
Test name
Test status
Simulation time 166219043 ps
CPU time 4.03 seconds
Started Jul 10 06:00:37 PM PDT 24
Finished Jul 10 06:00:44 PM PDT 24
Peak memory 224480 kb
Host smart-542e0239-c7ca-478d-8cb7-11061c917d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226926690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.1226926690
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.2778109623
Short name T45
Test name
Test status
Simulation time 32298140757 ps
CPU time 74.23 seconds
Started Jul 10 06:00:36 PM PDT 24
Finished Jul 10 06:01:53 PM PDT 24
Peak memory 257104 kb
Host smart-9888602b-f17f-459f-8840-ecd5b89eb615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778109623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmd
s.2778109623
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.3075780009
Short name T642
Test name
Test status
Simulation time 98945100 ps
CPU time 2.44 seconds
Started Jul 10 06:00:32 PM PDT 24
Finished Jul 10 06:00:36 PM PDT 24
Peak memory 232412 kb
Host smart-b7dca987-369a-4f34-8a26-1ce966160b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075780009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.3075780009
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.4025654790
Short name T39
Test name
Test status
Simulation time 75118321 ps
CPU time 2.22 seconds
Started Jul 10 06:00:28 PM PDT 24
Finished Jul 10 06:00:32 PM PDT 24
Peak memory 223884 kb
Host smart-da510403-d8da-4fea-8acf-5d03437f24f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025654790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.4025654790
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.591312690
Short name T588
Test name
Test status
Simulation time 77506374 ps
CPU time 2.16 seconds
Started Jul 10 06:00:30 PM PDT 24
Finished Jul 10 06:00:35 PM PDT 24
Peak memory 224440 kb
Host smart-4781c32c-6c0a-4f3f-aaa5-60735cb31f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591312690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swap
.591312690
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.571054137
Short name T687
Test name
Test status
Simulation time 5186697848 ps
CPU time 14.85 seconds
Started Jul 10 06:00:29 PM PDT 24
Finished Jul 10 06:00:45 PM PDT 24
Peak memory 232808 kb
Host smart-d37e2d75-1aa6-4893-831b-b8a06484a55d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571054137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.571054137
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.1670995293
Short name T499
Test name
Test status
Simulation time 371868688 ps
CPU time 6.58 seconds
Started Jul 10 06:00:36 PM PDT 24
Finished Jul 10 06:00:45 PM PDT 24
Peak memory 223004 kb
Host smart-3b59d870-de37-42c3-af23-6092c2712bd4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1670995293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.1670995293
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.2250541873
Short name T634
Test name
Test status
Simulation time 10391689214 ps
CPU time 29.74 seconds
Started Jul 10 06:00:31 PM PDT 24
Finished Jul 10 06:01:02 PM PDT 24
Peak memory 216504 kb
Host smart-92502f63-debb-4ffb-83ea-1c60ca84d3d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250541873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.2250541873
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.583259018
Short name T941
Test name
Test status
Simulation time 974573122 ps
CPU time 6.15 seconds
Started Jul 10 06:00:31 PM PDT 24
Finished Jul 10 06:00:39 PM PDT 24
Peak memory 216168 kb
Host smart-3b98c709-8dac-4ff7-af1f-1bf44fe4295d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583259018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.583259018
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.209510996
Short name T814
Test name
Test status
Simulation time 176777971 ps
CPU time 1.16 seconds
Started Jul 10 06:00:31 PM PDT 24
Finished Jul 10 06:00:34 PM PDT 24
Peak memory 207984 kb
Host smart-90ab4f1b-3914-48f4-b6a4-72398366cd44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209510996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.209510996
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.1174412303
Short name T477
Test name
Test status
Simulation time 88514027 ps
CPU time 1.07 seconds
Started Jul 10 06:00:30 PM PDT 24
Finished Jul 10 06:00:32 PM PDT 24
Peak memory 206968 kb
Host smart-06d4f8f3-c1ec-4a3d-992d-20888db5f25e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174412303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.1174412303
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.3677628044
Short name T266
Test name
Test status
Simulation time 854656883 ps
CPU time 5.78 seconds
Started Jul 10 06:00:31 PM PDT 24
Finished Jul 10 06:00:39 PM PDT 24
Peak memory 232712 kb
Host smart-ee4eac70-bf12-4685-a3fa-2dbb88d5e744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677628044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.3677628044
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.1101542982
Short name T705
Test name
Test status
Simulation time 43521217 ps
CPU time 0.72 seconds
Started Jul 10 05:57:57 PM PDT 24
Finished Jul 10 05:57:59 PM PDT 24
Peak memory 204968 kb
Host smart-b9af2ca4-a40a-4142-88d1-08296f0bb187
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101542982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.1
101542982
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.4223566017
Short name T693
Test name
Test status
Simulation time 94134669 ps
CPU time 2.49 seconds
Started Jul 10 05:57:46 PM PDT 24
Finished Jul 10 05:57:49 PM PDT 24
Peak memory 224456 kb
Host smart-cc12e7cd-8d8f-45db-8559-449291787b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223566017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.4223566017
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.4017856545
Short name T853
Test name
Test status
Simulation time 14966612 ps
CPU time 0.8 seconds
Started Jul 10 05:57:40 PM PDT 24
Finished Jul 10 05:57:42 PM PDT 24
Peak memory 206576 kb
Host smart-2bf086a2-3aee-4b1a-a02c-4c106fb6b88c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017856545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.4017856545
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.4091642616
Short name T209
Test name
Test status
Simulation time 13219785226 ps
CPU time 51.83 seconds
Started Jul 10 05:57:52 PM PDT 24
Finished Jul 10 05:58:45 PM PDT 24
Peak memory 251040 kb
Host smart-56659414-0c04-4ba2-9311-9e04ae5622de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091642616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.4091642616
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.100603719
Short name T54
Test name
Test status
Simulation time 4688033691 ps
CPU time 48.72 seconds
Started Jul 10 05:57:52 PM PDT 24
Finished Jul 10 05:58:42 PM PDT 24
Peak memory 251012 kb
Host smart-bc4d13e3-fed5-4caf-b324-cc81123aec19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100603719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.100603719
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.1489560668
Short name T955
Test name
Test status
Simulation time 9182385669 ps
CPU time 44.45 seconds
Started Jul 10 05:57:55 PM PDT 24
Finished Jul 10 05:58:41 PM PDT 24
Peak memory 256560 kb
Host smart-f9ee261b-a943-4b83-bb17-3783e6a7b7dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489560668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.1489560668
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.1806562593
Short name T12
Test name
Test status
Simulation time 371344389 ps
CPU time 4.23 seconds
Started Jul 10 05:57:47 PM PDT 24
Finished Jul 10 05:57:53 PM PDT 24
Peak memory 224380 kb
Host smart-e24e2a97-7474-46da-8d0f-441c222b6fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806562593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.1806562593
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.3039272876
Short name T40
Test name
Test status
Simulation time 85521035371 ps
CPU time 116.7 seconds
Started Jul 10 05:57:48 PM PDT 24
Finished Jul 10 05:59:46 PM PDT 24
Peak memory 252256 kb
Host smart-1bb333f0-cbc3-4b2d-9de7-ecec1df7ce52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039272876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds
.3039272876
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.1667388226
Short name T623
Test name
Test status
Simulation time 115865802 ps
CPU time 2.57 seconds
Started Jul 10 05:57:47 PM PDT 24
Finished Jul 10 05:57:51 PM PDT 24
Peak memory 232636 kb
Host smart-f9a7b56b-7e1b-4e6a-8b85-8e5c8e149e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667388226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.1667388226
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.3817113471
Short name T253
Test name
Test status
Simulation time 7969847546 ps
CPU time 14.07 seconds
Started Jul 10 05:57:49 PM PDT 24
Finished Jul 10 05:58:04 PM PDT 24
Peak memory 232728 kb
Host smart-ab97e480-4dec-4be8-8b43-5ae6c1a0335b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817113471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.3817113471
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.2548993193
Short name T286
Test name
Test status
Simulation time 21719200767 ps
CPU time 18.12 seconds
Started Jul 10 05:57:47 PM PDT 24
Finished Jul 10 05:58:06 PM PDT 24
Peak memory 232736 kb
Host smart-999a00c8-72d7-4f10-9602-d693cde36a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548993193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.2548993193
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.746591461
Short name T218
Test name
Test status
Simulation time 44065500954 ps
CPU time 26.89 seconds
Started Jul 10 05:57:47 PM PDT 24
Finished Jul 10 05:58:14 PM PDT 24
Peak memory 248336 kb
Host smart-1e1daa29-337d-4f2d-8f5b-91f8d53e62b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746591461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.746591461
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.3647987019
Short name T973
Test name
Test status
Simulation time 2058599170 ps
CPU time 7.96 seconds
Started Jul 10 05:57:54 PM PDT 24
Finished Jul 10 05:58:03 PM PDT 24
Peak memory 222040 kb
Host smart-18e35be3-603d-43ce-b149-19a65e29f5f0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3647987019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.3647987019
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.3385401186
Short name T75
Test name
Test status
Simulation time 55555239 ps
CPU time 1.11 seconds
Started Jul 10 05:57:54 PM PDT 24
Finished Jul 10 05:57:57 PM PDT 24
Peak memory 235972 kb
Host smart-786e4d3b-7bca-4444-b97a-66e51722ad98
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385401186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.3385401186
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.393404920
Short name T578
Test name
Test status
Simulation time 4691046187 ps
CPU time 19.22 seconds
Started Jul 10 05:57:48 PM PDT 24
Finished Jul 10 05:58:08 PM PDT 24
Peak memory 216372 kb
Host smart-e90ca0e8-b056-48ff-b6fd-6321426eff87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393404920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.393404920
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.299183790
Short name T431
Test name
Test status
Simulation time 999412658 ps
CPU time 3.35 seconds
Started Jul 10 05:57:41 PM PDT 24
Finished Jul 10 05:57:45 PM PDT 24
Peak memory 216200 kb
Host smart-b3f1fac2-f843-4bda-b16e-508df0da337e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299183790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.299183790
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.3057605662
Short name T380
Test name
Test status
Simulation time 390369591 ps
CPU time 3.04 seconds
Started Jul 10 05:57:47 PM PDT 24
Finished Jul 10 05:57:50 PM PDT 24
Peak memory 216188 kb
Host smart-1f6e0751-028f-4e83-9870-789dc585f208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057605662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.3057605662
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.4001714304
Short name T29
Test name
Test status
Simulation time 17556633 ps
CPU time 0.79 seconds
Started Jul 10 05:57:47 PM PDT 24
Finished Jul 10 05:57:49 PM PDT 24
Peak memory 205980 kb
Host smart-3a99e0e1-6b8f-473d-b8b6-729f8bb3069a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001714304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.4001714304
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.1966475788
Short name T847
Test name
Test status
Simulation time 2617569310 ps
CPU time 4.02 seconds
Started Jul 10 05:57:49 PM PDT 24
Finished Jul 10 05:57:54 PM PDT 24
Peak memory 224568 kb
Host smart-8a59d2bf-ba91-4db2-b0f3-5c876fcf3a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966475788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.1966475788
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.3674610604
Short name T575
Test name
Test status
Simulation time 17560491 ps
CPU time 0.75 seconds
Started Jul 10 06:00:37 PM PDT 24
Finished Jul 10 06:00:41 PM PDT 24
Peak memory 205508 kb
Host smart-b6583e2e-f575-448f-8541-9b72990e6d98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674610604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
3674610604
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.1188611006
Short name T415
Test name
Test status
Simulation time 199663640 ps
CPU time 2.48 seconds
Started Jul 10 06:00:36 PM PDT 24
Finished Jul 10 06:00:41 PM PDT 24
Peak memory 224456 kb
Host smart-aec9f18d-d010-4e8a-86ca-fe8aab79e5da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188611006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.1188611006
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.1990861892
Short name T482
Test name
Test status
Simulation time 62251160 ps
CPU time 0.77 seconds
Started Jul 10 06:00:38 PM PDT 24
Finished Jul 10 06:00:42 PM PDT 24
Peak memory 205904 kb
Host smart-96f3105c-db13-40ec-b722-78c986a41b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990861892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.1990861892
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.4207533506
Short name T514
Test name
Test status
Simulation time 307641311 ps
CPU time 4.83 seconds
Started Jul 10 06:00:38 PM PDT 24
Finished Jul 10 06:00:46 PM PDT 24
Peak memory 234120 kb
Host smart-11432d70-3db3-49d1-a496-2f764a046981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207533506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.4207533506
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.2510094044
Short name T442
Test name
Test status
Simulation time 17478430409 ps
CPU time 48.94 seconds
Started Jul 10 06:00:37 PM PDT 24
Finished Jul 10 06:01:30 PM PDT 24
Peak memory 249224 kb
Host smart-cec71507-f19f-440d-b265-35037d997336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510094044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.2510094044
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.1738846171
Short name T957
Test name
Test status
Simulation time 106163229685 ps
CPU time 170.96 seconds
Started Jul 10 06:00:40 PM PDT 24
Finished Jul 10 06:03:34 PM PDT 24
Peak memory 249552 kb
Host smart-bc350dad-14ad-4b81-b260-372e5cb51123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738846171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.1738846171
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.2373607050
Short name T326
Test name
Test status
Simulation time 17015159206 ps
CPU time 19.4 seconds
Started Jul 10 06:00:36 PM PDT 24
Finished Jul 10 06:00:59 PM PDT 24
Peak memory 224600 kb
Host smart-28a3d1ce-a593-44df-8033-f53d8a9b1c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373607050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.2373607050
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.4130228623
Short name T78
Test name
Test status
Simulation time 13420451721 ps
CPU time 87.67 seconds
Started Jul 10 06:00:37 PM PDT 24
Finished Jul 10 06:02:07 PM PDT 24
Peak memory 260660 kb
Host smart-062f5fe6-9e82-4007-814e-04cd2b5d19f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130228623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmd
s.4130228623
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.2636110079
Short name T727
Test name
Test status
Simulation time 3219668701 ps
CPU time 10.57 seconds
Started Jul 10 06:00:35 PM PDT 24
Finished Jul 10 06:00:47 PM PDT 24
Peak memory 224600 kb
Host smart-4d4b3b2d-a298-443b-a6c8-0ccefc9b9173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636110079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.2636110079
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.2336196281
Short name T508
Test name
Test status
Simulation time 296642270 ps
CPU time 8.09 seconds
Started Jul 10 06:00:39 PM PDT 24
Finished Jul 10 06:00:50 PM PDT 24
Peak memory 232720 kb
Host smart-6b4e5c94-eff2-44e7-a9cc-3b4cbbb3a865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336196281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.2336196281
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.3318595103
Short name T558
Test name
Test status
Simulation time 30913836842 ps
CPU time 21.05 seconds
Started Jul 10 06:00:37 PM PDT 24
Finished Jul 10 06:01:01 PM PDT 24
Peak memory 239940 kb
Host smart-814cd9a2-284a-454d-9f97-d0e65c57f80f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318595103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.3318595103
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.2406365959
Short name T395
Test name
Test status
Simulation time 12763330868 ps
CPU time 18.57 seconds
Started Jul 10 06:00:36 PM PDT 24
Finished Jul 10 06:00:56 PM PDT 24
Peak memory 224624 kb
Host smart-0b0edce3-d2b9-4a8f-bfae-208b51dc8a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406365959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.2406365959
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.504430448
Short name T371
Test name
Test status
Simulation time 808608541 ps
CPU time 6.42 seconds
Started Jul 10 06:00:36 PM PDT 24
Finished Jul 10 06:00:46 PM PDT 24
Peak memory 223056 kb
Host smart-c2e029bf-5808-40af-bc01-8d48e042e965
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=504430448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dire
ct.504430448
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.680852970
Short name T20
Test name
Test status
Simulation time 768177884 ps
CPU time 0.99 seconds
Started Jul 10 06:00:40 PM PDT 24
Finished Jul 10 06:00:44 PM PDT 24
Peak memory 207596 kb
Host smart-2f126000-71df-4762-8c3e-ddf102744599
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680852970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stres
s_all.680852970
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.3635710554
Short name T331
Test name
Test status
Simulation time 949428687 ps
CPU time 7.89 seconds
Started Jul 10 06:00:37 PM PDT 24
Finished Jul 10 06:00:48 PM PDT 24
Peak memory 219340 kb
Host smart-9e443bd2-42ad-4708-a511-c68bc22eb369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635710554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.3635710554
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.446165758
Short name T928
Test name
Test status
Simulation time 19402307 ps
CPU time 0.73 seconds
Started Jul 10 06:00:37 PM PDT 24
Finished Jul 10 06:00:42 PM PDT 24
Peak memory 205704 kb
Host smart-0077ae5a-de87-49e8-a0ff-b0589a487943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446165758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.446165758
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.3285106212
Short name T343
Test name
Test status
Simulation time 114444911 ps
CPU time 1.05 seconds
Started Jul 10 06:00:40 PM PDT 24
Finished Jul 10 06:00:44 PM PDT 24
Peak memory 206732 kb
Host smart-d8637a6d-e72a-4f50-86e8-becb73679590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285106212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.3285106212
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.1340247646
Short name T421
Test name
Test status
Simulation time 204662017 ps
CPU time 0.89 seconds
Started Jul 10 06:00:40 PM PDT 24
Finished Jul 10 06:00:44 PM PDT 24
Peak memory 205972 kb
Host smart-f89ccee1-f30f-4848-a2aa-63459114cbe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340247646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.1340247646
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.635910767
Short name T884
Test name
Test status
Simulation time 312619580 ps
CPU time 2.46 seconds
Started Jul 10 06:00:38 PM PDT 24
Finished Jul 10 06:00:43 PM PDT 24
Peak memory 224128 kb
Host smart-0dd01c07-87f4-485b-b70b-7074ceab1ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635910767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.635910767
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.732816955
Short name T399
Test name
Test status
Simulation time 17461695 ps
CPU time 0.74 seconds
Started Jul 10 06:00:47 PM PDT 24
Finished Jul 10 06:00:49 PM PDT 24
Peak memory 205528 kb
Host smart-3e0a488e-f83a-4043-9389-e15cde791919
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732816955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.732816955
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.1522429243
Short name T885
Test name
Test status
Simulation time 156317331 ps
CPU time 3.04 seconds
Started Jul 10 06:00:47 PM PDT 24
Finished Jul 10 06:00:51 PM PDT 24
Peak memory 224456 kb
Host smart-61234f17-c4b5-40dc-a531-3bccfa9711f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522429243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.1522429243
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.1927884910
Short name T2
Test name
Test status
Simulation time 19822675 ps
CPU time 0.83 seconds
Started Jul 10 06:00:38 PM PDT 24
Finished Jul 10 06:00:42 PM PDT 24
Peak memory 206604 kb
Host smart-36715a39-7e1d-4f56-9a6e-83460fa046d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927884910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.1927884910
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.1860990488
Short name T299
Test name
Test status
Simulation time 5147392320 ps
CPU time 68 seconds
Started Jul 10 06:00:43 PM PDT 24
Finished Jul 10 06:01:52 PM PDT 24
Peak memory 251656 kb
Host smart-48ccb13a-55e4-41e0-937c-1fe9f542783a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860990488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.1860990488
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.2204413119
Short name T315
Test name
Test status
Simulation time 26399440358 ps
CPU time 322.21 seconds
Started Jul 10 06:00:40 PM PDT 24
Finished Jul 10 06:06:05 PM PDT 24
Peak memory 262092 kb
Host smart-872e234b-aab2-46f3-9b00-14b39253c5bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204413119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.2204413119
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.109250933
Short name T444
Test name
Test status
Simulation time 5178192863 ps
CPU time 40.15 seconds
Started Jul 10 06:00:41 PM PDT 24
Finished Jul 10 06:01:23 PM PDT 24
Peak memory 224628 kb
Host smart-44053b95-a877-4306-b3f8-c0a8b7c0478f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109250933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idle
.109250933
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.4030765611
Short name T319
Test name
Test status
Simulation time 931004536 ps
CPU time 9.18 seconds
Started Jul 10 06:00:42 PM PDT 24
Finished Jul 10 06:00:53 PM PDT 24
Peak memory 232712 kb
Host smart-6d1508c3-2f16-49bf-982c-909f0bc56c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030765611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.4030765611
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.2259678174
Short name T264
Test name
Test status
Simulation time 18914128232 ps
CPU time 68.89 seconds
Started Jul 10 06:00:47 PM PDT 24
Finished Jul 10 06:01:57 PM PDT 24
Peak memory 250616 kb
Host smart-d7e49ee6-a55a-4d56-a87f-835862f24add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259678174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmd
s.2259678174
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.3332080116
Short name T573
Test name
Test status
Simulation time 1832253559 ps
CPU time 7.38 seconds
Started Jul 10 06:00:41 PM PDT 24
Finished Jul 10 06:00:51 PM PDT 24
Peak memory 232652 kb
Host smart-fe8884ab-b416-4404-91cd-1a211122b797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332080116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.3332080116
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.1415512409
Short name T984
Test name
Test status
Simulation time 22797047193 ps
CPU time 71.39 seconds
Started Jul 10 06:00:39 PM PDT 24
Finished Jul 10 06:01:53 PM PDT 24
Peak memory 240488 kb
Host smart-8e180af4-60e9-4c7a-9f45-72eb55065704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415512409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.1415512409
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.1271578230
Short name T48
Test name
Test status
Simulation time 12694004627 ps
CPU time 11.36 seconds
Started Jul 10 06:00:38 PM PDT 24
Finished Jul 10 06:00:52 PM PDT 24
Peak memory 224592 kb
Host smart-2df77009-0dcf-4bf1-b408-242b25ec146f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271578230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.1271578230
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.3276295679
Short name T554
Test name
Test status
Simulation time 378088234 ps
CPU time 6.25 seconds
Started Jul 10 06:00:37 PM PDT 24
Finished Jul 10 06:00:47 PM PDT 24
Peak memory 238268 kb
Host smart-7aec3ecf-8813-4610-9621-74990c866d4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276295679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.3276295679
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.3257697287
Short name T964
Test name
Test status
Simulation time 169464495 ps
CPU time 4.51 seconds
Started Jul 10 06:00:40 PM PDT 24
Finished Jul 10 06:00:48 PM PDT 24
Peak memory 222404 kb
Host smart-61d7e88d-4a75-42db-84f9-ff0e7d5a3bfa
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3257697287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.3257697287
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.2776501380
Short name T689
Test name
Test status
Simulation time 14057853548 ps
CPU time 27.47 seconds
Started Jul 10 06:00:37 PM PDT 24
Finished Jul 10 06:01:07 PM PDT 24
Peak memory 216684 kb
Host smart-79cf06b7-ff81-4c35-ba2f-bdcf6d7abe14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776501380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.2776501380
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.204464965
Short name T411
Test name
Test status
Simulation time 3452972316 ps
CPU time 10.38 seconds
Started Jul 10 06:00:36 PM PDT 24
Finished Jul 10 06:00:49 PM PDT 24
Peak memory 216316 kb
Host smart-1f0713b6-7900-4e51-bfb4-df4d5301029e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204464965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.204464965
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.738855705
Short name T435
Test name
Test status
Simulation time 59783158 ps
CPU time 1.09 seconds
Started Jul 10 06:00:36 PM PDT 24
Finished Jul 10 06:00:39 PM PDT 24
Peak memory 207476 kb
Host smart-6f656526-de31-42aa-9b10-f85f8dd2119a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738855705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.738855705
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.1685161401
Short name T452
Test name
Test status
Simulation time 81615291 ps
CPU time 1.05 seconds
Started Jul 10 06:00:38 PM PDT 24
Finished Jul 10 06:00:42 PM PDT 24
Peak memory 207000 kb
Host smart-edd8b3a5-5b02-4c5e-87f1-378b1fb9a1a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685161401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.1685161401
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.1482658362
Short name T862
Test name
Test status
Simulation time 5805291871 ps
CPU time 21.32 seconds
Started Jul 10 06:00:42 PM PDT 24
Finished Jul 10 06:01:05 PM PDT 24
Peak memory 232828 kb
Host smart-d8b2a201-17f3-48f4-8938-2fb5b1798c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482658362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.1482658362
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.1180161859
Short name T436
Test name
Test status
Simulation time 119067991 ps
CPU time 0.71 seconds
Started Jul 10 06:00:51 PM PDT 24
Finished Jul 10 06:00:54 PM PDT 24
Peak memory 204976 kb
Host smart-7e57c181-be79-4546-a948-f0b72385b7d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180161859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
1180161859
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.1759389704
Short name T969
Test name
Test status
Simulation time 140152062 ps
CPU time 3.64 seconds
Started Jul 10 06:00:47 PM PDT 24
Finished Jul 10 06:00:52 PM PDT 24
Peak memory 224280 kb
Host smart-355daac3-5541-49f6-b0f1-cc133a01988a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759389704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.1759389704
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.1509811840
Short name T834
Test name
Test status
Simulation time 78282498 ps
CPU time 0.76 seconds
Started Jul 10 06:00:42 PM PDT 24
Finished Jul 10 06:00:45 PM PDT 24
Peak memory 206592 kb
Host smart-e1abfea4-ba17-477b-918e-a26c66d9c3b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509811840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.1509811840
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.699437734
Short name T238
Test name
Test status
Simulation time 28522839636 ps
CPU time 71.19 seconds
Started Jul 10 06:00:42 PM PDT 24
Finished Jul 10 06:01:55 PM PDT 24
Peak memory 250504 kb
Host smart-e7cee48e-097d-4f5e-a88d-7484c9135466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699437734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.699437734
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.3630133450
Short name T1004
Test name
Test status
Simulation time 29126541815 ps
CPU time 67.08 seconds
Started Jul 10 06:00:40 PM PDT 24
Finished Jul 10 06:01:50 PM PDT 24
Peak memory 249220 kb
Host smart-0382b72e-3cfb-4664-b99c-f2670aaf1b7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630133450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.3630133450
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.1470037937
Short name T466
Test name
Test status
Simulation time 78408818681 ps
CPU time 111.26 seconds
Started Jul 10 06:00:47 PM PDT 24
Finished Jul 10 06:02:40 PM PDT 24
Peak memory 249220 kb
Host smart-d595f89b-c74a-4ab8-bbb3-935c2dcb2745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470037937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.1470037937
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.686937475
Short name T454
Test name
Test status
Simulation time 8871952902 ps
CPU time 20.28 seconds
Started Jul 10 06:00:44 PM PDT 24
Finished Jul 10 06:01:06 PM PDT 24
Peak memory 232796 kb
Host smart-835b6b63-a3bc-4054-be12-905ffde6c996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686937475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.686937475
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.2293127547
Short name T784
Test name
Test status
Simulation time 45012773 ps
CPU time 0.94 seconds
Started Jul 10 06:00:44 PM PDT 24
Finished Jul 10 06:00:46 PM PDT 24
Peak memory 215936 kb
Host smart-e456f9f7-021e-4561-9ea2-2530bddb5318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293127547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmd
s.2293127547
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.47045706
Short name T655
Test name
Test status
Simulation time 498456326 ps
CPU time 4.73 seconds
Started Jul 10 06:00:43 PM PDT 24
Finished Jul 10 06:00:50 PM PDT 24
Peak memory 218748 kb
Host smart-078078cf-495e-4629-bb79-6a79a6193c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47045706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.47045706
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.2772952381
Short name T714
Test name
Test status
Simulation time 1517217075 ps
CPU time 9.97 seconds
Started Jul 10 06:00:42 PM PDT 24
Finished Jul 10 06:00:54 PM PDT 24
Peak memory 224500 kb
Host smart-38ac3a83-981e-4f36-83e5-d2b2833391e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772952381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.2772952381
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.3120144000
Short name T720
Test name
Test status
Simulation time 492815197 ps
CPU time 2.73 seconds
Started Jul 10 06:00:42 PM PDT 24
Finished Jul 10 06:00:47 PM PDT 24
Peak memory 224404 kb
Host smart-97e161cf-ddce-41a3-9a69-01a5fe8c807b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120144000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.3120144000
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.2709800484
Short name T295
Test name
Test status
Simulation time 2153192641 ps
CPU time 8.98 seconds
Started Jul 10 06:00:40 PM PDT 24
Finished Jul 10 06:00:52 PM PDT 24
Peak memory 232696 kb
Host smart-f0e4ade7-b576-48e7-92fe-639e4cf09763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709800484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.2709800484
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.4044043393
Short name T383
Test name
Test status
Simulation time 299291361 ps
CPU time 3.63 seconds
Started Jul 10 06:00:41 PM PDT 24
Finished Jul 10 06:00:47 PM PDT 24
Peak memory 219440 kb
Host smart-6ae089e9-9031-4638-aa83-0bdb54bdc538
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4044043393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.4044043393
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.1850230618
Short name T489
Test name
Test status
Simulation time 100196371551 ps
CPU time 126.98 seconds
Started Jul 10 06:00:50 PM PDT 24
Finished Jul 10 06:02:58 PM PDT 24
Peak memory 249252 kb
Host smart-10255c66-ffb4-42c1-bc55-f7dc714e0785
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850230618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.1850230618
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.2198419561
Short name T848
Test name
Test status
Simulation time 5732171465 ps
CPU time 14.12 seconds
Started Jul 10 06:00:41 PM PDT 24
Finished Jul 10 06:00:57 PM PDT 24
Peak memory 216264 kb
Host smart-99e1a025-ed59-4cec-873f-72b8c10bef47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198419561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.2198419561
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.889354959
Short name T472
Test name
Test status
Simulation time 134901387 ps
CPU time 1.19 seconds
Started Jul 10 06:00:41 PM PDT 24
Finished Jul 10 06:00:45 PM PDT 24
Peak memory 207892 kb
Host smart-a2f7ceef-89fb-4590-b55f-7a1354341a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889354959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.889354959
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.3707705919
Short name T58
Test name
Test status
Simulation time 18997513 ps
CPU time 0.81 seconds
Started Jul 10 06:00:42 PM PDT 24
Finished Jul 10 06:00:45 PM PDT 24
Peak memory 205972 kb
Host smart-1cc04e3a-8898-4489-8709-e9a8a90a85f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707705919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.3707705919
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.1083955288
Short name T871
Test name
Test status
Simulation time 66633764 ps
CPU time 0.74 seconds
Started Jul 10 06:00:41 PM PDT 24
Finished Jul 10 06:00:44 PM PDT 24
Peak memory 205968 kb
Host smart-b025c7f1-ccf5-4d53-a467-1a1189047683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083955288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.1083955288
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.2486688912
Short name T293
Test name
Test status
Simulation time 8828622575 ps
CPU time 10.67 seconds
Started Jul 10 06:00:41 PM PDT 24
Finished Jul 10 06:00:54 PM PDT 24
Peak memory 232860 kb
Host smart-23cd0bce-daca-4991-afdc-996ffa8ae201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486688912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.2486688912
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.2478814919
Short name T629
Test name
Test status
Simulation time 36956350 ps
CPU time 0.76 seconds
Started Jul 10 06:00:55 PM PDT 24
Finished Jul 10 06:00:57 PM PDT 24
Peak memory 205848 kb
Host smart-1f60ac6d-9b7c-4a72-9bf2-4f0ad9364aea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478814919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
2478814919
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.2209944832
Short name T658
Test name
Test status
Simulation time 1135518112 ps
CPU time 5.79 seconds
Started Jul 10 06:00:50 PM PDT 24
Finished Jul 10 06:00:58 PM PDT 24
Peak memory 224440 kb
Host smart-d2fb1360-98e5-4dc6-a7cc-d5297672c1e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209944832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.2209944832
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.159234727
Short name T358
Test name
Test status
Simulation time 31112262 ps
CPU time 0.78 seconds
Started Jul 10 06:00:50 PM PDT 24
Finished Jul 10 06:00:52 PM PDT 24
Peak memory 206916 kb
Host smart-9961c7f8-2a3f-4716-881c-f573d38587f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159234727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.159234727
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.953881853
Short name T497
Test name
Test status
Simulation time 16409750221 ps
CPU time 86.63 seconds
Started Jul 10 06:00:49 PM PDT 24
Finished Jul 10 06:02:17 PM PDT 24
Peak memory 249276 kb
Host smart-97b8beb6-aaa7-4af5-967c-29fed71f5230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953881853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.953881853
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.1255806117
Short name T580
Test name
Test status
Simulation time 8441081133 ps
CPU time 67.71 seconds
Started Jul 10 06:00:49 PM PDT 24
Finished Jul 10 06:01:57 PM PDT 24
Peak memory 250596 kb
Host smart-39ae35e2-474f-4ba4-ac8e-4b097b7ca73c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255806117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.1255806117
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.654247953
Short name T728
Test name
Test status
Simulation time 46861331243 ps
CPU time 222.86 seconds
Started Jul 10 06:00:47 PM PDT 24
Finished Jul 10 06:04:31 PM PDT 24
Peak memory 249268 kb
Host smart-dfb6659a-b54c-497a-a299-174bb86d57d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654247953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idle
.654247953
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.1050752160
Short name T56
Test name
Test status
Simulation time 621877580 ps
CPU time 7.01 seconds
Started Jul 10 06:00:46 PM PDT 24
Finished Jul 10 06:00:54 PM PDT 24
Peak memory 232920 kb
Host smart-fe887b4d-e53f-4e53-9d89-c780b9ea63bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050752160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.1050752160
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.792603502
Short name T589
Test name
Test status
Simulation time 1115201601 ps
CPU time 18.08 seconds
Started Jul 10 06:00:48 PM PDT 24
Finished Jul 10 06:01:07 PM PDT 24
Peak memory 239544 kb
Host smart-30947c94-1765-48d6-aecc-0436267dc4d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792603502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmds
.792603502
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.3740753016
Short name T620
Test name
Test status
Simulation time 682249212 ps
CPU time 8.72 seconds
Started Jul 10 06:00:48 PM PDT 24
Finished Jul 10 06:00:57 PM PDT 24
Peak memory 232672 kb
Host smart-ace2fdcc-7c62-4940-9b3e-a2ac34add457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740753016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.3740753016
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.1059789923
Short name T828
Test name
Test status
Simulation time 5880049231 ps
CPU time 14.52 seconds
Started Jul 10 06:00:49 PM PDT 24
Finished Jul 10 06:01:04 PM PDT 24
Peak memory 237696 kb
Host smart-74ac97ba-7d0c-4938-97a7-12a8ec490960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059789923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.1059789923
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.733043734
Short name T414
Test name
Test status
Simulation time 1540253677 ps
CPU time 4.8 seconds
Started Jul 10 06:00:48 PM PDT 24
Finished Jul 10 06:00:54 PM PDT 24
Peak memory 224484 kb
Host smart-62e7a057-cf56-4402-8b67-ff637e06dd37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733043734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swap
.733043734
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.1848405760
Short name T516
Test name
Test status
Simulation time 1334426909 ps
CPU time 4.16 seconds
Started Jul 10 06:00:51 PM PDT 24
Finished Jul 10 06:00:57 PM PDT 24
Peak memory 232644 kb
Host smart-11875850-7c6a-4844-af7d-5b5b62cbe552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848405760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.1848405760
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.3432648119
Short name T149
Test name
Test status
Simulation time 7899739367 ps
CPU time 22.15 seconds
Started Jul 10 06:00:47 PM PDT 24
Finished Jul 10 06:01:10 PM PDT 24
Peak memory 220628 kb
Host smart-2ce79580-018d-4a03-abc3-9e5a087b752e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3432648119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.3432648119
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.1794651839
Short name T829
Test name
Test status
Simulation time 18844785253 ps
CPU time 47.26 seconds
Started Jul 10 06:00:49 PM PDT 24
Finished Jul 10 06:01:37 PM PDT 24
Peak memory 217776 kb
Host smart-aa082ac2-f502-422d-8a88-2054abb169e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794651839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.1794651839
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.265598997
Short name T329
Test name
Test status
Simulation time 5944470344 ps
CPU time 13.42 seconds
Started Jul 10 06:00:48 PM PDT 24
Finished Jul 10 06:01:03 PM PDT 24
Peak memory 220180 kb
Host smart-49becefc-7e66-4dc3-b493-66eb00ea6055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265598997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.265598997
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.1873864521
Short name T958
Test name
Test status
Simulation time 28398145950 ps
CPU time 20.65 seconds
Started Jul 10 06:00:50 PM PDT 24
Finished Jul 10 06:01:13 PM PDT 24
Peak memory 216348 kb
Host smart-376d0b01-3dff-4911-9a0c-757179569a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873864521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.1873864521
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.3848563057
Short name T997
Test name
Test status
Simulation time 635186334 ps
CPU time 2.54 seconds
Started Jul 10 06:00:48 PM PDT 24
Finished Jul 10 06:00:52 PM PDT 24
Peak memory 216248 kb
Host smart-de03f989-7164-4a75-8087-3fc95c788126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848563057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.3848563057
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.1138263473
Short name T447
Test name
Test status
Simulation time 42317206 ps
CPU time 0.79 seconds
Started Jul 10 06:00:51 PM PDT 24
Finished Jul 10 06:00:53 PM PDT 24
Peak memory 205944 kb
Host smart-31af2364-84c8-40fb-b5bd-f4b28d55e3cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138263473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.1138263473
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.1033006253
Short name T478
Test name
Test status
Simulation time 145665460 ps
CPU time 2.47 seconds
Started Jul 10 06:00:53 PM PDT 24
Finished Jul 10 06:00:57 PM PDT 24
Peak memory 224360 kb
Host smart-5524ba98-ab82-4283-b088-3e9dc0f8e5d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033006253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.1033006253
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.3755672228
Short name T432
Test name
Test status
Simulation time 23987041 ps
CPU time 0.72 seconds
Started Jul 10 06:00:53 PM PDT 24
Finished Jul 10 06:00:55 PM PDT 24
Peak memory 204944 kb
Host smart-95845a01-93e3-46db-b010-36277a65e2bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755672228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
3755672228
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.2289002451
Short name T88
Test name
Test status
Simulation time 118352000 ps
CPU time 2.41 seconds
Started Jul 10 06:00:52 PM PDT 24
Finished Jul 10 06:00:56 PM PDT 24
Peak memory 224412 kb
Host smart-9ec7f300-4f21-4e07-b3bb-0a6aae85402e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289002451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.2289002451
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.805011485
Short name T419
Test name
Test status
Simulation time 17279273 ps
CPU time 0.77 seconds
Started Jul 10 06:00:53 PM PDT 24
Finished Jul 10 06:00:55 PM PDT 24
Peak memory 205564 kb
Host smart-d9bfc4d7-d831-49d5-98fa-4903f4eea7de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805011485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.805011485
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.3233232239
Short name T945
Test name
Test status
Simulation time 18412692011 ps
CPU time 135.45 seconds
Started Jul 10 06:00:53 PM PDT 24
Finished Jul 10 06:03:10 PM PDT 24
Peak memory 253452 kb
Host smart-2f514392-3d99-4550-ad0e-46cef997ecf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233232239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.3233232239
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.2404556306
Short name T258
Test name
Test status
Simulation time 213109815223 ps
CPU time 362.17 seconds
Started Jul 10 06:00:50 PM PDT 24
Finished Jul 10 06:06:53 PM PDT 24
Peak memory 262912 kb
Host smart-0a5be0fb-b773-4f57-9dba-62eb9c87f4b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404556306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.2404556306
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.3976043733
Short name T147
Test name
Test status
Simulation time 21782822918 ps
CPU time 172.84 seconds
Started Jul 10 06:00:52 PM PDT 24
Finished Jul 10 06:03:47 PM PDT 24
Peak memory 254572 kb
Host smart-502583df-c453-4ddb-b0b8-c86fdc491cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976043733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.3976043733
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.4161414935
Short name T1005
Test name
Test status
Simulation time 123943572798 ps
CPU time 452.35 seconds
Started Jul 10 06:00:52 PM PDT 24
Finished Jul 10 06:08:26 PM PDT 24
Peak memory 265900 kb
Host smart-e1ada974-dca6-4a0b-b992-6276e44b462e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161414935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmd
s.4161414935
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.1589181795
Short name T988
Test name
Test status
Simulation time 7992120042 ps
CPU time 18.43 seconds
Started Jul 10 06:00:52 PM PDT 24
Finished Jul 10 06:01:12 PM PDT 24
Peak memory 232828 kb
Host smart-9f3768a0-cb92-431c-8aee-5f704c4af7f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589181795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.1589181795
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.3072555582
Short name T142
Test name
Test status
Simulation time 2868156549 ps
CPU time 13.33 seconds
Started Jul 10 06:00:52 PM PDT 24
Finished Jul 10 06:01:07 PM PDT 24
Peak memory 232748 kb
Host smart-1cc20767-548f-42bf-bffa-b76d832735cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072555582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.3072555582
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.3192456990
Short name T932
Test name
Test status
Simulation time 486082624 ps
CPU time 6.45 seconds
Started Jul 10 06:00:51 PM PDT 24
Finished Jul 10 06:00:59 PM PDT 24
Peak memory 232612 kb
Host smart-e7e564d8-074d-452d-b71a-4f0c27ee16ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192456990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.3192456990
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.3385069629
Short name T488
Test name
Test status
Simulation time 11647422874 ps
CPU time 10.11 seconds
Started Jul 10 06:00:55 PM PDT 24
Finished Jul 10 06:01:06 PM PDT 24
Peak memory 232776 kb
Host smart-d7299602-1014-4512-b0bb-d0a995ede754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385069629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.3385069629
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.2604962836
Short name T155
Test name
Test status
Simulation time 2642087282 ps
CPU time 10.51 seconds
Started Jul 10 06:00:53 PM PDT 24
Finished Jul 10 06:01:05 PM PDT 24
Peak memory 219336 kb
Host smart-49fbf1c7-6eda-4afd-bc9e-c829d93c7584
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2604962836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.2604962836
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.1587772957
Short name T303
Test name
Test status
Simulation time 3784829171 ps
CPU time 89.77 seconds
Started Jul 10 06:00:52 PM PDT 24
Finished Jul 10 06:02:24 PM PDT 24
Peak memory 273040 kb
Host smart-5f7518f3-d064-4289-b547-8cf3f820de65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587772957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.1587772957
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.2257011848
Short name T789
Test name
Test status
Simulation time 1083863329 ps
CPU time 3.76 seconds
Started Jul 10 06:00:54 PM PDT 24
Finished Jul 10 06:00:59 PM PDT 24
Peak memory 216324 kb
Host smart-1a394de4-08a1-4d1a-91d8-1fda0c11a8f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257011848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.2257011848
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.2994825506
Short name T1008
Test name
Test status
Simulation time 22386418032 ps
CPU time 19.51 seconds
Started Jul 10 06:00:55 PM PDT 24
Finished Jul 10 06:01:15 PM PDT 24
Peak memory 216332 kb
Host smart-564e2441-11c6-4eca-b047-eb8636935b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994825506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.2994825506
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.1219396668
Short name T678
Test name
Test status
Simulation time 263393559 ps
CPU time 3.97 seconds
Started Jul 10 06:00:57 PM PDT 24
Finished Jul 10 06:01:02 PM PDT 24
Peak memory 216212 kb
Host smart-f31f262a-d705-402a-82a7-4bec3e354c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219396668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.1219396668
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.2247706066
Short name T559
Test name
Test status
Simulation time 109561356 ps
CPU time 0.87 seconds
Started Jul 10 06:00:52 PM PDT 24
Finished Jul 10 06:00:54 PM PDT 24
Peak memory 205988 kb
Host smart-a603f8bf-5610-4404-8676-a1bcaa5a78be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247706066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.2247706066
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.778813268
Short name T199
Test name
Test status
Simulation time 589603336 ps
CPU time 3.54 seconds
Started Jul 10 06:00:51 PM PDT 24
Finished Jul 10 06:00:57 PM PDT 24
Peak memory 232624 kb
Host smart-4fdb62e0-725a-4e60-a0a4-c3d90fa78058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778813268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.778813268
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.115197019
Short name T640
Test name
Test status
Simulation time 10451518 ps
CPU time 0.73 seconds
Started Jul 10 06:00:57 PM PDT 24
Finished Jul 10 06:00:59 PM PDT 24
Peak memory 205872 kb
Host smart-35f2876c-7d64-45bb-867c-6f54852e50c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115197019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.115197019
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.148512703
Short name T669
Test name
Test status
Simulation time 144427699 ps
CPU time 2.3 seconds
Started Jul 10 06:00:57 PM PDT 24
Finished Jul 10 06:01:01 PM PDT 24
Peak memory 232316 kb
Host smart-f2e7afa6-bb4f-4ab3-a076-461d514ce6c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148512703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.148512703
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.408988202
Short name T336
Test name
Test status
Simulation time 16488451 ps
CPU time 0.78 seconds
Started Jul 10 06:00:51 PM PDT 24
Finished Jul 10 06:00:54 PM PDT 24
Peak memory 205588 kb
Host smart-ce21a88e-1a08-4fc1-867c-d558baf62306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408988202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.408988202
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.2965937024
Short name T376
Test name
Test status
Simulation time 41876722821 ps
CPU time 32.08 seconds
Started Jul 10 06:00:57 PM PDT 24
Finished Jul 10 06:01:30 PM PDT 24
Peak memory 236080 kb
Host smart-53fd5793-6290-4b3e-b00d-0706c66ecf38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965937024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.2965937024
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.2894985191
Short name T248
Test name
Test status
Simulation time 946895262 ps
CPU time 9.96 seconds
Started Jul 10 06:00:59 PM PDT 24
Finished Jul 10 06:01:10 PM PDT 24
Peak memory 238444 kb
Host smart-316bd80f-2695-4239-ac27-069357a57326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894985191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.2894985191
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.1892654000
Short name T334
Test name
Test status
Simulation time 43568388456 ps
CPU time 179.46 seconds
Started Jul 10 06:00:56 PM PDT 24
Finished Jul 10 06:03:57 PM PDT 24
Peak memory 254292 kb
Host smart-04fe25ef-018d-4d8c-a23f-4b7527734275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892654000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.1892654000
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.2498709768
Short name T855
Test name
Test status
Simulation time 146060975 ps
CPU time 3.1 seconds
Started Jul 10 06:00:56 PM PDT 24
Finished Jul 10 06:01:00 PM PDT 24
Peak memory 232708 kb
Host smart-eb63c796-2069-4c2c-9202-a7f6acdcad91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498709768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.2498709768
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.2089629428
Short name T944
Test name
Test status
Simulation time 1788904647 ps
CPU time 8.53 seconds
Started Jul 10 06:00:57 PM PDT 24
Finished Jul 10 06:01:07 PM PDT 24
Peak memory 235532 kb
Host smart-1db0896d-90ed-43c3-b052-450832162931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089629428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmd
s.2089629428
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.1822482104
Short name T259
Test name
Test status
Simulation time 124824124 ps
CPU time 4.21 seconds
Started Jul 10 06:00:58 PM PDT 24
Finished Jul 10 06:01:03 PM PDT 24
Peak memory 232640 kb
Host smart-c826e260-a4a6-4bdb-9640-8c3e901a2f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822482104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.1822482104
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.3323424811
Short name T263
Test name
Test status
Simulation time 41440801374 ps
CPU time 163.62 seconds
Started Jul 10 06:00:57 PM PDT 24
Finished Jul 10 06:03:42 PM PDT 24
Peak memory 232748 kb
Host smart-4abe8284-ab57-45b4-811d-1c8082c50d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323424811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.3323424811
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.3368498562
Short name T498
Test name
Test status
Simulation time 205560642 ps
CPU time 3.32 seconds
Started Jul 10 06:00:55 PM PDT 24
Finished Jul 10 06:00:59 PM PDT 24
Peak memory 232684 kb
Host smart-b64adc59-8a3e-42f9-92a7-ea7bd00433cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368498562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.3368498562
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.2364522756
Short name T682
Test name
Test status
Simulation time 37757742776 ps
CPU time 29.51 seconds
Started Jul 10 06:00:55 PM PDT 24
Finished Jul 10 06:01:26 PM PDT 24
Peak memory 224608 kb
Host smart-62eedec5-821f-47f6-b19d-707a29fe99fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364522756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.2364522756
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.1525620698
Short name T546
Test name
Test status
Simulation time 627470667 ps
CPU time 3.76 seconds
Started Jul 10 06:00:58 PM PDT 24
Finished Jul 10 06:01:03 PM PDT 24
Peak memory 220380 kb
Host smart-a5efcd86-4030-45bf-b808-63d5fc1a840f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1525620698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.1525620698
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.157117633
Short name T163
Test name
Test status
Simulation time 10102749548 ps
CPU time 54.63 seconds
Started Jul 10 06:00:59 PM PDT 24
Finished Jul 10 06:01:54 PM PDT 24
Peak memory 256128 kb
Host smart-eafd5b08-8257-4417-937c-46f6d311e90a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157117633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stres
s_all.157117633
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.3893763608
Short name T136
Test name
Test status
Simulation time 25399790837 ps
CPU time 33.81 seconds
Started Jul 10 06:00:58 PM PDT 24
Finished Jul 10 06:01:33 PM PDT 24
Peak memory 216372 kb
Host smart-ff57ab93-7753-4215-bb70-2d5a2d4245fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893763608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.3893763608
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.231131173
Short name T748
Test name
Test status
Simulation time 7603063420 ps
CPU time 20.59 seconds
Started Jul 10 06:00:56 PM PDT 24
Finished Jul 10 06:01:18 PM PDT 24
Peak memory 216264 kb
Host smart-403479dc-a39e-4be8-8f89-afe2aca8c3b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231131173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.231131173
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.2094754099
Short name T535
Test name
Test status
Simulation time 228792665 ps
CPU time 3.11 seconds
Started Jul 10 06:00:57 PM PDT 24
Finished Jul 10 06:01:01 PM PDT 24
Peak memory 216256 kb
Host smart-8c858206-bf42-4e3d-8b4d-d0aa97071139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094754099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.2094754099
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.3166324509
Short name T485
Test name
Test status
Simulation time 128357652 ps
CPU time 0.81 seconds
Started Jul 10 06:00:57 PM PDT 24
Finished Jul 10 06:00:59 PM PDT 24
Peak memory 205988 kb
Host smart-b5944976-e909-4042-a97c-f3db6f2af949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166324509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.3166324509
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.1284272889
Short name T171
Test name
Test status
Simulation time 10189989861 ps
CPU time 31.51 seconds
Started Jul 10 06:00:56 PM PDT 24
Finished Jul 10 06:01:29 PM PDT 24
Peak memory 232784 kb
Host smart-9b6be7f2-c175-4145-92f1-7f5e2e5587e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284272889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.1284272889
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.3733505452
Short name T954
Test name
Test status
Simulation time 13895194 ps
CPU time 0.76 seconds
Started Jul 10 06:01:02 PM PDT 24
Finished Jul 10 06:01:04 PM PDT 24
Peak memory 206084 kb
Host smart-03e556a3-5df0-4db5-a1b8-629043dfb2a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733505452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
3733505452
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.2740210644
Short name T408
Test name
Test status
Simulation time 3588628823 ps
CPU time 11.48 seconds
Started Jul 10 06:01:02 PM PDT 24
Finished Jul 10 06:01:15 PM PDT 24
Peak memory 224524 kb
Host smart-7b6bac59-3501-4743-9ef4-7b7546eec48e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740210644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.2740210644
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.55444905
Short name T643
Test name
Test status
Simulation time 42783738 ps
CPU time 0.77 seconds
Started Jul 10 06:01:03 PM PDT 24
Finished Jul 10 06:01:05 PM PDT 24
Peak memory 205900 kb
Host smart-60ea51ba-1c0e-4800-aa2e-28339beb4229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55444905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.55444905
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.3923829084
Short name T930
Test name
Test status
Simulation time 6586350396 ps
CPU time 77.9 seconds
Started Jul 10 06:01:03 PM PDT 24
Finished Jul 10 06:02:23 PM PDT 24
Peak memory 257088 kb
Host smart-104a44fe-9535-4807-b849-9e9be8455651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923829084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.3923829084
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.4293698830
Short name T196
Test name
Test status
Simulation time 1517790911 ps
CPU time 28.05 seconds
Started Jul 10 06:01:04 PM PDT 24
Finished Jul 10 06:01:34 PM PDT 24
Peak memory 240648 kb
Host smart-781c9ef4-25db-407d-8816-cf37dc1c5f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293698830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.4293698830
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.1444892602
Short name T618
Test name
Test status
Simulation time 22952693908 ps
CPU time 222.71 seconds
Started Jul 10 06:01:04 PM PDT 24
Finished Jul 10 06:04:48 PM PDT 24
Peak memory 261348 kb
Host smart-da6f5202-fbf9-416c-9299-32d846d9f4c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444892602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.1444892602
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.1537481513
Short name T321
Test name
Test status
Simulation time 3360511056 ps
CPU time 18.96 seconds
Started Jul 10 06:01:04 PM PDT 24
Finished Jul 10 06:01:24 PM PDT 24
Peak memory 249224 kb
Host smart-f433e8d5-2f79-48cf-8750-702bda84ad3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537481513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.1537481513
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.540832749
Short name T179
Test name
Test status
Simulation time 48679757566 ps
CPU time 114.24 seconds
Started Jul 10 06:01:02 PM PDT 24
Finished Jul 10 06:02:57 PM PDT 24
Peak memory 256924 kb
Host smart-1dd4cf28-1dde-4fd4-a749-7afcc788cf07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540832749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmds
.540832749
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.2733640467
Short name T254
Test name
Test status
Simulation time 694606321 ps
CPU time 4.34 seconds
Started Jul 10 06:01:06 PM PDT 24
Finished Jul 10 06:01:12 PM PDT 24
Peak memory 224408 kb
Host smart-dbe5b9c6-fe3d-4e49-8f17-064e664dc59a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733640467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.2733640467
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.2703898024
Short name T243
Test name
Test status
Simulation time 788460046 ps
CPU time 6.99 seconds
Started Jul 10 06:01:04 PM PDT 24
Finished Jul 10 06:01:13 PM PDT 24
Peak memory 232708 kb
Host smart-27925252-446c-48a5-85b1-f3e529259d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703898024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.2703898024
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.2002203949
Short name T214
Test name
Test status
Simulation time 1435721506 ps
CPU time 6.42 seconds
Started Jul 10 06:01:02 PM PDT 24
Finished Jul 10 06:01:10 PM PDT 24
Peak memory 232636 kb
Host smart-b23fb7fd-950e-430f-b99f-e96f6bc959be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002203949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.2002203949
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.3707875220
Short name T515
Test name
Test status
Simulation time 2718309859 ps
CPU time 5.6 seconds
Started Jul 10 06:01:03 PM PDT 24
Finished Jul 10 06:01:11 PM PDT 24
Peak memory 232768 kb
Host smart-78d8fa50-5d32-47f4-9360-6d0eaa281aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707875220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.3707875220
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.1582729720
Short name T468
Test name
Test status
Simulation time 1483433894 ps
CPU time 6.53 seconds
Started Jul 10 06:01:03 PM PDT 24
Finished Jul 10 06:01:11 PM PDT 24
Peak memory 220452 kb
Host smart-65b619d5-1bed-476f-95a8-e100ddd9a885
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1582729720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.1582729720
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.3333843813
Short name T785
Test name
Test status
Simulation time 190437757 ps
CPU time 2.9 seconds
Started Jul 10 06:01:04 PM PDT 24
Finished Jul 10 06:01:08 PM PDT 24
Peak memory 219712 kb
Host smart-e1f42ba2-794a-4c9a-87a4-fd47e0af51fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333843813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.3333843813
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.2864320784
Short name T332
Test name
Test status
Simulation time 2937442449 ps
CPU time 17.6 seconds
Started Jul 10 06:01:02 PM PDT 24
Finished Jul 10 06:01:21 PM PDT 24
Peak memory 216384 kb
Host smart-10fb8c19-3e66-4a97-9ef3-1334cf5ba588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864320784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.2864320784
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.3013954845
Short name T571
Test name
Test status
Simulation time 3730465229 ps
CPU time 3.19 seconds
Started Jul 10 06:01:06 PM PDT 24
Finished Jul 10 06:01:10 PM PDT 24
Peak memory 207984 kb
Host smart-972fd32e-9330-45cc-bc4e-7cbd45a3e804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013954845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.3013954845
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.4156255184
Short name T396
Test name
Test status
Simulation time 116367540 ps
CPU time 2.7 seconds
Started Jul 10 06:01:05 PM PDT 24
Finished Jul 10 06:01:09 PM PDT 24
Peak memory 216196 kb
Host smart-cff2d921-4fca-4a69-a7dd-4cedfba158a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156255184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.4156255184
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.3425476580
Short name T410
Test name
Test status
Simulation time 43510581 ps
CPU time 0.85 seconds
Started Jul 10 06:01:03 PM PDT 24
Finished Jul 10 06:01:06 PM PDT 24
Peak memory 205980 kb
Host smart-59ad7e03-a031-46d3-b5b4-6efef0a005a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425476580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.3425476580
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.2682821544
Short name T803
Test name
Test status
Simulation time 32366402163 ps
CPU time 13.04 seconds
Started Jul 10 06:01:05 PM PDT 24
Finished Jul 10 06:01:19 PM PDT 24
Peak memory 232772 kb
Host smart-bc60c811-c7c6-44d9-9075-2772ae299bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682821544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.2682821544
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.3229031531
Short name T494
Test name
Test status
Simulation time 38391014 ps
CPU time 0.74 seconds
Started Jul 10 06:01:08 PM PDT 24
Finished Jul 10 06:01:11 PM PDT 24
Peak memory 205540 kb
Host smart-99a1ec07-3f0f-444b-b598-d6521cac932e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229031531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
3229031531
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.2687307563
Short name T894
Test name
Test status
Simulation time 2714621649 ps
CPU time 32.83 seconds
Started Jul 10 06:01:06 PM PDT 24
Finished Jul 10 06:01:40 PM PDT 24
Peak memory 224616 kb
Host smart-169813c7-e3e5-4b7b-bdfe-ee3b25ea97f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687307563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.2687307563
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.653276985
Short name T365
Test name
Test status
Simulation time 59924846 ps
CPU time 0.81 seconds
Started Jul 10 06:01:06 PM PDT 24
Finished Jul 10 06:01:08 PM PDT 24
Peak memory 206884 kb
Host smart-21f612f4-683a-4c51-b73b-e335817410f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653276985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.653276985
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.3237780629
Short name T966
Test name
Test status
Simulation time 61958861365 ps
CPU time 161.41 seconds
Started Jul 10 06:01:07 PM PDT 24
Finished Jul 10 06:03:50 PM PDT 24
Peak memory 254744 kb
Host smart-5aa51943-5d57-4794-aa1d-a2b665b2eefe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237780629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.3237780629
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.3689339426
Short name T574
Test name
Test status
Simulation time 7354941019 ps
CPU time 43.87 seconds
Started Jul 10 06:01:10 PM PDT 24
Finished Jul 10 06:01:56 PM PDT 24
Peak memory 219372 kb
Host smart-b516b837-4f2a-4209-9400-7c151217d0a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689339426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.3689339426
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.3967155212
Short name T612
Test name
Test status
Simulation time 149375668 ps
CPU time 5.44 seconds
Started Jul 10 06:01:06 PM PDT 24
Finished Jul 10 06:01:12 PM PDT 24
Peak memory 236232 kb
Host smart-fed767e0-1048-4bbc-b029-953c8980f32c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967155212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.3967155212
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.946269204
Short name T289
Test name
Test status
Simulation time 9415415648 ps
CPU time 43.75 seconds
Started Jul 10 06:01:06 PM PDT 24
Finished Jul 10 06:01:51 PM PDT 24
Peak memory 224620 kb
Host smart-0d348977-bbdc-4e34-b5c2-520bda57d6c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946269204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmds
.946269204
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.2176143081
Short name T267
Test name
Test status
Simulation time 138591613 ps
CPU time 4.02 seconds
Started Jul 10 06:01:07 PM PDT 24
Finished Jul 10 06:01:12 PM PDT 24
Peak memory 224420 kb
Host smart-bc0b174d-1c6a-49d9-a489-3e5af6729168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176143081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.2176143081
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.762829930
Short name T418
Test name
Test status
Simulation time 413740362 ps
CPU time 2.44 seconds
Started Jul 10 06:01:08 PM PDT 24
Finished Jul 10 06:01:12 PM PDT 24
Peak memory 223736 kb
Host smart-6cceaba4-99a9-480f-aafa-431757899bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762829930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.762829930
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.2594214507
Short name T1021
Test name
Test status
Simulation time 2407997067 ps
CPU time 10.01 seconds
Started Jul 10 06:01:08 PM PDT 24
Finished Jul 10 06:01:20 PM PDT 24
Peak memory 240652 kb
Host smart-a332edde-0f35-49fb-bfae-abbe727654be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594214507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.2594214507
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.3222767371
Short name T242
Test name
Test status
Simulation time 1400753740 ps
CPU time 10.4 seconds
Started Jul 10 06:01:11 PM PDT 24
Finished Jul 10 06:01:24 PM PDT 24
Peak memory 232688 kb
Host smart-2ce151a3-c935-41a2-890d-86e8ffb9e94a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222767371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.3222767371
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.1435894662
Short name T779
Test name
Test status
Simulation time 128389815 ps
CPU time 4.14 seconds
Started Jul 10 06:01:06 PM PDT 24
Finished Jul 10 06:01:11 PM PDT 24
Peak memory 223068 kb
Host smart-b6fdc62d-3ecd-49ad-b96b-37b0c609e982
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1435894662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.1435894662
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.2094149660
Short name T145
Test name
Test status
Simulation time 54867898167 ps
CPU time 136.16 seconds
Started Jul 10 06:01:09 PM PDT 24
Finished Jul 10 06:03:28 PM PDT 24
Peak memory 253048 kb
Host smart-e0f25791-62e4-4ba4-986f-f9c1f12a9776
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094149660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.2094149660
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.518930188
Short name T858
Test name
Test status
Simulation time 6152757106 ps
CPU time 34.08 seconds
Started Jul 10 06:01:03 PM PDT 24
Finished Jul 10 06:01:38 PM PDT 24
Peak memory 216408 kb
Host smart-557258f7-1c8d-4db4-888e-ded6aeeeafb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518930188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.518930188
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.2527917372
Short name T729
Test name
Test status
Simulation time 1825217051 ps
CPU time 5.78 seconds
Started Jul 10 06:01:04 PM PDT 24
Finished Jul 10 06:01:11 PM PDT 24
Peak memory 216236 kb
Host smart-9f25ac0f-a114-453a-aa56-22dd515064b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527917372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.2527917372
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.2507882749
Short name T348
Test name
Test status
Simulation time 56228615 ps
CPU time 0.83 seconds
Started Jul 10 06:01:03 PM PDT 24
Finished Jul 10 06:01:05 PM PDT 24
Peak memory 205992 kb
Host smart-516eb399-9ba6-4444-b87f-fb05c0843123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507882749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.2507882749
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.2729629506
Short name T593
Test name
Test status
Simulation time 263619746 ps
CPU time 0.84 seconds
Started Jul 10 06:01:01 PM PDT 24
Finished Jul 10 06:01:03 PM PDT 24
Peak memory 205972 kb
Host smart-01cc8e46-c350-4222-8931-19a9eec55b08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729629506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.2729629506
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.1469191037
Short name T246
Test name
Test status
Simulation time 6239675277 ps
CPU time 3.92 seconds
Started Jul 10 06:01:09 PM PDT 24
Finished Jul 10 06:01:15 PM PDT 24
Peak memory 232972 kb
Host smart-2ac6689e-cd69-429a-9313-a3e49e6093d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469191037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.1469191037
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.2525243172
Short name T68
Test name
Test status
Simulation time 18622891 ps
CPU time 0.67 seconds
Started Jul 10 06:01:09 PM PDT 24
Finished Jul 10 06:01:12 PM PDT 24
Peak memory 205540 kb
Host smart-c75659cb-71be-4be2-b12d-2dedf0213ede
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525243172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
2525243172
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.1314376988
Short name T708
Test name
Test status
Simulation time 75340668 ps
CPU time 2.78 seconds
Started Jul 10 06:01:08 PM PDT 24
Finished Jul 10 06:01:13 PM PDT 24
Peak memory 232632 kb
Host smart-a4d98607-40d8-4f93-bd1f-e42fc6155989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314376988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.1314376988
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.2513683192
Short name T681
Test name
Test status
Simulation time 53938031 ps
CPU time 0.78 seconds
Started Jul 10 06:01:09 PM PDT 24
Finished Jul 10 06:01:11 PM PDT 24
Peak memory 205756 kb
Host smart-02d10af0-57e5-47d5-977a-6d1e9a6b595e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513683192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.2513683192
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.4008366212
Short name T310
Test name
Test status
Simulation time 94523735466 ps
CPU time 642.19 seconds
Started Jul 10 06:01:09 PM PDT 24
Finished Jul 10 06:11:54 PM PDT 24
Peak memory 267588 kb
Host smart-d1f827d6-e24a-4805-ae6d-addf4ae76d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008366212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.4008366212
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.3030379443
Short name T717
Test name
Test status
Simulation time 16428686957 ps
CPU time 68.77 seconds
Started Jul 10 06:01:12 PM PDT 24
Finished Jul 10 06:02:23 PM PDT 24
Peak memory 256388 kb
Host smart-f2f28c42-d047-4b86-859b-a6b70d4fb06a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030379443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.3030379443
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.311169788
Short name T857
Test name
Test status
Simulation time 15314408733 ps
CPU time 81.23 seconds
Started Jul 10 06:01:12 PM PDT 24
Finished Jul 10 06:02:35 PM PDT 24
Peak memory 257124 kb
Host smart-e1003d1e-bbd5-4101-847f-5f73ce9912bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311169788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idle
.311169788
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.836392995
Short name T875
Test name
Test status
Simulation time 303519717 ps
CPU time 6.94 seconds
Started Jul 10 06:01:09 PM PDT 24
Finished Jul 10 06:01:17 PM PDT 24
Peak memory 232660 kb
Host smart-568b7d9d-eb26-4061-b51c-0d7c04f9660c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836392995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.836392995
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.3567932625
Short name T224
Test name
Test status
Simulation time 7260042926 ps
CPU time 71.93 seconds
Started Jul 10 06:01:08 PM PDT 24
Finished Jul 10 06:02:21 PM PDT 24
Peak memory 249728 kb
Host smart-3e199d37-50c1-47fe-8c21-00200240d1e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567932625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmd
s.3567932625
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.3265577592
Short name T211
Test name
Test status
Simulation time 1777663780 ps
CPU time 4.49 seconds
Started Jul 10 06:01:09 PM PDT 24
Finished Jul 10 06:01:15 PM PDT 24
Peak memory 224412 kb
Host smart-d9bc74d7-fecc-4802-9e55-9f2b055f2b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265577592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.3265577592
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.3608442053
Short name T87
Test name
Test status
Simulation time 2599595726 ps
CPU time 27.17 seconds
Started Jul 10 06:01:08 PM PDT 24
Finished Jul 10 06:01:37 PM PDT 24
Peak memory 233844 kb
Host smart-61b9fa4a-1b23-4fb7-9f86-4dbf14c014ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608442053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.3608442053
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.3774644565
Short name T316
Test name
Test status
Simulation time 9111629744 ps
CPU time 5.03 seconds
Started Jul 10 06:01:09 PM PDT 24
Finished Jul 10 06:01:16 PM PDT 24
Peak memory 224528 kb
Host smart-093b3b77-4acb-4710-8b60-3cebc914c77d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774644565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.3774644565
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.201167114
Short name T440
Test name
Test status
Simulation time 266848943 ps
CPU time 2.91 seconds
Started Jul 10 06:01:10 PM PDT 24
Finished Jul 10 06:01:15 PM PDT 24
Peak memory 224484 kb
Host smart-475361be-e430-435f-9918-c090d7c4b197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201167114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.201167114
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.2925608117
Short name T747
Test name
Test status
Simulation time 121233596 ps
CPU time 4.16 seconds
Started Jul 10 06:01:12 PM PDT 24
Finished Jul 10 06:01:18 PM PDT 24
Peak memory 223076 kb
Host smart-53b78c30-179d-4217-9986-c8ba0a2394e4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2925608117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.2925608117
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.1673868767
Short name T161
Test name
Test status
Simulation time 89862000345 ps
CPU time 519.61 seconds
Started Jul 10 06:01:19 PM PDT 24
Finished Jul 10 06:10:00 PM PDT 24
Peak memory 269432 kb
Host smart-27bc0dcf-b083-4276-a667-fa230050f6f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673868767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.1673868767
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.2772629185
Short name T921
Test name
Test status
Simulation time 15096935 ps
CPU time 0.75 seconds
Started Jul 10 06:01:11 PM PDT 24
Finished Jul 10 06:01:14 PM PDT 24
Peak memory 205684 kb
Host smart-206671f1-581f-4491-aea3-c38f82af7a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772629185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.2772629185
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.4225943657
Short name T86
Test name
Test status
Simulation time 9896481932 ps
CPU time 10.04 seconds
Started Jul 10 06:01:06 PM PDT 24
Finished Jul 10 06:01:17 PM PDT 24
Peak memory 217444 kb
Host smart-ae782373-695b-4035-9a41-5940f17777d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225943657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.4225943657
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.1683544886
Short name T526
Test name
Test status
Simulation time 495137108 ps
CPU time 2.05 seconds
Started Jul 10 06:01:06 PM PDT 24
Finished Jul 10 06:01:10 PM PDT 24
Peak memory 216180 kb
Host smart-bd8349d7-86f3-48c4-ae77-62920a9ff81b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683544886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.1683544886
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.633827746
Short name T568
Test name
Test status
Simulation time 222645022 ps
CPU time 0.93 seconds
Started Jul 10 06:01:09 PM PDT 24
Finished Jul 10 06:01:11 PM PDT 24
Peak memory 206968 kb
Host smart-2ba608e6-e667-427f-95b2-130f17559ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633827746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.633827746
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.102946056
Short name T530
Test name
Test status
Simulation time 726998708 ps
CPU time 4.93 seconds
Started Jul 10 06:01:08 PM PDT 24
Finished Jul 10 06:01:15 PM PDT 24
Peak memory 232660 kb
Host smart-8b4b0556-18d9-44c5-836f-c3dcd84803e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102946056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.102946056
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.427339401
Short name T456
Test name
Test status
Simulation time 12725801 ps
CPU time 0.72 seconds
Started Jul 10 06:01:17 PM PDT 24
Finished Jul 10 06:01:19 PM PDT 24
Peak memory 205540 kb
Host smart-3d99f0f0-4518-4ac1-8a1e-2223e971b039
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427339401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.427339401
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.1194413211
Short name T437
Test name
Test status
Simulation time 7601176719 ps
CPU time 13.43 seconds
Started Jul 10 06:01:12 PM PDT 24
Finished Jul 10 06:01:27 PM PDT 24
Peak memory 232760 kb
Host smart-1a5d27ef-d960-40e1-8285-0dc3acbd800a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194413211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.1194413211
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.4130598358
Short name T793
Test name
Test status
Simulation time 49600105 ps
CPU time 0.8 seconds
Started Jul 10 06:01:14 PM PDT 24
Finished Jul 10 06:01:16 PM PDT 24
Peak memory 207104 kb
Host smart-e4aced17-6431-4861-81a6-c632000145f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130598358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.4130598358
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.3726871437
Short name T393
Test name
Test status
Simulation time 56176922 ps
CPU time 0.78 seconds
Started Jul 10 06:01:10 PM PDT 24
Finished Jul 10 06:01:13 PM PDT 24
Peak memory 215756 kb
Host smart-f7408791-7c70-42c8-9e8e-14d8fc589f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726871437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.3726871437
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.3259172008
Short name T536
Test name
Test status
Simulation time 20034249490 ps
CPU time 198.5 seconds
Started Jul 10 06:01:19 PM PDT 24
Finished Jul 10 06:04:39 PM PDT 24
Peak memory 257436 kb
Host smart-5850eebd-1d48-4318-97dd-a94a4c8fb289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259172008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.3259172008
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.247442827
Short name T666
Test name
Test status
Simulation time 39087685929 ps
CPU time 388.82 seconds
Started Jul 10 06:01:12 PM PDT 24
Finished Jul 10 06:07:43 PM PDT 24
Peak memory 264832 kb
Host smart-6d705ee0-7a36-406d-921c-f2eb40e86113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247442827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idle
.247442827
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.3938819098
Short name T965
Test name
Test status
Simulation time 227923549 ps
CPU time 6.94 seconds
Started Jul 10 06:01:11 PM PDT 24
Finished Jul 10 06:01:20 PM PDT 24
Peak memory 233668 kb
Host smart-d985823e-808a-4b89-9379-cbe51cc7cbef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938819098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.3938819098
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.2130868072
Short name T719
Test name
Test status
Simulation time 42472876949 ps
CPU time 297.21 seconds
Started Jul 10 06:01:12 PM PDT 24
Finished Jul 10 06:06:11 PM PDT 24
Peak memory 250396 kb
Host smart-94f36e50-5a2c-4293-8663-c89cc8a3c85c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130868072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmd
s.2130868072
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.74650203
Short name T936
Test name
Test status
Simulation time 1179087715 ps
CPU time 14.36 seconds
Started Jul 10 06:01:17 PM PDT 24
Finished Jul 10 06:01:32 PM PDT 24
Peak memory 232664 kb
Host smart-88228d80-edbd-4be7-88ce-4cbacb78fec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74650203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.74650203
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.2847660981
Short name T27
Test name
Test status
Simulation time 55634726629 ps
CPU time 138.33 seconds
Started Jul 10 06:01:12 PM PDT 24
Finished Jul 10 06:03:33 PM PDT 24
Peak memory 249976 kb
Host smart-c40edb0d-760f-46e5-a7e1-59e8ca100904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847660981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.2847660981
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.1298188903
Short name T292
Test name
Test status
Simulation time 4213180948 ps
CPU time 13.36 seconds
Started Jul 10 06:01:12 PM PDT 24
Finished Jul 10 06:01:28 PM PDT 24
Peak memory 224484 kb
Host smart-70d12855-6435-409f-b285-ef6cf42265b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298188903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.1298188903
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.1947721044
Short name T740
Test name
Test status
Simulation time 3745677132 ps
CPU time 7.49 seconds
Started Jul 10 06:01:10 PM PDT 24
Finished Jul 10 06:01:20 PM PDT 24
Peak memory 232788 kb
Host smart-842608eb-a67e-41a0-8d30-9467b25d35b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947721044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.1947721044
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.2517588709
Short name T364
Test name
Test status
Simulation time 3488652948 ps
CPU time 8.45 seconds
Started Jul 10 06:01:13 PM PDT 24
Finished Jul 10 06:01:23 PM PDT 24
Peak memory 220916 kb
Host smart-7250bd86-8bf0-45e0-b2d6-0363fb92cac1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2517588709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.2517588709
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.3251975300
Short name T167
Test name
Test status
Simulation time 236421975472 ps
CPU time 286.69 seconds
Started Jul 10 06:01:24 PM PDT 24
Finished Jul 10 06:06:12 PM PDT 24
Peak memory 255380 kb
Host smart-fbd43b5e-91fe-4748-acd3-432969ee7aab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251975300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.3251975300
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.1731873938
Short name T330
Test name
Test status
Simulation time 6839255631 ps
CPU time 20.09 seconds
Started Jul 10 06:01:12 PM PDT 24
Finished Jul 10 06:01:34 PM PDT 24
Peak memory 216316 kb
Host smart-637a1ac6-523a-401d-aae0-e1bd4d883331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731873938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.1731873938
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.2646415098
Short name T337
Test name
Test status
Simulation time 17579833 ps
CPU time 0.71 seconds
Started Jul 10 06:01:12 PM PDT 24
Finished Jul 10 06:01:15 PM PDT 24
Peak memory 205636 kb
Host smart-e2615b1b-a958-4798-bc7b-fa5a614270fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646415098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.2646415098
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.3111209338
Short name T1018
Test name
Test status
Simulation time 19148995 ps
CPU time 0.95 seconds
Started Jul 10 06:01:12 PM PDT 24
Finished Jul 10 06:01:15 PM PDT 24
Peak memory 207124 kb
Host smart-0bc767da-b0f7-4c57-a4f2-cac18adbd081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111209338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.3111209338
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.2478067114
Short name T600
Test name
Test status
Simulation time 15412480 ps
CPU time 0.78 seconds
Started Jul 10 06:01:14 PM PDT 24
Finished Jul 10 06:01:16 PM PDT 24
Peak memory 205980 kb
Host smart-3be7bf29-2470-45d9-b175-6d21bb574c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478067114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.2478067114
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.618812791
Short name T660
Test name
Test status
Simulation time 5347888932 ps
CPU time 7.44 seconds
Started Jul 10 06:01:10 PM PDT 24
Finished Jul 10 06:01:20 PM PDT 24
Peak memory 224640 kb
Host smart-57a9a5c9-343b-4a15-ae4f-1bc87a93a436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618812791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.618812791
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.539995138
Short name T67
Test name
Test status
Simulation time 15338964 ps
CPU time 0.77 seconds
Started Jul 10 05:57:52 PM PDT 24
Finished Jul 10 05:57:54 PM PDT 24
Peak memory 205896 kb
Host smart-586588db-2161-4a6f-9395-e4a6bb4fe41d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539995138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.539995138
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.1412341898
Short name T290
Test name
Test status
Simulation time 79831436 ps
CPU time 2.78 seconds
Started Jul 10 05:57:57 PM PDT 24
Finished Jul 10 05:58:01 PM PDT 24
Peak memory 224480 kb
Host smart-9d9070fc-cf32-4b14-a633-109cbf446b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412341898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.1412341898
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.4143677717
Short name T443
Test name
Test status
Simulation time 70529298 ps
CPU time 0.8 seconds
Started Jul 10 05:57:54 PM PDT 24
Finished Jul 10 05:57:56 PM PDT 24
Peak memory 206620 kb
Host smart-2688857a-4468-42e6-8b64-3360a01e0e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143677717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.4143677717
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.237631320
Short name T1000
Test name
Test status
Simulation time 10717509982 ps
CPU time 51.28 seconds
Started Jul 10 05:57:52 PM PDT 24
Finished Jul 10 05:58:44 PM PDT 24
Peak memory 255968 kb
Host smart-12908c7e-17fb-4969-abe2-42d215e6f7d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237631320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.237631320
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.3283540583
Short name T247
Test name
Test status
Simulation time 77854637968 ps
CPU time 154.39 seconds
Started Jul 10 05:57:57 PM PDT 24
Finished Jul 10 06:00:33 PM PDT 24
Peak memory 251896 kb
Host smart-37e6230a-22a6-412b-87b6-cf44586a2a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283540583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.3283540583
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.2648320752
Short name T794
Test name
Test status
Simulation time 535552493 ps
CPU time 13.44 seconds
Started Jul 10 05:57:55 PM PDT 24
Finished Jul 10 05:58:10 PM PDT 24
Peak memory 235416 kb
Host smart-fb246309-c471-4752-986c-3e161cf5eddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648320752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.2648320752
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.978333839
Short name T873
Test name
Test status
Simulation time 201822534 ps
CPU time 4.07 seconds
Started Jul 10 05:57:52 PM PDT 24
Finished Jul 10 05:57:57 PM PDT 24
Peak memory 234832 kb
Host smart-85a90ac0-be4b-4aaa-8eec-ae3de3303a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978333839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds.
978333839
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.3088007047
Short name T446
Test name
Test status
Simulation time 462896230 ps
CPU time 3.38 seconds
Started Jul 10 05:57:52 PM PDT 24
Finished Jul 10 05:57:57 PM PDT 24
Peak memory 232640 kb
Host smart-d2e396cb-dbf5-4498-93c7-beaaeffd3c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088007047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.3088007047
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.485167166
Short name T274
Test name
Test status
Simulation time 36433541426 ps
CPU time 78.9 seconds
Started Jul 10 05:57:56 PM PDT 24
Finished Jul 10 05:59:16 PM PDT 24
Peak memory 224804 kb
Host smart-d63b5ead-6b89-4651-8edb-4e9fcf6f7979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485167166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.485167166
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.3687683318
Short name T493
Test name
Test status
Simulation time 809669851 ps
CPU time 4.01 seconds
Started Jul 10 05:57:54 PM PDT 24
Finished Jul 10 05:58:00 PM PDT 24
Peak memory 232632 kb
Host smart-0e20b6d4-4041-48c2-a60f-0c4d4bb871e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687683318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.3687683318
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.209799225
Short name T229
Test name
Test status
Simulation time 2128015888 ps
CPU time 6.17 seconds
Started Jul 10 05:57:53 PM PDT 24
Finished Jul 10 05:58:01 PM PDT 24
Peak memory 232612 kb
Host smart-9c3029ad-6351-4375-97b1-0aab04cd2bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209799225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.209799225
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.1786671589
Short name T505
Test name
Test status
Simulation time 2857331400 ps
CPU time 11.52 seconds
Started Jul 10 05:57:53 PM PDT 24
Finished Jul 10 05:58:06 PM PDT 24
Peak memory 219080 kb
Host smart-6389b5b7-bbe3-4d65-b2ca-3b5495601b7c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1786671589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.1786671589
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.3783035946
Short name T1014
Test name
Test status
Simulation time 90615274 ps
CPU time 1.04 seconds
Started Jul 10 05:57:54 PM PDT 24
Finished Jul 10 05:57:57 PM PDT 24
Peak memory 206624 kb
Host smart-44aa22c5-a009-447f-8922-8321cc15541e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783035946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.3783035946
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.1096612664
Short name T651
Test name
Test status
Simulation time 5184760250 ps
CPU time 30.04 seconds
Started Jul 10 05:57:53 PM PDT 24
Finished Jul 10 05:58:25 PM PDT 24
Peak memory 216496 kb
Host smart-c2321566-1a18-43b3-886a-72e6d55f9bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096612664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.1096612664
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.1556446247
Short name T950
Test name
Test status
Simulation time 6136343980 ps
CPU time 7.61 seconds
Started Jul 10 05:57:53 PM PDT 24
Finished Jul 10 05:58:02 PM PDT 24
Peak memory 216328 kb
Host smart-55425b0f-1b21-49d8-8855-a842e01de4b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556446247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.1556446247
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.3139813923
Short name T757
Test name
Test status
Simulation time 347564983 ps
CPU time 1.24 seconds
Started Jul 10 05:57:53 PM PDT 24
Finished Jul 10 05:57:56 PM PDT 24
Peak memory 208048 kb
Host smart-7df997e5-63db-431a-917d-f82b05be9674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139813923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.3139813923
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.3282953642
Short name T602
Test name
Test status
Simulation time 80127034 ps
CPU time 0.93 seconds
Started Jul 10 05:57:54 PM PDT 24
Finished Jul 10 05:57:56 PM PDT 24
Peak memory 205940 kb
Host smart-924d1b8c-e0f5-4c08-91ce-b7646263bd3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282953642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.3282953642
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.3998701180
Short name T838
Test name
Test status
Simulation time 28447754870 ps
CPU time 22.82 seconds
Started Jul 10 05:57:54 PM PDT 24
Finished Jul 10 05:58:19 PM PDT 24
Peak memory 240792 kb
Host smart-014b5940-026f-451c-8180-c0eca7001605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998701180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.3998701180
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.2760090081
Short name T464
Test name
Test status
Simulation time 12766914 ps
CPU time 0.7 seconds
Started Jul 10 05:58:06 PM PDT 24
Finished Jul 10 05:58:07 PM PDT 24
Peak memory 205524 kb
Host smart-7d6b0406-8881-421b-9c65-b81afab2f91f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760090081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.2
760090081
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.1465601851
Short name T463
Test name
Test status
Simulation time 977902360 ps
CPU time 4.56 seconds
Started Jul 10 05:58:00 PM PDT 24
Finished Jul 10 05:58:05 PM PDT 24
Peak memory 232612 kb
Host smart-330bf8ff-0081-4f6e-b9ff-7d62bc293731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465601851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.1465601851
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.3317268205
Short name T579
Test name
Test status
Simulation time 14922008 ps
CPU time 0.75 seconds
Started Jul 10 05:57:52 PM PDT 24
Finished Jul 10 05:57:54 PM PDT 24
Peak memory 205904 kb
Host smart-bef26418-37da-402e-bc07-c70333bbceed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317268205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.3317268205
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.4239459185
Short name T300
Test name
Test status
Simulation time 25494918829 ps
CPU time 204.03 seconds
Started Jul 10 05:57:58 PM PDT 24
Finished Jul 10 06:01:23 PM PDT 24
Peak memory 253864 kb
Host smart-d71f56a3-fbd9-43b8-be84-46fd085327cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239459185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.4239459185
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.763898594
Short name T790
Test name
Test status
Simulation time 6849917332 ps
CPU time 41.48 seconds
Started Jul 10 05:57:58 PM PDT 24
Finished Jul 10 05:58:41 PM PDT 24
Peak memory 249280 kb
Host smart-f6175092-ae06-4707-8584-d2febbd309d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763898594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.763898594
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.3573055158
Short name T756
Test name
Test status
Simulation time 5889535473 ps
CPU time 22.32 seconds
Started Jul 10 05:57:58 PM PDT 24
Finished Jul 10 05:58:21 PM PDT 24
Peak memory 237880 kb
Host smart-2e6b0e29-b45e-42e9-bee1-4c98e243592e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573055158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.3573055158
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.2359819047
Short name T978
Test name
Test status
Simulation time 14460244412 ps
CPU time 50.92 seconds
Started Jul 10 05:57:57 PM PDT 24
Finished Jul 10 05:58:50 PM PDT 24
Peak memory 248924 kb
Host smart-18c9d61d-8256-4656-9953-402da8c28526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359819047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.2359819047
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.3507122430
Short name T841
Test name
Test status
Simulation time 14070758488 ps
CPU time 95.33 seconds
Started Jul 10 05:57:57 PM PDT 24
Finished Jul 10 05:59:33 PM PDT 24
Peak memory 234212 kb
Host smart-ecacda98-f15b-43da-8508-ba4993b300ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507122430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds
.3507122430
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.2980825733
Short name T887
Test name
Test status
Simulation time 57312134 ps
CPU time 2.94 seconds
Started Jul 10 05:57:58 PM PDT 24
Finished Jul 10 05:58:02 PM PDT 24
Peak memory 232668 kb
Host smart-88b938b9-9847-48e8-a982-93939790d632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980825733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.2980825733
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.1997353036
Short name T8
Test name
Test status
Simulation time 64744198038 ps
CPU time 40.73 seconds
Started Jul 10 05:57:57 PM PDT 24
Finished Jul 10 05:58:40 PM PDT 24
Peak memory 224584 kb
Host smart-8ec82487-f542-4456-aece-e7ca60175bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997353036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.1997353036
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.4005582369
Short name T233
Test name
Test status
Simulation time 3500219016 ps
CPU time 16.06 seconds
Started Jul 10 05:57:58 PM PDT 24
Finished Jul 10 05:58:16 PM PDT 24
Peak memory 250672 kb
Host smart-62ca4ee6-f0de-4e7c-a088-c1b428bb9052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005582369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.4005582369
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.2997982147
Short name T868
Test name
Test status
Simulation time 7438259819 ps
CPU time 23.95 seconds
Started Jul 10 05:58:00 PM PDT 24
Finished Jul 10 05:58:24 PM PDT 24
Peak memory 236476 kb
Host smart-1610e8a7-f38c-4b30-a13b-9e9d04bbd7d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997982147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.2997982147
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.2597817677
Short name T483
Test name
Test status
Simulation time 386057159 ps
CPU time 4 seconds
Started Jul 10 05:57:58 PM PDT 24
Finished Jul 10 05:58:03 PM PDT 24
Peak memory 222948 kb
Host smart-12d5afc6-8c77-4b04-9498-89af27370d44
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2597817677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.2597817677
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.4166141325
Short name T328
Test name
Test status
Simulation time 2294955106 ps
CPU time 21.33 seconds
Started Jul 10 05:57:54 PM PDT 24
Finished Jul 10 05:58:17 PM PDT 24
Peak memory 219560 kb
Host smart-83ca6b4e-a207-4def-8b2b-027ed4f4fec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166141325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.4166141325
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.4184407562
Short name T353
Test name
Test status
Simulation time 962228572 ps
CPU time 2.38 seconds
Started Jul 10 05:57:52 PM PDT 24
Finished Jul 10 05:57:56 PM PDT 24
Peak memory 216244 kb
Host smart-d8370787-bb19-44d4-aebd-40bdc93bab5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184407562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.4184407562
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.666186032
Short name T621
Test name
Test status
Simulation time 75085465 ps
CPU time 1.59 seconds
Started Jul 10 05:57:59 PM PDT 24
Finished Jul 10 05:58:02 PM PDT 24
Peak memory 216428 kb
Host smart-c6e4c159-207f-4861-b1be-73682bf0bade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666186032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.666186032
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.579333096
Short name T592
Test name
Test status
Simulation time 89577042 ps
CPU time 0.8 seconds
Started Jul 10 05:58:00 PM PDT 24
Finished Jul 10 05:58:01 PM PDT 24
Peak memory 205980 kb
Host smart-de9cd1b7-f795-4e07-977a-405db959587a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579333096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.579333096
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.2439986919
Short name T813
Test name
Test status
Simulation time 22284121202 ps
CPU time 21.98 seconds
Started Jul 10 05:57:58 PM PDT 24
Finished Jul 10 05:58:21 PM PDT 24
Peak memory 240756 kb
Host smart-3a62ebfe-34cd-4805-912d-137ad6aa5aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439986919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.2439986919
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.154036070
Short name T916
Test name
Test status
Simulation time 36966787 ps
CPU time 0.73 seconds
Started Jul 10 05:58:05 PM PDT 24
Finished Jul 10 05:58:07 PM PDT 24
Peak memory 205844 kb
Host smart-34685492-6fbd-49c6-82f7-a10e7187f107
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154036070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.154036070
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.3381582854
Short name T10
Test name
Test status
Simulation time 725400275 ps
CPU time 9.49 seconds
Started Jul 10 05:58:06 PM PDT 24
Finished Jul 10 05:58:17 PM PDT 24
Peak memory 224488 kb
Host smart-7ba1f29f-5455-41f1-8b71-77248e9a9477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381582854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.3381582854
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.3941624264
Short name T398
Test name
Test status
Simulation time 110897682 ps
CPU time 0.76 seconds
Started Jul 10 05:58:06 PM PDT 24
Finished Jul 10 05:58:08 PM PDT 24
Peak memory 205584 kb
Host smart-3d640cb5-f7c3-40a9-8dc2-cebfae706db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941624264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.3941624264
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.4218191609
Short name T703
Test name
Test status
Simulation time 455701781 ps
CPU time 8.7 seconds
Started Jul 10 05:58:06 PM PDT 24
Finished Jul 10 05:58:16 PM PDT 24
Peak memory 233704 kb
Host smart-19027d74-3c03-482e-8581-60531c6d0744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218191609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.4218191609
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.2228041303
Short name T993
Test name
Test status
Simulation time 3508959247 ps
CPU time 26.47 seconds
Started Jul 10 05:58:06 PM PDT 24
Finished Jul 10 05:58:34 PM PDT 24
Peak memory 232836 kb
Host smart-f6837546-e23f-4248-82c8-bdca901762c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228041303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.2228041303
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.627320909
Short name T937
Test name
Test status
Simulation time 1170216123 ps
CPU time 7.25 seconds
Started Jul 10 05:58:09 PM PDT 24
Finished Jul 10 05:58:17 PM PDT 24
Peak memory 228940 kb
Host smart-d477da62-53a7-4ca0-8c5a-2adc62a00ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627320909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.627320909
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.1600426702
Short name T866
Test name
Test status
Simulation time 52945756350 ps
CPU time 387.36 seconds
Started Jul 10 05:58:05 PM PDT 24
Finished Jul 10 06:04:33 PM PDT 24
Peak memory 251984 kb
Host smart-82664dfa-bd64-489b-9feb-cdbb201941fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600426702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds
.1600426702
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.290184201
Short name T722
Test name
Test status
Simulation time 3455884214 ps
CPU time 10.68 seconds
Started Jul 10 05:58:05 PM PDT 24
Finished Jul 10 05:58:17 PM PDT 24
Peak memory 232764 kb
Host smart-75f74c3d-68aa-4b96-8227-5f2db3d9f593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290184201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.290184201
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.4065978222
Short name T840
Test name
Test status
Simulation time 39947989097 ps
CPU time 38.36 seconds
Started Jul 10 05:58:08 PM PDT 24
Finished Jul 10 05:58:47 PM PDT 24
Peak memory 233704 kb
Host smart-99e9b050-a8fb-4127-a94d-24e991c24649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065978222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.4065978222
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.3481699376
Short name T752
Test name
Test status
Simulation time 657009751 ps
CPU time 5.37 seconds
Started Jul 10 05:58:05 PM PDT 24
Finished Jul 10 05:58:11 PM PDT 24
Peak memory 232628 kb
Host smart-0ef256e7-a081-4e09-8f19-2eaec5c956b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481699376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.3481699376
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.3133664204
Short name T959
Test name
Test status
Simulation time 2785189707 ps
CPU time 7.6 seconds
Started Jul 10 05:58:06 PM PDT 24
Finished Jul 10 05:58:15 PM PDT 24
Peak memory 224628 kb
Host smart-17ddd541-e4ad-4828-ae4f-95898cfd2325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133664204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.3133664204
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.1354451061
Short name T925
Test name
Test status
Simulation time 444828081 ps
CPU time 5.96 seconds
Started Jul 10 05:58:06 PM PDT 24
Finished Jul 10 05:58:14 PM PDT 24
Peak memory 223116 kb
Host smart-c0dde17e-8065-4ee6-93b7-e936ed424c66
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1354451061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.1354451061
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.3934878582
Short name T783
Test name
Test status
Simulation time 131761819564 ps
CPU time 462.14 seconds
Started Jul 10 05:58:05 PM PDT 24
Finished Jul 10 06:05:48 PM PDT 24
Peak memory 273860 kb
Host smart-eeb6bf81-39d3-4709-83c0-f663f916dc63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934878582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.3934878582
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.3561766241
Short name T137
Test name
Test status
Simulation time 3814308621 ps
CPU time 26.19 seconds
Started Jul 10 05:58:05 PM PDT 24
Finished Jul 10 05:58:32 PM PDT 24
Peak memory 220332 kb
Host smart-bb10595c-48a0-4e21-a8ee-992143790b38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561766241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.3561766241
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.2826657687
Short name T865
Test name
Test status
Simulation time 3386215950 ps
CPU time 10.3 seconds
Started Jul 10 05:58:06 PM PDT 24
Finished Jul 10 05:58:18 PM PDT 24
Peak memory 216316 kb
Host smart-be464248-95a6-4538-8c58-970fb6d6cb99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826657687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.2826657687
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.692812927
Short name T737
Test name
Test status
Simulation time 72228338 ps
CPU time 0.85 seconds
Started Jul 10 05:58:09 PM PDT 24
Finished Jul 10 05:58:10 PM PDT 24
Peak memory 205900 kb
Host smart-9835c627-d44b-4073-ba71-0acfb25f0a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692812927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.692812927
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.2848758411
Short name T1003
Test name
Test status
Simulation time 36478069 ps
CPU time 0.84 seconds
Started Jul 10 05:58:06 PM PDT 24
Finished Jul 10 05:58:08 PM PDT 24
Peak memory 205980 kb
Host smart-25d02b21-cfd2-4922-ab73-d7541f316456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848758411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.2848758411
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.756727972
Short name T764
Test name
Test status
Simulation time 5001435919 ps
CPU time 11.04 seconds
Started Jul 10 05:58:08 PM PDT 24
Finished Jul 10 05:58:20 PM PDT 24
Peak memory 224808 kb
Host smart-813b2829-a0bc-4bbe-ae57-8917306515fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756727972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.756727972
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.172561961
Short name T138
Test name
Test status
Simulation time 36534474 ps
CPU time 0.73 seconds
Started Jul 10 05:58:11 PM PDT 24
Finished Jul 10 05:58:14 PM PDT 24
Peak memory 205868 kb
Host smart-8c60693a-aecc-4401-b70b-a1e126de91d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172561961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.172561961
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.432580200
Short name T372
Test name
Test status
Simulation time 212823368 ps
CPU time 3.86 seconds
Started Jul 10 05:58:10 PM PDT 24
Finished Jul 10 05:58:16 PM PDT 24
Peak memory 224440 kb
Host smart-7539af9e-2216-4f25-ad94-fcac5718cf85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432580200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.432580200
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.190834230
Short name T378
Test name
Test status
Simulation time 13695528 ps
CPU time 0.78 seconds
Started Jul 10 05:58:07 PM PDT 24
Finished Jul 10 05:58:09 PM PDT 24
Peak memory 206924 kb
Host smart-e28cfce2-5105-493e-886e-b6c441a62c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190834230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.190834230
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.3518813711
Short name T685
Test name
Test status
Simulation time 18617751334 ps
CPU time 63.78 seconds
Started Jul 10 05:58:11 PM PDT 24
Finished Jul 10 05:59:18 PM PDT 24
Peak memory 255036 kb
Host smart-bc1f53f8-425e-4ccd-a045-f08509838f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518813711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.3518813711
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.4277116022
Short name T503
Test name
Test status
Simulation time 22222659514 ps
CPU time 186.1 seconds
Started Jul 10 05:58:17 PM PDT 24
Finished Jul 10 06:01:25 PM PDT 24
Peak memory 232868 kb
Host smart-69c6999e-19cf-42c8-951d-1e69b8e0eb5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277116022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.4277116022
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.753481821
Short name T806
Test name
Test status
Simulation time 148913758336 ps
CPU time 211.04 seconds
Started Jul 10 05:58:10 PM PDT 24
Finished Jul 10 06:01:43 PM PDT 24
Peak memory 250292 kb
Host smart-4194b1c5-36fd-4232-9004-833ebb18878d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753481821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle.
753481821
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.1359432989
Short name T24
Test name
Test status
Simulation time 368206384 ps
CPU time 3.06 seconds
Started Jul 10 05:58:10 PM PDT 24
Finished Jul 10 05:58:16 PM PDT 24
Peak memory 224428 kb
Host smart-8d52b8e5-347c-4561-b36f-74650f76d897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359432989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.1359432989
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.365460856
Short name T758
Test name
Test status
Simulation time 40788446131 ps
CPU time 164.1 seconds
Started Jul 10 05:58:11 PM PDT 24
Finished Jul 10 06:00:58 PM PDT 24
Peak memory 254768 kb
Host smart-54e96a9c-2679-4bb7-bd20-f163cb78513c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365460856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds.
365460856
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.1313389302
Short name T774
Test name
Test status
Simulation time 666590320 ps
CPU time 9.79 seconds
Started Jul 10 05:58:10 PM PDT 24
Finished Jul 10 05:58:23 PM PDT 24
Peak memory 224432 kb
Host smart-d7477be6-fd87-435d-a274-d3dc7d708686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313389302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.1313389302
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.1290997124
Short name T818
Test name
Test status
Simulation time 259532959 ps
CPU time 3.4 seconds
Started Jul 10 05:58:10 PM PDT 24
Finished Jul 10 05:58:15 PM PDT 24
Peak memory 218920 kb
Host smart-d9414341-96db-40af-bc85-730285ce352e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290997124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.1290997124
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.1587285413
Short name T606
Test name
Test status
Simulation time 2591455953 ps
CPU time 4.04 seconds
Started Jul 10 05:58:17 PM PDT 24
Finished Jul 10 05:58:23 PM PDT 24
Peak memory 224524 kb
Host smart-722a6082-6bdb-4400-b565-c382714a667b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587285413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.1587285413
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.4267630423
Short name T484
Test name
Test status
Simulation time 1605597113 ps
CPU time 9.33 seconds
Started Jul 10 05:58:10 PM PDT 24
Finished Jul 10 05:58:21 PM PDT 24
Peak memory 232636 kb
Host smart-9bada72a-c90b-44ee-b255-93acb940125e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267630423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.4267630423
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.1106554198
Short name T657
Test name
Test status
Simulation time 182384835 ps
CPU time 3.98 seconds
Started Jul 10 05:58:11 PM PDT 24
Finished Jul 10 05:58:17 PM PDT 24
Peak memory 222616 kb
Host smart-9f3640c2-0b0b-4e1b-a77a-5514dc7b149a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1106554198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.1106554198
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.1786010205
Short name T168
Test name
Test status
Simulation time 3017764858 ps
CPU time 69.36 seconds
Started Jul 10 05:58:09 PM PDT 24
Finished Jul 10 05:59:21 PM PDT 24
Peak memory 253844 kb
Host smart-e6c763a4-aa46-4f27-ae82-8279cdeca1e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786010205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.1786010205
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.4090916169
Short name T990
Test name
Test status
Simulation time 17967953635 ps
CPU time 28.68 seconds
Started Jul 10 05:58:09 PM PDT 24
Finished Jul 10 05:58:39 PM PDT 24
Peak memory 218352 kb
Host smart-3de42ea1-dddc-4591-9688-9f933220f9c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090916169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.4090916169
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.1998588645
Short name T903
Test name
Test status
Simulation time 516947844 ps
CPU time 3.69 seconds
Started Jul 10 05:58:11 PM PDT 24
Finished Jul 10 05:58:17 PM PDT 24
Peak memory 216276 kb
Host smart-8276ada9-a369-41e9-8da3-cc664097bddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998588645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.1998588645
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.3219993790
Short name T543
Test name
Test status
Simulation time 56419460 ps
CPU time 1.19 seconds
Started Jul 10 05:58:17 PM PDT 24
Finished Jul 10 05:58:21 PM PDT 24
Peak memory 207264 kb
Host smart-6591ab7f-7d0c-45a4-9fae-6f3241428ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219993790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.3219993790
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.2877231207
Short name T822
Test name
Test status
Simulation time 42653462 ps
CPU time 0.71 seconds
Started Jul 10 05:58:09 PM PDT 24
Finished Jul 10 05:58:12 PM PDT 24
Peak memory 205944 kb
Host smart-9e216511-be63-4b5e-bde3-dd68745305f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877231207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.2877231207
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.31915075
Short name T912
Test name
Test status
Simulation time 8959176975 ps
CPU time 24.43 seconds
Started Jul 10 05:58:10 PM PDT 24
Finished Jul 10 05:58:37 PM PDT 24
Peak memory 224616 kb
Host smart-85c44c40-3735-4d21-9c8f-f81b0f058862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31915075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.31915075
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.134611914
Short name T833
Test name
Test status
Simulation time 14902055 ps
CPU time 0.72 seconds
Started Jul 10 05:58:17 PM PDT 24
Finished Jul 10 05:58:20 PM PDT 24
Peak memory 205916 kb
Host smart-000f9425-55fa-4596-9cdd-0dc76ad33137
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134611914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.134611914
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.2073834180
Short name T491
Test name
Test status
Simulation time 62692029 ps
CPU time 3.17 seconds
Started Jul 10 05:58:12 PM PDT 24
Finished Jul 10 05:58:18 PM PDT 24
Peak memory 224464 kb
Host smart-4f172e93-2055-4f6d-a1d9-d021f61f32c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073834180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.2073834180
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.2793875673
Short name T802
Test name
Test status
Simulation time 17060351 ps
CPU time 0.79 seconds
Started Jul 10 05:58:10 PM PDT 24
Finished Jul 10 05:58:13 PM PDT 24
Peak memory 206916 kb
Host smart-1b8aee6d-9fc7-4545-8815-790d3d9241f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793875673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.2793875673
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.747658168
Short name T759
Test name
Test status
Simulation time 56529175189 ps
CPU time 107.74 seconds
Started Jul 10 05:58:15 PM PDT 24
Finished Jul 10 06:00:04 PM PDT 24
Peak memory 249204 kb
Host smart-bf39cdc7-66c2-439e-9cd5-310ede1ef5d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747658168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.747658168
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.2253876204
Short name T178
Test name
Test status
Simulation time 93911996769 ps
CPU time 235.49 seconds
Started Jul 10 05:58:17 PM PDT 24
Finished Jul 10 06:02:15 PM PDT 24
Peak memory 264172 kb
Host smart-a36687bc-7996-4ede-a49a-0384a2e8afb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253876204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.2253876204
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.1757615214
Short name T668
Test name
Test status
Simulation time 92798662040 ps
CPU time 244.56 seconds
Started Jul 10 05:58:16 PM PDT 24
Finished Jul 10 06:02:22 PM PDT 24
Peak memory 250284 kb
Host smart-6f3749b1-e220-4983-8158-6bbe20962932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757615214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.1757615214
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.2105133364
Short name T323
Test name
Test status
Simulation time 2260031773 ps
CPU time 21.13 seconds
Started Jul 10 05:58:17 PM PDT 24
Finished Jul 10 05:58:41 PM PDT 24
Peak memory 223852 kb
Host smart-cd2d19e2-2ced-496c-a26b-bf63661a6b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105133364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.2105133364
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.2005363338
Short name T725
Test name
Test status
Simulation time 9490459968 ps
CPU time 19.09 seconds
Started Jul 10 05:58:16 PM PDT 24
Finished Jul 10 05:58:36 PM PDT 24
Peak memory 236524 kb
Host smart-26f6af8e-2a99-4186-a1ef-e8845901b1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005363338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds
.2005363338
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.2018162778
Short name T754
Test name
Test status
Simulation time 106478666 ps
CPU time 2.88 seconds
Started Jul 10 05:58:09 PM PDT 24
Finished Jul 10 05:58:14 PM PDT 24
Peak memory 232628 kb
Host smart-956d5c20-ba29-471f-9e06-ea2eb0088571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018162778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.2018162778
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.1287331067
Short name T766
Test name
Test status
Simulation time 269325622 ps
CPU time 8.05 seconds
Started Jul 10 05:58:11 PM PDT 24
Finished Jul 10 05:58:22 PM PDT 24
Peak memory 232620 kb
Host smart-bf7291ce-06c1-4686-9724-93ad0f12093d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287331067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.1287331067
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.3318778573
Short name T694
Test name
Test status
Simulation time 488685971 ps
CPU time 2.96 seconds
Started Jul 10 05:58:11 PM PDT 24
Finished Jul 10 05:58:17 PM PDT 24
Peak memory 232708 kb
Host smart-3921e204-177d-4f56-9d98-e6fa30176918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318778573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.3318778573
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.1966577921
Short name T270
Test name
Test status
Simulation time 300861292 ps
CPU time 4.8 seconds
Started Jul 10 05:58:17 PM PDT 24
Finished Jul 10 05:58:24 PM PDT 24
Peak memory 232616 kb
Host smart-583de4d2-c2be-4501-973c-0f2d445de1cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966577921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.1966577921
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.1391410368
Short name T859
Test name
Test status
Simulation time 1701528856 ps
CPU time 8.96 seconds
Started Jul 10 05:58:16 PM PDT 24
Finished Jul 10 05:58:28 PM PDT 24
Peak memory 219260 kb
Host smart-2012c76f-890e-414a-a076-8d567eeaa747
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1391410368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.1391410368
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.2219116297
Short name T288
Test name
Test status
Simulation time 136109746364 ps
CPU time 257.42 seconds
Started Jul 10 05:58:16 PM PDT 24
Finished Jul 10 06:02:34 PM PDT 24
Peak memory 265208 kb
Host smart-bfc295a4-eff8-4ac9-beaf-545dd0e050bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219116297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.2219116297
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.112963709
Short name T170
Test name
Test status
Simulation time 3474908470 ps
CPU time 27.57 seconds
Started Jul 10 05:58:12 PM PDT 24
Finished Jul 10 05:58:42 PM PDT 24
Peak memory 216356 kb
Host smart-3e35131b-edd0-4b5d-9a7d-b5786f6fdb0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112963709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.112963709
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.3056331317
Short name T692
Test name
Test status
Simulation time 4223064858 ps
CPU time 4.86 seconds
Started Jul 10 05:58:10 PM PDT 24
Finished Jul 10 05:58:17 PM PDT 24
Peak memory 216340 kb
Host smart-46d7da41-117b-4174-8d73-561e7e5cd32d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056331317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.3056331317
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.2415225812
Short name T595
Test name
Test status
Simulation time 474899242 ps
CPU time 2.03 seconds
Started Jul 10 05:58:12 PM PDT 24
Finished Jul 10 05:58:16 PM PDT 24
Peak memory 216248 kb
Host smart-34c94115-7651-44e4-bc63-c669fddd3287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415225812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.2415225812
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.1209870851
Short name T647
Test name
Test status
Simulation time 46655739 ps
CPU time 0.72 seconds
Started Jul 10 05:58:11 PM PDT 24
Finished Jul 10 05:58:15 PM PDT 24
Peak memory 205968 kb
Host smart-ae9c7afc-4e98-4344-b8c4-f70c0ddeff95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209870851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.1209870851
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.2257050166
Short name T893
Test name
Test status
Simulation time 11085861987 ps
CPU time 19.78 seconds
Started Jul 10 05:58:12 PM PDT 24
Finished Jul 10 05:58:34 PM PDT 24
Peak memory 233012 kb
Host smart-61eb98bd-8df1-483d-9e57-9747982eb517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257050166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.2257050166
Directory /workspace/9.spi_device_upload/latest
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