Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2875327	1			T1	1		T2	1		T3	34
all_values[1]	2875327	1			T1	1		T2	1		T3	34
all_values[2]	2875327	1			T1	1		T2	1		T3	34
all_values[3]	2875327	1			T1	1		T2	1		T3	34
all_values[4]	2875327	1			T1	1		T2	1		T3	34
all_values[5]	2875327	1			T1	1		T2	1		T3	34
all_values[6]	2875327	1			T1	1		T2	1		T3	34
all_values[7]	2875327	1			T1	1		T2	1		T3	34

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22778470

1

T1

8

T2

8

T3

272

auto[1]

224146

1

T15

32

T16

112

T18

44

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22974721

1

T1

8

T2

8

T3

272

auto[1]

27895

1

T5

17

T7

401

T8

327

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2823828	1			T1	1		T2	1		T3	34
all_values[0]	auto[0]	auto[1]	13290	1			T5	17		T7	238		T8	194
all_values[0]	auto[1]	auto[0]	37802	1			T15	7		T16	12		T18	6
all_values[0]	auto[1]	auto[1]	407	1			T15	2		T16	5		T18	2
all_values[1]	auto[0]	auto[0]	2856528	1			T1	1		T2	1		T3	34
all_values[1]	auto[0]	auto[1]	8618	1			T7	123		T8	87		T14	119
all_values[1]	auto[1]	auto[0]	9830	1			T15	2		T16	4		T18	5
all_values[1]	auto[1]	auto[1]	351	1			T15	4		T16	3		T18	1
all_values[2]	auto[0]	auto[0]	2845694	1			T1	1		T2	1		T3	34
all_values[2]	auto[0]	auto[1]	2992	1			T7	40		T8	46		T14	64
all_values[2]	auto[1]	auto[0]	26353	1			T15	2		T16	7		T18	2
all_values[2]	auto[1]	auto[1]	288	1			T16	5		T18	3		T19	1
all_values[3]	auto[0]	auto[0]	2842287	1			T1	1		T2	1		T3	34
all_values[3]	auto[0]	auto[1]	193	1			T15	4		T16	9		T18	2
all_values[3]	auto[1]	auto[0]	32641	1			T15	1		T16	6		T18	2
all_values[3]	auto[1]	auto[1]	206	1			T15	1		T16	7		T18	2
all_values[4]	auto[0]	auto[0]	2864870	1			T1	1		T2	1		T3	34
all_values[4]	auto[0]	auto[1]	227	1			T15	4		T16	3		T18	2
all_values[4]	auto[1]	auto[0]	10016	1			T15	2		T16	7		T18	1
all_values[4]	auto[1]	auto[1]	214	1			T15	1		T16	10		T18	6
all_values[5]	auto[0]	auto[0]	2838998	1			T1	1		T2	1		T3	34
all_values[5]	auto[0]	auto[1]	172	1			T16	6		T18	3		T21	1
all_values[5]	auto[1]	auto[0]	35970	1			T15	6		T16	15		T18	1
all_values[5]	auto[1]	auto[1]	187	1			T15	1		T16	4		T18	4
all_values[6]	auto[0]	auto[0]	2840653	1			T1	1		T2	1		T3	34
all_values[6]	auto[0]	auto[1]	182	1			T15	6		T16	7		T18	3
all_values[6]	auto[1]	auto[0]	34288	1			T16	8		T18	4		T19	1
all_values[6]	auto[1]	auto[1]	204	1			T15	1		T16	8		T18	2
all_values[7]	auto[0]	auto[0]	2839762	1			T1	1		T2	1		T3	34
all_values[7]	auto[0]	auto[1]	176	1			T15	4		T16	6		T18	4
all_values[7]	auto[1]	auto[0]	35201	1			T15	1		T16	5		T18	2
all_values[7]	auto[1]	auto[1]	188	1			T15	1		T16	6		T18	1