Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	40269	1			T1	14		T2	12		T3	4
auto[SpiFlashAddrCfg]	8220	1			T3	4		T5	21		T7	40
auto[SpiFlashAddr3b]	9983	1			T5	18		T7	47		T8	40
auto[SpiFlashAddr4b]	8228	1			T5	7		T7	38		T8	44

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

37672

1

T1

14

T2

12

T3

8

auto[1]

29028

1

T5

38

T7

147

T8

96

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

35425

1

T1

14

T2

12

T3

6

auto[1]

31275

1

T3

2

T5

25

T7

136

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	45293	1			T1	14		T2	12		T5	46
values[1]	1298	1			T5	3		T7	8		T8	1
values[2]	1641	1			T5	5		T7	7		T8	4
values[3]	1564	1			T5	3		T7	6		T8	10
values[4]	1572	1			T5	2		T7	1		T8	8
values[5]	1559	1			T7	5		T8	6		T10	1
values[6]	1656	1			T7	8		T8	10		T13	4
values[7]	1555	1			T5	1		T7	8		T8	3
values[8]	10562	1			T3	8		T5	25		T7	48

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33381

1

T1

14

T2

12

T3

8

auto[1]

33319

1

T5

85

T7

277

T10

6

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

63106

1

T1

14

T2

12

T3

8

write

3594

1

T5

3

T7

18

T8

8

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

20979

1

T1

14

T2

12

T3

4

valids[0x1]

45721

1

T3

4

T5

48

T7

187

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1726	1			T5	2		T7	8		T8	7
internal_process_ops[0x5a]	1686	1			T5	2		T7	8		T8	2
internal_process_ops[0x05]	25073	1			T5	10		T7	86		T8	28
internal_process_ops[0x35]	1712	1			T5	5		T7	11		T8	7
internal_process_ops[0x15]	1683	1			T5	3		T7	15		T8	11
internal_process_ops[0x03]	1176	1			T5	1		T7	10		T8	8
internal_process_ops[0x0b]	1165	1			T5	2		T7	4		T8	6
internal_process_ops[0x3b]	1132	1			T5	3		T7	6		T8	5
internal_process_ops[0x6b]	1210	1			T7	2		T8	9		T13	4
internal_process_ops[0xbb]	1082	1			T3	2		T7	1		T8	3
internal_process_ops[0xeb]	1163	1			T7	3		T8	7		T10	2

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

64921

1

T1

14

T2

12

T3

8

auto[1]

1779

1

T5

2

T7

5

T8

3

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

64105

1

T1

14

T2

12

T3

8

auto[1]

2595

1

T5

1

T7

23

T8

12

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10996

1

T1

14

T2

12

T3

4

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7009

1

T8

38

T13

9

T26

52

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2251

1

T3

4

T8

25

T13

12

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1984

1

T8

17

T13

4

T26

21

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2747

1

T8

24

T12

4

T13

11

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2431

1

T8

14

T13

12

T26

29

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2295

1

T8

20

T13

13

T26

19

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1973

1

T8

21

T13

6

T26

21

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

122

1

T26

1

T146

2

T40

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

118

1

T26

1

T30

2

T41

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

106

1

T8

2

T40

1

T39

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

123

1

T26

1

T14

2

T40

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

120

1

T13

3

T14

4

T21

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

86

1

T13

1

T30

1

T14

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

100

1

T26

1

T40

2

T21

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

124

1

T8

1

T13

3

T26

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

117

1

T8

1

T26

1

T14

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

91

1

T13

1

T26

1

T17

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

73

1

T26

2

T14

3

T39

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

115

1

T8

1

T30

1

T40

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

105

1

T26

1

T40

1

T41

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

95

1

T8

1

T30

1

T14

4

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

90

1

T8

2

T40

1

T39

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

110

1

T29

2

T14

1

T40

2

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

12477

1

T5

26

T7

71

T35

128

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

8820

1

T5

13

T7

78

T35

464

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1609

1

T5

8

T7

18

T10

2

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1499

1

T5

13

T7

15

T35

17

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1972

1

T5

11

T7

16

T10

3

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1949

1

T5

6

T7

27

T35

28

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1554

1

T5

2

T7

13

T10

1

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1540

1

T5

3

T7

21

T35

18

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

143

1

T7

2

T35

2

T15

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

115

1

T7

1

T35

5

T43

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

130

1

T35

1

T15

4

T17

4

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

110

1

T35

3

T15

2

T18

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

105

1

T7

1

T35

2

T15

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

113

1

T7

2

T35

2

T70

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

123

1

T7

3

T35

1

T43

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

106

1

T7

1

T35

2

T15

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

113

1

T7

3

T35

4

T17

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

112

1

T35

4

T70

2

T17

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

139

1

T5

1

T7

1

T35

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

124

1

T17

4

T18

3

T19

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

119

1

T7

3

T43

2

T15

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

97

1

T35

1

T43

1

T17

7

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

110

1

T35

1

T15

2

T70

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

140

1

T5

2

T7

1

T35

7

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	4190	1			T1	14		T2	12		T8	42
auto[0]	values[0]	valids[0x1]	16827	1			T8	87		T12	4		T13	22
auto[0]	values[1]	valids[0x1]	677	1			T8	1		T13	12		T26	4
auto[0]	values[2]	valids[0x0]	594	1			T8	2		T13	1		T26	4
auto[0]	values[2]	valids[0x1]	337	1			T8	2		T13	3		T26	8
auto[0]	values[3]	valids[0x0]	581	1			T8	6		T26	3		T30	3
auto[0]	values[3]	valids[0x1]	313	1			T8	4		T26	4		T14	2
auto[0]	values[4]	valids[0x0]	570	1			T8	6		T13	4		T26	13
auto[0]	values[4]	valids[0x1]	336	1			T8	2		T13	1		T26	10
auto[0]	values[5]	valids[0x0]	611	1			T8	4		T13	3		T26	9
auto[0]	values[5]	valids[0x1]	330	1			T8	2		T13	1		T26	2
auto[0]	values[6]	valids[0x0]	634	1			T8	7		T13	2		T26	3
auto[0]	values[6]	valids[0x1]	335	1			T8	3		T13	2		T26	5
auto[0]	values[7]	valids[0x0]	608	1			T8	2		T13	1		T26	8
auto[0]	values[7]	valids[0x1]	304	1			T8	1		T26	3		T38	2
auto[0]	values[8]	valids[0x0]	3930	1			T3	4		T8	37		T13	7
auto[0]	values[8]	valids[0x1]	2204	1			T3	4		T8	13		T13	23
auto[1]	values[0]	valids[0x0]	4233	1			T5	15		T7	35		T35	47
auto[1]	values[0]	valids[0x1]	20043	1			T5	31		T7	151		T35	594
auto[1]	values[1]	valids[0x1]	621	1			T5	3		T7	8		T35	11
auto[1]	values[2]	valids[0x0]	414	1			T5	5		T7	5		T35	1
auto[1]	values[2]	valids[0x1]	296	1			T7	2		T35	1		T43	3
auto[1]	values[3]	valids[0x0]	378	1			T5	1		T7	1		T35	8
auto[1]	values[3]	valids[0x1]	292	1			T5	2		T7	5		T35	7
auto[1]	values[4]	valids[0x0]	389	1			T5	2		T37	1		T35	14
auto[1]	values[4]	valids[0x1]	277	1			T7	1		T10	1		T35	2
auto[1]	values[5]	valids[0x0]	372	1			T7	5		T35	2		T43	7
auto[1]	values[5]	valids[0x1]	246	1			T10	1		T35	8		T43	2
auto[1]	values[6]	valids[0x0]	409	1			T7	6		T37	6		T35	4
auto[1]	values[6]	valids[0x1]	278	1			T7	2		T35	3		T15	1
auto[1]	values[7]	valids[0x0]	374	1			T5	1		T7	5		T43	2
auto[1]	values[7]	valids[0x1]	269	1			T7	3		T35	3		T17	5
auto[1]	values[8]	valids[0x0]	2692	1			T5	13		T7	33		T10	4
auto[1]	values[8]	valids[0x1]	1736	1			T5	12		T7	15		T35	24