Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3762192

1

T1

1400

T2

4501

T3

1

auto[1]

34078

1

T5

5

T7

77

T8

21

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1062889

1

T1

1400

T2

4501

T3

1

auto[1]

2733381

1

T5

7923

T7

15721

T8

10208

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	734019	1			T1	19		T2	1844		T3	1
auto[524288:1048575]	400959	1			T1	494		T2	568		T5	4
auto[1048576:1572863]	446209	1			T2	828		T5	396		T7	784
auto[1572864:2097151]	444416	1			T1	451		T2	713		T5	2806
auto[2097152:2621439]	496237	1			T1	8		T2	346		T5	2935
auto[2621440:3145727]	420388	1			T1	1		T5	3		T7	4907
auto[3145728:3670015]	423628	1			T1	424		T2	157		T5	2
auto[3670016:4194303]	430414	1			T1	3		T2	45		T5	1784

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2768534

1

T1

33

T2

115

T3

1

auto[1]

1027736

1

T1

1367

T2

4386

T7

2

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3302128

1

T1

905

T2

391

T3

1

auto[1]

494142

1

T1

495

T2

4110

T5

3

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	271469	1			T1	19		T2	1		T3	1
auto[0]	auto[0]	auto[0:524287]	auto[1]	397174	1			T5	9		T7	1		T8	1
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	78253	1			T2	39		T5	4		T7	8
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	237418	1			T7	2829		T26	129		T14	1
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	116353	1			T5	2		T7	4		T8	1
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	268061	1			T5	394		T7	257		T8	640
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	137855	1			T1	450		T5	1		T7	10
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	246147	1			T5	2805		T7	8		T8	129
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	95788	1			T1	8		T2	346		T5	1
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	336294	1			T5	2934		T7	128		T26	2056
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	124147	1			T1	1		T7	10		T8	4
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	230331	1			T7	4867		T8	2629		T26	1999
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	115988	1			T1	424		T7	6		T8	4
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	251872	1			T5	2		T7	515		T8	775
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	106330	1			T1	3		T2	5		T5	4
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	261296	1			T5	1775		T7	4053		T8	4736
auto[0]	auto[1]	auto[0:524287]	auto[0]	2660	1			T2	1843		T8	4		T13	5
auto[0]	auto[1]	auto[0:524287]	auto[1]	57984	1			T8	896		T30	2944		T14	129
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	2429	1			T1	494		T2	529		T13	7
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	78936	1			T13	2891		T14	4		T70	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	1548	1			T2	828		T7	3		T13	22
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	56005	1			T7	514		T26	1		T14	512
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	1345	1			T1	1		T2	713		T8	5
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	54672	1			T8	391		T35	769		T70	256
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	1507	1			T7	2		T13	11		T26	3
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	57454	1			T7	2495		T26	2956		T35	640
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	1762	1			T5	3		T8	2		T13	33
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	60519	1			T8	1		T13	5		T26	2592
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	751	1			T2	157		T8	3		T26	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	50386	1			T8	1		T30	631		T14	1
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	625	1			T2	40		T7	1		T13	18
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	58833	1			T13	133		T14	256		T43	128
auto[1]	auto[0]	auto[0:524287]	auto[0]	538	1			T7	1		T8	1		T26	2
auto[1]	auto[0]	auto[0:524287]	auto[1]	3486	1			T14	3		T35	15		T15	7
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	374	1			T7	3		T26	1		T14	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	2693	1			T7	2		T26	3		T14	6
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	418	1			T7	1		T14	2		T35	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	3020	1			T7	1		T14	4		T35	40
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	344	1			T7	4		T8	1		T30	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	2792	1			T7	11		T30	50		T17	31
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	531	1			T26	5		T35	2		T15	3
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	3700	1			T26	42		T35	42		T15	4
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	362	1			T7	5		T8	2		T26	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2526	1			T7	25		T26	35		T35	42
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	417	1			T7	3		T8	2		T14	2
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	3425	1			T7	2		T8	2		T14	2
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	373	1			T5	1		T7	3		T8	2
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2353	1			T5	4		T7	9		T30	76
auto[1]	auto[1]	auto[0:524287]	auto[0]	64	1			T14	1		T35	1		T18	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	644	1			T14	2		T35	23		T39	25
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	91	1			T14	4		T70	1		T17	2
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	765	1			T14	23		T70	12		T17	14
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	120	1			T7	2		T13	10		T26	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	684	1			T7	2		T26	13		T35	27
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	86	1			T8	2		T13	3		T35	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	1175	1			T8	3		T35	37		T18	43
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	101	1			T7	1		T13	2		T40	10
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	862	1			T7	2		T70	1		T17	102
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	95	1			T8	1		T14	1		T40	9
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	646	1			T8	4		T14	2		T40	52
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	89	1			T8	1		T14	1		T40	5
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	700	1			T14	2		T39	126		T41	3
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	76	1			T19	1		T52	14		T184	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	528	1			T19	7		T184	1		T159	59

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	2255493	1			T1	32		T2	42		T3	1
auto[0]	auto[0]	auto[1]	1019283	1			T1	873		T2	349		T7	1
auto[0]	auto[1]	auto[0]	479630	1			T1	1		T2	73		T5	3
auto[0]	auto[1]	auto[1]	7786	1			T1	494		T2	4037		T26	1
auto[1]	auto[0]	auto[0]	26813	1			T5	5		T7	69		T8	10
auto[1]	auto[0]	auto[1]	539	1			T7	1		T13	1		T26	1
auto[1]	auto[1]	auto[0]	6598	1			T7	7		T8	11		T13	11
auto[1]	auto[1]	auto[1]	128	1			T13	4		T35	1		T40	5