Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2875327	1			T1	1		T2	1		T3	34
all_pins[1]	2875327	1			T1	1		T2	1		T3	34
all_pins[2]	2875327	1			T1	1		T2	1		T3	34
all_pins[3]	2875327	1			T1	1		T2	1		T3	34
all_pins[4]	2875327	1			T1	1		T2	1		T3	34
all_pins[5]	2875327	1			T1	1		T2	1		T3	34
all_pins[6]	2875327	1			T1	1		T2	1		T3	34
all_pins[7]	2875327	1			T1	1		T2	1		T3	34

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	22965347	1			T1	8		T2	8		T3	272
values[0x1]	37269	1			T15	11		T16	48		T18	21
transitions[0x0=>0x1]	35951	1			T15	9		T16	34		T18	14
transitions[0x1=>0x0]	35967	1			T15	9		T16	35		T18	14

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2874903	1			T1	1		T2	1		T3	34
all_pins[0]	values[0x1]	424	1			T15	2		T16	5		T18	2
all_pins[0]	transitions[0x0=>0x1]	242	1			T15	1		T16	5		T18	1
all_pins[0]	transitions[0x1=>0x0]	194	1			T15	3		T16	3		T19	17
all_pins[1]	values[0x0]	2874951	1			T1	1		T2	1		T3	34
all_pins[1]	values[0x1]	376	1			T15	4		T16	3		T18	1
all_pins[1]	transitions[0x0=>0x1]	263	1			T15	4		T16	3		T18	1
all_pins[1]	transitions[0x1=>0x0]	180	1			T16	5		T18	3		T19	1
all_pins[2]	values[0x0]	2875034	1			T1	1		T2	1		T3	34
all_pins[2]	values[0x1]	293	1			T16	5		T18	3		T19	1
all_pins[2]	transitions[0x0=>0x1]	238	1			T16	5		T18	3		T19	1
all_pins[2]	transitions[0x1=>0x0]	151	1			T15	1		T16	7		T18	2
all_pins[3]	values[0x0]	2875121	1			T1	1		T2	1		T3	34
all_pins[3]	values[0x1]	206	1			T15	1		T16	7		T18	2
all_pins[3]	transitions[0x0=>0x1]	166	1			T15	1		T16	2		T21	2
all_pins[3]	transitions[0x1=>0x0]	174	1			T15	1		T16	5		T18	4
all_pins[4]	values[0x0]	2875113	1			T1	1		T2	1		T3	34
all_pins[4]	values[0x1]	214	1			T15	1		T16	10		T18	6
all_pins[4]	transitions[0x0=>0x1]	164	1			T15	1		T16	7		T18	5
all_pins[4]	transitions[0x1=>0x0]	1426	1			T15	1		T16	1		T18	3
all_pins[5]	values[0x0]	2873851	1			T1	1		T2	1		T3	34
all_pins[5]	values[0x1]	1476	1			T15	1		T16	4		T18	4
all_pins[5]	transitions[0x0=>0x1]	714	1			T15	1		T16	3		T18	2
all_pins[5]	transitions[0x1=>0x0]	33330	1			T15	1		T16	7		T21	1
all_pins[6]	values[0x0]	2841235	1			T1	1		T2	1		T3	34
all_pins[6]	values[0x1]	34092	1			T15	1		T16	8		T18	2
all_pins[6]	transitions[0x0=>0x1]	34033	1			T16	6		T18	2		T147	5
all_pins[6]	transitions[0x1=>0x0]	129	1			T16	4		T18	1		T21	2
all_pins[7]	values[0x0]	2875139	1			T1	1		T2	1		T3	34
all_pins[7]	values[0x1]	188	1			T15	1		T16	6		T18	1
all_pins[7]	transitions[0x0=>0x1]	131	1			T15	1		T16	3		T21	2
all_pins[7]	transitions[0x1=>0x0]	383	1			T15	2		T16	3		T18	1