Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19143

1

T1

14

T2

12

T3

8

auto[1]

14238

1

T8

96

T13

34

T26

128

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4021	1			T8	42		T25	8		T28	4
values[1]	4216	1			T2	12		T8	24		T26	65
values[2]	4978	1			T8	53		T26	104		T14	44
values[3]	3838	1			T13	40		T26	45		T38	18
values[4]	3744	1			T8	41		T12	4		T13	20
values[5]	3892	1			T3	8		T13	20		T26	64
values[6]	3992	1			T1	14		T8	20		T13	20
values[7]	4700	1			T8	41		T29	14		T72	14

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	5215	1			T1	14		T8	62		T25	8
values[1]	4717	1			T8	62		T13	40		T14	43
values[2]	3812	1			T3	8		T28	4		T30	20
values[3]	4363	1			T8	44		T13	20		T26	148
values[4]	4053	1			T8	31		T12	4		T26	40
values[5]	3881	1			T13	20		T26	25		T14	23
values[6]	3252	1			T2	12		T8	22		T13	20
values[7]	4088	1			T30	97		T14	26		T40	40

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	323	1			T8	28		T25	8		T14	7
auto[0]	values[0]	values[1]	372	1			T213	10		T161	67		T197	21
auto[0]	values[0]	values[2]	221	1			T28	4		T214	8		T139	19
auto[0]	values[0]	values[3]	394	1			T30	60		T161	66		T215	12
auto[0]	values[0]	values[4]	283	1			T39	15		T197	83		T216	11
auto[0]	values[0]	values[5]	344	1			T39	8		T188	10		T217	6
auto[0]	values[0]	values[6]	234	1			T110	57		T178	10		T160	10
auto[0]	values[0]	values[7]	179	1			T30	12		T41	13		T163	22
auto[0]	values[1]	values[0]	316	1			T26	13		T14	11		T21	30
auto[0]	values[1]	values[1]	435	1			T146	24		T193	32		T194	4
auto[0]	values[1]	values[2]	407	1			T50	18		T168	16		T197	121
auto[0]	values[1]	values[3]	203	1			T8	18		T30	8		T40	15
auto[0]	values[1]	values[4]	364	1			T26	20		T40	13		T110	125
auto[0]	values[1]	values[5]	245	1			T178	17		T218	9		T219	83
auto[0]	values[1]	values[6]	279	1			T2	12		T184	11		T159	12
auto[0]	values[1]	values[7]	325	1			T21	16		T206	18		T179	9
auto[0]	values[2]	values[0]	370	1			T39	18		T41	12		T163	9
auto[0]	values[2]	values[1]	388	1			T14	13		T96	4		T39	8
auto[0]	values[2]	values[2]	279	1			T40	11		T206	13		T147	14
auto[0]	values[2]	values[3]	442	1			T26	88		T220	2		T208	3
auto[0]	values[2]	values[4]	416	1			T8	14		T40	9		T21	12
auto[0]	values[2]	values[5]	335	1			T14	14		T163	13		T169	42
auto[0]	values[2]	values[6]	192	1			T8	12		T221	2		T184	9
auto[0]	values[2]	values[7]	272	1			T40	9		T163	15		T184	30
auto[0]	values[3]	values[0]	294	1			T26	11		T14	14		T184	13
auto[0]	values[3]	values[1]	521	1			T13	16		T169	50		T206	13
auto[0]	values[3]	values[2]	239	1			T144	4		T168	12		T222	22
auto[0]	values[3]	values[3]	257	1			T13	11		T38	18		T14	24
auto[0]	values[3]	values[4]	256	1			T206	8		T147	14		T179	9
auto[0]	values[3]	values[5]	146	1			T163	13		T168	12		T164	7
auto[0]	values[3]	values[6]	249	1			T223	18		T163	9		T21	13
auto[0]	values[3]	values[7]	333	1			T21	13		T110	71		T159	7
auto[0]	values[4]	values[0]	267	1			T159	11		T166	13		T224	13
auto[0]	values[4]	values[1]	225	1			T8	19		T40	12		T225	2
auto[0]	values[4]	values[2]	212	1			T159	8		T166	15		T226	10
auto[0]	values[4]	values[3]	198	1			T40	6		T163	13		T166	56
auto[0]	values[4]	values[4]	245	1			T12	4		T163	13		T184	8
auto[0]	values[4]	values[5]	401	1			T21	9		T184	14		T168	15
auto[0]	values[4]	values[6]	218	1			T13	14		T26	14		T40	8
auto[0]	values[4]	values[7]	246	1			T40	15		T17	11		T159	10
auto[0]	values[5]	values[0]	208	1			T26	10		T179	10		T190	7
auto[0]	values[5]	values[1]	290	1			T13	12		T41	13		T227	6
auto[0]	values[5]	values[2]	237	1			T3	8		T30	12		T21	11
auto[0]	values[5]	values[3]	341	1			T26	20		T20	18		T21	11
auto[0]	values[5]	values[4]	244	1			T39	14		T21	11		T110	13
auto[0]	values[5]	values[5]	250	1			T228	22		T168	11		T166	12
auto[0]	values[5]	values[6]	178	1			T229	8		T195	27		T32	13
auto[0]	values[5]	values[7]	317	1			T21	12		T206	11		T208	10
auto[0]	values[6]	values[0]	561	1			T1	14		T8	12		T175	18
auto[0]	values[6]	values[1]	212	1			T14	16		T230	8		T166	12
auto[0]	values[6]	values[2]	256	1			T40	13		T163	67		T184	15
auto[0]	values[6]	values[3]	196	1			T21	10		T76	9		T182	26
auto[0]	values[6]	values[4]	230	1			T167	18		T39	10		T112	24
auto[0]	values[6]	values[5]	295	1			T13	13		T26	19		T39	10
auto[0]	values[6]	values[6]	207	1			T40	7		T17	16		T41	29
auto[0]	values[6]	values[7]	265	1			T14	8		T39	14		T159	8
auto[0]	values[7]	values[0]	746	1			T110	11		T161	130		T147	13
auto[0]	values[7]	values[1]	296	1			T8	11		T173	14		T164	10
auto[0]	values[7]	values[2]	372	1			T41	20		T169	9		T159	12
auto[0]	values[7]	values[3]	478	1			T8	11		T14	9		T40	14
auto[0]	values[7]	values[4]	231	1			T72	14		T79	22		T39	16
auto[0]	values[7]	values[5]	368	1			T40	9		T184	46		T212	14
auto[0]	values[7]	values[6]	209	1			T53	10		T41	8		T21	33
auto[0]	values[7]	values[7]	231	1			T73	8		T193	12		T21	5
auto[1]	values[0]	values[0]	172	1			T8	14		T14	16		T39	6
auto[1]	values[0]	values[1]	176	1			T161	4		T197	6		T164	9
auto[1]	values[0]	values[2]	124	1			T139	21		T231	8		T232	5
auto[1]	values[0]	values[3]	340	1			T30	11		T161	3		T178	6
auto[1]	values[0]	values[4]	187	1			T39	5		T197	9		T216	24
auto[1]	values[0]	values[5]	228	1			T39	46		T187	12		T190	6
auto[1]	values[0]	values[6]	138	1			T110	7		T178	10		T160	20
auto[1]	values[0]	values[7]	306	1			T30	85		T41	11		T163	80
auto[1]	values[1]	values[0]	305	1			T26	12		T14	9		T36	8
auto[1]	values[1]	values[1]	269	1			T193	7		T161	73		T173	4
auto[1]	values[1]	values[2]	182	1			T168	4		T197	10		T76	2
auto[1]	values[1]	values[3]	148	1			T8	6		T30	12		T40	5
auto[1]	values[1]	values[4]	186	1			T26	20		T40	7		T110	26
auto[1]	values[1]	values[5]	130	1			T178	3		T218	11		T219	11
auto[1]	values[1]	values[6]	250	1			T184	9		T159	8		T147	7
auto[1]	values[1]	values[7]	172	1			T21	4		T206	37		T179	28
auto[1]	values[2]	values[0]	339	1			T39	2		T41	8		T163	11
auto[1]	values[2]	values[1]	389	1			T14	8		T39	49		T233	24
auto[1]	values[2]	values[2]	332	1			T40	9		T206	18		T147	6
auto[1]	values[2]	values[3]	252	1			T26	16		T208	17		T166	8
auto[1]	values[2]	values[4]	183	1			T8	17		T40	11		T21	8
auto[1]	values[2]	values[5]	257	1			T14	9		T163	33		T169	12
auto[1]	values[2]	values[6]	281	1			T8	10		T184	11		T234	2
auto[1]	values[2]	values[7]	251	1			T40	11		T163	5		T235	4
auto[1]	values[3]	values[0]	260	1			T26	34		T14	9		T184	7
auto[1]	values[3]	values[1]	261	1			T13	4		T169	10		T206	7
auto[1]	values[3]	values[2]	139	1			T168	8		T112	22		T182	8
auto[1]	values[3]	values[3]	137	1			T13	9		T14	51		T163	2
auto[1]	values[3]	values[4]	223	1			T206	12		T147	16		T179	14
auto[1]	values[3]	values[5]	107	1			T163	7		T168	8		T164	25
auto[1]	values[3]	values[6]	187	1			T163	11		T21	7		T169	12
auto[1]	values[3]	values[7]	229	1			T21	12		T110	12		T159	13
auto[1]	values[4]	values[0]	274	1			T159	9		T166	7		T236	16
auto[1]	values[4]	values[1]	212	1			T8	22		T40	8		T224	13
auto[1]	values[4]	values[2]	216	1			T159	12		T166	10		T226	10
auto[1]	values[4]	values[3]	137	1			T40	14		T163	7		T166	12
auto[1]	values[4]	values[4]	303	1			T163	82		T184	12		T168	6
auto[1]	values[4]	values[5]	160	1			T21	18		T184	6		T168	5
auto[1]	values[4]	values[6]	193	1			T13	6		T26	6		T40	12
auto[1]	values[4]	values[7]	237	1			T40	5		T17	11		T159	10
auto[1]	values[5]	values[0]	191	1			T26	10		T179	10		T190	35
auto[1]	values[5]	values[1]	362	1			T13	8		T41	9		T168	11
auto[1]	values[5]	values[2]	206	1			T30	8		T21	51		T168	9
auto[1]	values[5]	values[3]	381	1			T26	24		T20	4		T21	26
auto[1]	values[5]	values[4]	206	1			T39	6		T21	20		T110	35
auto[1]	values[5]	values[5]	189	1			T168	9		T166	22		T173	16
auto[1]	values[5]	values[6]	92	1			T195	18		T32	7		T204	8
auto[1]	values[5]	values[7]	200	1			T21	8		T206	9		T208	10
auto[1]	values[6]	values[0]	212	1			T8	8		T39	10		T20	5
auto[1]	values[6]	values[1]	135	1			T14	6		T166	8		T147	11
auto[1]	values[6]	values[2]	212	1			T40	7		T163	8		T184	5
auto[1]	values[6]	values[3]	203	1			T21	10		T76	11		T182	91
auto[1]	values[6]	values[4]	261	1			T39	75		T237	18		T112	5
auto[1]	values[6]	values[5]	267	1			T13	7		T26	6		T39	66
auto[1]	values[6]	values[6]	166	1			T40	13		T17	4		T41	5
auto[1]	values[6]	values[7]	314	1			T14	18		T39	96		T159	12
auto[1]	values[7]	values[0]	377	1			T110	11		T161	7		T147	10
auto[1]	values[7]	values[1]	174	1			T8	10		T173	7		T164	15
auto[1]	values[7]	values[2]	178	1			T41	7		T169	21		T159	8
auto[1]	values[7]	values[3]	256	1			T8	9		T14	18		T40	6
auto[1]	values[7]	values[4]	235	1			T29	14		T39	19		T110	8
auto[1]	values[7]	values[5]	159	1			T40	11		T184	5		T183	13
auto[1]	values[7]	values[6]	179	1			T41	12		T238	6		T21	8
auto[1]	values[7]	values[7]	211	1			T193	8		T21	81		T239	8