Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	433	1			T8	3		T26	5		T30	1
auto[ReadAddrCrossIntoMailbox]	287	1			T8	4		T26	2		T30	2
auto[ReadAddrCrossOutOfMailbox]	324	1			T8	5		T13	2		T26	1
auto[ReadAddrCrossAllMailbox]	239	1			T8	4		T13	1		T26	3
auto[ReadAddrOutsideMailbox]	3971	1			T3	2		T8	22		T13	18

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2487

1

T3

1

T8

12

T13

11

auto[1]

2767

1

T3

1

T8

26

T13

10

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	886	1			T8	8		T13	4		T26	9
read_ops[0x0b]	885	1			T8	6		T13	7		T26	13
read_ops[0x3b]	861	1			T8	5		T13	1		T26	11
read_ops[0x6b]	911	1			T8	9		T13	4		T26	12
read_ops[0xbb]	820	1			T3	2		T8	3		T13	3
read_ops[0xeb]	891	1			T8	7		T13	2		T26	9

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	32	1			T26	1		T185	1		T39	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	36	1			T8	1		T185	1		T40	2
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T26	1		T39	1		T159	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	30	1			T8	1		T30	1		T14	2
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	32	1			T40	1		T168	1		T206	2
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	26	1			T8	2		T13	1		T193	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	22	1			T13	1		T30	1		T206	2
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	23	1			T30	1		T40	1		T39	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	309	1			T8	3		T13	2		T26	3
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	354	1			T8	1		T26	4		T30	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	35	1			T14	1		T169	1		T159	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	38	1			T26	1		T39	1		T168	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	33	1			T40	1		T21	3		T110	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	20	1			T17	1		T21	1		T184	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T8	1		T40	1		T166	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T26	1		T40	2		T21	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T30	1		T40	2		T110	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T208	1		T164	1		T240	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	324	1			T13	4		T26	6		T29	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	351	1			T8	5		T13	3		T26	5
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	36	1			T30	1		T40	1		T206	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	36	1			T14	3		T40	1		T168	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	24	1			T30	1		T168	1		T173	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	31	1			T14	1		T166	1		T161	2
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	32	1			T30	1		T21	1		T206	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	23	1			T8	1		T14	1		T40	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	26	1			T96	1		T39	1		T166	2
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T26	1		T96	1		T110	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	300	1			T8	1		T13	1		T26	7
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	333	1			T8	3		T26	3		T14	3
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	47	1			T26	2		T185	1		T40	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	35	1			T8	2		T14	2		T185	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	31	1			T26	1		T39	1		T166	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	20	1			T8	1		T14	1		T40	2
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T30	1		T39	1		T206	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	31	1			T8	1		T14	1		T184	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	14	1			T163	1		T168	1		T206	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	24	1			T8	1		T14	2		T40	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	297	1			T8	2		T13	1		T26	3
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	391	1			T8	2		T13	3		T26	6
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	34	1			T26	1		T14	1		T96	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	34	1			T14	1		T96	1		T17	2
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	19	1			T8	1		T166	1		T173	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	20	1			T14	1		T168	1		T161	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	25	1			T110	1		T166	1		T161	2
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	26	1			T14	2		T39	1		T159	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T8	1		T39	2		T184	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T168	1		T166	1		T164	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	275	1			T3	1		T8	1		T13	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	356	1			T3	1		T13	1		T26	4
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	35	1			T14	2		T144	1		T39	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	35	1			T144	1		T39	1		T189	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	17	1			T8	1		T184	1		T168	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	20	1			T193	1		T21	1		T173	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	31	1			T14	1		T40	1		T39	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	27	1			T13	1		T30	1		T40	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	22	1			T8	1		T26	2		T184	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	23	1			T8	1		T164	2		T202	2
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	338	1			T26	4		T14	2		T79	2
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	343	1			T8	4		T13	1		T26	3