Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3741	1			T1	14		T8	31		T13	20
values[1]	4992	1			T8	64		T13	20		T26	104
values[2]	4329	1			T8	20		T26	44		T79	22
values[3]	4198	1			T8	24		T26	40		T28	4
values[4]	3320	1			T8	20		T12	4		T13	20
values[5]	4260	1			T13	40		T26	65		T38	18
values[6]	4229	1			T3	8		T26	45		T72	14
values[7]	4312	1			T2	12		T8	62		T14	23

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4264	1			T8	20		T13	40		T26	45
values[1]	3410	1			T13	20		T26	84		T14	23
values[2]	4211	1			T13	20		T26	129		T38	18
values[3]	3635	1			T8	20		T12	4		T26	25
values[4]	3984	1			T1	14		T8	67		T13	20
values[5]	5233	1			T3	8		T8	42		T30	117
values[6]	4519	1			T8	21		T14	27		T40	60
values[7]	4125	1			T2	12		T8	51		T25	8

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32519

1

T1

14

T2

12

T3

8

auto[1]

862

1

T8

3

T13

5

T26

4

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	313	1			T40	40		T183	20		T241	24
auto[0]	values[0]	values[1]	179	1			T163	20		T227	6		T169	20
auto[0]	values[0]	values[2]	268	1			T163	20		T184	33		T110	111
auto[0]	values[0]	values[3]	422	1			T223	18		T41	33		T206	20
auto[0]	values[0]	values[4]	574	1			T1	14		T13	20		T50	18
auto[0]	values[0]	values[5]	473	1			T30	19		T39	83		T163	45
auto[0]	values[0]	values[6]	624	1			T39	55		T110	81		T206	20
auto[0]	values[0]	values[7]	783	1			T8	29		T208	20		T197	129
auto[0]	values[1]	values[0]	671	1			T13	15		T168	40		T161	133
auto[0]	values[1]	values[1]	426	1			T163	73		T197	20		T224	24
auto[0]	values[1]	values[2]	641	1			T26	83		T30	69		T40	19
auto[0]	values[1]	values[3]	589	1			T14	18		T21	39		T222	22
auto[0]	values[1]	values[4]	555	1			T8	43		T238	4		T242	6
auto[0]	values[1]	values[5]	621	1			T30	96		T41	27		T184	20
auto[0]	values[1]	values[6]	737	1			T8	21		T14	26		T39	20
auto[0]	values[1]	values[7]	630	1			T26	20		T29	12		T14	52
auto[0]	values[2]	values[0]	546	1			T41	19		T184	20		T206	38
auto[0]	values[2]	values[1]	404	1			T26	24		T243	4		T147	20
auto[0]	values[2]	values[2]	440	1			T41	19		T163	20		T184	20
auto[0]	values[2]	values[3]	434	1			T161	19		T192	26		T160	46
auto[0]	values[2]	values[4]	557	1			T79	22		T39	167		T179	32
auto[0]	values[2]	values[5]	705	1			T8	20		T213	10		T206	20
auto[0]	values[2]	values[6]	668	1			T21	52		T184	20		T244	4
auto[0]	values[2]	values[7]	455	1			T26	19		T193	32		T20	47
auto[0]	values[3]	values[0]	560	1			T193	20		T36	8		T234	2
auto[0]	values[3]	values[1]	437	1			T26	39		T21	18		T184	20
auto[0]	values[3]	values[2]	655	1			T39	20		T193	39		T163	20
auto[0]	values[3]	values[3]	299	1			T168	20		T190	20		T245	2
auto[0]	values[3]	values[4]	569	1			T8	23		T28	4		T14	21
auto[0]	values[3]	values[5]	680	1			T14	20		T40	20		T168	20
auto[0]	values[3]	values[6]	443	1			T168	17		T183	39		T178	18
auto[0]	values[3]	values[7]	453	1			T197	62		T178	54		T246	40
auto[0]	values[4]	values[0]	336	1			T26	25		T30	19		T110	25
auto[0]	values[4]	values[1]	313	1			T13	20		T247	14		T179	20
auto[0]	values[4]	values[2]	300	1			T40	20		T39	20		T235	4
auto[0]	values[4]	values[3]	434	1			T8	20		T12	4		T40	20
auto[0]	values[4]	values[4]	459	1			T21	20		T161	20		T183	19
auto[0]	values[4]	values[5]	621	1			T163	20		T168	18		T212	14
auto[0]	values[4]	values[6]	428	1			T248	4		T21	25		T199	16
auto[0]	values[4]	values[7]	342	1			T25	8		T17	20		T21	39
auto[0]	values[5]	values[0]	525	1			T13	20		T26	19		T221	2
auto[0]	values[5]	values[1]	530	1			T26	20		T40	17		T20	22
auto[0]	values[5]	values[2]	753	1			T13	20		T38	18		T39	34
auto[0]	values[5]	values[3]	329	1			T26	25		T14	21		T216	20
auto[0]	values[5]	values[4]	298	1			T110	65		T183	37		T197	24
auto[0]	values[5]	values[5]	807	1			T14	23		T110	22		T168	18
auto[0]	values[5]	values[6]	532	1			T40	39		T175	18		T183	21
auto[0]	values[5]	values[7]	387	1			T39	53		T225	2		T110	20
auto[0]	values[6]	values[0]	521	1			T17	20		T168	39		T249	19
auto[0]	values[6]	values[1]	521	1			T220	2		T184	20		T166	68
auto[0]	values[6]	values[2]	688	1			T26	45		T72	14		T14	26
auto[0]	values[6]	values[3]	343	1			T40	20		T168	19		T206	31
auto[0]	values[6]	values[4]	452	1			T40	20		T184	37		T208	20
auto[0]	values[6]	values[5]	706	1			T3	8		T14	21		T39	110
auto[0]	values[6]	values[6]	475	1			T250	20		T184	50		T215	12
auto[0]	values[6]	values[7]	408	1			T39	20		T182	20		T187	29
auto[0]	values[7]	values[0]	672	1			T8	20		T39	74		T163	79
auto[0]	values[7]	values[1]	511	1			T14	21		T53	10		T41	24
auto[0]	values[7]	values[2]	365	1			T178	25		T251	20		T182	35
auto[0]	values[7]	values[3]	643	1			T185	14		T40	18		T39	20
auto[0]	values[7]	values[4]	412	1			T21	29		T165	14		T176	2
auto[0]	values[7]	values[5]	513	1			T8	22		T144	4		T21	20
auto[0]	values[7]	values[6]	519	1			T40	20		T167	18		T21	86
auto[0]	values[7]	values[7]	565	1			T2	12		T8	20		T163	92
auto[1]	values[0]	values[0]	10	1			T139	3		T252	2		T33	1
auto[1]	values[0]	values[1]	6	1			T239	4		T218	1		T112	1
auto[1]	values[0]	values[2]	7	1			T184	3		T190	1		T204	3
auto[1]	values[0]	values[3]	14	1			T41	1		T183	1		T182	2
auto[1]	values[0]	values[4]	25	1			T21	2		T166	2		T113	4
auto[1]	values[0]	values[5]	6	1			T30	1		T39	2		T163	1
auto[1]	values[0]	values[6]	21	1			T39	2		T110	2		T206	2
auto[1]	values[0]	values[7]	16	1			T8	2		T197	2		T179	1
auto[1]	values[1]	values[0]	15	1			T13	5		T161	3		T216	2
auto[1]	values[1]	values[1]	15	1			T163	2		T112	3		T253	2
auto[1]	values[1]	values[2]	19	1			T26	1		T30	2		T40	1
auto[1]	values[1]	values[3]	12	1			T14	2		T21	1		T195	2
auto[1]	values[1]	values[4]	11	1			T238	2		T166	2		T224	1
auto[1]	values[1]	values[5]	16	1			T30	1		T236	2		T164	1
auto[1]	values[1]	values[6]	15	1			T14	1		T164	1		T174	2
auto[1]	values[1]	values[7]	19	1			T29	2		T14	2		T110	2
auto[1]	values[2]	values[0]	13	1			T41	1		T206	4		T147	1
auto[1]	values[2]	values[1]	10	1			T202	3		T254	2		T255	1
auto[1]	values[2]	values[2]	16	1			T41	1		T161	1		T182	2
auto[1]	values[2]	values[3]	27	1			T161	1		T160	5		T174	5
auto[1]	values[2]	values[4]	19	1			T39	3		T179	4		T139	2
auto[1]	values[2]	values[5]	15	1			T112	2		T202	2		T32	2
auto[1]	values[2]	values[6]	10	1			T21	4		T183	1		T216	1
auto[1]	values[2]	values[7]	10	1			T26	1		T193	2		T139	2
auto[1]	values[3]	values[0]	18	1			T166	1		T173	3		T179	5
auto[1]	values[3]	values[1]	13	1			T26	1		T21	2		T183	2
auto[1]	values[3]	values[2]	12	1			T169	1		T187	1		T256	3
auto[1]	values[3]	values[3]	9	1			T139	2		T257	1		T258	1
auto[1]	values[3]	values[4]	8	1			T8	1		T166	2		T161	1
auto[1]	values[3]	values[5]	20	1			T14	1		T169	1		T159	2
auto[1]	values[3]	values[6]	9	1			T168	3		T178	2		T259	1
auto[1]	values[3]	values[7]	13	1			T197	1		T178	1		T202	1
auto[1]	values[4]	values[0]	19	1			T30	1		T110	1		T169	2
auto[1]	values[4]	values[1]	9	1			T260	2		T112	1		T187	1
auto[1]	values[4]	values[2]	12	1			T169	1		T195	4		T33	2
auto[1]	values[4]	values[3]	21	1			T159	1		T164	1		T216	3
auto[1]	values[4]	values[4]	7	1			T183	1		T246	2		T195	2
auto[1]	values[4]	values[5]	10	1			T168	2		T197	1		T76	1
auto[1]	values[4]	values[6]	3	1			T178	1		T261	1		T32	1
auto[1]	values[4]	values[7]	6	1			T21	2		T204	1		T259	1
auto[1]	values[5]	values[0]	21	1			T26	1		T159	1		T112	3
auto[1]	values[5]	values[1]	13	1			T40	3		T76	2		T32	1
auto[1]	values[5]	values[2]	13	1			T39	1		T169	1		T76	1
auto[1]	values[5]	values[3]	11	1			T14	2		T231	4		T255	2
auto[1]	values[5]	values[4]	8	1			T187	5		T262	1		T33	1
auto[1]	values[5]	values[5]	16	1			T168	2		T197	1		T76	2
auto[1]	values[5]	values[6]	12	1			T40	1		T179	2		T182	1
auto[1]	values[5]	values[7]	5	1			T39	1		T33	2		T263	2
auto[1]	values[6]	values[0]	7	1			T17	2		T168	1		T249	1
auto[1]	values[6]	values[1]	7	1			T160	3		T232	2		T264	1
auto[1]	values[6]	values[2]	14	1			T41	1		T163	1		T161	1
auto[1]	values[6]	values[3]	23	1			T168	1		T206	4		T76	3
auto[1]	values[6]	values[4]	20	1			T218	3		T112	3		T174	2
auto[1]	values[6]	values[5]	11	1			T14	1		T164	1		T33	1
auto[1]	values[6]	values[6]	12	1			T184	1		T197	1		T164	1
auto[1]	values[6]	values[7]	21	1			T187	3		T190	3		T202	2
auto[1]	values[7]	values[0]	17	1			T39	2		T163	3		T173	3
auto[1]	values[7]	values[1]	16	1			T14	2		T190	1		T261	2
auto[1]	values[7]	values[2]	8	1			T182	1		T187	2		T253	1
auto[1]	values[7]	values[3]	25	1			T40	2		T110	5		T161	1
auto[1]	values[7]	values[4]	10	1			T21	2		T197	3		T187	1
auto[1]	values[7]	values[5]	13	1			T197	1		T190	1		T246	1
auto[1]	values[7]	values[6]	11	1			T178	1		T139	2		T265	3
auto[1]	values[7]	values[7]	12	1			T163	3		T160	1		T246	2