Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	836	1			T15	7		T16	24		T18	10
all_values[1]	836	1			T15	7		T16	24		T18	10
all_values[2]	836	1			T15	7		T16	24		T18	10
all_values[3]	836	1			T15	7		T16	24		T18	10
all_values[4]	836	1			T15	7		T16	24		T18	10
all_values[5]	836	1			T15	7		T16	24		T18	10
all_values[6]	836	1			T15	7		T16	24		T18	10
all_values[7]	836	1			T15	7		T16	24		T18	10

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3571

1

T15

32

T16

98

T18

46

auto[1]

3117

1

T15

24

T16

94

T18

34

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2645

1

T15

21

T16

72

T18

28

auto[1]

4043

1

T15

35

T16

120

T18

52

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3823

1

T15

37

T16

115

T18

41

auto[1]

2865

1

T15

19

T16

77

T18

39

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	163	1			T15	1		T16	2		T18	2
all_values[0]	auto[0]	auto[0]	auto[1]	75	1			T16	2		T19	1		T21	1
all_values[0]	auto[0]	auto[1]	auto[0]	152	1			T15	4		T16	8		T18	2
all_values[0]	auto[0]	auto[1]	auto[1]	81	1			T16	2		T18	1		T21	1
all_values[0]	auto[1]	auto[0]	auto[1]	199	1			T16	6		T18	3		T19	2
all_values[0]	auto[1]	auto[1]	auto[1]	166	1			T15	2		T16	4		T18	2
all_values[1]	auto[0]	auto[0]	auto[0]	167	1			T16	11		T18	4		T19	2
all_values[1]	auto[0]	auto[0]	auto[1]	72	1			T16	2		T18	1		T145	2
all_values[1]	auto[0]	auto[1]	auto[0]	136	1			T16	2		T18	2		T21	2
all_values[1]	auto[0]	auto[1]	auto[1]	90	1			T15	5		T16	1		T19	1
all_values[1]	auto[1]	auto[0]	auto[1]	213	1			T15	2		T16	4		T18	1
all_values[1]	auto[1]	auto[1]	auto[1]	158	1			T16	4		T18	2		T31	3
all_values[2]	auto[0]	auto[0]	auto[0]	168	1			T15	3		T16	5		T18	2
all_values[2]	auto[0]	auto[0]	auto[1]	98	1			T15	1		T16	2		T18	1
all_values[2]	auto[0]	auto[1]	auto[0]	130	1			T15	2		T16	5		T18	1
all_values[2]	auto[0]	auto[1]	auto[1]	85	1			T16	2		T18	1		T21	1
all_values[2]	auto[1]	auto[0]	auto[1]	194	1			T15	1		T16	8		T19	1
all_values[2]	auto[1]	auto[1]	auto[1]	161	1			T16	2		T18	5		T19	1
all_values[3]	auto[0]	auto[0]	auto[0]	152	1			T15	1		T16	3		T18	4
all_values[3]	auto[0]	auto[0]	auto[1]	81	1			T15	2		T16	5		T18	1
all_values[3]	auto[0]	auto[1]	auto[0]	151	1			T16	3		T19	1		T31	1
all_values[3]	auto[0]	auto[1]	auto[1]	96	1			T15	1		T16	3		T18	1
all_values[3]	auto[1]	auto[0]	auto[1]	184	1			T15	2		T16	3		T18	4
all_values[3]	auto[1]	auto[1]	auto[1]	172	1			T15	1		T16	7		T21	1
all_values[4]	auto[0]	auto[0]	auto[0]	175	1			T16	3		T19	1		T21	2
all_values[4]	auto[0]	auto[0]	auto[1]	95	1			T15	1		T16	1		T18	1
all_values[4]	auto[0]	auto[1]	auto[0]	105	1			T15	2		T16	3		T31	1
all_values[4]	auto[0]	auto[1]	auto[1]	92	1			T16	8		T18	3		T145	1
all_values[4]	auto[1]	auto[0]	auto[1]	215	1			T15	4		T16	4		T18	4
all_values[4]	auto[1]	auto[1]	auto[1]	154	1			T16	5		T18	2		T21	1
all_values[5]	auto[0]	auto[0]	auto[0]	273	1			T15	3		T16	6		T18	3
all_values[5]	auto[0]	auto[1]	auto[0]	204	1			T15	3		T16	8		T19	2
all_values[5]	auto[1]	auto[0]	auto[1]	189	1			T16	4		T18	2		T19	1
all_values[5]	auto[1]	auto[1]	auto[1]	170	1			T15	1		T16	6		T18	5
all_values[6]	auto[0]	auto[0]	auto[0]	166	1			T16	1		T18	2		T19	3
all_values[6]	auto[0]	auto[0]	auto[1]	78	1			T15	4		T16	4		T18	1
all_values[6]	auto[0]	auto[1]	auto[0]	150	1			T16	4		T18	2		T19	1
all_values[6]	auto[0]	auto[1]	auto[1]	84	1			T16	5		T18	1		T145	1
all_values[6]	auto[1]	auto[0]	auto[1]	176	1			T15	2		T16	5		T18	3
all_values[6]	auto[1]	auto[1]	auto[1]	182	1			T15	1		T16	5		T18	1
all_values[7]	auto[0]	auto[0]	auto[0]	197	1			T15	1		T16	6		T18	3
all_values[7]	auto[0]	auto[0]	auto[1]	69	1			T15	2		T16	3		T18	1
all_values[7]	auto[0]	auto[1]	auto[0]	156	1			T15	1		T16	2		T18	1
all_values[7]	auto[0]	auto[1]	auto[1]	82	1			T16	3		T21	1		T145	1
all_values[7]	auto[1]	auto[0]	auto[1]	172	1			T15	2		T16	8		T18	3
all_values[7]	auto[1]	auto[1]	auto[1]	160	1			T15	1		T16	2		T18	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal