Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1673

1

T5

2

T6

1

T7

5

auto[1]

1722

1

T5

1

T6

7

T7

12

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1951

1

T5

3

T7

9

T8

11

auto[1]

1444

1

T6

8

T7

8

T23

17

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2664

1

T5

3

T6

8

T7

13

auto[1]

731

1

T7

4

T8

3

T26

2

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	661	1			T5	1		T6	1		T7	7
valid[1]	698	1			T5	1		T6	4		T7	5
valid[2]	699	1			T6	2		T7	1		T8	2
valid[3]	648	1			T7	1		T8	3		T23	4
valid[4]	689	1			T5	1		T6	1		T7	3

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	113	1			T5	1		T7	2		T14	1
auto[0]	auto[0]	valid[0]	auto[1]	124	1			T7	1		T23	4		T14	1
auto[0]	auto[0]	valid[1]	auto[0]	130	1			T8	1		T14	1		T15	3
auto[0]	auto[0]	valid[1]	auto[1]	146	1			T23	1		T14	1		T69	1
auto[0]	auto[0]	valid[2]	auto[0]	134	1			T8	1		T26	1		T14	1
auto[0]	auto[0]	valid[2]	auto[1]	146	1			T6	1		T23	2		T14	2
auto[0]	auto[0]	valid[3]	auto[0]	103	1			T8	1		T26	1		T14	2
auto[0]	auto[0]	valid[3]	auto[1]	125	1			T23	4		T15	1		T48	1
auto[0]	auto[0]	valid[4]	auto[0]	130	1			T5	1		T7	1		T8	1
auto[0]	auto[0]	valid[4]	auto[1]	144	1			T23	3		T69	1		T19	1
auto[0]	auto[1]	valid[0]	auto[0]	128	1			T7	1		T15	1		T70	1
auto[0]	auto[1]	valid[0]	auto[1]	141	1			T6	1		T7	1		T68	3
auto[0]	auto[1]	valid[1]	auto[0]	142	1			T5	1		T7	1		T8	1
auto[0]	auto[1]	valid[1]	auto[1]	139	1			T6	4		T7	2		T23	1
auto[0]	auto[1]	valid[2]	auto[0]	116	1			T26	1		T14	2		T16	1
auto[0]	auto[1]	valid[2]	auto[1]	151	1			T6	1		T7	1		T23	1
auto[0]	auto[1]	valid[3]	auto[0]	104	1			T26	2		T14	1		T142	2
auto[0]	auto[1]	valid[3]	auto[1]	173	1			T7	1		T14	1		T68	3
auto[0]	auto[1]	valid[4]	auto[0]	120	1			T8	3		T26	1		T15	1
auto[0]	auto[1]	valid[4]	auto[1]	155	1			T6	1		T7	2		T23	1
auto[1]	auto[0]	valid[0]	auto[0]	78	1			T26	1		T14	1		T16	1
auto[1]	auto[0]	valid[1]	auto[0]	70	1			T7	1		T14	2		T142	1
auto[1]	auto[0]	valid[2]	auto[0]	91	1			T14	1		T15	1		T16	2
auto[1]	auto[0]	valid[3]	auto[0]	68	1			T8	1		T15	1		T16	3
auto[1]	auto[0]	valid[4]	auto[0]	71	1			T14	2		T142	2		T17	1
auto[1]	auto[1]	valid[0]	auto[0]	77	1			T7	2		T14	1		T16	1
auto[1]	auto[1]	valid[1]	auto[0]	71	1			T7	1		T14	1		T17	1
auto[1]	auto[1]	valid[2]	auto[0]	61	1			T8	1		T26	1		T14	1
auto[1]	auto[1]	valid[3]	auto[0]	75	1			T8	1		T16	1		T142	1
auto[1]	auto[1]	valid[4]	auto[0]	69	1			T14	1		T17	1		T18	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal