Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48692

1

T4

14

T5

65

T7

321

auto[1]

14813

1

T6

8

T7

87

T23

208

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

45938

1

T4

6

T5

49

T6

8

auto[1]

17567

1

T4

8

T5

16

T7

126

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	32760	1			T4	6		T5	35		T6	8
others[1]	5388	1			T4	1		T5	6		T7	36
others[2]	5345	1			T4	1		T5	3		T7	32
others[3]	6050	1			T4	2		T5	7		T7	44
interest[1]	3452	1			T4	1		T5	6		T7	20
interest[4]	21491	1			T4	2		T5	22		T6	8
interest[64]	10510	1			T4	3		T5	8		T7	74

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	15901	1			T4	2		T5	24		T7	103
auto[0]	auto[0]	others[1]	2663	1			T4	1		T5	5		T7	19
auto[0]	auto[0]	others[2]	2645	1			T5	3		T7	18		T8	21
auto[0]	auto[0]	others[3]	3048	1			T5	6		T7	16		T8	18
auto[0]	auto[0]	interest[1]	1663	1			T4	1		T5	4		T7	9
auto[0]	auto[0]	interest[4]	10291	1			T4	1		T5	11		T7	54
auto[0]	auto[0]	interest[64]	5205	1			T4	2		T5	7		T7	30
auto[0]	auto[1]	others[0]	7837	1			T6	8		T7	38		T23	108
auto[0]	auto[1]	others[1]	1249	1			T7	10		T23	19		T14	7
auto[0]	auto[1]	others[2]	1236	1			T7	6		T23	19		T14	3
auto[0]	auto[1]	others[3]	1336	1			T7	10		T23	12		T14	4
auto[0]	auto[1]	interest[1]	829	1			T7	4		T23	9		T14	3
auto[0]	auto[1]	interest[4]	5297	1			T6	8		T7	29		T23	69
auto[0]	auto[1]	interest[64]	2326	1			T7	19		T23	41		T14	13
auto[1]	auto[0]	others[0]	9022	1			T4	4		T5	11		T7	61
auto[1]	auto[0]	others[1]	1476	1			T5	1		T7	7		T8	11
auto[1]	auto[0]	others[2]	1464	1			T4	1		T7	8		T8	11
auto[1]	auto[0]	others[3]	1666	1			T4	2		T5	1		T7	18
auto[1]	auto[0]	interest[1]	960	1			T5	2		T7	7		T8	4
auto[1]	auto[0]	interest[4]	5903	1			T4	1		T5	11		T7	37
auto[1]	auto[0]	interest[64]	2979	1			T4	1		T5	1		T7	25

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal