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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.03 98.38 93.99 98.62 89.36 97.19 95.45 99.21


Total test records in report: 1129
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T1034 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.3556612700 Jul 11 06:24:45 PM PDT 24 Jul 11 06:24:58 PM PDT 24 21591168 ps
T102 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.2515687047 Jul 11 06:24:39 PM PDT 24 Jul 11 06:24:50 PM PDT 24 51269377 ps
T1035 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2547982977 Jul 11 06:24:31 PM PDT 24 Jul 11 06:24:42 PM PDT 24 211325880 ps
T1036 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.3832614230 Jul 11 06:24:47 PM PDT 24 Jul 11 06:24:59 PM PDT 24 18627768 ps
T1037 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.621708957 Jul 11 06:24:27 PM PDT 24 Jul 11 06:24:40 PM PDT 24 34608168 ps
T103 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2992972831 Jul 11 06:24:22 PM PDT 24 Jul 11 06:24:30 PM PDT 24 264639516 ps
T1038 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1924794635 Jul 11 06:24:52 PM PDT 24 Jul 11 06:25:05 PM PDT 24 13236882 ps
T1039 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.768368011 Jul 11 06:25:05 PM PDT 24 Jul 11 06:25:14 PM PDT 24 92968348 ps
T1040 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.588471806 Jul 11 06:24:42 PM PDT 24 Jul 11 06:24:55 PM PDT 24 377091420 ps
T1041 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.1193562798 Jul 11 06:24:30 PM PDT 24 Jul 11 06:24:40 PM PDT 24 46809485 ps
T130 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.4124923413 Jul 11 06:24:46 PM PDT 24 Jul 11 06:25:01 PM PDT 24 1314027155 ps
T131 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1981719745 Jul 11 06:24:45 PM PDT 24 Jul 11 06:25:02 PM PDT 24 808554170 ps
T65 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3894315093 Jul 11 06:24:32 PM PDT 24 Jul 11 06:24:41 PM PDT 24 121795086 ps
T66 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3312416677 Jul 11 06:24:28 PM PDT 24 Jul 11 06:24:36 PM PDT 24 59975624 ps
T67 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1223643836 Jul 11 06:24:21 PM PDT 24 Jul 11 06:24:29 PM PDT 24 120408541 ps
T149 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1739806873 Jul 11 06:24:48 PM PDT 24 Jul 11 06:25:16 PM PDT 24 2183139445 ps
T1042 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2607625716 Jul 11 06:24:44 PM PDT 24 Jul 11 06:24:55 PM PDT 24 78985571 ps
T154 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1981306420 Jul 11 06:24:35 PM PDT 24 Jul 11 06:24:58 PM PDT 24 564639948 ps
T132 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.4191721276 Jul 11 06:24:33 PM PDT 24 Jul 11 06:24:57 PM PDT 24 756024125 ps
T1043 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.1246928493 Jul 11 06:24:46 PM PDT 24 Jul 11 06:25:02 PM PDT 24 14705346 ps
T104 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2990853814 Jul 11 06:24:29 PM PDT 24 Jul 11 06:24:39 PM PDT 24 283929465 ps
T133 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.629218382 Jul 11 06:24:43 PM PDT 24 Jul 11 06:24:55 PM PDT 24 567108637 ps
T1044 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.3156067599 Jul 11 06:24:50 PM PDT 24 Jul 11 06:25:04 PM PDT 24 17176598 ps
T105 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1568126677 Jul 11 06:24:21 PM PDT 24 Jul 11 06:24:29 PM PDT 24 136269031 ps
T87 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.4220881957 Jul 11 06:24:37 PM PDT 24 Jul 11 06:24:50 PM PDT 24 447854717 ps
T106 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.894910457 Jul 11 06:24:42 PM PDT 24 Jul 11 06:24:55 PM PDT 24 71811937 ps
T134 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.3335684135 Jul 11 06:24:38 PM PDT 24 Jul 11 06:25:02 PM PDT 24 684849543 ps
T155 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1111825205 Jul 11 06:24:41 PM PDT 24 Jul 11 06:25:03 PM PDT 24 214743502 ps
T1045 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3963041289 Jul 11 06:24:31 PM PDT 24 Jul 11 06:24:40 PM PDT 24 25972159 ps
T1046 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.4244332193 Jul 11 06:24:33 PM PDT 24 Jul 11 06:24:56 PM PDT 24 4057769994 ps
T1047 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.627076742 Jul 11 06:24:45 PM PDT 24 Jul 11 06:24:57 PM PDT 24 43459109 ps
T1048 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1369529746 Jul 11 06:24:30 PM PDT 24 Jul 11 06:24:38 PM PDT 24 10892078 ps
T156 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.4288101912 Jul 11 06:24:29 PM PDT 24 Jul 11 06:24:56 PM PDT 24 1184265575 ps
T135 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.3892309326 Jul 11 06:24:38 PM PDT 24 Jul 11 06:24:52 PM PDT 24 426820283 ps
T107 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1107035865 Jul 11 06:24:30 PM PDT 24 Jul 11 06:24:39 PM PDT 24 72927932 ps
T1049 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3356636859 Jul 11 06:24:44 PM PDT 24 Jul 11 06:24:55 PM PDT 24 10987389 ps
T1050 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2252663002 Jul 11 06:24:37 PM PDT 24 Jul 11 06:24:47 PM PDT 24 25457302 ps
T108 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1438522877 Jul 11 06:24:48 PM PDT 24 Jul 11 06:25:02 PM PDT 24 23024299 ps
T152 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.1701415624 Jul 11 06:24:42 PM PDT 24 Jul 11 06:25:13 PM PDT 24 832624510 ps
T1051 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2248805644 Jul 11 06:24:32 PM PDT 24 Jul 11 06:24:42 PM PDT 24 70076349 ps
T150 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.3238198544 Jul 11 06:24:24 PM PDT 24 Jul 11 06:24:36 PM PDT 24 105764148 ps
T1052 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.2481593659 Jul 11 06:24:46 PM PDT 24 Jul 11 06:24:59 PM PDT 24 57978582 ps
T1053 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.458715918 Jul 11 06:24:21 PM PDT 24 Jul 11 06:24:28 PM PDT 24 23040630 ps
T84 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.844625335 Jul 11 06:24:46 PM PDT 24 Jul 11 06:25:00 PM PDT 24 117876766 ps
T1054 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2734826358 Jul 11 06:24:40 PM PDT 24 Jul 11 06:24:50 PM PDT 24 20599621 ps
T1055 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.1959222006 Jul 11 06:24:34 PM PDT 24 Jul 11 06:24:45 PM PDT 24 83612981 ps
T1056 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2843769577 Jul 11 06:24:32 PM PDT 24 Jul 11 06:24:41 PM PDT 24 49589196 ps
T1057 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.2282324133 Jul 11 06:24:40 PM PDT 24 Jul 11 06:24:49 PM PDT 24 11605682 ps
T1058 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.3418092092 Jul 11 06:24:40 PM PDT 24 Jul 11 06:24:51 PM PDT 24 39766686 ps
T1059 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2638855368 Jul 11 06:24:38 PM PDT 24 Jul 11 06:24:50 PM PDT 24 78834028 ps
T1060 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2540625920 Jul 11 06:25:07 PM PDT 24 Jul 11 06:25:16 PM PDT 24 19576235 ps
T158 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1132378295 Jul 11 06:24:39 PM PDT 24 Jul 11 06:24:55 PM PDT 24 409119581 ps
T151 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.1606434504 Jul 11 06:24:45 PM PDT 24 Jul 11 06:25:19 PM PDT 24 3278576801 ps
T1061 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.4198127189 Jul 11 06:24:37 PM PDT 24 Jul 11 06:24:47 PM PDT 24 587829157 ps
T90 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3170490732 Jul 11 06:24:34 PM PDT 24 Jul 11 06:24:45 PM PDT 24 207199820 ps
T94 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.3980022374 Jul 11 06:24:36 PM PDT 24 Jul 11 06:24:47 PM PDT 24 52691116 ps
T1062 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.3206057395 Jul 11 06:25:05 PM PDT 24 Jul 11 06:25:23 PM PDT 24 164810788 ps
T1063 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.2561811566 Jul 11 06:24:49 PM PDT 24 Jul 11 06:25:03 PM PDT 24 12649356 ps
T1064 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3058882569 Jul 11 06:24:22 PM PDT 24 Jul 11 06:24:34 PM PDT 24 66799185 ps
T1065 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3509969724 Jul 11 06:24:37 PM PDT 24 Jul 11 06:24:48 PM PDT 24 375858341 ps
T1066 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.4024361487 Jul 11 06:24:59 PM PDT 24 Jul 11 06:25:11 PM PDT 24 16021615 ps
T88 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2848042668 Jul 11 06:24:32 PM PDT 24 Jul 11 06:24:44 PM PDT 24 318627142 ps
T1067 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1035388565 Jul 11 06:24:29 PM PDT 24 Jul 11 06:24:38 PM PDT 24 135759954 ps
T109 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.1659078716 Jul 11 06:24:32 PM PDT 24 Jul 11 06:24:56 PM PDT 24 2431575913 ps
T157 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.3003217188 Jul 11 06:24:42 PM PDT 24 Jul 11 06:25:11 PM PDT 24 1165803997 ps
T1068 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.957268666 Jul 11 06:24:52 PM PDT 24 Jul 11 06:25:05 PM PDT 24 89041271 ps
T1069 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.651066296 Jul 11 06:24:33 PM PDT 24 Jul 11 06:24:44 PM PDT 24 179323118 ps
T1070 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3131632869 Jul 11 06:24:37 PM PDT 24 Jul 11 06:24:46 PM PDT 24 20681336 ps
T1071 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.3949911836 Jul 11 06:25:02 PM PDT 24 Jul 11 06:25:12 PM PDT 24 45097393 ps
T1072 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2215101780 Jul 11 06:24:48 PM PDT 24 Jul 11 06:25:03 PM PDT 24 56776927 ps
T1073 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.4078056912 Jul 11 06:24:43 PM PDT 24 Jul 11 06:24:57 PM PDT 24 1160340666 ps
T1074 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2417542580 Jul 11 06:25:01 PM PDT 24 Jul 11 06:25:12 PM PDT 24 78468741 ps
T1075 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3277745111 Jul 11 06:24:42 PM PDT 24 Jul 11 06:24:53 PM PDT 24 23755410 ps
T1076 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3349850342 Jul 11 06:24:33 PM PDT 24 Jul 11 06:24:44 PM PDT 24 131221978 ps
T1077 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3613686378 Jul 11 06:25:01 PM PDT 24 Jul 11 06:25:12 PM PDT 24 28428394 ps
T1078 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.992709138 Jul 11 06:24:43 PM PDT 24 Jul 11 06:24:55 PM PDT 24 277734154 ps
T1079 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.319723953 Jul 11 06:24:41 PM PDT 24 Jul 11 06:24:54 PM PDT 24 616638109 ps
T1080 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3156465851 Jul 11 06:24:46 PM PDT 24 Jul 11 06:25:00 PM PDT 24 72226177 ps
T1081 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.2525727995 Jul 11 06:24:49 PM PDT 24 Jul 11 06:25:03 PM PDT 24 27833540 ps
T1082 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.793880892 Jul 11 06:24:33 PM PDT 24 Jul 11 06:24:46 PM PDT 24 616262224 ps
T1083 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.4215603846 Jul 11 06:24:33 PM PDT 24 Jul 11 06:24:43 PM PDT 24 13729969 ps
T1084 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2931305754 Jul 11 06:24:39 PM PDT 24 Jul 11 06:24:50 PM PDT 24 25907128 ps
T1085 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.533991960 Jul 11 06:24:27 PM PDT 24 Jul 11 06:24:37 PM PDT 24 583875590 ps
T1086 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.4234022060 Jul 11 06:24:53 PM PDT 24 Jul 11 06:25:07 PM PDT 24 94042049 ps
T1087 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.853900892 Jul 11 06:24:54 PM PDT 24 Jul 11 06:25:07 PM PDT 24 20011194 ps
T1088 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.704531316 Jul 11 06:24:46 PM PDT 24 Jul 11 06:25:03 PM PDT 24 120632070 ps
T1089 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.316597921 Jul 11 06:24:33 PM PDT 24 Jul 11 06:24:42 PM PDT 24 19028474 ps
T1090 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3962259934 Jul 11 06:24:33 PM PDT 24 Jul 11 06:24:42 PM PDT 24 44245762 ps
T1091 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1288643176 Jul 11 06:24:45 PM PDT 24 Jul 11 06:25:00 PM PDT 24 45526405 ps
T1092 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2667028733 Jul 11 06:24:41 PM PDT 24 Jul 11 06:24:58 PM PDT 24 557878693 ps
T1093 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.252467126 Jul 11 06:24:41 PM PDT 24 Jul 11 06:25:04 PM PDT 24 1038558265 ps
T1094 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.2667026738 Jul 11 06:24:33 PM PDT 24 Jul 11 06:24:46 PM PDT 24 200291725 ps
T1095 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.3166191286 Jul 11 06:24:29 PM PDT 24 Jul 11 06:24:39 PM PDT 24 454964728 ps
T1096 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.658261956 Jul 11 06:24:34 PM PDT 24 Jul 11 06:24:44 PM PDT 24 38157554 ps
T1097 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2362256803 Jul 11 06:24:30 PM PDT 24 Jul 11 06:24:39 PM PDT 24 100702959 ps
T1098 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2798788411 Jul 11 06:24:45 PM PDT 24 Jul 11 06:24:58 PM PDT 24 15322040 ps
T1099 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2993415991 Jul 11 06:24:33 PM PDT 24 Jul 11 06:25:05 PM PDT 24 1674971840 ps
T1100 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1795858397 Jul 11 06:24:44 PM PDT 24 Jul 11 06:24:58 PM PDT 24 38956571 ps
T1101 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1985467542 Jul 11 06:24:38 PM PDT 24 Jul 11 06:24:55 PM PDT 24 313560692 ps
T1102 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3847115757 Jul 11 06:24:48 PM PDT 24 Jul 11 06:25:05 PM PDT 24 480955542 ps
T1103 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2332652008 Jul 11 06:24:21 PM PDT 24 Jul 11 06:24:31 PM PDT 24 104301395 ps
T1104 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.233220983 Jul 11 06:24:33 PM PDT 24 Jul 11 06:24:42 PM PDT 24 17644849 ps
T1105 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3608926073 Jul 11 06:24:38 PM PDT 24 Jul 11 06:24:51 PM PDT 24 1161490371 ps
T1106 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.4028018153 Jul 11 06:24:41 PM PDT 24 Jul 11 06:24:52 PM PDT 24 25105769 ps
T1107 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3586363735 Jul 11 06:24:28 PM PDT 24 Jul 11 06:24:37 PM PDT 24 28938542 ps
T1108 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.4268333411 Jul 11 06:24:37 PM PDT 24 Jul 11 06:24:48 PM PDT 24 374063706 ps
T1109 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2632971599 Jul 11 06:24:37 PM PDT 24 Jul 11 06:24:46 PM PDT 24 16359037 ps
T1110 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.811131142 Jul 11 06:24:45 PM PDT 24 Jul 11 06:24:58 PM PDT 24 46507559 ps
T1111 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3412548654 Jul 11 06:24:26 PM PDT 24 Jul 11 06:24:34 PM PDT 24 133286378 ps
T1112 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.1166335541 Jul 11 06:24:52 PM PDT 24 Jul 11 06:25:06 PM PDT 24 12028808 ps
T153 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3569689131 Jul 11 06:24:26 PM PDT 24 Jul 11 06:24:53 PM PDT 24 2198013261 ps
T1113 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1703462921 Jul 11 06:24:54 PM PDT 24 Jul 11 06:25:07 PM PDT 24 51324372 ps
T1114 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3899505088 Jul 11 06:24:43 PM PDT 24 Jul 11 06:24:55 PM PDT 24 248903489 ps
T1115 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3788952091 Jul 11 06:24:45 PM PDT 24 Jul 11 06:25:01 PM PDT 24 45460802 ps
T1116 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.1988412345 Jul 11 06:24:38 PM PDT 24 Jul 11 06:24:51 PM PDT 24 140730733 ps
T1117 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.3192062763 Jul 11 06:24:43 PM PDT 24 Jul 11 06:24:57 PM PDT 24 115266453 ps
T1118 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.2302897640 Jul 11 06:24:28 PM PDT 24 Jul 11 06:24:37 PM PDT 24 83664984 ps
T1119 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3397649492 Jul 11 06:24:47 PM PDT 24 Jul 11 06:25:04 PM PDT 24 215712906 ps
T1120 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.682556745 Jul 11 06:24:22 PM PDT 24 Jul 11 06:24:29 PM PDT 24 10857642 ps
T1121 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1670711172 Jul 11 06:24:36 PM PDT 24 Jul 11 06:25:03 PM PDT 24 311791425 ps
T1122 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1476261552 Jul 11 06:24:46 PM PDT 24 Jul 11 06:25:00 PM PDT 24 273661810 ps
T1123 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.2081726047 Jul 11 06:24:44 PM PDT 24 Jul 11 06:24:55 PM PDT 24 37480886 ps
T1124 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3626715564 Jul 11 06:24:28 PM PDT 24 Jul 11 06:24:35 PM PDT 24 27508702 ps
T1125 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.428603077 Jul 11 06:24:25 PM PDT 24 Jul 11 06:25:09 PM PDT 24 1906038497 ps
T148 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3810528196 Jul 11 06:24:52 PM PDT 24 Jul 11 06:25:11 PM PDT 24 385010592 ps
T1126 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2991276768 Jul 11 06:24:31 PM PDT 24 Jul 11 06:24:43 PM PDT 24 136068492 ps
T1127 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1918642111 Jul 11 06:24:32 PM PDT 24 Jul 11 06:24:41 PM PDT 24 26684492 ps
T1128 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.3375012158 Jul 11 06:24:25 PM PDT 24 Jul 11 06:24:44 PM PDT 24 1039941113 ps
T1129 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.85885313 Jul 11 06:24:42 PM PDT 24 Jul 11 06:24:55 PM PDT 24 235407291 ps

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.470982684
Short name T8
Test name
Test status
Simulation time 58590929451 ps
CPU time 561.69 seconds
Started Jul 11 06:35:48 PM PDT 24
Finished Jul 11 06:45:12 PM PDT 24
Peak memory 257076 kb
Host smart-f9126583-59f1-4657-a738-59b8d3402fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470982684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle.
470982684
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.3600275697
Short name T15
Test name
Test status
Simulation time 13866736434 ps
CPU time 183.59 seconds
Started Jul 11 06:34:48 PM PDT 24
Finished Jul 11 06:37:52 PM PDT 24
Peak memory 265860 kb
Host smart-41ff06ae-aef8-4bb1-99c0-631ac759999b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600275697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.3600275697
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.2612821321
Short name T26
Test name
Test status
Simulation time 40677666934 ps
CPU time 148.58 seconds
Started Jul 11 06:40:28 PM PDT 24
Finished Jul 11 06:42:58 PM PDT 24
Peak memory 254212 kb
Host smart-9711962f-0763-4210-96ab-20d47db34005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612821321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.2612821321
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3348203845
Short name T80
Test name
Test status
Simulation time 6500249106 ps
CPU time 14.68 seconds
Started Jul 11 06:24:28 PM PDT 24
Finished Jul 11 06:24:49 PM PDT 24
Peak memory 215852 kb
Host smart-dedef1a8-64c3-4ce6-a257-8e14201bc91a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348203845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.3348203845
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.327572264
Short name T20
Test name
Test status
Simulation time 17678953348 ps
CPU time 103.17 seconds
Started Jul 11 06:36:15 PM PDT 24
Finished Jul 11 06:37:59 PM PDT 24
Peak memory 254152 kb
Host smart-23c06963-8502-4f82-ac54-d95f46bbd86d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327572264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stres
s_all.327572264
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.3770399253
Short name T17
Test name
Test status
Simulation time 123967215683 ps
CPU time 299.97 seconds
Started Jul 11 06:35:25 PM PDT 24
Finished Jul 11 06:40:26 PM PDT 24
Peak memory 273824 kb
Host smart-50344659-cf4e-4888-b46a-ac95dfe5ea41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770399253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.3770399253
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.1970143485
Short name T60
Test name
Test status
Simulation time 28970178 ps
CPU time 0.77 seconds
Started Jul 11 06:34:24 PM PDT 24
Finished Jul 11 06:34:26 PM PDT 24
Peak memory 216100 kb
Host smart-bd026265-88c5-441b-9383-fe406e6c7631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970143485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.1970143485
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.3182794224
Short name T21
Test name
Test status
Simulation time 117411552257 ps
CPU time 342.07 seconds
Started Jul 11 06:41:05 PM PDT 24
Finished Jul 11 06:46:49 PM PDT 24
Peak memory 262692 kb
Host smart-7867263f-ccb6-4a26-95de-c538a06fd30d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182794224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.3182794224
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.3655981741
Short name T139
Test name
Test status
Simulation time 345474519372 ps
CPU time 915.28 seconds
Started Jul 11 06:40:46 PM PDT 24
Finished Jul 11 06:56:02 PM PDT 24
Peak memory 290056 kb
Host smart-2dfc2246-d3c0-4af9-8cea-08e483f65eca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655981741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.3655981741
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.3649893669
Short name T161
Test name
Test status
Simulation time 9607670949 ps
CPU time 73.46 seconds
Started Jul 11 06:35:00 PM PDT 24
Finished Jul 11 06:36:15 PM PDT 24
Peak memory 257332 kb
Host smart-14879ace-33fc-4430-9cb2-0b08d77964a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649893669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.3649893669
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.3638802901
Short name T82
Test name
Test status
Simulation time 826541813 ps
CPU time 5.22 seconds
Started Jul 11 06:24:32 PM PDT 24
Finished Jul 11 06:24:45 PM PDT 24
Peak memory 216040 kb
Host smart-31b506ef-f6d2-4168-97fb-61566b5fc7de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638802901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.3
638802901
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.3144070699
Short name T112
Test name
Test status
Simulation time 154516809191 ps
CPU time 324.77 seconds
Started Jul 11 06:34:46 PM PDT 24
Finished Jul 11 06:40:12 PM PDT 24
Peak memory 265500 kb
Host smart-f6162702-8939-4c7e-9853-3097c078293c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144070699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.3144070699
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.3762056216
Short name T11
Test name
Test status
Simulation time 133523011 ps
CPU time 1.16 seconds
Started Jul 11 06:34:57 PM PDT 24
Finished Jul 11 06:34:59 PM PDT 24
Peak memory 236412 kb
Host smart-d11abd10-488c-4a6b-a559-a302db1978f3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762056216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.3762056216
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.691506453
Short name T10
Test name
Test status
Simulation time 161144172 ps
CPU time 6.37 seconds
Started Jul 11 06:40:01 PM PDT 24
Finished Jul 11 06:40:08 PM PDT 24
Peak memory 224512 kb
Host smart-05613837-a78d-45a3-8ce5-cb4efd43453e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691506453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.691506453
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.3802274853
Short name T178
Test name
Test status
Simulation time 42314185103 ps
CPU time 110.11 seconds
Started Jul 11 06:41:35 PM PDT 24
Finished Jul 11 06:43:26 PM PDT 24
Peak memory 249296 kb
Host smart-b6cbec41-70f3-4bfe-8011-f45dd34eeafa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802274853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.3802274853
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.1747556433
Short name T166
Test name
Test status
Simulation time 54585211136 ps
CPU time 406.01 seconds
Started Jul 11 06:36:29 PM PDT 24
Finished Jul 11 06:43:17 PM PDT 24
Peak memory 257412 kb
Host smart-19aedd75-b402-4f3b-bccb-fa78f28a434f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747556433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.1747556433
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.609226899
Short name T190
Test name
Test status
Simulation time 369032358161 ps
CPU time 810.76 seconds
Started Jul 11 06:41:07 PM PDT 24
Finished Jul 11 06:54:40 PM PDT 24
Peak memory 289844 kb
Host smart-ed14effb-a558-4a9c-83cc-1b99e9b8ff5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609226899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stres
s_all.609226899
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3294712326
Short name T98
Test name
Test status
Simulation time 645669314 ps
CPU time 15.96 seconds
Started Jul 11 06:24:22 PM PDT 24
Finished Jul 11 06:24:44 PM PDT 24
Peak memory 215728 kb
Host smart-a6b965a6-8032-4d1a-9f6d-14a1df46a83e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294712326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.3294712326
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.1046013354
Short name T168
Test name
Test status
Simulation time 69709731292 ps
CPU time 534.64 seconds
Started Jul 11 06:35:37 PM PDT 24
Finished Jul 11 06:44:33 PM PDT 24
Peak memory 265608 kb
Host smart-b096e637-c0d7-4949-9727-89fa90f5d9fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046013354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds
.1046013354
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.3672335576
Short name T147
Test name
Test status
Simulation time 42243236554 ps
CPU time 356.26 seconds
Started Jul 11 06:35:56 PM PDT 24
Finished Jul 11 06:41:53 PM PDT 24
Peak memory 255396 kb
Host smart-b39a6786-9dad-48e6-aaa3-651892f2d5b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672335576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.3672335576
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.2481547805
Short name T14
Test name
Test status
Simulation time 320968538058 ps
CPU time 255 seconds
Started Jul 11 06:41:39 PM PDT 24
Finished Jul 11 06:45:55 PM PDT 24
Peak memory 272792 kb
Host smart-91bd1177-cd35-456b-949f-0fb01ed5f13f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481547805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.2481547805
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.996940826
Short name T33
Test name
Test status
Simulation time 479692307023 ps
CPU time 1254.71 seconds
Started Jul 11 06:38:09 PM PDT 24
Finished Jul 11 06:59:05 PM PDT 24
Peak memory 282084 kb
Host smart-4d9a8c04-0ee4-409b-9a7d-822af76e3aba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996940826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stres
s_all.996940826
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.593545815
Short name T367
Test name
Test status
Simulation time 10994171 ps
CPU time 0.8 seconds
Started Jul 11 06:36:02 PM PDT 24
Finished Jul 11 06:36:04 PM PDT 24
Peak memory 205788 kb
Host smart-83ded1e6-ad19-4296-961a-40b9da174c8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593545815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.593545815
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.2288398718
Short name T171
Test name
Test status
Simulation time 4913287495 ps
CPU time 76.66 seconds
Started Jul 11 06:36:01 PM PDT 24
Finished Jul 11 06:37:18 PM PDT 24
Peak memory 256260 kb
Host smart-d921421b-f1c6-4151-9cda-e024c7c31669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288398718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.2288398718
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.4143585958
Short name T253
Test name
Test status
Simulation time 8454705907 ps
CPU time 114.35 seconds
Started Jul 11 06:37:28 PM PDT 24
Finished Jul 11 06:39:24 PM PDT 24
Peak memory 257044 kb
Host smart-df57a89a-461e-430f-8391-b1ab90f39857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143585958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmd
s.4143585958
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.2639051986
Short name T164
Test name
Test status
Simulation time 10272029165 ps
CPU time 104.73 seconds
Started Jul 11 06:39:54 PM PDT 24
Finished Jul 11 06:41:40 PM PDT 24
Peak memory 265936 kb
Host smart-bf6e8596-0327-4b61-b0bd-69d0869a2fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639051986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.2639051986
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.1256959010
Short name T76
Test name
Test status
Simulation time 4014854664 ps
CPU time 104.3 seconds
Started Jul 11 06:38:12 PM PDT 24
Finished Jul 11 06:39:57 PM PDT 24
Peak memory 254524 kb
Host smart-0f9ed303-ab5f-45db-88da-5ad679bbff18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256959010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmd
s.1256959010
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2848042668
Short name T88
Test name
Test status
Simulation time 318627142 ps
CPU time 4.24 seconds
Started Jul 11 06:24:32 PM PDT 24
Finished Jul 11 06:24:44 PM PDT 24
Peak memory 217052 kb
Host smart-59d9b9bb-c683-4ac0-b666-0100356d6dc9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848042668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.2
848042668
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3569689131
Short name T153
Test name
Test status
Simulation time 2198013261 ps
CPU time 21.57 seconds
Started Jul 11 06:24:26 PM PDT 24
Finished Jul 11 06:24:53 PM PDT 24
Peak memory 215828 kb
Host smart-824dd75f-aec3-4be3-aa9a-33cce2d569f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569689131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.3569689131
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.2135168037
Short name T81
Test name
Test status
Simulation time 377634764 ps
CPU time 8.66 seconds
Started Jul 11 06:24:45 PM PDT 24
Finished Jul 11 06:25:06 PM PDT 24
Peak memory 215932 kb
Host smart-51ff35a0-f1cf-46c6-ab46-dfa22da66dd6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135168037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.2135168037
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.3972806336
Short name T254
Test name
Test status
Simulation time 22383000783 ps
CPU time 166.81 seconds
Started Jul 11 06:34:48 PM PDT 24
Finished Jul 11 06:37:36 PM PDT 24
Peak memory 252856 kb
Host smart-d80c46e5-4ca6-4a13-947b-fe8f60ab5daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972806336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.3972806336
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.425147794
Short name T268
Test name
Test status
Simulation time 16622079205 ps
CPU time 68.71 seconds
Started Jul 11 06:38:12 PM PDT 24
Finished Jul 11 06:39:21 PM PDT 24
Peak memory 240936 kb
Host smart-7beb69ff-a41f-4146-8e7b-5c65bcad4b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425147794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.425147794
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.4032391530
Short name T30
Test name
Test status
Simulation time 1818112584 ps
CPU time 40.09 seconds
Started Jul 11 06:40:05 PM PDT 24
Finished Jul 11 06:40:46 PM PDT 24
Peak memory 249116 kb
Host smart-e4578a18-88fe-42e5-a1f9-b4b356de7bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032391530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.4032391530
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.2943114880
Short name T52
Test name
Test status
Simulation time 47358826986 ps
CPU time 116.21 seconds
Started Jul 11 06:37:00 PM PDT 24
Finished Jul 11 06:38:57 PM PDT 24
Peak memory 269188 kb
Host smart-414f6851-5f5a-40bd-b836-1a612573b79c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943114880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmd
s.2943114880
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.6827090
Short name T224
Test name
Test status
Simulation time 8925475936 ps
CPU time 88.21 seconds
Started Jul 11 06:37:17 PM PDT 24
Finished Jul 11 06:38:46 PM PDT 24
Peak memory 249272 kb
Host smart-8de60d08-cac2-4ce3-ab2a-cd5b4d30bfbb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6827090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stress_
all.6827090
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.2624030771
Short name T216
Test name
Test status
Simulation time 5226396569 ps
CPU time 110.47 seconds
Started Jul 11 06:40:03 PM PDT 24
Finished Jul 11 06:41:54 PM PDT 24
Peak memory 251668 kb
Host smart-b0acbe76-6c0c-4273-aa83-babd4d45a62e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624030771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.2624030771
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_intercept.1778017893
Short name T72
Test name
Test status
Simulation time 111223761 ps
CPU time 3.69 seconds
Started Jul 11 06:38:02 PM PDT 24
Finished Jul 11 06:38:08 PM PDT 24
Peak memory 227436 kb
Host smart-52461b8c-a36e-4832-b2cf-4ab43d5c8ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778017893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.1778017893
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2257970624
Short name T83
Test name
Test status
Simulation time 2294114448 ps
CPU time 14.77 seconds
Started Jul 11 06:24:34 PM PDT 24
Finished Jul 11 06:24:57 PM PDT 24
Peak memory 215812 kb
Host smart-f5c5bd9f-2ffa-4fc4-b580-9d1b20e8267e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257970624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.2257970624
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.1606434504
Short name T151
Test name
Test status
Simulation time 3278576801 ps
CPU time 21.92 seconds
Started Jul 11 06:24:45 PM PDT 24
Finished Jul 11 06:25:19 PM PDT 24
Peak memory 216212 kb
Host smart-a36ec8a7-a127-47db-a2dc-c91ce6152ef8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606434504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.1606434504
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.2698332896
Short name T119
Test name
Test status
Simulation time 201053648 ps
CPU time 7.2 seconds
Started Jul 11 06:34:33 PM PDT 24
Finished Jul 11 06:34:42 PM PDT 24
Peak memory 232552 kb
Host smart-5327af50-1019-468e-aff8-b8cc55985384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698332896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.2698332896
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.2993613731
Short name T428
Test name
Test status
Simulation time 6283228376 ps
CPU time 12.64 seconds
Started Jul 11 06:34:34 PM PDT 24
Finished Jul 11 06:34:48 PM PDT 24
Peak memory 239500 kb
Host smart-9c0c105e-0481-45f0-91cb-f8536edf3f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993613731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.2993613731
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.3193297639
Short name T264
Test name
Test status
Simulation time 8013382998 ps
CPU time 132.13 seconds
Started Jul 11 06:34:44 PM PDT 24
Finished Jul 11 06:36:57 PM PDT 24
Peak memory 257476 kb
Host smart-45308954-97b3-4e2c-8745-3848800ad551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193297639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.3193297639
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.1409583136
Short name T291
Test name
Test status
Simulation time 4652290715 ps
CPU time 19.95 seconds
Started Jul 11 06:40:54 PM PDT 24
Finished Jul 11 06:41:15 PM PDT 24
Peak memory 216416 kb
Host smart-19fa2a27-3443-4f82-98f8-0a2c855f1108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409583136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.1409583136
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.2821386786
Short name T93
Test name
Test status
Simulation time 102100555 ps
CPU time 2.79 seconds
Started Jul 11 06:24:35 PM PDT 24
Finished Jul 11 06:24:47 PM PDT 24
Peak memory 216104 kb
Host smart-8bce01cd-a132-4c81-87a4-1f8e7d37f274
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821386786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
2821386786
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3412548654
Short name T1111
Test name
Test status
Simulation time 133286378 ps
CPU time 1.22 seconds
Started Jul 11 06:24:26 PM PDT 24
Finished Jul 11 06:24:34 PM PDT 24
Peak memory 207544 kb
Host smart-4986c605-003d-4e94-943c-a423493fa0b2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412548654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.3412548654
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.4244332193
Short name T1046
Test name
Test status
Simulation time 4057769994 ps
CPU time 13.23 seconds
Started Jul 11 06:24:33 PM PDT 24
Finished Jul 11 06:24:56 PM PDT 24
Peak memory 215632 kb
Host smart-f0d29b7a-8324-4528-ba2b-29ab9e51cde1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244332193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.4244332193
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.533991960
Short name T1085
Test name
Test status
Simulation time 583875590 ps
CPU time 3.77 seconds
Started Jul 11 06:24:27 PM PDT 24
Finished Jul 11 06:24:37 PM PDT 24
Peak memory 217688 kb
Host smart-7c3ad493-be21-4311-897f-af9319413f62
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533991960 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.533991960
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.1959222006
Short name T1055
Test name
Test status
Simulation time 83612981 ps
CPU time 2.06 seconds
Started Jul 11 06:24:34 PM PDT 24
Finished Jul 11 06:24:45 PM PDT 24
Peak memory 215728 kb
Host smart-b093cc86-8065-47bf-bfef-2fefd363cf33
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959222006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.1
959222006
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.621708957
Short name T1037
Test name
Test status
Simulation time 34608168 ps
CPU time 0.75 seconds
Started Jul 11 06:24:27 PM PDT 24
Finished Jul 11 06:24:40 PM PDT 24
Peak memory 204312 kb
Host smart-b06f0a4b-6054-49a0-9f4e-404e2f465749
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621708957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.621708957
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.496393810
Short name T99
Test name
Test status
Simulation time 31426641 ps
CPU time 1.75 seconds
Started Jul 11 06:24:29 PM PDT 24
Finished Jul 11 06:24:37 PM PDT 24
Peak memory 215776 kb
Host smart-b257c1b3-be04-405f-ab8e-157cec5ee699
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496393810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_
device_mem_partial_access.496393810
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1592311385
Short name T1022
Test name
Test status
Simulation time 151821393 ps
CPU time 0.66 seconds
Started Jul 11 06:24:29 PM PDT 24
Finished Jul 11 06:24:37 PM PDT 24
Peak memory 204420 kb
Host smart-676e454c-12a4-49f5-94c1-d24bf478ce8d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592311385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.1592311385
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.175871335
Short name T128
Test name
Test status
Simulation time 280543961 ps
CPU time 1.89 seconds
Started Jul 11 06:24:27 PM PDT 24
Finished Jul 11 06:24:35 PM PDT 24
Peak memory 207548 kb
Host smart-688747cd-ec47-4938-9f88-aeb16f43cef1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175871335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sp
i_device_same_csr_outstanding.175871335
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1258695521
Short name T92
Test name
Test status
Simulation time 123536767 ps
CPU time 2.22 seconds
Started Jul 11 06:24:32 PM PDT 24
Finished Jul 11 06:24:42 PM PDT 24
Peak memory 216052 kb
Host smart-fdabf269-b5c0-42ea-959b-92dd6f0ae87e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258695521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.1
258695521
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3531939583
Short name T127
Test name
Test status
Simulation time 2239485941 ps
CPU time 9.31 seconds
Started Jul 11 06:24:30 PM PDT 24
Finished Jul 11 06:24:46 PM PDT 24
Peak memory 215672 kb
Host smart-6167e5aa-4beb-49e6-abab-1bd97e60ba9f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531939583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.3531939583
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.428603077
Short name T1125
Test name
Test status
Simulation time 1906038497 ps
CPU time 37.51 seconds
Started Jul 11 06:24:25 PM PDT 24
Finished Jul 11 06:25:09 PM PDT 24
Peak memory 215632 kb
Host smart-cb2b7618-de72-4ca1-9b07-4ea12777b8e0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428603077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_bit_bash.428603077
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1223643836
Short name T67
Test name
Test status
Simulation time 120408541 ps
CPU time 1.42 seconds
Started Jul 11 06:24:21 PM PDT 24
Finished Jul 11 06:24:29 PM PDT 24
Peak memory 207432 kb
Host smart-5eaead11-d68b-4234-aad0-32e90dcb953a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223643836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.1223643836
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3586363735
Short name T1107
Test name
Test status
Simulation time 28938542 ps
CPU time 2.06 seconds
Started Jul 11 06:24:28 PM PDT 24
Finished Jul 11 06:24:37 PM PDT 24
Peak memory 215868 kb
Host smart-439e1751-eb50-47ff-b30b-c0142cee35ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586363735 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.3586363735
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1568126677
Short name T105
Test name
Test status
Simulation time 136269031 ps
CPU time 1.24 seconds
Started Jul 11 06:24:21 PM PDT 24
Finished Jul 11 06:24:29 PM PDT 24
Peak memory 215708 kb
Host smart-1d7d5d07-a9b4-4c60-8339-55f3bb7698c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568126677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.1
568126677
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.682556745
Short name T1120
Test name
Test status
Simulation time 10857642 ps
CPU time 0.72 seconds
Started Jul 11 06:24:22 PM PDT 24
Finished Jul 11 06:24:29 PM PDT 24
Peak memory 204304 kb
Host smart-5335b9d8-54bc-48db-9c6d-ad190a50b301
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682556745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.682556745
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2992972831
Short name T103
Test name
Test status
Simulation time 264639516 ps
CPU time 1.87 seconds
Started Jul 11 06:24:22 PM PDT 24
Finished Jul 11 06:24:30 PM PDT 24
Peak memory 215796 kb
Host smart-e53e493d-4ad6-44e1-8b55-87dfeed00496
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992972831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.2992972831
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3493277270
Short name T1019
Test name
Test status
Simulation time 12099210 ps
CPU time 0.66 seconds
Started Jul 11 06:24:32 PM PDT 24
Finished Jul 11 06:24:41 PM PDT 24
Peak memory 204436 kb
Host smart-532ee098-c004-4835-aed0-d459a60a286e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493277270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.3493277270
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2332652008
Short name T1103
Test name
Test status
Simulation time 104301395 ps
CPU time 3.01 seconds
Started Jul 11 06:24:21 PM PDT 24
Finished Jul 11 06:24:31 PM PDT 24
Peak memory 215720 kb
Host smart-90323b09-3f95-49eb-bb30-f0c19237b19d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332652008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.2332652008
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.4220881957
Short name T87
Test name
Test status
Simulation time 447854717 ps
CPU time 4.37 seconds
Started Jul 11 06:24:37 PM PDT 24
Finished Jul 11 06:24:50 PM PDT 24
Peak memory 216012 kb
Host smart-2c720577-2095-40a3-9353-1295058f5c2a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220881957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.4
220881957
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.3375012158
Short name T1128
Test name
Test status
Simulation time 1039941113 ps
CPU time 12.93 seconds
Started Jul 11 06:24:25 PM PDT 24
Finished Jul 11 06:24:44 PM PDT 24
Peak memory 215784 kb
Host smart-f8cacdab-2a1c-44bb-b8cb-4457725148b1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375012158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.3375012158
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.651066296
Short name T1069
Test name
Test status
Simulation time 179323118 ps
CPU time 2.86 seconds
Started Jul 11 06:24:33 PM PDT 24
Finished Jul 11 06:24:44 PM PDT 24
Peak memory 217584 kb
Host smart-82b2d842-3804-4276-9e6d-4814f771592c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651066296 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.651066296
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3962259934
Short name T1090
Test name
Test status
Simulation time 44245762 ps
CPU time 1.37 seconds
Started Jul 11 06:24:33 PM PDT 24
Finished Jul 11 06:24:42 PM PDT 24
Peak memory 215732 kb
Host smart-8a80ad57-d7bb-4dd6-97c8-a0a302b50610
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962259934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
3962259934
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.3215589592
Short name T1013
Test name
Test status
Simulation time 25128371 ps
CPU time 0.69 seconds
Started Jul 11 06:24:41 PM PDT 24
Finished Jul 11 06:24:53 PM PDT 24
Peak memory 204304 kb
Host smart-9cb26336-1204-41e0-929b-6b609929f458
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215589592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
3215589592
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.319723953
Short name T1079
Test name
Test status
Simulation time 616638109 ps
CPU time 3.82 seconds
Started Jul 11 06:24:41 PM PDT 24
Finished Jul 11 06:24:54 PM PDT 24
Peak memory 215820 kb
Host smart-06ef7a56-6217-4c80-8dce-11f2a7986022
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319723953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.s
pi_device_same_csr_outstanding.319723953
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.3003217188
Short name T157
Test name
Test status
Simulation time 1165803997 ps
CPU time 18.6 seconds
Started Jul 11 06:24:42 PM PDT 24
Finished Jul 11 06:25:11 PM PDT 24
Peak memory 215912 kb
Host smart-d04bddeb-f38e-4ee6-ae8c-3c3c11d36e71
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003217188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.3003217188
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.950672349
Short name T1032
Test name
Test status
Simulation time 117902065 ps
CPU time 1.66 seconds
Started Jul 11 06:24:42 PM PDT 24
Finished Jul 11 06:24:54 PM PDT 24
Peak memory 215760 kb
Host smart-6225a7db-e174-4c56-afc8-bdec44a67c36
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950672349 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.950672349
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.658261956
Short name T1096
Test name
Test status
Simulation time 38157554 ps
CPU time 1.21 seconds
Started Jul 11 06:24:34 PM PDT 24
Finished Jul 11 06:24:44 PM PDT 24
Peak memory 207656 kb
Host smart-5d17056e-a0e6-499b-8652-a9a5b4163b0a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658261956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.658261956
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.3843607454
Short name T1014
Test name
Test status
Simulation time 28117628 ps
CPU time 0.71 seconds
Started Jul 11 06:24:39 PM PDT 24
Finished Jul 11 06:24:49 PM PDT 24
Peak memory 204640 kb
Host smart-e5de5f09-da98-40fc-b8bb-f942d5c2f810
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843607454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
3843607454
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1141526981
Short name T118
Test name
Test status
Simulation time 153598573 ps
CPU time 4.01 seconds
Started Jul 11 06:24:43 PM PDT 24
Finished Jul 11 06:24:59 PM PDT 24
Peak memory 215668 kb
Host smart-40cc0c8a-9db1-449d-a41e-f955608a385c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141526981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.1141526981
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.2667026738
Short name T1094
Test name
Test status
Simulation time 200291725 ps
CPU time 3.64 seconds
Started Jul 11 06:24:33 PM PDT 24
Finished Jul 11 06:24:46 PM PDT 24
Peak memory 216012 kb
Host smart-56055d22-6d39-4fd0-a165-ab43bc2732b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667026738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
2667026738
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3608926073
Short name T1105
Test name
Test status
Simulation time 1161490371 ps
CPU time 3.43 seconds
Started Jul 11 06:24:38 PM PDT 24
Finished Jul 11 06:24:51 PM PDT 24
Peak memory 216888 kb
Host smart-d7ac840d-528a-48c2-bf6b-8451bb7b8a43
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608926073 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.3608926073
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.85885313
Short name T1129
Test name
Test status
Simulation time 235407291 ps
CPU time 2.7 seconds
Started Jul 11 06:24:42 PM PDT 24
Finished Jul 11 06:24:55 PM PDT 24
Peak memory 215580 kb
Host smart-84e7ee66-e8e3-4168-9ece-233541fbee28
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85885313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.85885313
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.2282324133
Short name T1057
Test name
Test status
Simulation time 11605682 ps
CPU time 0.73 seconds
Started Jul 11 06:24:40 PM PDT 24
Finished Jul 11 06:24:49 PM PDT 24
Peak memory 204628 kb
Host smart-459cf294-5aaf-46e1-aff4-6ecefdb5eb87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282324133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
2282324133
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3788952091
Short name T1115
Test name
Test status
Simulation time 45460802 ps
CPU time 2.72 seconds
Started Jul 11 06:24:45 PM PDT 24
Finished Jul 11 06:25:01 PM PDT 24
Peak memory 215724 kb
Host smart-d5367e8c-c03e-4ef6-9af1-06d9629caa22
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788952091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.3788952091
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1455254903
Short name T86
Test name
Test status
Simulation time 234110383 ps
CPU time 3.8 seconds
Started Jul 11 06:24:45 PM PDT 24
Finished Jul 11 06:25:01 PM PDT 24
Peak memory 216248 kb
Host smart-67363aed-3b6b-4c92-b283-ab35bc8be634
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455254903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
1455254903
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3810528196
Short name T148
Test name
Test status
Simulation time 385010592 ps
CPU time 6.15 seconds
Started Jul 11 06:24:52 PM PDT 24
Finished Jul 11 06:25:11 PM PDT 24
Peak memory 216200 kb
Host smart-7568393e-3edb-407b-a3b9-9da28bcc596f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810528196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.3810528196
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.629218382
Short name T133
Test name
Test status
Simulation time 567108637 ps
CPU time 1.89 seconds
Started Jul 11 06:24:43 PM PDT 24
Finished Jul 11 06:24:55 PM PDT 24
Peak memory 216760 kb
Host smart-af12abdd-e852-4abc-b207-372072d4e7e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629218382 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.629218382
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.894910457
Short name T106
Test name
Test status
Simulation time 71811937 ps
CPU time 1.85 seconds
Started Jul 11 06:24:42 PM PDT 24
Finished Jul 11 06:24:55 PM PDT 24
Peak memory 215740 kb
Host smart-64cf7f59-d79f-4fe7-83d1-c0e68b320dc2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894910457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.894910457
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.1246928493
Short name T1043
Test name
Test status
Simulation time 14705346 ps
CPU time 0.73 seconds
Started Jul 11 06:24:46 PM PDT 24
Finished Jul 11 06:25:02 PM PDT 24
Peak memory 204296 kb
Host smart-a8f7e074-c271-4364-906a-2fc7705d12eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246928493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
1246928493
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1288643176
Short name T1091
Test name
Test status
Simulation time 45526405 ps
CPU time 2.85 seconds
Started Jul 11 06:24:45 PM PDT 24
Finished Jul 11 06:25:00 PM PDT 24
Peak memory 215808 kb
Host smart-bab9f387-af64-4650-ba91-ec8b3002d975
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288643176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.1288643176
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3170490732
Short name T90
Test name
Test status
Simulation time 207199820 ps
CPU time 2.76 seconds
Started Jul 11 06:24:34 PM PDT 24
Finished Jul 11 06:24:45 PM PDT 24
Peak memory 215976 kb
Host smart-4ea64dbe-66db-41b1-88cc-5db053b1731a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170490732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
3170490732
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.1701415624
Short name T152
Test name
Test status
Simulation time 832624510 ps
CPU time 20.77 seconds
Started Jul 11 06:24:42 PM PDT 24
Finished Jul 11 06:25:13 PM PDT 24
Peak memory 216004 kb
Host smart-d4491e52-0d9e-4c69-8d7b-5590d7ae93d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701415624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.1701415624
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.704531316
Short name T1088
Test name
Test status
Simulation time 120632070 ps
CPU time 4.04 seconds
Started Jul 11 06:24:46 PM PDT 24
Finished Jul 11 06:25:03 PM PDT 24
Peak memory 217804 kb
Host smart-36d38c4f-9c7a-45dc-9d5c-55848f411be1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704531316 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.704531316
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2215101780
Short name T1072
Test name
Test status
Simulation time 56776927 ps
CPU time 1.41 seconds
Started Jul 11 06:24:48 PM PDT 24
Finished Jul 11 06:25:03 PM PDT 24
Peak memory 207468 kb
Host smart-ed475cc7-4d17-4eac-b370-751bc76e9b33
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215101780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
2215101780
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.4021150812
Short name T1015
Test name
Test status
Simulation time 31562005 ps
CPU time 0.76 seconds
Started Jul 11 06:24:38 PM PDT 24
Finished Jul 11 06:24:48 PM PDT 24
Peak memory 204624 kb
Host smart-ae681b64-79c8-424d-b35f-f3273acd6709
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021150812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
4021150812
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.588471806
Short name T1040
Test name
Test status
Simulation time 377091420 ps
CPU time 2.79 seconds
Started Jul 11 06:24:42 PM PDT 24
Finished Jul 11 06:24:55 PM PDT 24
Peak memory 215656 kb
Host smart-b5b4441b-2957-49b6-b9a9-7b710a2d24b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588471806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.s
pi_device_same_csr_outstanding.588471806
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1795858397
Short name T1100
Test name
Test status
Simulation time 38956571 ps
CPU time 2.44 seconds
Started Jul 11 06:24:44 PM PDT 24
Finished Jul 11 06:24:58 PM PDT 24
Peak memory 216036 kb
Host smart-42f6a743-10cb-41c8-8687-085e7dea3fc8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795858397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
1795858397
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.950695257
Short name T95
Test name
Test status
Simulation time 71650423 ps
CPU time 2.5 seconds
Started Jul 11 06:24:40 PM PDT 24
Finished Jul 11 06:24:53 PM PDT 24
Peak memory 217136 kb
Host smart-467a25d8-d046-495f-b1d5-9811687b51fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950695257 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.950695257
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3899505088
Short name T1114
Test name
Test status
Simulation time 248903489 ps
CPU time 2.52 seconds
Started Jul 11 06:24:43 PM PDT 24
Finished Jul 11 06:24:55 PM PDT 24
Peak memory 215696 kb
Host smart-a0dfa8a6-2565-403d-b034-76075844a47a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899505088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
3899505088
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.1661115158
Short name T1020
Test name
Test status
Simulation time 12070326 ps
CPU time 0.72 seconds
Started Jul 11 06:24:45 PM PDT 24
Finished Jul 11 06:24:59 PM PDT 24
Peak memory 204300 kb
Host smart-37cd8537-7d0b-4c44-b9f0-bff6a477d472
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661115158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
1661115158
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3397649492
Short name T1119
Test name
Test status
Simulation time 215712906 ps
CPU time 4.03 seconds
Started Jul 11 06:24:47 PM PDT 24
Finished Jul 11 06:25:04 PM PDT 24
Peak memory 215732 kb
Host smart-2888df5d-9563-46ee-99a3-db38313a0bd7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397649492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.3397649492
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1476261552
Short name T1122
Test name
Test status
Simulation time 273661810 ps
CPU time 1.79 seconds
Started Jul 11 06:24:46 PM PDT 24
Finished Jul 11 06:25:00 PM PDT 24
Peak memory 216100 kb
Host smart-12f87cc5-0c9e-4cb4-8042-b65bb72197ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476261552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
1476261552
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1111825205
Short name T155
Test name
Test status
Simulation time 214743502 ps
CPU time 12.01 seconds
Started Jul 11 06:24:41 PM PDT 24
Finished Jul 11 06:25:03 PM PDT 24
Peak memory 215596 kb
Host smart-78418c36-fbf9-46af-8e04-6f20a51e580b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111825205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.1111825205
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.811131142
Short name T1110
Test name
Test status
Simulation time 46507559 ps
CPU time 1.81 seconds
Started Jul 11 06:24:45 PM PDT 24
Finished Jul 11 06:24:58 PM PDT 24
Peak memory 216864 kb
Host smart-7f9a1658-8b71-4cd3-a9cd-19e05e101768
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811131142 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.811131142
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.3774364337
Short name T126
Test name
Test status
Simulation time 47776073 ps
CPU time 1.39 seconds
Started Jul 11 06:24:42 PM PDT 24
Finished Jul 11 06:24:54 PM PDT 24
Peak memory 207616 kb
Host smart-477e396c-7cdb-4abc-816e-ae4ac33ced5b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774364337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
3774364337
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.627076742
Short name T1047
Test name
Test status
Simulation time 43459109 ps
CPU time 0.71 seconds
Started Jul 11 06:24:45 PM PDT 24
Finished Jul 11 06:24:57 PM PDT 24
Peak memory 204260 kb
Host smart-78e76fce-c451-44da-8b21-afd2a0322ca7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627076742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.627076742
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1981719745
Short name T131
Test name
Test status
Simulation time 808554170 ps
CPU time 4.21 seconds
Started Jul 11 06:24:45 PM PDT 24
Finished Jul 11 06:25:02 PM PDT 24
Peak memory 215672 kb
Host smart-698ab27c-e360-48d7-a6f2-cdc97b24ae72
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981719745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.1981719745
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.313240297
Short name T58
Test name
Test status
Simulation time 79911329 ps
CPU time 2.15 seconds
Started Jul 11 06:24:40 PM PDT 24
Finished Jul 11 06:24:52 PM PDT 24
Peak memory 215972 kb
Host smart-dc09c168-5679-4201-a736-272cacee61eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313240297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.313240297
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2667028733
Short name T1092
Test name
Test status
Simulation time 557878693 ps
CPU time 6.86 seconds
Started Jul 11 06:24:41 PM PDT 24
Finished Jul 11 06:24:58 PM PDT 24
Peak memory 215704 kb
Host smart-5b03a9a7-180a-4f3a-bbce-d5704c185946
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667028733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.2667028733
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3847115757
Short name T1102
Test name
Test status
Simulation time 480955542 ps
CPU time 3.96 seconds
Started Jul 11 06:24:48 PM PDT 24
Finished Jul 11 06:25:05 PM PDT 24
Peak memory 217864 kb
Host smart-b37bc90b-192d-48af-a13f-bfe65b0c8aed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847115757 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.3847115757
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1438522877
Short name T108
Test name
Test status
Simulation time 23024299 ps
CPU time 1.19 seconds
Started Jul 11 06:24:48 PM PDT 24
Finished Jul 11 06:25:02 PM PDT 24
Peak memory 207524 kb
Host smart-d98f1676-2b38-47e2-88eb-19882603feb2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438522877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
1438522877
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2252663002
Short name T1050
Test name
Test status
Simulation time 25457302 ps
CPU time 0.73 seconds
Started Jul 11 06:24:37 PM PDT 24
Finished Jul 11 06:24:47 PM PDT 24
Peak memory 204632 kb
Host smart-0a8ee109-ddd9-42d7-8a81-4917d9f969ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252663002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
2252663002
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.4078056912
Short name T1073
Test name
Test status
Simulation time 1160340666 ps
CPU time 4.07 seconds
Started Jul 11 06:24:43 PM PDT 24
Finished Jul 11 06:24:57 PM PDT 24
Peak memory 216292 kb
Host smart-2c058f9a-d2b0-4cc1-af2e-11198ad04d1d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078056912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.4078056912
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3156465851
Short name T1080
Test name
Test status
Simulation time 72226177 ps
CPU time 1.8 seconds
Started Jul 11 06:24:46 PM PDT 24
Finished Jul 11 06:25:00 PM PDT 24
Peak memory 216028 kb
Host smart-16980b1f-afea-4576-aeb9-b58b12777d59
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156465851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
3156465851
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2321952611
Short name T59
Test name
Test status
Simulation time 546859404 ps
CPU time 3.36 seconds
Started Jul 11 06:24:50 PM PDT 24
Finished Jul 11 06:25:07 PM PDT 24
Peak memory 217648 kb
Host smart-cfe2ab8a-e0e5-4c4f-b83d-22512b961913
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321952611 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.2321952611
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.4037479162
Short name T100
Test name
Test status
Simulation time 59598215 ps
CPU time 1.84 seconds
Started Jul 11 06:24:45 PM PDT 24
Finished Jul 11 06:24:59 PM PDT 24
Peak memory 215660 kb
Host smart-f8965139-05f8-4878-a398-47ac9d2fd6ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037479162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
4037479162
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.3556612700
Short name T1034
Test name
Test status
Simulation time 21591168 ps
CPU time 0.69 seconds
Started Jul 11 06:24:45 PM PDT 24
Finished Jul 11 06:24:58 PM PDT 24
Peak memory 204640 kb
Host smart-0230762d-1102-4e29-b80f-2f1939675a20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556612700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
3556612700
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.4124923413
Short name T130
Test name
Test status
Simulation time 1314027155 ps
CPU time 1.96 seconds
Started Jul 11 06:24:46 PM PDT 24
Finished Jul 11 06:25:01 PM PDT 24
Peak memory 215760 kb
Host smart-0f2548a2-292f-4003-b225-c5852f19e611
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124923413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.4124923413
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.992709138
Short name T1078
Test name
Test status
Simulation time 277734154 ps
CPU time 2.77 seconds
Started Jul 11 06:24:43 PM PDT 24
Finished Jul 11 06:24:55 PM PDT 24
Peak memory 215896 kb
Host smart-c39a7f63-c1dc-4d3f-a3a6-3a3344db63c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992709138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.992709138
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.252467126
Short name T1093
Test name
Test status
Simulation time 1038558265 ps
CPU time 14.1 seconds
Started Jul 11 06:24:41 PM PDT 24
Finished Jul 11 06:25:04 PM PDT 24
Peak memory 216188 kb
Host smart-f0639a70-3994-4a6f-9ae1-9e21ca4af362
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252467126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device
_tl_intg_err.252467126
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2931305754
Short name T1084
Test name
Test status
Simulation time 25907128 ps
CPU time 1.69 seconds
Started Jul 11 06:24:39 PM PDT 24
Finished Jul 11 06:24:50 PM PDT 24
Peak memory 215816 kb
Host smart-3cae2ef0-095f-45e8-aeec-b4eb0eba9870
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931305754 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.2931305754
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3277745111
Short name T1075
Test name
Test status
Simulation time 23755410 ps
CPU time 1.37 seconds
Started Jul 11 06:24:42 PM PDT 24
Finished Jul 11 06:24:53 PM PDT 24
Peak memory 207524 kb
Host smart-988dcb0b-b7ec-42c9-9c2d-bbc39950d3f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277745111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
3277745111
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2798788411
Short name T1098
Test name
Test status
Simulation time 15322040 ps
CPU time 0.82 seconds
Started Jul 11 06:24:45 PM PDT 24
Finished Jul 11 06:24:58 PM PDT 24
Peak memory 204304 kb
Host smart-d395544f-9633-45cf-8e40-110bb71223b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798788411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
2798788411
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.3192062763
Short name T1117
Test name
Test status
Simulation time 115266453 ps
CPU time 3.05 seconds
Started Jul 11 06:24:43 PM PDT 24
Finished Jul 11 06:24:57 PM PDT 24
Peak memory 215812 kb
Host smart-ac71cf53-41b8-4f32-b174-d654753834f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192062763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.3192062763
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.844625335
Short name T84
Test name
Test status
Simulation time 117876766 ps
CPU time 2.32 seconds
Started Jul 11 06:24:46 PM PDT 24
Finished Jul 11 06:25:00 PM PDT 24
Peak memory 217008 kb
Host smart-c9ae9beb-e048-4f2d-97c9-16a3a6e27987
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844625335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.844625335
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1739806873
Short name T149
Test name
Test status
Simulation time 2183139445 ps
CPU time 14.99 seconds
Started Jul 11 06:24:48 PM PDT 24
Finished Jul 11 06:25:16 PM PDT 24
Peak memory 216176 kb
Host smart-193b89ea-c20e-4581-9ba7-fad1b0fab8c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739806873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.1739806873
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.452928942
Short name T1021
Test name
Test status
Simulation time 418854869 ps
CPU time 7.07 seconds
Started Jul 11 06:24:38 PM PDT 24
Finished Jul 11 06:24:54 PM PDT 24
Peak memory 207540 kb
Host smart-d0a1ee8f-a948-40bd-a241-c1063dfbb037
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452928942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_aliasing.452928942
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2993415991
Short name T1099
Test name
Test status
Simulation time 1674971840 ps
CPU time 23.57 seconds
Started Jul 11 06:24:33 PM PDT 24
Finished Jul 11 06:25:05 PM PDT 24
Peak memory 207524 kb
Host smart-82b6294b-80de-4226-a55a-ee69d66555f7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993415991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.2993415991
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3058882569
Short name T1064
Test name
Test status
Simulation time 66799185 ps
CPU time 1.21 seconds
Started Jul 11 06:24:22 PM PDT 24
Finished Jul 11 06:24:34 PM PDT 24
Peak memory 207500 kb
Host smart-a3fd8eee-7588-4379-ae77-b47061c6cf4a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058882569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.3058882569
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2843769577
Short name T1056
Test name
Test status
Simulation time 49589196 ps
CPU time 1.64 seconds
Started Jul 11 06:24:32 PM PDT 24
Finished Jul 11 06:24:41 PM PDT 24
Peak memory 215836 kb
Host smart-569c8115-2cbe-44bd-811e-aa4656cf9746
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843769577 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.2843769577
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2990853814
Short name T104
Test name
Test status
Simulation time 283929465 ps
CPU time 2.8 seconds
Started Jul 11 06:24:29 PM PDT 24
Finished Jul 11 06:24:39 PM PDT 24
Peak memory 215640 kb
Host smart-e81ed9c5-155f-4cd8-bffd-a752f8ae5fe3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990853814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.2
990853814
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.3694692870
Short name T1012
Test name
Test status
Simulation time 29641895 ps
CPU time 0.77 seconds
Started Jul 11 06:24:27 PM PDT 24
Finished Jul 11 06:24:34 PM PDT 24
Peak memory 204308 kb
Host smart-81b82962-b4f5-434a-8da6-530cfffa59f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694692870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.3
694692870
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.882864545
Short name T97
Test name
Test status
Simulation time 18275292 ps
CPU time 1.17 seconds
Started Jul 11 06:24:20 PM PDT 24
Finished Jul 11 06:24:28 PM PDT 24
Peak memory 215704 kb
Host smart-d2d4c1c0-9258-4f9c-8e39-7736ce03ef03
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882864545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_
device_mem_partial_access.882864545
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.458715918
Short name T1053
Test name
Test status
Simulation time 23040630 ps
CPU time 0.66 seconds
Started Jul 11 06:24:21 PM PDT 24
Finished Jul 11 06:24:28 PM PDT 24
Peak memory 204080 kb
Host smart-562761a4-0eb9-4b7a-a840-5f8f17147595
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458715918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem
_walk.458715918
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3509969724
Short name T1065
Test name
Test status
Simulation time 375858341 ps
CPU time 2.93 seconds
Started Jul 11 06:24:37 PM PDT 24
Finished Jul 11 06:24:48 PM PDT 24
Peak memory 215664 kb
Host smart-49dc8188-a211-4ea3-a96d-9f8606500054
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509969724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.3509969724
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.2302897640
Short name T1118
Test name
Test status
Simulation time 83664984 ps
CPU time 2.56 seconds
Started Jul 11 06:24:28 PM PDT 24
Finished Jul 11 06:24:37 PM PDT 24
Peak memory 215952 kb
Host smart-94296543-0a2c-4f1a-9b53-397226a55170
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302897640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.2
302897640
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.3238198544
Short name T150
Test name
Test status
Simulation time 105764148 ps
CPU time 6.29 seconds
Started Jul 11 06:24:24 PM PDT 24
Finished Jul 11 06:24:36 PM PDT 24
Peak memory 215808 kb
Host smart-dcfa7ad2-7f3c-49bb-8ae4-3450eceb170a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238198544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.3238198544
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.4028018153
Short name T1106
Test name
Test status
Simulation time 25105769 ps
CPU time 0.76 seconds
Started Jul 11 06:24:41 PM PDT 24
Finished Jul 11 06:24:52 PM PDT 24
Peak memory 204264 kb
Host smart-9cf82edb-5624-419c-8775-aafec762cc77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028018153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
4028018153
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2540625920
Short name T1060
Test name
Test status
Simulation time 19576235 ps
CPU time 0.74 seconds
Started Jul 11 06:25:07 PM PDT 24
Finished Jul 11 06:25:16 PM PDT 24
Peak memory 204316 kb
Host smart-77d011bb-8934-4d91-8ddf-d771b9451b9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540625920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
2540625920
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.2481593659
Short name T1052
Test name
Test status
Simulation time 57978582 ps
CPU time 0.73 seconds
Started Jul 11 06:24:46 PM PDT 24
Finished Jul 11 06:24:59 PM PDT 24
Peak memory 204620 kb
Host smart-24f3bb7f-88e2-4ff1-927b-524e71571572
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481593659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
2481593659
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.957268666
Short name T1068
Test name
Test status
Simulation time 89041271 ps
CPU time 0.71 seconds
Started Jul 11 06:24:52 PM PDT 24
Finished Jul 11 06:25:05 PM PDT 24
Peak memory 204316 kb
Host smart-32489b2c-918b-4691-9972-39612483f611
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957268666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.957268666
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.3832614230
Short name T1036
Test name
Test status
Simulation time 18627768 ps
CPU time 0.77 seconds
Started Jul 11 06:24:47 PM PDT 24
Finished Jul 11 06:24:59 PM PDT 24
Peak memory 204308 kb
Host smart-0d9b04d9-c9ca-4cdd-befc-2df36e6e1dc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832614230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
3832614230
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.1968677213
Short name T1031
Test name
Test status
Simulation time 43931765 ps
CPU time 0.75 seconds
Started Jul 11 06:24:43 PM PDT 24
Finished Jul 11 06:24:54 PM PDT 24
Peak memory 204320 kb
Host smart-49b746f3-48d1-41bb-aa63-7c1e9b217878
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968677213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
1968677213
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2607625716
Short name T1042
Test name
Test status
Simulation time 78985571 ps
CPU time 0.77 seconds
Started Jul 11 06:24:44 PM PDT 24
Finished Jul 11 06:24:55 PM PDT 24
Peak memory 204304 kb
Host smart-442dd640-cc7b-4415-a3f6-fbacd24b93a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607625716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
2607625716
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.2794477169
Short name T1023
Test name
Test status
Simulation time 116106608 ps
CPU time 0.69 seconds
Started Jul 11 06:24:45 PM PDT 24
Finished Jul 11 06:24:58 PM PDT 24
Peak memory 204284 kb
Host smart-03376096-5c1d-4b02-9a60-a38bbfaf8899
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794477169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
2794477169
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.2081726047
Short name T1123
Test name
Test status
Simulation time 37480886 ps
CPU time 0.7 seconds
Started Jul 11 06:24:44 PM PDT 24
Finished Jul 11 06:24:55 PM PDT 24
Peak memory 204316 kb
Host smart-a1134bf7-4013-406e-b900-3f6632dca346
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081726047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
2081726047
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2687529357
Short name T1028
Test name
Test status
Simulation time 59064980 ps
CPU time 0.77 seconds
Started Jul 11 06:24:47 PM PDT 24
Finished Jul 11 06:25:02 PM PDT 24
Peak memory 204272 kb
Host smart-08fdbba5-6cdc-4af9-86a4-cf7b69982ca7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687529357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
2687529357
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1985467542
Short name T1101
Test name
Test status
Simulation time 313560692 ps
CPU time 8.08 seconds
Started Jul 11 06:24:38 PM PDT 24
Finished Jul 11 06:24:55 PM PDT 24
Peak memory 215736 kb
Host smart-a1231021-4a2a-448b-b427-e26aad1356a7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985467542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.1985467542
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3368895373
Short name T1016
Test name
Test status
Simulation time 1222728098 ps
CPU time 13.04 seconds
Started Jul 11 06:24:30 PM PDT 24
Finished Jul 11 06:24:50 PM PDT 24
Peak memory 207644 kb
Host smart-12af4813-647f-4941-8aa0-edd364ac29c7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368895373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.3368895373
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3894315093
Short name T65
Test name
Test status
Simulation time 121795086 ps
CPU time 1.21 seconds
Started Jul 11 06:24:32 PM PDT 24
Finished Jul 11 06:24:41 PM PDT 24
Peak memory 207408 kb
Host smart-2c8ef4da-5c19-436e-bb0e-7cd4e29ef89a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894315093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.3894315093
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2991276768
Short name T1126
Test name
Test status
Simulation time 136068492 ps
CPU time 4.2 seconds
Started Jul 11 06:24:31 PM PDT 24
Finished Jul 11 06:24:43 PM PDT 24
Peak memory 218768 kb
Host smart-ecf465e5-f587-421c-97c3-c3d5abb13107
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991276768 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.2991276768
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1918642111
Short name T1127
Test name
Test status
Simulation time 26684492 ps
CPU time 1.8 seconds
Started Jul 11 06:24:32 PM PDT 24
Finished Jul 11 06:24:41 PM PDT 24
Peak memory 215636 kb
Host smart-bc229404-66d0-4d2a-901e-39349e1cea2a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918642111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.1
918642111
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.4215603846
Short name T1083
Test name
Test status
Simulation time 13729969 ps
CPU time 0.72 seconds
Started Jul 11 06:24:33 PM PDT 24
Finished Jul 11 06:24:43 PM PDT 24
Peak memory 204304 kb
Host smart-a2748eba-9458-40ac-9981-b96186577e83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215603846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.4
215603846
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.316597921
Short name T1089
Test name
Test status
Simulation time 19028474 ps
CPU time 1.26 seconds
Started Jul 11 06:24:33 PM PDT 24
Finished Jul 11 06:24:42 PM PDT 24
Peak memory 215768 kb
Host smart-bce0d735-2db5-4f03-87d8-be8987cdfee6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316597921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_
device_mem_partial_access.316597921
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1369529746
Short name T1048
Test name
Test status
Simulation time 10892078 ps
CPU time 0.69 seconds
Started Jul 11 06:24:30 PM PDT 24
Finished Jul 11 06:24:38 PM PDT 24
Peak memory 203988 kb
Host smart-fcce4c0a-6a18-46f4-a041-2c9b6138e7fe
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369529746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.1369529746
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2248805644
Short name T1051
Test name
Test status
Simulation time 70076349 ps
CPU time 2.2 seconds
Started Jul 11 06:24:32 PM PDT 24
Finished Jul 11 06:24:42 PM PDT 24
Peak memory 215804 kb
Host smart-51c7c904-833b-48e3-80f5-24485b3e8a51
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248805644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.2248805644
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.4191721276
Short name T132
Test name
Test status
Simulation time 756024125 ps
CPU time 16.58 seconds
Started Jul 11 06:24:33 PM PDT 24
Finished Jul 11 06:24:57 PM PDT 24
Peak memory 216192 kb
Host smart-b7f990e6-c999-421a-8b51-d8b66e241c4e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191721276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.4191721276
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.340565409
Short name T1018
Test name
Test status
Simulation time 40342043 ps
CPU time 0.67 seconds
Started Jul 11 06:24:48 PM PDT 24
Finished Jul 11 06:25:02 PM PDT 24
Peak memory 204256 kb
Host smart-17d5c6b5-ae40-444b-9eab-4659b46fb7f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340565409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.340565409
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.2561811566
Short name T1063
Test name
Test status
Simulation time 12649356 ps
CPU time 0.76 seconds
Started Jul 11 06:24:49 PM PDT 24
Finished Jul 11 06:25:03 PM PDT 24
Peak memory 204296 kb
Host smart-a4ccaecb-2181-46a2-af52-8c2a68ff3504
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561811566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
2561811566
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3356636859
Short name T1049
Test name
Test status
Simulation time 10987389 ps
CPU time 0.7 seconds
Started Jul 11 06:24:44 PM PDT 24
Finished Jul 11 06:24:55 PM PDT 24
Peak memory 204324 kb
Host smart-8984cd30-8d8c-4d93-b8f9-04898c76f4d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356636859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
3356636859
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.2525727995
Short name T1081
Test name
Test status
Simulation time 27833540 ps
CPU time 0.79 seconds
Started Jul 11 06:24:49 PM PDT 24
Finished Jul 11 06:25:03 PM PDT 24
Peak memory 204224 kb
Host smart-3e0f4a86-0508-4cf5-b671-297d76c84e5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525727995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
2525727995
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3613686378
Short name T1077
Test name
Test status
Simulation time 28428394 ps
CPU time 0.77 seconds
Started Jul 11 06:25:01 PM PDT 24
Finished Jul 11 06:25:12 PM PDT 24
Peak memory 204596 kb
Host smart-6a5910d5-4b8d-4d56-a828-59a601c67b9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613686378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
3613686378
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1924794635
Short name T1038
Test name
Test status
Simulation time 13236882 ps
CPU time 0.7 seconds
Started Jul 11 06:24:52 PM PDT 24
Finished Jul 11 06:25:05 PM PDT 24
Peak memory 204320 kb
Host smart-b955bb23-ee10-450f-88d4-e177c76dde8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924794635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
1924794635
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.853900892
Short name T1087
Test name
Test status
Simulation time 20011194 ps
CPU time 0.75 seconds
Started Jul 11 06:24:54 PM PDT 24
Finished Jul 11 06:25:07 PM PDT 24
Peak memory 204268 kb
Host smart-f9ddb37a-55be-4506-8aac-b29a0d8da6e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853900892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.853900892
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.2378366842
Short name T1026
Test name
Test status
Simulation time 18733508 ps
CPU time 0.78 seconds
Started Jul 11 06:24:51 PM PDT 24
Finished Jul 11 06:25:04 PM PDT 24
Peak memory 204236 kb
Host smart-7d7b944b-91f4-4ac2-8165-48f25db53d1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378366842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
2378366842
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.1166335541
Short name T1112
Test name
Test status
Simulation time 12028808 ps
CPU time 0.74 seconds
Started Jul 11 06:24:52 PM PDT 24
Finished Jul 11 06:25:06 PM PDT 24
Peak memory 204624 kb
Host smart-90b5598b-2f4b-4f89-9f4c-da975da98525
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166335541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
1166335541
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.3156067599
Short name T1044
Test name
Test status
Simulation time 17176598 ps
CPU time 0.74 seconds
Started Jul 11 06:24:50 PM PDT 24
Finished Jul 11 06:25:04 PM PDT 24
Peak memory 204304 kb
Host smart-c48790d9-f877-421c-b066-a7726b29d2df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156067599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
3156067599
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.1659078716
Short name T109
Test name
Test status
Simulation time 2431575913 ps
CPU time 16.28 seconds
Started Jul 11 06:24:32 PM PDT 24
Finished Jul 11 06:24:56 PM PDT 24
Peak memory 215812 kb
Host smart-c9bcef3c-693b-4019-838f-a31ba2cd31db
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659078716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.1659078716
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2893723652
Short name T101
Test name
Test status
Simulation time 367460485 ps
CPU time 12.78 seconds
Started Jul 11 06:24:35 PM PDT 24
Finished Jul 11 06:24:56 PM PDT 24
Peak memory 207408 kb
Host smart-855495ba-1ca8-440d-b5e8-216e247a8459
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893723652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.2893723652
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3312416677
Short name T66
Test name
Test status
Simulation time 59975624 ps
CPU time 1.21 seconds
Started Jul 11 06:24:28 PM PDT 24
Finished Jul 11 06:24:36 PM PDT 24
Peak memory 207496 kb
Host smart-ee4c7ea4-abd7-4d7e-b445-af1fb5bb001e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312416677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.3312416677
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1849289354
Short name T91
Test name
Test status
Simulation time 155866934 ps
CPU time 2.76 seconds
Started Jul 11 06:24:34 PM PDT 24
Finished Jul 11 06:24:46 PM PDT 24
Peak memory 216856 kb
Host smart-775deb40-6b7d-4d0f-ab31-7c0cb40a039c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849289354 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.1849289354
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.3166191286
Short name T1095
Test name
Test status
Simulation time 454964728 ps
CPU time 2.7 seconds
Started Jul 11 06:24:29 PM PDT 24
Finished Jul 11 06:24:39 PM PDT 24
Peak memory 215752 kb
Host smart-c792219d-4244-42da-a29f-44934d616973
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166191286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.3
166191286
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3626715564
Short name T1124
Test name
Test status
Simulation time 27508702 ps
CPU time 0.77 seconds
Started Jul 11 06:24:28 PM PDT 24
Finished Jul 11 06:24:35 PM PDT 24
Peak memory 204320 kb
Host smart-e4423d5f-feda-493e-8c44-65ec5276df47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626715564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.3
626715564
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.4198127189
Short name T1061
Test name
Test status
Simulation time 587829157 ps
CPU time 1.72 seconds
Started Jul 11 06:24:37 PM PDT 24
Finished Jul 11 06:24:47 PM PDT 24
Peak memory 215768 kb
Host smart-7a7178a3-4839-4015-a021-84acccdfb988
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198127189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.4198127189
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2632971599
Short name T1109
Test name
Test status
Simulation time 16359037 ps
CPU time 0.74 seconds
Started Jul 11 06:24:37 PM PDT 24
Finished Jul 11 06:24:46 PM PDT 24
Peak memory 204092 kb
Host smart-95913d0c-ca51-46f7-8a69-5b67486a8f95
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632971599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.2632971599
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.3892309326
Short name T135
Test name
Test status
Simulation time 426820283 ps
CPU time 4.34 seconds
Started Jul 11 06:24:38 PM PDT 24
Finished Jul 11 06:24:52 PM PDT 24
Peak memory 215836 kb
Host smart-d61c9db4-8f62-49cf-b12d-345f0a9c2644
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892309326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.3892309326
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.793880892
Short name T1082
Test name
Test status
Simulation time 616262224 ps
CPU time 3.41 seconds
Started Jul 11 06:24:33 PM PDT 24
Finished Jul 11 06:24:46 PM PDT 24
Peak memory 217016 kb
Host smart-c3310785-bbcf-402e-8c3a-eb6e88c2e5ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793880892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.793880892
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.4288101912
Short name T156
Test name
Test status
Simulation time 1184265575 ps
CPU time 19.79 seconds
Started Jul 11 06:24:29 PM PDT 24
Finished Jul 11 06:24:56 PM PDT 24
Peak memory 215864 kb
Host smart-96a5f00b-4fd9-4e82-9d7e-04309379dad6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288101912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.4288101912
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.84976765
Short name T1027
Test name
Test status
Simulation time 22326770 ps
CPU time 0.72 seconds
Started Jul 11 06:25:01 PM PDT 24
Finished Jul 11 06:25:12 PM PDT 24
Peak memory 204276 kb
Host smart-b2ab48b4-5ef3-4b64-9dfa-b023994f2e92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84976765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.84976765
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.3162620991
Short name T1030
Test name
Test status
Simulation time 83136393 ps
CPU time 0.7 seconds
Started Jul 11 06:24:55 PM PDT 24
Finished Jul 11 06:25:08 PM PDT 24
Peak memory 204304 kb
Host smart-0ab565a6-ba1c-4a92-bc23-c333dbffebd4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162620991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
3162620991
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.3949911836
Short name T1071
Test name
Test status
Simulation time 45097393 ps
CPU time 0.75 seconds
Started Jul 11 06:25:02 PM PDT 24
Finished Jul 11 06:25:12 PM PDT 24
Peak memory 204768 kb
Host smart-cae8b368-9542-458e-9e28-966a94a94812
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949911836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
3949911836
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.4234022060
Short name T1086
Test name
Test status
Simulation time 94042049 ps
CPU time 0.74 seconds
Started Jul 11 06:24:53 PM PDT 24
Finished Jul 11 06:25:07 PM PDT 24
Peak memory 204580 kb
Host smart-0d936c5d-0ed8-4933-9db6-9815e43ca184
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234022060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
4234022060
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1703462921
Short name T1113
Test name
Test status
Simulation time 51324372 ps
CPU time 0.71 seconds
Started Jul 11 06:24:54 PM PDT 24
Finished Jul 11 06:25:07 PM PDT 24
Peak memory 204308 kb
Host smart-d2f0a02d-8582-45c9-bd7d-106a46051bb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703462921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
1703462921
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3020034584
Short name T1033
Test name
Test status
Simulation time 31557869 ps
CPU time 0.76 seconds
Started Jul 11 06:25:01 PM PDT 24
Finished Jul 11 06:25:12 PM PDT 24
Peak memory 204284 kb
Host smart-0de0e58d-5157-429b-9f0b-fd42f318fd5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020034584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
3020034584
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.3206057395
Short name T1062
Test name
Test status
Simulation time 164810788 ps
CPU time 0.77 seconds
Started Jul 11 06:25:05 PM PDT 24
Finished Jul 11 06:25:23 PM PDT 24
Peak memory 204636 kb
Host smart-8e8aa4db-344e-4391-9a94-6ca5dca3ed92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206057395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
3206057395
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.4024361487
Short name T1066
Test name
Test status
Simulation time 16021615 ps
CPU time 0.74 seconds
Started Jul 11 06:24:59 PM PDT 24
Finished Jul 11 06:25:11 PM PDT 24
Peak memory 204304 kb
Host smart-45d253a8-3f01-44cf-bed6-979b48899229
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024361487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
4024361487
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2417542580
Short name T1074
Test name
Test status
Simulation time 78468741 ps
CPU time 0.75 seconds
Started Jul 11 06:25:01 PM PDT 24
Finished Jul 11 06:25:12 PM PDT 24
Peak memory 204636 kb
Host smart-bd411073-e94f-4217-bad4-4da04d815f0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417542580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
2417542580
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.768368011
Short name T1039
Test name
Test status
Simulation time 92968348 ps
CPU time 0.79 seconds
Started Jul 11 06:25:05 PM PDT 24
Finished Jul 11 06:25:14 PM PDT 24
Peak memory 204440 kb
Host smart-12974ed3-cf25-4db7-ace1-2a1807016ad5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768368011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.768368011
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.582028736
Short name T1029
Test name
Test status
Simulation time 99473680 ps
CPU time 1.93 seconds
Started Jul 11 06:24:36 PM PDT 24
Finished Jul 11 06:24:47 PM PDT 24
Peak memory 216884 kb
Host smart-f9574351-d1a6-41b7-bda9-31f15505ea3f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582028736 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.582028736
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3349850342
Short name T1076
Test name
Test status
Simulation time 131221978 ps
CPU time 2.72 seconds
Started Jul 11 06:24:33 PM PDT 24
Finished Jul 11 06:24:44 PM PDT 24
Peak memory 215724 kb
Host smart-4ad356c3-90ce-464b-87c6-3c981b4c6f1e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349850342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.3
349850342
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3131632869
Short name T1070
Test name
Test status
Simulation time 20681336 ps
CPU time 0.7 seconds
Started Jul 11 06:24:37 PM PDT 24
Finished Jul 11 06:24:46 PM PDT 24
Peak memory 204296 kb
Host smart-4cb17019-bf64-41b5-a1fa-d21f1d15f758
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131632869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.3
131632869
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2638855368
Short name T1059
Test name
Test status
Simulation time 78834028 ps
CPU time 2.94 seconds
Started Jul 11 06:24:38 PM PDT 24
Finished Jul 11 06:24:50 PM PDT 24
Peak memory 215812 kb
Host smart-1d32524c-12a1-459f-a095-8eb1161dea86
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638855368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.2638855368
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.2762155213
Short name T89
Test name
Test status
Simulation time 47439883 ps
CPU time 1.4 seconds
Started Jul 11 06:24:36 PM PDT 24
Finished Jul 11 06:24:46 PM PDT 24
Peak memory 216048 kb
Host smart-752f1a45-054a-493a-9356-c9afb12114e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762155213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.2
762155213
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.1988412345
Short name T1116
Test name
Test status
Simulation time 140730733 ps
CPU time 3.43 seconds
Started Jul 11 06:24:38 PM PDT 24
Finished Jul 11 06:24:51 PM PDT 24
Peak memory 219032 kb
Host smart-be1fc54f-41e4-482c-9dc6-b5b96b2f4b58
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988412345 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.1988412345
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1527891340
Short name T129
Test name
Test status
Simulation time 88280702 ps
CPU time 1.32 seconds
Started Jul 11 06:24:46 PM PDT 24
Finished Jul 11 06:25:00 PM PDT 24
Peak memory 207668 kb
Host smart-07579127-3c63-433e-9545-822154dc1ba2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527891340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.1
527891340
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.3418092092
Short name T1058
Test name
Test status
Simulation time 39766686 ps
CPU time 0.77 seconds
Started Jul 11 06:24:40 PM PDT 24
Finished Jul 11 06:24:51 PM PDT 24
Peak memory 204316 kb
Host smart-f19c7098-43e6-4faa-8eea-425e8bcd2a9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418092092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.3
418092092
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2547982977
Short name T1035
Test name
Test status
Simulation time 211325880 ps
CPU time 3.5 seconds
Started Jul 11 06:24:31 PM PDT 24
Finished Jul 11 06:24:42 PM PDT 24
Peak memory 215632 kb
Host smart-e0d27a0f-1d49-4938-9611-175ed3973167
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547982977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.2547982977
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2634418902
Short name T57
Test name
Test status
Simulation time 129909764 ps
CPU time 2 seconds
Started Jul 11 06:24:36 PM PDT 24
Finished Jul 11 06:24:47 PM PDT 24
Peak memory 216144 kb
Host smart-a6e0a0b3-66c2-419b-a325-d3be18ce9f4b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634418902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.2
634418902
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1132378295
Short name T158
Test name
Test status
Simulation time 409119581 ps
CPU time 7.01 seconds
Started Jul 11 06:24:39 PM PDT 24
Finished Jul 11 06:24:55 PM PDT 24
Peak memory 215820 kb
Host smart-4ae95a25-0337-4c7c-bfa2-ddfbd8ca8545
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132378295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.1132378295
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2362256803
Short name T1097
Test name
Test status
Simulation time 100702959 ps
CPU time 2.73 seconds
Started Jul 11 06:24:30 PM PDT 24
Finished Jul 11 06:24:39 PM PDT 24
Peak memory 217672 kb
Host smart-99bba1ad-1976-423b-b807-512f6b25f8ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362256803 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.2362256803
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1107035865
Short name T107
Test name
Test status
Simulation time 72927932 ps
CPU time 2.37 seconds
Started Jul 11 06:24:30 PM PDT 24
Finished Jul 11 06:24:39 PM PDT 24
Peak memory 215720 kb
Host smart-f8b505b3-bf74-4f51-8db7-7b05036cd38a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107035865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.1
107035865
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.233220983
Short name T1104
Test name
Test status
Simulation time 17644849 ps
CPU time 0.7 seconds
Started Jul 11 06:24:33 PM PDT 24
Finished Jul 11 06:24:42 PM PDT 24
Peak memory 204308 kb
Host smart-9654fcb4-24c7-43d1-bebe-d06f82abd4b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233220983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.233220983
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3732181192
Short name T1017
Test name
Test status
Simulation time 209077511 ps
CPU time 3.42 seconds
Started Jul 11 06:24:37 PM PDT 24
Finished Jul 11 06:24:49 PM PDT 24
Peak memory 215828 kb
Host smart-13533aa1-c4f8-4c6c-b5ab-459585b3087b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732181192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.3732181192
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2659925014
Short name T85
Test name
Test status
Simulation time 773011529 ps
CPU time 4.66 seconds
Started Jul 11 06:24:38 PM PDT 24
Finished Jul 11 06:24:52 PM PDT 24
Peak memory 216088 kb
Host smart-40023786-69e6-4deb-9775-964f4c231277
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659925014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.2
659925014
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.3335684135
Short name T134
Test name
Test status
Simulation time 684849543 ps
CPU time 14.71 seconds
Started Jul 11 06:24:38 PM PDT 24
Finished Jul 11 06:25:02 PM PDT 24
Peak memory 215732 kb
Host smart-6d361d90-c2b3-4295-8d54-aac97dc8d179
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335684135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.3335684135
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.4268333411
Short name T1108
Test name
Test status
Simulation time 374063706 ps
CPU time 3.22 seconds
Started Jul 11 06:24:37 PM PDT 24
Finished Jul 11 06:24:48 PM PDT 24
Peak memory 217508 kb
Host smart-b2dae208-5488-4373-b862-d8b61fd62fe3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268333411 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.4268333411
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.2515687047
Short name T102
Test name
Test status
Simulation time 51269377 ps
CPU time 1.86 seconds
Started Jul 11 06:24:39 PM PDT 24
Finished Jul 11 06:24:50 PM PDT 24
Peak memory 215704 kb
Host smart-0468bb9c-8106-4be1-8080-22bf8d09ac25
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515687047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.2
515687047
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1837837140
Short name T1025
Test name
Test status
Simulation time 28124530 ps
CPU time 0.73 seconds
Started Jul 11 06:24:36 PM PDT 24
Finished Jul 11 06:24:46 PM PDT 24
Peak memory 204216 kb
Host smart-2ba7ae99-32fb-4913-bda4-d82f6b057d9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837837140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.1
837837140
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1035388565
Short name T1067
Test name
Test status
Simulation time 135759954 ps
CPU time 1.85 seconds
Started Jul 11 06:24:29 PM PDT 24
Finished Jul 11 06:24:38 PM PDT 24
Peak memory 215788 kb
Host smart-657cad66-b213-4768-b0a5-5394790bdd25
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035388565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.1035388565
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.3980022374
Short name T94
Test name
Test status
Simulation time 52691116 ps
CPU time 1.89 seconds
Started Jul 11 06:24:36 PM PDT 24
Finished Jul 11 06:24:47 PM PDT 24
Peak memory 216016 kb
Host smart-32d484de-a67f-40f4-98d7-9c67f0417d03
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980022374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.3
980022374
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1670711172
Short name T1121
Test name
Test status
Simulation time 311791425 ps
CPU time 18.32 seconds
Started Jul 11 06:24:36 PM PDT 24
Finished Jul 11 06:25:03 PM PDT 24
Peak memory 215632 kb
Host smart-89f03dc1-2582-42e7-863e-6d8a787d0737
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670711172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.1670711172
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3963041289
Short name T1045
Test name
Test status
Simulation time 25972159 ps
CPU time 1.97 seconds
Started Jul 11 06:24:31 PM PDT 24
Finished Jul 11 06:24:40 PM PDT 24
Peak memory 216772 kb
Host smart-e16a4b9e-7f4a-456a-8448-aeb6763e67b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963041289 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.3963041289
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2734826358
Short name T1054
Test name
Test status
Simulation time 20599621 ps
CPU time 1.35 seconds
Started Jul 11 06:24:40 PM PDT 24
Finished Jul 11 06:24:50 PM PDT 24
Peak memory 207532 kb
Host smart-2e50e705-4702-4d96-8e35-88492dfc02d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734826358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.2
734826358
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2148442203
Short name T1024
Test name
Test status
Simulation time 25075645 ps
CPU time 0.76 seconds
Started Jul 11 06:24:38 PM PDT 24
Finished Jul 11 06:24:48 PM PDT 24
Peak memory 204624 kb
Host smart-1861e1da-a5e5-43e7-96b9-f60a5d406f7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148442203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.2
148442203
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.1193562798
Short name T1041
Test name
Test status
Simulation time 46809485 ps
CPU time 2.86 seconds
Started Jul 11 06:24:30 PM PDT 24
Finished Jul 11 06:24:40 PM PDT 24
Peak memory 215788 kb
Host smart-e4568714-a4ab-4642-b60a-6b7d8d83f60c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193562798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.1193562798
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1981306420
Short name T154
Test name
Test status
Simulation time 564639948 ps
CPU time 14.47 seconds
Started Jul 11 06:24:35 PM PDT 24
Finished Jul 11 06:24:58 PM PDT 24
Peak memory 215764 kb
Host smart-fabfbc72-cc5c-4e58-9b20-9889ca11422f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981306420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.1981306420
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.832832910
Short name T715
Test name
Test status
Simulation time 14410162 ps
CPU time 0.76 seconds
Started Jul 11 06:34:35 PM PDT 24
Finished Jul 11 06:34:37 PM PDT 24
Peak memory 205896 kb
Host smart-89af1c7e-efbc-470b-a586-ae29e7a7aad7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832832910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.832832910
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.3426662499
Short name T244
Test name
Test status
Simulation time 516731001 ps
CPU time 3.82 seconds
Started Jul 11 06:34:27 PM PDT 24
Finished Jul 11 06:34:32 PM PDT 24
Peak memory 224468 kb
Host smart-6166c506-116d-4d1b-8e90-b184bb511083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426662499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.3426662499
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.3650144316
Short name T704
Test name
Test status
Simulation time 41005883 ps
CPU time 0.83 seconds
Started Jul 11 06:34:23 PM PDT 24
Finished Jul 11 06:34:24 PM PDT 24
Peak memory 206632 kb
Host smart-906cec4b-31eb-46ca-b970-b00cfa54f5a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650144316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.3650144316
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.3586675960
Short name T265
Test name
Test status
Simulation time 128047709988 ps
CPU time 458.79 seconds
Started Jul 11 06:34:31 PM PDT 24
Finished Jul 11 06:42:12 PM PDT 24
Peak memory 256368 kb
Host smart-e371b3a5-1e74-41d8-ab8e-a8ffb8b422dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586675960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.3586675960
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.2681690208
Short name T495
Test name
Test status
Simulation time 34174420794 ps
CPU time 350.13 seconds
Started Jul 11 06:34:30 PM PDT 24
Finished Jul 11 06:40:22 PM PDT 24
Peak memory 254804 kb
Host smart-a08241ad-3c1f-475e-8892-4753f2654ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681690208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.2681690208
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.4015330900
Short name T643
Test name
Test status
Simulation time 12573258655 ps
CPU time 118.33 seconds
Started Jul 11 06:34:31 PM PDT 24
Finished Jul 11 06:36:31 PM PDT 24
Peak memory 250276 kb
Host smart-aa717715-4bf2-4259-843b-8ad5a6e997da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015330900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.4015330900
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.16241388
Short name T700
Test name
Test status
Simulation time 1137654436 ps
CPU time 13.52 seconds
Started Jul 11 06:34:27 PM PDT 24
Finished Jul 11 06:34:41 PM PDT 24
Peak memory 240864 kb
Host smart-d8e9f630-9b3e-4ec9-a91f-0677cde176a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16241388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds.16241388
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_intercept.3090610419
Short name T401
Test name
Test status
Simulation time 145380560 ps
CPU time 4.32 seconds
Started Jul 11 06:34:33 PM PDT 24
Finished Jul 11 06:34:39 PM PDT 24
Peak memory 230172 kb
Host smart-ecdcd297-20a1-4446-bae3-08ef2fd11b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090610419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.3090610419
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.2732869347
Short name T489
Test name
Test status
Simulation time 59113108081 ps
CPU time 24.03 seconds
Started Jul 11 06:34:27 PM PDT 24
Finished Jul 11 06:34:52 PM PDT 24
Peak memory 239728 kb
Host smart-ed1a69af-d110-4d24-8bf2-636a1d2f5537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732869347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.2732869347
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.1166486891
Short name T260
Test name
Test status
Simulation time 19273960289 ps
CPU time 9.36 seconds
Started Jul 11 06:34:26 PM PDT 24
Finished Jul 11 06:34:36 PM PDT 24
Peak memory 232808 kb
Host smart-905d0f3d-a274-46f2-86eb-d342df8fb498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166486891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.1166486891
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.2241671289
Short name T322
Test name
Test status
Simulation time 862085219 ps
CPU time 3.9 seconds
Started Jul 11 06:34:31 PM PDT 24
Finished Jul 11 06:34:37 PM PDT 24
Peak memory 222960 kb
Host smart-1dcbb80e-b4aa-4366-95ec-8c033c44ee21
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2241671289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.2241671289
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.850193266
Short name T62
Test name
Test status
Simulation time 140658486 ps
CPU time 1.04 seconds
Started Jul 11 06:34:35 PM PDT 24
Finished Jul 11 06:34:37 PM PDT 24
Peak memory 235976 kb
Host smart-2be8b6a3-7efb-4871-bece-f3326fba7f4e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850193266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.850193266
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.3975303424
Short name T46
Test name
Test status
Simulation time 18854508090 ps
CPU time 50.22 seconds
Started Jul 11 06:34:36 PM PDT 24
Finished Jul 11 06:35:27 PM PDT 24
Peak memory 250496 kb
Host smart-2a1d32ad-2dd2-41c6-8540-c2aa6fe4ec47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975303424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.3975303424
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.3868722883
Short name T286
Test name
Test status
Simulation time 3164002999 ps
CPU time 21.09 seconds
Started Jul 11 06:34:24 PM PDT 24
Finished Jul 11 06:34:46 PM PDT 24
Peak memory 220020 kb
Host smart-bb723ab0-73c8-4080-9c38-2cae0338a7a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868722883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.3868722883
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.2897047993
Short name T897
Test name
Test status
Simulation time 1146887004 ps
CPU time 3.38 seconds
Started Jul 11 06:34:24 PM PDT 24
Finished Jul 11 06:34:28 PM PDT 24
Peak memory 216260 kb
Host smart-316cfbfb-b9b4-4e7d-ac15-3e768e7c7b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897047993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.2897047993
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.3426102680
Short name T882
Test name
Test status
Simulation time 161178095 ps
CPU time 1.28 seconds
Started Jul 11 06:34:28 PM PDT 24
Finished Jul 11 06:34:30 PM PDT 24
Peak memory 208368 kb
Host smart-7115eba7-c4dd-49fc-ba45-7e25ef6d74b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426102680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.3426102680
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.611192662
Short name T1002
Test name
Test status
Simulation time 35047907 ps
CPU time 0.81 seconds
Started Jul 11 06:34:22 PM PDT 24
Finished Jul 11 06:34:24 PM PDT 24
Peak memory 205972 kb
Host smart-e0e56280-8b3c-4b27-a00c-2d86106c02b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611192662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.611192662
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.2014270015
Short name T831
Test name
Test status
Simulation time 27896015470 ps
CPU time 21.03 seconds
Started Jul 11 06:34:28 PM PDT 24
Finished Jul 11 06:34:50 PM PDT 24
Peak memory 224644 kb
Host smart-dc5cef7a-a811-4c95-a527-7325c752cb79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014270015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.2014270015
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.2894553800
Short name T824
Test name
Test status
Simulation time 15451380 ps
CPU time 0.74 seconds
Started Jul 11 06:34:46 PM PDT 24
Finished Jul 11 06:34:48 PM PDT 24
Peak memory 205896 kb
Host smart-25868e1b-e6c5-4b10-81c8-9d56ddb4ea7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894553800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.2
894553800
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.1264503408
Short name T679
Test name
Test status
Simulation time 51992969 ps
CPU time 2.37 seconds
Started Jul 11 06:34:45 PM PDT 24
Finished Jul 11 06:34:49 PM PDT 24
Peak memory 232328 kb
Host smart-d0db54b1-186d-498f-8e5d-6470b3356ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264503408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.1264503408
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.2116418754
Short name T977
Test name
Test status
Simulation time 60605796 ps
CPU time 0.81 seconds
Started Jul 11 06:34:36 PM PDT 24
Finished Jul 11 06:34:38 PM PDT 24
Peak memory 206640 kb
Host smart-51f03b53-e925-4e92-a7c1-eb24fd9ab930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116418754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.2116418754
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.2145654113
Short name T204
Test name
Test status
Simulation time 6102904305 ps
CPU time 104.4 seconds
Started Jul 11 06:34:45 PM PDT 24
Finished Jul 11 06:36:30 PM PDT 24
Peak memory 255544 kb
Host smart-3befe491-8ddb-4771-8819-b9e6e6a4f59b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145654113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.2145654113
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.2806267421
Short name T434
Test name
Test status
Simulation time 90576079805 ps
CPU time 207.76 seconds
Started Jul 11 06:34:43 PM PDT 24
Finished Jul 11 06:38:12 PM PDT 24
Peak memory 249360 kb
Host smart-f0b88c6f-dccf-4c07-bb12-2f59cd8a7e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806267421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.2806267421
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.3477369998
Short name T331
Test name
Test status
Simulation time 783885214 ps
CPU time 10.6 seconds
Started Jul 11 06:34:40 PM PDT 24
Finished Jul 11 06:34:51 PM PDT 24
Peak memory 224500 kb
Host smart-94e7b68a-790d-48c3-ab26-d4e1175d214c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477369998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.3477369998
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.804076372
Short name T887
Test name
Test status
Simulation time 33852366795 ps
CPU time 244.35 seconds
Started Jul 11 06:34:42 PM PDT 24
Finished Jul 11 06:38:47 PM PDT 24
Peak memory 252392 kb
Host smart-0e1e3baf-bf30-4817-991b-f7c0d145afc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804076372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds.
804076372
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_intercept.758934365
Short name T181
Test name
Test status
Simulation time 3739679058 ps
CPU time 14.61 seconds
Started Jul 11 06:34:41 PM PDT 24
Finished Jul 11 06:34:57 PM PDT 24
Peak memory 232756 kb
Host smart-f3274433-6eec-4d6e-9736-60aa0eaf100f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758934365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.758934365
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.3309925277
Short name T968
Test name
Test status
Simulation time 2157911797 ps
CPU time 32.98 seconds
Started Jul 11 06:34:39 PM PDT 24
Finished Jul 11 06:35:13 PM PDT 24
Peak memory 224508 kb
Host smart-b3e2947c-7eb7-4101-a540-b12efc13903a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309925277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.3309925277
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.2124331277
Short name T519
Test name
Test status
Simulation time 9015091850 ps
CPU time 8.29 seconds
Started Jul 11 06:34:42 PM PDT 24
Finished Jul 11 06:34:51 PM PDT 24
Peak memory 232776 kb
Host smart-ae7a2a17-a583-48f9-8117-b9857a92f57a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124331277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.2124331277
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.2396503824
Short name T668
Test name
Test status
Simulation time 582394448 ps
CPU time 7.13 seconds
Started Jul 11 06:34:41 PM PDT 24
Finished Jul 11 06:34:50 PM PDT 24
Peak memory 232860 kb
Host smart-8da7a837-2529-4171-ab0b-e179bd48e03c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396503824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.2396503824
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.2168016832
Short name T120
Test name
Test status
Simulation time 250679957 ps
CPU time 3.46 seconds
Started Jul 11 06:34:41 PM PDT 24
Finished Jul 11 06:34:46 PM PDT 24
Peak memory 219776 kb
Host smart-bf777b94-b9d8-464c-a2d8-8c2c7b8ec270
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2168016832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.2168016832
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.2738198522
Short name T61
Test name
Test status
Simulation time 60504621 ps
CPU time 1.14 seconds
Started Jul 11 06:34:44 PM PDT 24
Finished Jul 11 06:34:47 PM PDT 24
Peak memory 235916 kb
Host smart-e41dbd0b-0ed9-4979-8270-8a69afe1a0a0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738198522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.2738198522
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.1759067123
Short name T986
Test name
Test status
Simulation time 5081790897 ps
CPU time 19.43 seconds
Started Jul 11 06:34:37 PM PDT 24
Finished Jul 11 06:34:58 PM PDT 24
Peak memory 216388 kb
Host smart-a4eaa775-e9e6-4f34-bba0-b510bea3683a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759067123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.1759067123
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.2621004188
Short name T352
Test name
Test status
Simulation time 649548266 ps
CPU time 3.12 seconds
Started Jul 11 06:34:36 PM PDT 24
Finished Jul 11 06:34:40 PM PDT 24
Peak memory 216160 kb
Host smart-f859aa21-7292-4ccc-a0c3-3b7eceaa567e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621004188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.2621004188
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.2363675447
Short name T386
Test name
Test status
Simulation time 46884139 ps
CPU time 1.4 seconds
Started Jul 11 06:34:35 PM PDT 24
Finished Jul 11 06:34:37 PM PDT 24
Peak memory 208020 kb
Host smart-04779ed7-6d56-47eb-8823-bac4bb754850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363675447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.2363675447
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.1640174301
Short name T6
Test name
Test status
Simulation time 113301874 ps
CPU time 0.81 seconds
Started Jul 11 06:34:38 PM PDT 24
Finished Jul 11 06:34:40 PM PDT 24
Peak memory 205980 kb
Host smart-bba784eb-7538-4540-994f-69af876af2a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640174301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.1640174301
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.3907531658
Short name T910
Test name
Test status
Simulation time 7458916889 ps
CPU time 18.86 seconds
Started Jul 11 06:34:42 PM PDT 24
Finished Jul 11 06:35:02 PM PDT 24
Peak memory 249072 kb
Host smart-871bc440-3d44-4156-bc03-0775f69b5a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907531658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.3907531658
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.2390914041
Short name T509
Test name
Test status
Simulation time 3002091401 ps
CPU time 4.57 seconds
Started Jul 11 06:36:01 PM PDT 24
Finished Jul 11 06:36:06 PM PDT 24
Peak memory 224660 kb
Host smart-844469d9-5ae6-4a3a-a2d6-8bf36c4267d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390914041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.2390914041
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.4259453307
Short name T512
Test name
Test status
Simulation time 28734201 ps
CPU time 0.79 seconds
Started Jul 11 06:35:48 PM PDT 24
Finished Jul 11 06:35:50 PM PDT 24
Peak memory 206644 kb
Host smart-5cc74891-7ace-48d1-a775-1bf50268f66b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259453307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.4259453307
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.2302909641
Short name T350
Test name
Test status
Simulation time 2690545158 ps
CPU time 19.67 seconds
Started Jul 11 06:35:58 PM PDT 24
Finished Jul 11 06:36:19 PM PDT 24
Peak memory 237660 kb
Host smart-906536f0-b52c-4b45-a2f7-858275547b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302909641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.2302909641
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.3136297765
Short name T524
Test name
Test status
Simulation time 33943823852 ps
CPU time 297.81 seconds
Started Jul 11 06:35:55 PM PDT 24
Finished Jul 11 06:40:54 PM PDT 24
Peak memory 256372 kb
Host smart-eedae080-9d5d-4d48-863b-b88965679228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136297765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.3136297765
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.951412437
Short name T361
Test name
Test status
Simulation time 12609125373 ps
CPU time 45.31 seconds
Started Jul 11 06:35:56 PM PDT 24
Finished Jul 11 06:36:43 PM PDT 24
Peak memory 249208 kb
Host smart-94f3e28f-b732-445f-a4b2-e527262031cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951412437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.951412437
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.3058978944
Short name T755
Test name
Test status
Simulation time 142814941570 ps
CPU time 250.76 seconds
Started Jul 11 06:35:56 PM PDT 24
Finished Jul 11 06:40:08 PM PDT 24
Peak memory 253732 kb
Host smart-4f5d92ae-421f-4820-9ea2-e9f081a08e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058978944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmd
s.3058978944
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.1885380635
Short name T185
Test name
Test status
Simulation time 3684255899 ps
CPU time 35.83 seconds
Started Jul 11 06:35:54 PM PDT 24
Finished Jul 11 06:36:31 PM PDT 24
Peak memory 224632 kb
Host smart-295b82d9-0cde-44eb-bfcc-d87ac986b09f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885380635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.1885380635
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.4277360551
Short name T859
Test name
Test status
Simulation time 193075075 ps
CPU time 3.69 seconds
Started Jul 11 06:35:54 PM PDT 24
Finished Jul 11 06:35:59 PM PDT 24
Peak memory 224512 kb
Host smart-4e2f834b-d7b1-42aa-89b3-5d3ae9c89bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277360551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.4277360551
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.24130875
Short name T614
Test name
Test status
Simulation time 7031163572 ps
CPU time 17.75 seconds
Started Jul 11 06:35:51 PM PDT 24
Finished Jul 11 06:36:10 PM PDT 24
Peak memory 224560 kb
Host smart-ae030e6e-d481-484b-9707-99dac3918623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24130875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swap.24130875
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.3254281480
Short name T905
Test name
Test status
Simulation time 4973794832 ps
CPU time 17.76 seconds
Started Jul 11 06:35:53 PM PDT 24
Finished Jul 11 06:36:12 PM PDT 24
Peak memory 232836 kb
Host smart-3167a8b8-84fe-4a68-b650-b9f5b8e34776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254281480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.3254281480
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.2318842109
Short name T601
Test name
Test status
Simulation time 2545242196 ps
CPU time 9.29 seconds
Started Jul 11 06:35:56 PM PDT 24
Finished Jul 11 06:36:06 PM PDT 24
Peak memory 220744 kb
Host smart-30e8a602-a368-4431-a207-c0f5b7f71ce5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2318842109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.2318842109
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.3898454993
Short name T143
Test name
Test status
Simulation time 12271963 ps
CPU time 0.7 seconds
Started Jul 11 06:35:51 PM PDT 24
Finished Jul 11 06:35:54 PM PDT 24
Peak memory 205732 kb
Host smart-5525114a-1413-4911-820c-466fadd77c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898454993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.3898454993
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.1048857873
Short name T308
Test name
Test status
Simulation time 941338805 ps
CPU time 2.29 seconds
Started Jul 11 06:35:52 PM PDT 24
Finished Jul 11 06:35:56 PM PDT 24
Peak memory 207096 kb
Host smart-b5767a6e-74a7-4950-9473-5914f1190153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048857873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.1048857873
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.63531182
Short name T47
Test name
Test status
Simulation time 319592250 ps
CPU time 1.85 seconds
Started Jul 11 06:35:51 PM PDT 24
Finished Jul 11 06:35:55 PM PDT 24
Peak memory 216264 kb
Host smart-b4120e61-794a-4e5b-8191-8208381c01bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63531182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.63531182
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.2743372829
Short name T935
Test name
Test status
Simulation time 38120167 ps
CPU time 0.9 seconds
Started Jul 11 06:35:50 PM PDT 24
Finished Jul 11 06:35:52 PM PDT 24
Peak memory 206368 kb
Host smart-0a66f850-294a-439a-bd8e-4d626596ef65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743372829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.2743372829
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.308818483
Short name T215
Test name
Test status
Simulation time 572132998 ps
CPU time 2.77 seconds
Started Jul 11 06:35:52 PM PDT 24
Finished Jul 11 06:35:56 PM PDT 24
Peak memory 240800 kb
Host smart-a889b7bc-cec9-4eb9-879c-b3db2ab7c52c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308818483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.308818483
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.292483571
Short name T354
Test name
Test status
Simulation time 68806471 ps
CPU time 0.68 seconds
Started Jul 11 06:36:11 PM PDT 24
Finished Jul 11 06:36:13 PM PDT 24
Peak memory 205472 kb
Host smart-d7cf5f46-4162-496a-81e3-d3b2a32e16f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292483571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.292483571
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.956396496
Short name T213
Test name
Test status
Simulation time 146839390 ps
CPU time 3.1 seconds
Started Jul 11 06:36:06 PM PDT 24
Finished Jul 11 06:36:10 PM PDT 24
Peak memory 232716 kb
Host smart-6ac036a1-7c2a-484d-b013-0af5b6301bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956396496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.956396496
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.1213442903
Short name T480
Test name
Test status
Simulation time 54150689 ps
CPU time 0.83 seconds
Started Jul 11 06:36:02 PM PDT 24
Finished Jul 11 06:36:03 PM PDT 24
Peak memory 205604 kb
Host smart-4c746520-07a7-46e4-a12d-3af5357d2d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213442903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.1213442903
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.3719227878
Short name T183
Test name
Test status
Simulation time 175510212477 ps
CPU time 122.39 seconds
Started Jul 11 06:36:07 PM PDT 24
Finished Jul 11 06:38:10 PM PDT 24
Peak memory 256664 kb
Host smart-050f0896-8608-48dd-b9ac-fafbb5d74cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719227878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.3719227878
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.525086154
Short name T608
Test name
Test status
Simulation time 1257221343 ps
CPU time 15.8 seconds
Started Jul 11 06:36:10 PM PDT 24
Finished Jul 11 06:36:27 PM PDT 24
Peak memory 217332 kb
Host smart-63db73d0-b957-49c4-8210-5c84f037a210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525086154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.525086154
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.4175907731
Short name T672
Test name
Test status
Simulation time 1440503870 ps
CPU time 5.45 seconds
Started Jul 11 06:36:13 PM PDT 24
Finished Jul 11 06:36:19 PM PDT 24
Peak memory 224500 kb
Host smart-4782ed68-9ebb-46b3-81b5-56d1868618a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175907731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.4175907731
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.1776753688
Short name T806
Test name
Test status
Simulation time 615265445 ps
CPU time 4.16 seconds
Started Jul 11 06:36:06 PM PDT 24
Finished Jul 11 06:36:11 PM PDT 24
Peak memory 224512 kb
Host smart-adc2b552-6ff1-4d1d-adfc-a7a383131fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776753688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.1776753688
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.2590566083
Short name T78
Test name
Test status
Simulation time 753510043 ps
CPU time 9.59 seconds
Started Jul 11 06:36:06 PM PDT 24
Finished Jul 11 06:36:17 PM PDT 24
Peak memory 234644 kb
Host smart-8cc30bf1-adcf-495b-b0fa-1dc4e69f0677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590566083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd
s.2590566083
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.1182286127
Short name T144
Test name
Test status
Simulation time 59247245 ps
CPU time 2.73 seconds
Started Jul 11 06:36:10 PM PDT 24
Finished Jul 11 06:36:13 PM PDT 24
Peak memory 232656 kb
Host smart-ac93bdbe-b584-4b97-8f7c-19682078522c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182286127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.1182286127
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.3185818810
Short name T96
Test name
Test status
Simulation time 432874176 ps
CPU time 9.74 seconds
Started Jul 11 06:36:06 PM PDT 24
Finished Jul 11 06:36:17 PM PDT 24
Peak memory 232732 kb
Host smart-2985f53e-dd91-4b56-846b-a06d1cde895e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185818810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.3185818810
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.3808794004
Short name T597
Test name
Test status
Simulation time 275688334 ps
CPU time 2.33 seconds
Started Jul 11 06:36:07 PM PDT 24
Finished Jul 11 06:36:10 PM PDT 24
Peak memory 224408 kb
Host smart-e4cdea2a-11e6-4607-a13b-8a17747b72bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808794004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.3808794004
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.4072447329
Short name T650
Test name
Test status
Simulation time 3705104737 ps
CPU time 10.73 seconds
Started Jul 11 06:36:11 PM PDT 24
Finished Jul 11 06:36:22 PM PDT 24
Peak memory 232744 kb
Host smart-a2d0a0a6-5975-4437-a383-e1ff649747aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072447329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.4072447329
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.1708281927
Short name T122
Test name
Test status
Simulation time 2640519699 ps
CPU time 9.37 seconds
Started Jul 11 06:36:05 PM PDT 24
Finished Jul 11 06:36:16 PM PDT 24
Peak memory 222080 kb
Host smart-de654e4e-c5a2-48c8-b34c-a9404850c26a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1708281927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.1708281927
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.3228516101
Short name T886
Test name
Test status
Simulation time 187139579591 ps
CPU time 704.37 seconds
Started Jul 11 06:36:12 PM PDT 24
Finished Jul 11 06:47:57 PM PDT 24
Peak memory 273712 kb
Host smart-913ab61e-1153-43d6-8752-5b983074cd58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228516101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.3228516101
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.1028225283
Short name T466
Test name
Test status
Simulation time 7571720593 ps
CPU time 16.16 seconds
Started Jul 11 06:36:02 PM PDT 24
Finished Jul 11 06:36:19 PM PDT 24
Peak memory 216436 kb
Host smart-c133dc89-f37b-4f0d-b9f8-a2270f4c32fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028225283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.1028225283
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.485417214
Short name T923
Test name
Test status
Simulation time 546060592 ps
CPU time 2.08 seconds
Started Jul 11 06:36:02 PM PDT 24
Finished Jul 11 06:36:04 PM PDT 24
Peak memory 207076 kb
Host smart-d1031d62-92f8-471c-acbb-703152db69c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485417214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.485417214
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.1082374791
Short name T319
Test name
Test status
Simulation time 56375874 ps
CPU time 1.11 seconds
Started Jul 11 06:36:05 PM PDT 24
Finished Jul 11 06:36:07 PM PDT 24
Peak memory 207096 kb
Host smart-ca1b89b8-d5f8-4f4e-b6f4-13413c085c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082374791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.1082374791
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.875023944
Short name T959
Test name
Test status
Simulation time 61653696 ps
CPU time 0.75 seconds
Started Jul 11 06:36:02 PM PDT 24
Finished Jul 11 06:36:04 PM PDT 24
Peak memory 206008 kb
Host smart-91d57bb5-8c07-46c7-b8c4-dfd792dcbc30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875023944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.875023944
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.3828600407
Short name T329
Test name
Test status
Simulation time 2277743826 ps
CPU time 7.76 seconds
Started Jul 11 06:36:10 PM PDT 24
Finished Jul 11 06:36:18 PM PDT 24
Peak memory 224508 kb
Host smart-6ab9593b-52c1-4ccb-8c13-a5f4a9084a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828600407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.3828600407
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.579022299
Short name T833
Test name
Test status
Simulation time 54422339 ps
CPU time 0.69 seconds
Started Jul 11 06:36:14 PM PDT 24
Finished Jul 11 06:36:15 PM PDT 24
Peak memory 205560 kb
Host smart-8fbdcb6e-0aa5-4bfe-8ee5-6479dd7b87ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579022299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.579022299
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.3236294376
Short name T73
Test name
Test status
Simulation time 132325808 ps
CPU time 2.5 seconds
Started Jul 11 06:36:16 PM PDT 24
Finished Jul 11 06:36:20 PM PDT 24
Peak memory 224460 kb
Host smart-7d41abff-7971-4f73-be4d-2ca0cfed1212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236294376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.3236294376
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.204700445
Short name T398
Test name
Test status
Simulation time 17130178 ps
CPU time 0.79 seconds
Started Jul 11 06:36:11 PM PDT 24
Finished Jul 11 06:36:12 PM PDT 24
Peak memory 205580 kb
Host smart-fb768dbb-1e2b-4267-91ad-021aef3f765d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204700445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.204700445
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.418874421
Short name T767
Test name
Test status
Simulation time 3798111029 ps
CPU time 19.87 seconds
Started Jul 11 06:36:15 PM PDT 24
Finished Jul 11 06:36:36 PM PDT 24
Peak memory 241332 kb
Host smart-9fdaef3e-b2b4-40f7-90fc-233bb8c915a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418874421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.418874421
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.3567212262
Short name T451
Test name
Test status
Simulation time 48295977103 ps
CPU time 229.52 seconds
Started Jul 11 06:36:16 PM PDT 24
Finished Jul 11 06:40:06 PM PDT 24
Peak memory 249288 kb
Host smart-916e244f-1603-44c1-bc05-06ef93fda84f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567212262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.3567212262
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.1060296252
Short name T201
Test name
Test status
Simulation time 15595158387 ps
CPU time 165.59 seconds
Started Jul 11 06:36:16 PM PDT 24
Finished Jul 11 06:39:03 PM PDT 24
Peak memory 252256 kb
Host smart-3c442a49-f0ff-47f3-a4ef-e830c458b140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060296252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.1060296252
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.2113427098
Short name T961
Test name
Test status
Simulation time 3622060764 ps
CPU time 44.18 seconds
Started Jul 11 06:36:16 PM PDT 24
Finished Jul 11 06:37:01 PM PDT 24
Peak memory 232824 kb
Host smart-4270c67b-9969-4b9a-8ccb-16424d758c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113427098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.2113427098
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.2459327806
Short name T261
Test name
Test status
Simulation time 16770536425 ps
CPU time 42.73 seconds
Started Jul 11 06:36:15 PM PDT 24
Finished Jul 11 06:36:58 PM PDT 24
Peak memory 253464 kb
Host smart-f1ec18de-8f48-4343-92ad-9dae5feff87b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459327806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmd
s.2459327806
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_intercept.929864070
Short name T630
Test name
Test status
Simulation time 3116379590 ps
CPU time 28.01 seconds
Started Jul 11 06:36:10 PM PDT 24
Finished Jul 11 06:36:39 PM PDT 24
Peak memory 224604 kb
Host smart-12886a7a-f4c1-4f5b-8e6c-593e85ce4b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929864070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.929864070
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.2978858933
Short name T878
Test name
Test status
Simulation time 1310410960 ps
CPU time 6.22 seconds
Started Jul 11 06:36:10 PM PDT 24
Finished Jul 11 06:36:17 PM PDT 24
Peak memory 232668 kb
Host smart-bab6e24f-9577-4d0d-8e47-ab493c5bb075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978858933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.2978858933
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.3612651582
Short name T199
Test name
Test status
Simulation time 1571904650 ps
CPU time 13.5 seconds
Started Jul 11 06:36:11 PM PDT 24
Finished Jul 11 06:36:26 PM PDT 24
Peak memory 232600 kb
Host smart-d532bf22-b8e2-4e4c-b32d-6282bd25f4e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612651582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.3612651582
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.2403349889
Short name T217
Test name
Test status
Simulation time 1175400153 ps
CPU time 3.96 seconds
Started Jul 11 06:36:10 PM PDT 24
Finished Jul 11 06:36:15 PM PDT 24
Peak memory 232616 kb
Host smart-22cde9ce-17bf-487f-9e15-1a317c8d7b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403349889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.2403349889
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.4254124454
Short name T381
Test name
Test status
Simulation time 1220560917 ps
CPU time 4.68 seconds
Started Jul 11 06:36:15 PM PDT 24
Finished Jul 11 06:36:21 PM PDT 24
Peak memory 220580 kb
Host smart-9d91dfa4-9e78-4b05-b921-1ad64d3e2148
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4254124454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.4254124454
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.3670786646
Short name T872
Test name
Test status
Simulation time 3311172297 ps
CPU time 13.56 seconds
Started Jul 11 06:36:10 PM PDT 24
Finished Jul 11 06:36:25 PM PDT 24
Peak memory 216544 kb
Host smart-f029a527-e580-47cb-920a-4a397dae9e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670786646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.3670786646
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.1671040088
Short name T724
Test name
Test status
Simulation time 1574092572 ps
CPU time 6.48 seconds
Started Jul 11 06:36:12 PM PDT 24
Finished Jul 11 06:36:20 PM PDT 24
Peak memory 216188 kb
Host smart-ff661abd-f12f-487a-82b5-37e6058a04d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671040088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.1671040088
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.1523339649
Short name T468
Test name
Test status
Simulation time 59252965 ps
CPU time 1.47 seconds
Started Jul 11 06:36:10 PM PDT 24
Finished Jul 11 06:36:13 PM PDT 24
Peak memory 216256 kb
Host smart-e5fdcc84-575a-4296-9f2d-77889dc4095b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523339649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.1523339649
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.3284995112
Short name T293
Test name
Test status
Simulation time 10702106 ps
CPU time 0.72 seconds
Started Jul 11 06:36:10 PM PDT 24
Finished Jul 11 06:36:12 PM PDT 24
Peak memory 205672 kb
Host smart-303e53ff-a428-4ac5-8c9f-36fca60ea5b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284995112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.3284995112
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.3682201578
Short name T374
Test name
Test status
Simulation time 6976040191 ps
CPU time 25.49 seconds
Started Jul 11 06:36:09 PM PDT 24
Finished Jul 11 06:36:35 PM PDT 24
Peak memory 232792 kb
Host smart-11164a64-5d07-4f69-9c8a-9b87943c7884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682201578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.3682201578
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.4139927713
Short name T789
Test name
Test status
Simulation time 12769229 ps
CPU time 0.73 seconds
Started Jul 11 06:36:31 PM PDT 24
Finished Jul 11 06:36:33 PM PDT 24
Peak memory 204944 kb
Host smart-fcbf2350-3a31-4bb2-89f2-19af28ac2dc6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139927713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
4139927713
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.1102557789
Short name T799
Test name
Test status
Simulation time 1978949709 ps
CPU time 7.76 seconds
Started Jul 11 06:36:27 PM PDT 24
Finished Jul 11 06:36:36 PM PDT 24
Peak memory 232884 kb
Host smart-9d14702f-a2c8-4c3b-86e7-b7f4c9db7cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102557789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.1102557789
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.2843850364
Short name T571
Test name
Test status
Simulation time 36884307 ps
CPU time 0.75 seconds
Started Jul 11 06:36:18 PM PDT 24
Finished Jul 11 06:36:20 PM PDT 24
Peak memory 205644 kb
Host smart-7a5b3fd4-89ca-4c21-a6a0-6f304168b100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843850364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.2843850364
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.1058779136
Short name T562
Test name
Test status
Simulation time 3581368396 ps
CPU time 91.42 seconds
Started Jul 11 06:36:29 PM PDT 24
Finished Jul 11 06:38:02 PM PDT 24
Peak memory 265584 kb
Host smart-2a88ccb1-ff95-4ca2-8cf7-cbb90a703710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058779136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.1058779136
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.1884668240
Short name T116
Test name
Test status
Simulation time 108601500991 ps
CPU time 284.43 seconds
Started Jul 11 06:36:29 PM PDT 24
Finished Jul 11 06:41:15 PM PDT 24
Peak memory 273628 kb
Host smart-b8cc2c43-5bd7-4449-9839-da4073b7f6c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884668240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.1884668240
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.1729671285
Short name T273
Test name
Test status
Simulation time 2272816852 ps
CPU time 22.62 seconds
Started Jul 11 06:36:25 PM PDT 24
Finished Jul 11 06:36:48 PM PDT 24
Peak memory 249168 kb
Host smart-487d9bcb-f0a7-44b9-855f-4fa28d8c7297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729671285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.1729671285
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.1059361677
Short name T218
Test name
Test status
Simulation time 236347036418 ps
CPU time 143.07 seconds
Started Jul 11 06:36:30 PM PDT 24
Finished Jul 11 06:38:55 PM PDT 24
Peak memory 255052 kb
Host smart-223cc1cf-78bd-4d67-84a0-6a82f2a70aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059361677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd
s.1059361677
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_intercept.3943289424
Short name T220
Test name
Test status
Simulation time 2033991730 ps
CPU time 17.22 seconds
Started Jul 11 06:36:24 PM PDT 24
Finished Jul 11 06:36:41 PM PDT 24
Peak memory 224404 kb
Host smart-2b33eeba-840b-49df-804d-e69b709e70b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943289424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.3943289424
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.2925671964
Short name T28
Test name
Test status
Simulation time 162861351865 ps
CPU time 190.42 seconds
Started Jul 11 06:36:23 PM PDT 24
Finished Jul 11 06:39:34 PM PDT 24
Peak memory 248424 kb
Host smart-9a23308b-ad2b-4d4b-b1c7-0bc427fe384a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925671964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.2925671964
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.1430312597
Short name T165
Test name
Test status
Simulation time 1023807545 ps
CPU time 6.89 seconds
Started Jul 11 06:36:25 PM PDT 24
Finished Jul 11 06:36:33 PM PDT 24
Peak memory 232720 kb
Host smart-12e1a98d-2beb-41d9-b0d3-8698cd3c5793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430312597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.1430312597
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.4001497146
Short name T223
Test name
Test status
Simulation time 5095123605 ps
CPU time 8.56 seconds
Started Jul 11 06:36:20 PM PDT 24
Finished Jul 11 06:36:29 PM PDT 24
Peak memory 224596 kb
Host smart-2915d472-aaf7-4f65-a40e-650e1ec54690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001497146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.4001497146
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.3741797552
Short name T335
Test name
Test status
Simulation time 189962550 ps
CPU time 4.43 seconds
Started Jul 11 06:36:24 PM PDT 24
Finished Jul 11 06:36:30 PM PDT 24
Peak memory 220304 kb
Host smart-701cfd50-5a3a-4d83-9626-4063d5a0d2e2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3741797552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.3741797552
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.2077767883
Short name T115
Test name
Test status
Simulation time 290874619166 ps
CPU time 741.11 seconds
Started Jul 11 06:36:29 PM PDT 24
Finished Jul 11 06:48:52 PM PDT 24
Peak memory 287892 kb
Host smart-a210e7b8-3db6-49e4-bdad-2569b685a4a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077767883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.2077767883
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.2343478020
Short name T652
Test name
Test status
Simulation time 1607671092 ps
CPU time 18.31 seconds
Started Jul 11 06:36:25 PM PDT 24
Finished Jul 11 06:36:45 PM PDT 24
Peak memory 216232 kb
Host smart-f966b422-b662-4dcc-8e9b-4da4fc8bdeb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343478020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.2343478020
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.439395097
Short name T593
Test name
Test status
Simulation time 9518235663 ps
CPU time 5.84 seconds
Started Jul 11 06:36:20 PM PDT 24
Finished Jul 11 06:36:27 PM PDT 24
Peak memory 216344 kb
Host smart-0e96baa9-8b04-4e62-b56c-1c9af53b9d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439395097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.439395097
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.4139995700
Short name T781
Test name
Test status
Simulation time 1063687190 ps
CPU time 5.02 seconds
Started Jul 11 06:36:19 PM PDT 24
Finished Jul 11 06:36:25 PM PDT 24
Peak memory 216216 kb
Host smart-7e1a007c-89ab-4546-83f7-444639cb8d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139995700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.4139995700
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.4210775894
Short name T332
Test name
Test status
Simulation time 77546323 ps
CPU time 0.84 seconds
Started Jul 11 06:36:19 PM PDT 24
Finished Jul 11 06:36:21 PM PDT 24
Peak memory 205932 kb
Host smart-e9042d40-9cbf-463f-9931-dc0f1aa7d13a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210775894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.4210775894
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.3866128065
Short name T432
Test name
Test status
Simulation time 17183870177 ps
CPU time 7.64 seconds
Started Jul 11 06:36:23 PM PDT 24
Finished Jul 11 06:36:32 PM PDT 24
Peak memory 232872 kb
Host smart-5d76ac05-0ac9-45c2-92e5-8ab04fffd5e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866128065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.3866128065
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.1383383441
Short name T933
Test name
Test status
Simulation time 16486189 ps
CPU time 0.73 seconds
Started Jul 11 06:36:38 PM PDT 24
Finished Jul 11 06:36:39 PM PDT 24
Peak memory 204964 kb
Host smart-80cec9e8-c404-4ad6-a2b6-bfb765e46ecf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383383441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
1383383441
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.2836535506
Short name T927
Test name
Test status
Simulation time 1058448791 ps
CPU time 2.36 seconds
Started Jul 11 06:36:29 PM PDT 24
Finished Jul 11 06:36:33 PM PDT 24
Peak memory 224468 kb
Host smart-1e5694b2-1d55-4fe3-adc7-0e32b3f90b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836535506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.2836535506
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.260831516
Short name T55
Test name
Test status
Simulation time 37134452 ps
CPU time 0.81 seconds
Started Jul 11 06:36:29 PM PDT 24
Finished Jul 11 06:36:32 PM PDT 24
Peak memory 206636 kb
Host smart-d3d9f93d-6f68-4479-a388-c0582ee7e8f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260831516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.260831516
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.578076107
Short name T963
Test name
Test status
Simulation time 3497536270 ps
CPU time 43.82 seconds
Started Jul 11 06:36:34 PM PDT 24
Finished Jul 11 06:37:19 PM PDT 24
Peak memory 241044 kb
Host smart-e6a9010f-1582-44b0-8931-21cdedb8e947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578076107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.578076107
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.128739019
Short name T726
Test name
Test status
Simulation time 8706355284 ps
CPU time 87.64 seconds
Started Jul 11 06:36:34 PM PDT 24
Finished Jul 11 06:38:03 PM PDT 24
Peak memory 265904 kb
Host smart-329f70b1-1451-4e97-8864-65719a82c7c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128739019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.128739019
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.1292713759
Short name T70
Test name
Test status
Simulation time 12222779551 ps
CPU time 29.77 seconds
Started Jul 11 06:36:34 PM PDT 24
Finished Jul 11 06:37:05 PM PDT 24
Peak memory 238576 kb
Host smart-5b07066f-8ad9-4413-85a3-3b0049681bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292713759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.1292713759
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.2695741475
Short name T270
Test name
Test status
Simulation time 887237503 ps
CPU time 18.47 seconds
Started Jul 11 06:36:35 PM PDT 24
Finished Jul 11 06:36:54 PM PDT 24
Peak memory 232672 kb
Host smart-234281d4-04a1-4a6b-8e2e-08760a034a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695741475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.2695741475
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.3664282854
Short name T720
Test name
Test status
Simulation time 72662345049 ps
CPU time 519.13 seconds
Started Jul 11 06:36:34 PM PDT 24
Finished Jul 11 06:45:14 PM PDT 24
Peak memory 265044 kb
Host smart-122e8953-5c40-4d38-b7bd-65910956c79e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664282854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmd
s.3664282854
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_intercept.3693942563
Short name T533
Test name
Test status
Simulation time 802419482 ps
CPU time 4.45 seconds
Started Jul 11 06:36:28 PM PDT 24
Finished Jul 11 06:36:34 PM PDT 24
Peak memory 232652 kb
Host smart-b0eb6c4b-b37a-431c-8b90-e7350c7f879e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693942563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.3693942563
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.559074669
Short name T609
Test name
Test status
Simulation time 197071626 ps
CPU time 2.25 seconds
Started Jul 11 06:36:29 PM PDT 24
Finished Jul 11 06:36:32 PM PDT 24
Peak memory 223020 kb
Host smart-5a516b5c-748f-4e98-a185-14f9191609a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559074669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.559074669
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.2070963590
Short name T794
Test name
Test status
Simulation time 415155947 ps
CPU time 3.77 seconds
Started Jul 11 06:36:29 PM PDT 24
Finished Jul 11 06:36:34 PM PDT 24
Peak memory 232660 kb
Host smart-75e151f5-e4a5-42a5-bbea-aa905071dff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070963590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.2070963590
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.1005364483
Short name T355
Test name
Test status
Simulation time 3165641962 ps
CPU time 8.48 seconds
Started Jul 11 06:36:33 PM PDT 24
Finished Jul 11 06:36:43 PM PDT 24
Peak memory 224596 kb
Host smart-139a3314-5c82-42ee-a16d-b5d731e0b65f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005364483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.1005364483
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.2481958267
Short name T885
Test name
Test status
Simulation time 160403430 ps
CPU time 3.54 seconds
Started Jul 11 06:36:33 PM PDT 24
Finished Jul 11 06:36:37 PM PDT 24
Peak memory 223260 kb
Host smart-71730d3a-974d-4f63-b292-2decef5ec968
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2481958267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.2481958267
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.3621460370
Short name T240
Test name
Test status
Simulation time 54913965030 ps
CPU time 168.03 seconds
Started Jul 11 06:36:34 PM PDT 24
Finished Jul 11 06:39:23 PM PDT 24
Peak memory 270216 kb
Host smart-165070b9-6810-4ea9-9947-806b61db610d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621460370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.3621460370
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.4206287250
Short name T539
Test name
Test status
Simulation time 1427451806 ps
CPU time 19.69 seconds
Started Jul 11 06:36:28 PM PDT 24
Finished Jul 11 06:36:50 PM PDT 24
Peak memory 216212 kb
Host smart-a40f7f7a-c95d-4aa1-aa02-85ada470459a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206287250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.4206287250
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.2201303756
Short name T980
Test name
Test status
Simulation time 1253058546 ps
CPU time 4.53 seconds
Started Jul 11 06:36:33 PM PDT 24
Finished Jul 11 06:36:38 PM PDT 24
Peak memory 216288 kb
Host smart-eed625c2-9796-46ca-9452-0f50cae659ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201303756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.2201303756
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.527818494
Short name T327
Test name
Test status
Simulation time 197985669 ps
CPU time 4.86 seconds
Started Jul 11 06:36:30 PM PDT 24
Finished Jul 11 06:36:37 PM PDT 24
Peak memory 216272 kb
Host smart-e8ae40f4-9d77-467f-a2c1-bd4a352a5d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527818494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.527818494
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.3406074134
Short name T328
Test name
Test status
Simulation time 88363185 ps
CPU time 0.75 seconds
Started Jul 11 06:36:29 PM PDT 24
Finished Jul 11 06:36:32 PM PDT 24
Peak memory 206092 kb
Host smart-783f9af2-4df0-44bf-a4e4-14647bd7d845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406074134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.3406074134
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.3366900722
Short name T949
Test name
Test status
Simulation time 116766903982 ps
CPU time 40.61 seconds
Started Jul 11 06:36:29 PM PDT 24
Finished Jul 11 06:37:11 PM PDT 24
Peak memory 233800 kb
Host smart-350a1449-5a8b-40fd-8958-96212ca17c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366900722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.3366900722
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.4019293276
Short name T523
Test name
Test status
Simulation time 12472226 ps
CPU time 0.73 seconds
Started Jul 11 06:36:47 PM PDT 24
Finished Jul 11 06:36:49 PM PDT 24
Peak memory 204964 kb
Host smart-2fc98eb9-5ec7-4da0-b98d-f5f8175186cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019293276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
4019293276
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.3979005934
Short name T783
Test name
Test status
Simulation time 3604513851 ps
CPU time 10.46 seconds
Started Jul 11 06:36:45 PM PDT 24
Finished Jul 11 06:36:56 PM PDT 24
Peak memory 232980 kb
Host smart-81490a3c-0f99-4422-ada8-861ede6f6ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979005934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.3979005934
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.521082762
Short name T684
Test name
Test status
Simulation time 13738820 ps
CPU time 0.72 seconds
Started Jul 11 06:36:39 PM PDT 24
Finished Jul 11 06:36:41 PM PDT 24
Peak memory 205928 kb
Host smart-db0e3bd6-2e20-45a8-a725-923fc469de77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521082762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.521082762
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.3934037937
Short name T573
Test name
Test status
Simulation time 11854772644 ps
CPU time 69.69 seconds
Started Jul 11 06:36:56 PM PDT 24
Finished Jul 11 06:38:07 PM PDT 24
Peak memory 232772 kb
Host smart-ec255273-9338-4488-9917-4d75da269196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934037937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.3934037937
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.265477760
Short name T478
Test name
Test status
Simulation time 87795077016 ps
CPU time 208.58 seconds
Started Jul 11 06:36:56 PM PDT 24
Finished Jul 11 06:40:25 PM PDT 24
Peak memory 249232 kb
Host smart-38454351-3122-4217-a008-0daf4d56c7c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265477760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.265477760
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.127154240
Short name T857
Test name
Test status
Simulation time 66995380269 ps
CPU time 300.12 seconds
Started Jul 11 06:36:50 PM PDT 24
Finished Jul 11 06:41:51 PM PDT 24
Peak memory 250236 kb
Host smart-32eefccc-ef6e-47ba-aaa7-851fc439942e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127154240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idle
.127154240
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.1862912358
Short name T943
Test name
Test status
Simulation time 141277762 ps
CPU time 4.59 seconds
Started Jul 11 06:36:42 PM PDT 24
Finished Jul 11 06:36:47 PM PDT 24
Peak memory 232628 kb
Host smart-753aebe5-1244-473b-befd-15b94eaa7a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862912358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.1862912358
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.1740979466
Short name T371
Test name
Test status
Simulation time 101068309147 ps
CPU time 140.71 seconds
Started Jul 11 06:36:45 PM PDT 24
Finished Jul 11 06:39:06 PM PDT 24
Peak memory 253752 kb
Host smart-05a28835-364c-4b7b-a48c-b44622d64aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740979466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmd
s.1740979466
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.2216761700
Short name T461
Test name
Test status
Simulation time 653727221 ps
CPU time 3.2 seconds
Started Jul 11 06:36:43 PM PDT 24
Finished Jul 11 06:36:47 PM PDT 24
Peak memory 232676 kb
Host smart-01743f55-2e63-4a95-a02b-d105138a12bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216761700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.2216761700
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.3642203086
Short name T429
Test name
Test status
Simulation time 11329533798 ps
CPU time 13.6 seconds
Started Jul 11 06:36:44 PM PDT 24
Finished Jul 11 06:36:58 PM PDT 24
Peak memory 233812 kb
Host smart-9c7344e6-6f85-45fa-a87f-0181b1545ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642203086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.3642203086
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.3381697920
Short name T511
Test name
Test status
Simulation time 10353412424 ps
CPU time 26.9 seconds
Started Jul 11 06:36:56 PM PDT 24
Finished Jul 11 06:37:24 PM PDT 24
Peak memory 232800 kb
Host smart-ff094984-8e04-4f23-b284-fff213206fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381697920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.3381697920
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.933004648
Short name T353
Test name
Test status
Simulation time 8181615480 ps
CPU time 12.91 seconds
Started Jul 11 06:36:37 PM PDT 24
Finished Jul 11 06:36:51 PM PDT 24
Peak memory 232772 kb
Host smart-d6709de5-c3d1-4910-bb78-bf4cfb7fe20a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933004648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.933004648
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.1781227431
Short name T706
Test name
Test status
Simulation time 1667535463 ps
CPU time 8.24 seconds
Started Jul 11 06:36:41 PM PDT 24
Finished Jul 11 06:36:50 PM PDT 24
Peak memory 222184 kb
Host smart-cbd282c6-e4ce-44a6-bd18-a01f32cb821b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1781227431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.1781227431
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.128651557
Short name T812
Test name
Test status
Simulation time 163186212 ps
CPU time 0.92 seconds
Started Jul 11 06:36:48 PM PDT 24
Finished Jul 11 06:36:49 PM PDT 24
Peak memory 206764 kb
Host smart-5c614a89-e0ef-4474-8a32-df5a38c77111
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128651557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stres
s_all.128651557
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.366546540
Short name T299
Test name
Test status
Simulation time 42338065 ps
CPU time 0.74 seconds
Started Jul 11 06:36:38 PM PDT 24
Finished Jul 11 06:36:39 PM PDT 24
Peak memory 206072 kb
Host smart-1032f27d-8356-49eb-83dd-1fa1d1d32cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366546540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.366546540
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.4125822780
Short name T590
Test name
Test status
Simulation time 278053290 ps
CPU time 1.12 seconds
Started Jul 11 06:36:35 PM PDT 24
Finished Jul 11 06:36:37 PM PDT 24
Peak memory 207884 kb
Host smart-7828c8fb-0272-4212-aea3-a74351e9fb3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125822780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.4125822780
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.1506486630
Short name T940
Test name
Test status
Simulation time 115210464 ps
CPU time 1.06 seconds
Started Jul 11 06:36:38 PM PDT 24
Finished Jul 11 06:36:40 PM PDT 24
Peak memory 207924 kb
Host smart-af96892a-8d1c-484b-9bcc-87c3bfaaba7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506486630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.1506486630
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.1751128709
Short name T71
Test name
Test status
Simulation time 33983981 ps
CPU time 0.8 seconds
Started Jul 11 06:36:39 PM PDT 24
Finished Jul 11 06:36:41 PM PDT 24
Peak memory 206000 kb
Host smart-3ae351bc-5e79-4e6d-9f50-3490fcdd3ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751128709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.1751128709
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.3707787107
Short name T221
Test name
Test status
Simulation time 4710743334 ps
CPU time 8.39 seconds
Started Jul 11 06:36:43 PM PDT 24
Finished Jul 11 06:36:53 PM PDT 24
Peak memory 224732 kb
Host smart-6d323fb8-daa1-4308-af02-95d90d7b81d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707787107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.3707787107
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.3942788890
Short name T581
Test name
Test status
Simulation time 38957675 ps
CPU time 0.73 seconds
Started Jul 11 06:36:50 PM PDT 24
Finished Jul 11 06:36:52 PM PDT 24
Peak memory 205860 kb
Host smart-f4546bcd-8311-42f7-8fee-f6eba6e8c05c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942788890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
3942788890
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.3721496853
Short name T653
Test name
Test status
Simulation time 3148141394 ps
CPU time 9.22 seconds
Started Jul 11 06:36:51 PM PDT 24
Finished Jul 11 06:37:02 PM PDT 24
Peak memory 232800 kb
Host smart-c8bdbf12-1810-4f57-83a7-8aa709ef7816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721496853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.3721496853
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.1258403255
Short name T431
Test name
Test status
Simulation time 55841805 ps
CPU time 0.77 seconds
Started Jul 11 06:36:47 PM PDT 24
Finished Jul 11 06:36:48 PM PDT 24
Peak memory 205600 kb
Host smart-82dd74f0-853e-46e7-82ae-1fe8f7a8c7fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258403255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.1258403255
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.2455153718
Short name T163
Test name
Test status
Simulation time 18267281849 ps
CPU time 179.5 seconds
Started Jul 11 06:36:50 PM PDT 24
Finished Jul 11 06:39:51 PM PDT 24
Peak memory 265632 kb
Host smart-53e9e715-ddba-4455-b17e-14d88f9fff3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455153718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.2455153718
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.2965630203
Short name T917
Test name
Test status
Simulation time 47701902856 ps
CPU time 434.21 seconds
Started Jul 11 06:36:53 PM PDT 24
Finished Jul 11 06:44:08 PM PDT 24
Peak memory 265668 kb
Host smart-b72bdb75-fef6-45db-8ddc-ac9393e47544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965630203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.2965630203
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.1587994599
Short name T41
Test name
Test status
Simulation time 4438884146 ps
CPU time 85.35 seconds
Started Jul 11 06:36:51 PM PDT 24
Finished Jul 11 06:38:18 PM PDT 24
Peak memory 257436 kb
Host smart-23a9a97f-bd6e-403a-a879-d95f23841b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587994599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.1587994599
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.4200956354
Short name T816
Test name
Test status
Simulation time 12631239750 ps
CPU time 35.56 seconds
Started Jul 11 06:36:57 PM PDT 24
Finished Jul 11 06:37:34 PM PDT 24
Peak memory 224168 kb
Host smart-2e00be58-3a43-431d-a7ac-bafd6261b3cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200956354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.4200956354
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.422291835
Short name T249
Test name
Test status
Simulation time 100720313804 ps
CPU time 167.54 seconds
Started Jul 11 06:36:51 PM PDT 24
Finished Jul 11 06:39:40 PM PDT 24
Peak memory 254240 kb
Host smart-cb065ade-93d5-4af7-830e-35ea3cbbe65c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422291835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmds
.422291835
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.2247257695
Short name T845
Test name
Test status
Simulation time 2729152107 ps
CPU time 26.61 seconds
Started Jul 11 06:36:57 PM PDT 24
Finished Jul 11 06:37:25 PM PDT 24
Peak memory 232348 kb
Host smart-5eef9cb8-323a-4ba1-92e7-c0d7959ec099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247257695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.2247257695
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.3379499330
Short name T925
Test name
Test status
Simulation time 976541362 ps
CPU time 21.09 seconds
Started Jul 11 06:36:53 PM PDT 24
Finished Jul 11 06:37:15 PM PDT 24
Peak memory 232644 kb
Host smart-45c61ac6-d3cd-4eef-b391-5f8641dcb97d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379499330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.3379499330
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.4106082341
Short name T234
Test name
Test status
Simulation time 5527375837 ps
CPU time 7.02 seconds
Started Jul 11 06:36:53 PM PDT 24
Finished Jul 11 06:37:01 PM PDT 24
Peak memory 232724 kb
Host smart-1eb9359f-96ca-4956-9180-9d485fdbcb43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106082341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.4106082341
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.64615990
Short name T446
Test name
Test status
Simulation time 1348203033 ps
CPU time 4.57 seconds
Started Jul 11 06:36:50 PM PDT 24
Finished Jul 11 06:36:56 PM PDT 24
Peak memory 224496 kb
Host smart-93ff53a9-d0a4-4102-ae55-9a0d2d5f00b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64615990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.64615990
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.2404499185
Short name T957
Test name
Test status
Simulation time 785914415 ps
CPU time 8.89 seconds
Started Jul 11 06:36:53 PM PDT 24
Finished Jul 11 06:37:03 PM PDT 24
Peak memory 223092 kb
Host smart-2f55813e-06ad-4ee7-a270-177de60c83c3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2404499185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.2404499185
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.227011273
Short name T16
Test name
Test status
Simulation time 37084977027 ps
CPU time 41.73 seconds
Started Jul 11 06:36:52 PM PDT 24
Finished Jul 11 06:37:35 PM PDT 24
Peak memory 224580 kb
Host smart-b6268b0c-73b6-41c0-8037-820a68fd347e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227011273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stres
s_all.227011273
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.3658201697
Short name T773
Test name
Test status
Simulation time 112304459 ps
CPU time 0.72 seconds
Started Jul 11 06:36:46 PM PDT 24
Finished Jul 11 06:36:47 PM PDT 24
Peak memory 205816 kb
Host smart-61b1f2cb-aadb-466b-bde1-7dda271a551a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658201697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.3658201697
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.2172047195
Short name T903
Test name
Test status
Simulation time 754142175 ps
CPU time 3.57 seconds
Started Jul 11 06:36:45 PM PDT 24
Finished Jul 11 06:36:50 PM PDT 24
Peak memory 216248 kb
Host smart-77d2bf71-93d7-41fb-810a-8fdbce14d109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172047195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.2172047195
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.1110874651
Short name T786
Test name
Test status
Simulation time 10624826 ps
CPU time 0.7 seconds
Started Jul 11 06:36:57 PM PDT 24
Finished Jul 11 06:36:59 PM PDT 24
Peak memory 205608 kb
Host smart-d1caaa48-cea0-429a-bbf2-6462ecb2c30f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110874651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.1110874651
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.1592878838
Short name T324
Test name
Test status
Simulation time 48486596 ps
CPU time 0.78 seconds
Started Jul 11 06:36:50 PM PDT 24
Finished Jul 11 06:36:52 PM PDT 24
Peak memory 205964 kb
Host smart-882ff8d9-8921-4bb3-a01b-73bde56b8537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592878838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.1592878838
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.1526039777
Short name T909
Test name
Test status
Simulation time 622631625 ps
CPU time 2.68 seconds
Started Jul 11 06:36:53 PM PDT 24
Finished Jul 11 06:36:56 PM PDT 24
Peak memory 224472 kb
Host smart-6485010e-8823-4564-90c7-f27067631607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526039777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.1526039777
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.1744797494
Short name T27
Test name
Test status
Simulation time 11644236 ps
CPU time 0.73 seconds
Started Jul 11 06:37:04 PM PDT 24
Finished Jul 11 06:37:05 PM PDT 24
Peak memory 205492 kb
Host smart-9ebd76c2-a9dc-4815-9362-2900ba0f6041
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744797494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
1744797494
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.2246589096
Short name T307
Test name
Test status
Simulation time 535800554 ps
CPU time 7.65 seconds
Started Jul 11 06:36:59 PM PDT 24
Finished Jul 11 06:37:07 PM PDT 24
Peak memory 232604 kb
Host smart-557306a6-90df-4cfc-a407-be897b1b6fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246589096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.2246589096
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.1043040758
Short name T856
Test name
Test status
Simulation time 43135194 ps
CPU time 0.77 seconds
Started Jul 11 06:36:56 PM PDT 24
Finished Jul 11 06:36:58 PM PDT 24
Peak memory 206636 kb
Host smart-3677f2d2-f64c-4ffe-8851-d161a0c4ba79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043040758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.1043040758
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.947008611
Short name T210
Test name
Test status
Simulation time 69430018808 ps
CPU time 241.47 seconds
Started Jul 11 06:37:01 PM PDT 24
Finished Jul 11 06:41:03 PM PDT 24
Peak memory 257404 kb
Host smart-8917c65b-ba3a-4f64-af41-7d61c54e7970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947008611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.947008611
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.3995347031
Short name T114
Test name
Test status
Simulation time 37616603428 ps
CPU time 343.77 seconds
Started Jul 11 06:37:06 PM PDT 24
Finished Jul 11 06:42:51 PM PDT 24
Peak memory 249704 kb
Host smart-f6889d74-3a1d-4f62-964d-cc0c5b06b117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995347031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.3995347031
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.3842607232
Short name T255
Test name
Test status
Simulation time 245038519069 ps
CPU time 155.98 seconds
Started Jul 11 06:37:00 PM PDT 24
Finished Jul 11 06:39:37 PM PDT 24
Peak memory 251388 kb
Host smart-83ffe80e-b386-4b61-9249-5df5f8c48bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842607232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.3842607232
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.804422867
Short name T750
Test name
Test status
Simulation time 1150001000 ps
CPU time 6.13 seconds
Started Jul 11 06:37:01 PM PDT 24
Finished Jul 11 06:37:08 PM PDT 24
Peak memory 240912 kb
Host smart-431a4f1f-c4ff-4f6c-983b-01fb51deb3eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804422867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.804422867
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.1608155021
Short name T991
Test name
Test status
Simulation time 199952331 ps
CPU time 4.95 seconds
Started Jul 11 06:36:55 PM PDT 24
Finished Jul 11 06:37:01 PM PDT 24
Peak memory 224476 kb
Host smart-70cb8005-97d7-4117-afbe-4b4615212200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608155021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.1608155021
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.1378367969
Short name T690
Test name
Test status
Simulation time 2044406190 ps
CPU time 28.6 seconds
Started Jul 11 06:36:54 PM PDT 24
Finished Jul 11 06:37:23 PM PDT 24
Peak memory 224444 kb
Host smart-867966b9-1a98-49c3-8821-3eefd087b41a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378367969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.1378367969
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.1411873066
Short name T918
Test name
Test status
Simulation time 7489414864 ps
CPU time 18.7 seconds
Started Jul 11 06:36:55 PM PDT 24
Finished Jul 11 06:37:15 PM PDT 24
Peak memory 232784 kb
Host smart-c6e8d44b-d3af-49b8-a96b-911c44423a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411873066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.1411873066
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.3661703161
Short name T932
Test name
Test status
Simulation time 745878862 ps
CPU time 3.11 seconds
Started Jul 11 06:36:56 PM PDT 24
Finished Jul 11 06:37:00 PM PDT 24
Peak memory 232664 kb
Host smart-75e32081-fce5-4b5b-9310-6f3ebc6b3d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661703161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.3661703161
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.3075605950
Short name T125
Test name
Test status
Simulation time 196404551 ps
CPU time 4.6 seconds
Started Jul 11 06:36:59 PM PDT 24
Finished Jul 11 06:37:05 PM PDT 24
Peak memory 219440 kb
Host smart-39915bf8-e078-4485-9d8d-92081a159594
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3075605950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.3075605950
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.2564253580
Short name T34
Test name
Test status
Simulation time 152346569061 ps
CPU time 400.72 seconds
Started Jul 11 06:37:04 PM PDT 24
Finished Jul 11 06:43:45 PM PDT 24
Peak memory 268156 kb
Host smart-7243ea48-e788-4696-b5d9-20beea82d156
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564253580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.2564253580
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.3706730552
Short name T280
Test name
Test status
Simulation time 6663312734 ps
CPU time 10.78 seconds
Started Jul 11 06:37:00 PM PDT 24
Finished Jul 11 06:37:12 PM PDT 24
Peak memory 216276 kb
Host smart-e9ec7b4a-51ee-4a1d-b018-8b989fc0c454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706730552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.3706730552
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.55775596
Short name T356
Test name
Test status
Simulation time 13284408761 ps
CPU time 21.66 seconds
Started Jul 11 06:37:12 PM PDT 24
Finished Jul 11 06:37:35 PM PDT 24
Peak memory 216340 kb
Host smart-84332c87-05f4-4450-868d-abdac74e912b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55775596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.55775596
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.2361022230
Short name T336
Test name
Test status
Simulation time 792476223 ps
CPU time 2.33 seconds
Started Jul 11 06:36:54 PM PDT 24
Finished Jul 11 06:36:57 PM PDT 24
Peak memory 216200 kb
Host smart-e2532233-f86a-4110-961e-3e79c3c3d5f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361022230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.2361022230
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.3055674125
Short name T823
Test name
Test status
Simulation time 604846366 ps
CPU time 0.89 seconds
Started Jul 11 06:36:57 PM PDT 24
Finished Jul 11 06:36:59 PM PDT 24
Peak memory 207024 kb
Host smart-57433d4f-26c3-45e2-951f-29a885013d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055674125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.3055674125
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.2180893965
Short name T632
Test name
Test status
Simulation time 5002190140 ps
CPU time 20.24 seconds
Started Jul 11 06:36:56 PM PDT 24
Finished Jul 11 06:37:17 PM PDT 24
Peak memory 232860 kb
Host smart-0a2ab65c-8468-434e-a954-e2840a1df14c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180893965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.2180893965
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.3089557852
Short name T379
Test name
Test status
Simulation time 42158777 ps
CPU time 0.72 seconds
Started Jul 11 06:37:12 PM PDT 24
Finished Jul 11 06:37:14 PM PDT 24
Peak memory 205840 kb
Host smart-bd1ee3ee-2591-4917-b245-d91fa228b661
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089557852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
3089557852
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.2447339909
Short name T719
Test name
Test status
Simulation time 5591191167 ps
CPU time 14.8 seconds
Started Jul 11 06:37:08 PM PDT 24
Finished Jul 11 06:37:24 PM PDT 24
Peak memory 232788 kb
Host smart-d6362851-3a15-4f7c-a09d-df2650a3733b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447339909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.2447339909
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.3844446002
Short name T660
Test name
Test status
Simulation time 48567263 ps
CPU time 0.75 seconds
Started Jul 11 06:37:06 PM PDT 24
Finished Jul 11 06:37:08 PM PDT 24
Peak memory 205344 kb
Host smart-59244cb8-509a-43b4-ae1b-d7fc14a5eb1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844446002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.3844446002
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.64743682
Short name T516
Test name
Test status
Simulation time 90659269381 ps
CPU time 169.9 seconds
Started Jul 11 06:37:10 PM PDT 24
Finished Jul 11 06:40:01 PM PDT 24
Peak memory 249160 kb
Host smart-f03b84c5-bd59-42c9-aca7-2d352fbab989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64743682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.64743682
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.3872656039
Short name T232
Test name
Test status
Simulation time 71638745756 ps
CPU time 239.54 seconds
Started Jul 11 06:37:10 PM PDT 24
Finished Jul 11 06:41:11 PM PDT 24
Peak memory 257444 kb
Host smart-6261710f-1a99-4535-8c40-132302d6206c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872656039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.3872656039
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.1517315084
Short name T205
Test name
Test status
Simulation time 12131075364 ps
CPU time 100.33 seconds
Started Jul 11 06:37:10 PM PDT 24
Finished Jul 11 06:38:51 PM PDT 24
Peak memory 265424 kb
Host smart-e3609920-d14b-4afc-8264-a405059b8436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517315084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.1517315084
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.2588110559
Short name T707
Test name
Test status
Simulation time 2476021675 ps
CPU time 10.77 seconds
Started Jul 11 06:37:08 PM PDT 24
Finished Jul 11 06:37:20 PM PDT 24
Peak memory 232840 kb
Host smart-e16f621c-cbb4-4b8a-a32f-0e30c2f563b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588110559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.2588110559
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.620717337
Short name T657
Test name
Test status
Simulation time 47773727479 ps
CPU time 99.49 seconds
Started Jul 11 06:37:10 PM PDT 24
Finished Jul 11 06:38:50 PM PDT 24
Peak memory 255984 kb
Host smart-b4282f31-f7be-4ce9-a760-96637ddd0e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620717337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmds
.620717337
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_intercept.129757220
Short name T320
Test name
Test status
Simulation time 957183824 ps
CPU time 12.58 seconds
Started Jul 11 06:37:09 PM PDT 24
Finished Jul 11 06:37:22 PM PDT 24
Peak memory 224460 kb
Host smart-fe18112f-df7b-4cb2-bff1-3d3fe4c798e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129757220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.129757220
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.2260459222
Short name T576
Test name
Test status
Simulation time 14106183691 ps
CPU time 117.3 seconds
Started Jul 11 06:37:11 PM PDT 24
Finished Jul 11 06:39:10 PM PDT 24
Peak memory 238896 kb
Host smart-9cd94439-6ed0-42ff-8750-df03cc7ecf2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260459222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.2260459222
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.2723946625
Short name T624
Test name
Test status
Simulation time 678682874 ps
CPU time 10.74 seconds
Started Jul 11 06:37:18 PM PDT 24
Finished Jul 11 06:37:30 PM PDT 24
Peak memory 232704 kb
Host smart-44f3d05f-7d88-4d18-9f32-19e09fadc37a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723946625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.2723946625
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.4181593769
Short name T926
Test name
Test status
Simulation time 1012271001 ps
CPU time 8.07 seconds
Started Jul 11 06:37:18 PM PDT 24
Finished Jul 11 06:37:28 PM PDT 24
Peak memory 224516 kb
Host smart-2e0825e8-2176-4a7e-bb7b-d8e29753d7ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181593769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.4181593769
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.3702693582
Short name T574
Test name
Test status
Simulation time 1464065833 ps
CPU time 14.51 seconds
Started Jul 11 06:37:18 PM PDT 24
Finished Jul 11 06:37:34 PM PDT 24
Peak memory 220176 kb
Host smart-27507b1c-8143-4a28-8469-c3222d16f672
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3702693582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.3702693582
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.2122335334
Short name T780
Test name
Test status
Simulation time 4264989283 ps
CPU time 53.84 seconds
Started Jul 11 06:37:18 PM PDT 24
Finished Jul 11 06:38:13 PM PDT 24
Peak memory 253120 kb
Host smart-d527a70b-4be9-4f2f-9dd5-26e0820c0578
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122335334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.2122335334
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.308464086
Short name T895
Test name
Test status
Simulation time 6396632870 ps
CPU time 8.59 seconds
Started Jul 11 06:37:07 PM PDT 24
Finished Jul 11 06:37:16 PM PDT 24
Peak memory 216572 kb
Host smart-953ee333-449a-4f74-9d90-c9b20a858f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308464086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.308464086
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.1160924954
Short name T965
Test name
Test status
Simulation time 1491991911 ps
CPU time 4.78 seconds
Started Jul 11 06:37:06 PM PDT 24
Finished Jul 11 06:37:12 PM PDT 24
Peak memory 216020 kb
Host smart-744d955c-06ac-435a-b8ec-7b3be52d43f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160924954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.1160924954
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.2384211737
Short name T543
Test name
Test status
Simulation time 178069467 ps
CPU time 2.15 seconds
Started Jul 11 06:37:08 PM PDT 24
Finished Jul 11 06:37:11 PM PDT 24
Peak memory 216144 kb
Host smart-6bd53e60-c5ca-4ed3-9d55-4d0972368a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384211737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.2384211737
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.2546381974
Short name T998
Test name
Test status
Simulation time 42060632 ps
CPU time 0.89 seconds
Started Jul 11 06:37:04 PM PDT 24
Finished Jul 11 06:37:07 PM PDT 24
Peak memory 205972 kb
Host smart-e323be46-2506-462a-9bfd-54f3225c664b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546381974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.2546381974
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.2949567305
Short name T491
Test name
Test status
Simulation time 11040218665 ps
CPU time 31.21 seconds
Started Jul 11 06:37:18 PM PDT 24
Finished Jul 11 06:37:51 PM PDT 24
Peak memory 232780 kb
Host smart-ed8eda72-debf-4e92-a728-cabe92ec6b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949567305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.2949567305
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.1216400878
Short name T414
Test name
Test status
Simulation time 40908153 ps
CPU time 0.74 seconds
Started Jul 11 06:37:18 PM PDT 24
Finished Jul 11 06:37:20 PM PDT 24
Peak memory 205528 kb
Host smart-d878ab77-b458-4156-9b76-9780a7728be7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216400878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
1216400878
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.2601934360
Short name T805
Test name
Test status
Simulation time 107488986 ps
CPU time 2.57 seconds
Started Jul 11 06:37:11 PM PDT 24
Finished Jul 11 06:37:15 PM PDT 24
Peak memory 224436 kb
Host smart-d4bc6a31-f8a5-45ac-b435-48d66b3c4162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601934360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.2601934360
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.4225441323
Short name T580
Test name
Test status
Simulation time 28614966 ps
CPU time 0.76 seconds
Started Jul 11 06:37:13 PM PDT 24
Finished Jul 11 06:37:16 PM PDT 24
Peak memory 205604 kb
Host smart-f4e6d4c9-b94b-48d2-be69-184e378a51b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225441323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.4225441323
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.4010958543
Short name T568
Test name
Test status
Simulation time 51865243190 ps
CPU time 179.07 seconds
Started Jul 11 06:37:18 PM PDT 24
Finished Jul 11 06:40:18 PM PDT 24
Peak memory 249244 kb
Host smart-811129e0-184e-43e6-ac61-020275ee8dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010958543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.4010958543
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.1889384151
Short name T252
Test name
Test status
Simulation time 28942028023 ps
CPU time 72.02 seconds
Started Jul 11 06:37:18 PM PDT 24
Finished Jul 11 06:38:31 PM PDT 24
Peak memory 266468 kb
Host smart-3a71d874-31b0-46cf-b1ad-c8f2b5b4f250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889384151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.1889384151
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.3165349763
Short name T697
Test name
Test status
Simulation time 42083656755 ps
CPU time 59.76 seconds
Started Jul 11 06:37:17 PM PDT 24
Finished Jul 11 06:38:18 PM PDT 24
Peak memory 240968 kb
Host smart-33d37149-473e-40d8-b11f-709cd0605f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165349763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.3165349763
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.143595192
Short name T37
Test name
Test status
Simulation time 247299987 ps
CPU time 4.61 seconds
Started Jul 11 06:37:12 PM PDT 24
Finished Jul 11 06:37:19 PM PDT 24
Peak memory 232712 kb
Host smart-6e5c15eb-4c54-4a4e-8663-579f74713163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143595192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.143595192
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.4073152380
Short name T536
Test name
Test status
Simulation time 1755049518 ps
CPU time 21.14 seconds
Started Jul 11 06:37:26 PM PDT 24
Finished Jul 11 06:37:49 PM PDT 24
Peak memory 239472 kb
Host smart-7e0cc67e-83e8-4469-8670-020d59ed023e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073152380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.4073152380
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_intercept.3697198060
Short name T883
Test name
Test status
Simulation time 500996544 ps
CPU time 2.82 seconds
Started Jul 11 06:37:13 PM PDT 24
Finished Jul 11 06:37:18 PM PDT 24
Peak memory 218792 kb
Host smart-84ed7b10-2be0-44af-a475-9a7a6926b342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697198060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.3697198060
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.3338973585
Short name T791
Test name
Test status
Simulation time 4870144022 ps
CPU time 43.38 seconds
Started Jul 11 06:37:12 PM PDT 24
Finished Jul 11 06:37:57 PM PDT 24
Peak memory 241024 kb
Host smart-5c056d29-0a3c-4996-9d7b-71677cb293bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338973585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.3338973585
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.1746938970
Short name T929
Test name
Test status
Simulation time 136558174 ps
CPU time 3.38 seconds
Started Jul 11 06:37:18 PM PDT 24
Finished Jul 11 06:37:23 PM PDT 24
Peak memory 232632 kb
Host smart-371dcd26-db83-46cb-9ebe-5806ceb578f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746938970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.1746938970
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.3976391382
Short name T384
Test name
Test status
Simulation time 107892032 ps
CPU time 2.96 seconds
Started Jul 11 06:37:13 PM PDT 24
Finished Jul 11 06:37:18 PM PDT 24
Peak memory 224436 kb
Host smart-5aa43d22-7344-4095-9ab3-49690c326711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976391382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.3976391382
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.3625692638
Short name T550
Test name
Test status
Simulation time 2042214661 ps
CPU time 6.68 seconds
Started Jul 11 06:37:17 PM PDT 24
Finished Jul 11 06:37:25 PM PDT 24
Peak memory 223080 kb
Host smart-10e77a16-15dd-444b-9275-b7c281988b3b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3625692638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.3625692638
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.1660751807
Short name T502
Test name
Test status
Simulation time 13127037572 ps
CPU time 29.15 seconds
Started Jul 11 06:37:15 PM PDT 24
Finished Jul 11 06:37:45 PM PDT 24
Peak memory 216352 kb
Host smart-de0f61fd-11b2-4fd1-a731-a4e96fac7b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660751807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.1660751807
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.1617599095
Short name T787
Test name
Test status
Simulation time 327782691 ps
CPU time 2.38 seconds
Started Jul 11 06:37:13 PM PDT 24
Finished Jul 11 06:37:17 PM PDT 24
Peak memory 216184 kb
Host smart-44b29428-be7c-447e-a8f5-be4a33bfbbf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617599095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.1617599095
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.2628702706
Short name T317
Test name
Test status
Simulation time 41818355 ps
CPU time 0.74 seconds
Started Jul 11 06:37:13 PM PDT 24
Finished Jul 11 06:37:15 PM PDT 24
Peak memory 206008 kb
Host smart-4e566c93-a479-4e5c-9c6b-e612dd83ba7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628702706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.2628702706
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.2013772282
Short name T496
Test name
Test status
Simulation time 71722123 ps
CPU time 0.76 seconds
Started Jul 11 06:37:13 PM PDT 24
Finished Jul 11 06:37:15 PM PDT 24
Peak memory 205988 kb
Host smart-65615aff-98f7-4c15-bc68-42cf58b793d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013772282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.2013772282
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.4277235652
Short name T525
Test name
Test status
Simulation time 1498655877 ps
CPU time 8.61 seconds
Started Jul 11 06:37:13 PM PDT 24
Finished Jul 11 06:37:24 PM PDT 24
Peak memory 241020 kb
Host smart-10cfecb8-4dc8-455c-ad9d-08c1c71d305f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277235652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.4277235652
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.849495699
Short name T24
Test name
Test status
Simulation time 13105671 ps
CPU time 0.74 seconds
Started Jul 11 06:34:49 PM PDT 24
Finished Jul 11 06:34:51 PM PDT 24
Peak memory 205560 kb
Host smart-dd20e969-905a-4f85-94c3-8538a2840e44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849495699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.849495699
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.3793620711
Short name T691
Test name
Test status
Simulation time 295917968 ps
CPU time 2.19 seconds
Started Jul 11 06:34:46 PM PDT 24
Finished Jul 11 06:34:50 PM PDT 24
Peak memory 224420 kb
Host smart-ef37199c-5c98-4fe2-ac3e-b6bd593d9b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793620711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.3793620711
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.2582893745
Short name T658
Test name
Test status
Simulation time 69415149 ps
CPU time 0.78 seconds
Started Jul 11 06:34:48 PM PDT 24
Finished Jul 11 06:34:50 PM PDT 24
Peak memory 206636 kb
Host smart-7f0640ce-2d81-479e-a77f-c918ac62cf68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582893745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.2582893745
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.2507172395
Short name T117
Test name
Test status
Simulation time 8726787406 ps
CPU time 48.43 seconds
Started Jul 11 06:34:49 PM PDT 24
Finished Jul 11 06:35:39 PM PDT 24
Peak memory 256588 kb
Host smart-f5b785b8-6464-4863-9ddd-7446130af61b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507172395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.2507172395
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.2424600958
Short name T250
Test name
Test status
Simulation time 1546223529 ps
CPU time 21.76 seconds
Started Jul 11 06:34:49 PM PDT 24
Finished Jul 11 06:35:12 PM PDT 24
Peak memory 224572 kb
Host smart-6f98570c-d4bc-4fdb-a423-2db569d3e7f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424600958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.2424600958
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.1210130591
Short name T540
Test name
Test status
Simulation time 804976751 ps
CPU time 3.48 seconds
Started Jul 11 06:34:46 PM PDT 24
Finished Jul 11 06:34:51 PM PDT 24
Peak memory 232936 kb
Host smart-99793ccd-f0f5-4119-99e3-cb7dda63a54e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210130591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.1210130591
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.1848399025
Short name T953
Test name
Test status
Simulation time 21796332338 ps
CPU time 79.65 seconds
Started Jul 11 06:34:45 PM PDT 24
Finished Jul 11 06:36:06 PM PDT 24
Peak memory 257356 kb
Host smart-82c2d126-af70-4977-8598-7cec1b392a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848399025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds
.1848399025
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.3126816295
Short name T906
Test name
Test status
Simulation time 1838051729 ps
CPU time 8.11 seconds
Started Jul 11 06:34:47 PM PDT 24
Finished Jul 11 06:34:56 PM PDT 24
Peak memory 232684 kb
Host smart-ad805915-48dc-4497-9dfb-0752317f5d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126816295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.3126816295
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.2582207830
Short name T604
Test name
Test status
Simulation time 19855849033 ps
CPU time 89.67 seconds
Started Jul 11 06:34:45 PM PDT 24
Finished Jul 11 06:36:16 PM PDT 24
Peak memory 224628 kb
Host smart-e0dbc979-8791-4f89-8028-828244d0d714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582207830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.2582207830
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.2959828964
Short name T236
Test name
Test status
Simulation time 76241487601 ps
CPU time 23.79 seconds
Started Jul 11 06:34:44 PM PDT 24
Finished Jul 11 06:35:09 PM PDT 24
Peak memory 232856 kb
Host smart-01ebba47-260b-4402-9372-360f67e25eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959828964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.2959828964
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.1482167968
Short name T545
Test name
Test status
Simulation time 72870601710 ps
CPU time 17.26 seconds
Started Jul 11 06:34:49 PM PDT 24
Finished Jul 11 06:35:07 PM PDT 24
Peak memory 240968 kb
Host smart-e24ed896-a8c5-4c9b-b5dc-44fc5e4c5bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482167968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.1482167968
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.3590320162
Short name T676
Test name
Test status
Simulation time 7151067640 ps
CPU time 21.87 seconds
Started Jul 11 06:34:46 PM PDT 24
Finished Jul 11 06:35:09 PM PDT 24
Peak memory 218996 kb
Host smart-93daa10c-e6aa-4e2c-a532-2495df71d7db
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3590320162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.3590320162
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.2250907769
Short name T64
Test name
Test status
Simulation time 212646342 ps
CPU time 0.98 seconds
Started Jul 11 06:34:48 PM PDT 24
Finished Jul 11 06:34:51 PM PDT 24
Peak memory 236600 kb
Host smart-9c0a6b6b-8e0a-4df1-b279-b124aea880fa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250907769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.2250907769
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.2979244079
Short name T975
Test name
Test status
Simulation time 8296428472 ps
CPU time 46.58 seconds
Started Jul 11 06:34:47 PM PDT 24
Finished Jul 11 06:35:35 PM PDT 24
Peak memory 216392 kb
Host smart-cc85b83d-1e64-4400-b5eb-9092a3a5d235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979244079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.2979244079
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.4274926160
Short name T487
Test name
Test status
Simulation time 1759340258 ps
CPU time 2.87 seconds
Started Jul 11 06:34:45 PM PDT 24
Finished Jul 11 06:34:49 PM PDT 24
Peak memory 216248 kb
Host smart-1e8b4e7f-21d2-43a2-9a1f-41e112930248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274926160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.4274926160
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.3944344075
Short name T469
Test name
Test status
Simulation time 809682527 ps
CPU time 2.76 seconds
Started Jul 11 06:34:46 PM PDT 24
Finished Jul 11 06:34:50 PM PDT 24
Peak memory 216188 kb
Host smart-4176349f-badd-4177-87d1-35b50e453e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944344075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.3944344075
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.1025049436
Short name T378
Test name
Test status
Simulation time 76502599 ps
CPU time 0.93 seconds
Started Jul 11 06:34:46 PM PDT 24
Finished Jul 11 06:34:48 PM PDT 24
Peak memory 206992 kb
Host smart-61dee815-60d9-42c4-9fc7-c8e8314245c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025049436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.1025049436
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.3780169107
Short name T976
Test name
Test status
Simulation time 1051755790 ps
CPU time 2.33 seconds
Started Jul 11 06:34:47 PM PDT 24
Finished Jul 11 06:34:51 PM PDT 24
Peak memory 224200 kb
Host smart-479a8bf4-408e-4334-a43d-28db7baa00ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780169107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.3780169107
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.2100358835
Short name T762
Test name
Test status
Simulation time 30788547 ps
CPU time 0.78 seconds
Started Jul 11 06:37:57 PM PDT 24
Finished Jul 11 06:37:59 PM PDT 24
Peak memory 205528 kb
Host smart-6f51fb5a-7c87-4a5a-9b25-6efc3ac8e8de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100358835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
2100358835
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.1718321460
Short name T75
Test name
Test status
Simulation time 1013516418 ps
CPU time 5.22 seconds
Started Jul 11 06:37:28 PM PDT 24
Finished Jul 11 06:37:35 PM PDT 24
Peak memory 232712 kb
Host smart-5591a9b6-4424-44a0-b391-ee25fa41e238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718321460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.1718321460
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.139465707
Short name T665
Test name
Test status
Simulation time 68772523 ps
CPU time 0.82 seconds
Started Jul 11 06:37:27 PM PDT 24
Finished Jul 11 06:37:29 PM PDT 24
Peak memory 206612 kb
Host smart-a9746637-7038-49a7-833e-80bf6f5a1fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139465707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.139465707
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.1637054067
Short name T452
Test name
Test status
Simulation time 55214539426 ps
CPU time 196.91 seconds
Started Jul 11 06:37:30 PM PDT 24
Finished Jul 11 06:40:48 PM PDT 24
Peak memory 255676 kb
Host smart-89d168bf-9838-436a-b9a7-8fa056367d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637054067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.1637054067
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.354918185
Short name T5
Test name
Test status
Simulation time 13030779603 ps
CPU time 27.88 seconds
Started Jul 11 06:37:30 PM PDT 24
Finished Jul 11 06:37:58 PM PDT 24
Peak memory 237940 kb
Host smart-74f43b63-7e59-41bd-b448-a610fe5c1469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354918185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.354918185
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.765678551
Short name T990
Test name
Test status
Simulation time 20183169734 ps
CPU time 152.77 seconds
Started Jul 11 06:37:30 PM PDT 24
Finished Jul 11 06:40:03 PM PDT 24
Peak memory 249256 kb
Host smart-87e6bf07-6b2e-446d-8c22-1895841a0663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765678551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idle
.765678551
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.2282300230
Short name T671
Test name
Test status
Simulation time 193505496 ps
CPU time 4.48 seconds
Started Jul 11 06:37:30 PM PDT 24
Finished Jul 11 06:37:36 PM PDT 24
Peak memory 224516 kb
Host smart-ea2674bb-6a7b-4ff3-b341-969b5a4184f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282300230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.2282300230
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.2003235282
Short name T391
Test name
Test status
Simulation time 79832260 ps
CPU time 2.23 seconds
Started Jul 11 06:37:28 PM PDT 24
Finished Jul 11 06:37:32 PM PDT 24
Peak memory 226780 kb
Host smart-4e14060c-9804-4894-9310-f23b593e50e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003235282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.2003235282
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.1035935668
Short name T919
Test name
Test status
Simulation time 1969893178 ps
CPU time 15.98 seconds
Started Jul 11 06:37:29 PM PDT 24
Finished Jul 11 06:37:46 PM PDT 24
Peak memory 232668 kb
Host smart-2feb3ad8-59c1-472f-8975-a3e02b507c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035935668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.1035935668
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.808052436
Short name T29
Test name
Test status
Simulation time 7244347271 ps
CPU time 11.52 seconds
Started Jul 11 06:37:27 PM PDT 24
Finished Jul 11 06:37:39 PM PDT 24
Peak memory 232804 kb
Host smart-c197ef88-2aca-4936-a70a-445144606433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808052436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swap
.808052436
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.839730585
Short name T227
Test name
Test status
Simulation time 2836452339 ps
CPU time 10.64 seconds
Started Jul 11 06:37:27 PM PDT 24
Finished Jul 11 06:37:38 PM PDT 24
Peak memory 232744 kb
Host smart-00470449-03ac-4dd5-9fa8-23ac593e0765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839730585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.839730585
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.4248824145
Short name T437
Test name
Test status
Simulation time 3582758113 ps
CPU time 6.73 seconds
Started Jul 11 06:37:29 PM PDT 24
Finished Jul 11 06:37:37 PM PDT 24
Peak memory 220428 kb
Host smart-7ce83458-9825-4d2e-a615-bef34846ae29
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4248824145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.4248824145
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.3875804008
Short name T111
Test name
Test status
Simulation time 5078454394 ps
CPU time 31.84 seconds
Started Jul 11 06:37:56 PM PDT 24
Finished Jul 11 06:38:30 PM PDT 24
Peak memory 241104 kb
Host smart-a18741d7-9983-4de1-8278-c69193eb7aae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875804008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.3875804008
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.2048881061
Short name T423
Test name
Test status
Simulation time 34942553813 ps
CPU time 27.78 seconds
Started Jul 11 06:37:36 PM PDT 24
Finished Jul 11 06:38:04 PM PDT 24
Peak memory 217544 kb
Host smart-f71e419e-b0a0-4447-83ae-1a36c0a2f2a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048881061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.2048881061
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.384472546
Short name T722
Test name
Test status
Simulation time 2439168301 ps
CPU time 6.48 seconds
Started Jul 11 06:37:27 PM PDT 24
Finished Jul 11 06:37:35 PM PDT 24
Peak memory 216380 kb
Host smart-c593760f-846d-464d-a4d2-a485702daf36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384472546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.384472546
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.1497429245
Short name T503
Test name
Test status
Simulation time 141649597 ps
CPU time 3.23 seconds
Started Jul 11 06:37:27 PM PDT 24
Finished Jul 11 06:37:31 PM PDT 24
Peak memory 216208 kb
Host smart-7d648b4b-2ede-4654-8f25-4cfa7875fac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497429245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.1497429245
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.3887220682
Short name T346
Test name
Test status
Simulation time 85877679 ps
CPU time 0.83 seconds
Started Jul 11 06:37:26 PM PDT 24
Finished Jul 11 06:37:28 PM PDT 24
Peak memory 205968 kb
Host smart-d38c5e5f-0c57-4280-8cba-fe3006ddcd05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887220682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.3887220682
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.3461351637
Short name T517
Test name
Test status
Simulation time 4358555583 ps
CPU time 6.71 seconds
Started Jul 11 06:37:29 PM PDT 24
Finished Jul 11 06:37:37 PM PDT 24
Peak memory 232828 kb
Host smart-a0b7c402-149f-497d-8ee2-18c74f25f025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461351637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.3461351637
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.1555350178
Short name T56
Test name
Test status
Simulation time 93181158 ps
CPU time 0.74 seconds
Started Jul 11 06:38:00 PM PDT 24
Finished Jul 11 06:38:03 PM PDT 24
Peak memory 205888 kb
Host smart-0f20e8aa-4d79-4d05-b8b8-14be62d84cf4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555350178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
1555350178
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.1550476164
Short name T310
Test name
Test status
Simulation time 2099516107 ps
CPU time 18.84 seconds
Started Jul 11 06:37:59 PM PDT 24
Finished Jul 11 06:38:20 PM PDT 24
Peak memory 232632 kb
Host smart-298f2d46-4f15-4e6c-8adb-80f2dbe2efc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550476164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.1550476164
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.2793037644
Short name T558
Test name
Test status
Simulation time 174462715 ps
CPU time 0.78 seconds
Started Jul 11 06:37:57 PM PDT 24
Finished Jul 11 06:37:59 PM PDT 24
Peak memory 206632 kb
Host smart-b02d6100-d2ff-42d4-a2bd-baeceace65b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793037644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.2793037644
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.270792386
Short name T994
Test name
Test status
Simulation time 197682861932 ps
CPU time 138.03 seconds
Started Jul 11 06:37:59 PM PDT 24
Finished Jul 11 06:40:19 PM PDT 24
Peak memory 251668 kb
Host smart-b96c1019-f4ed-4f5b-9429-5f7170bba6f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270792386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.270792386
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.2151622806
Short name T801
Test name
Test status
Simulation time 25417852973 ps
CPU time 249.18 seconds
Started Jul 11 06:38:00 PM PDT 24
Finished Jul 11 06:42:11 PM PDT 24
Peak memory 254528 kb
Host smart-6e1dab3c-7d63-408b-8c7f-c876f588ce8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151622806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.2151622806
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.2610800021
Short name T462
Test name
Test status
Simulation time 6015910027 ps
CPU time 77.55 seconds
Started Jul 11 06:37:59 PM PDT 24
Finished Jul 11 06:39:18 PM PDT 24
Peak memory 250532 kb
Host smart-3758b784-7493-4e76-9a92-8be85e4c81f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610800021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.2610800021
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.2741516219
Short name T441
Test name
Test status
Simulation time 1013909963 ps
CPU time 12.69 seconds
Started Jul 11 06:37:59 PM PDT 24
Finished Jul 11 06:38:14 PM PDT 24
Peak memory 240860 kb
Host smart-ebd52c01-45bb-4162-8654-ddf490b57c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741516219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.2741516219
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.2013203296
Short name T978
Test name
Test status
Simulation time 19963616307 ps
CPU time 178.97 seconds
Started Jul 11 06:37:59 PM PDT 24
Finished Jul 11 06:41:00 PM PDT 24
Peak memory 256864 kb
Host smart-a1f50d17-fd77-4e00-8cc0-bf5860803919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013203296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmd
s.2013203296
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.3824480688
Short name T561
Test name
Test status
Simulation time 168652899 ps
CPU time 2.81 seconds
Started Jul 11 06:37:59 PM PDT 24
Finished Jul 11 06:38:04 PM PDT 24
Peak memory 232700 kb
Host smart-b18f1c15-775e-4b2a-b2a3-bc8624539fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824480688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.3824480688
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.1650375799
Short name T944
Test name
Test status
Simulation time 101065184 ps
CPU time 2.2 seconds
Started Jul 11 06:37:59 PM PDT 24
Finished Jul 11 06:38:03 PM PDT 24
Peak memory 224496 kb
Host smart-84c02e21-c33e-45f2-828a-279e63213d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650375799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.1650375799
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.1655594535
Short name T237
Test name
Test status
Simulation time 964685021 ps
CPU time 5.92 seconds
Started Jul 11 06:38:00 PM PDT 24
Finished Jul 11 06:38:08 PM PDT 24
Peak memory 224428 kb
Host smart-21720ff6-4fbf-4f32-87ee-23e4477a4937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655594535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.1655594535
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.1629255913
Short name T167
Test name
Test status
Simulation time 816926367 ps
CPU time 6.54 seconds
Started Jul 11 06:37:59 PM PDT 24
Finished Jul 11 06:38:08 PM PDT 24
Peak memory 232848 kb
Host smart-fb6bc6b4-76cf-4dcc-8374-5970ecf3517a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629255913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.1629255913
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.2193511821
Short name T830
Test name
Test status
Simulation time 921853380 ps
CPU time 6.64 seconds
Started Jul 11 06:38:00 PM PDT 24
Finished Jul 11 06:38:09 PM PDT 24
Peak memory 220336 kb
Host smart-b54fb33b-a1fe-43ba-8a20-633ffea2a3ca
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2193511821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.2193511821
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.2638974027
Short name T31
Test name
Test status
Simulation time 41630750014 ps
CPU time 64.06 seconds
Started Jul 11 06:38:00 PM PDT 24
Finished Jul 11 06:39:06 PM PDT 24
Peak memory 224688 kb
Host smart-805b0799-039a-4496-935a-858362330a16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638974027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.2638974027
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.2197256584
Short name T287
Test name
Test status
Simulation time 3370870856 ps
CPU time 18.1 seconds
Started Jul 11 06:37:57 PM PDT 24
Finished Jul 11 06:38:17 PM PDT 24
Peak memory 216592 kb
Host smart-aeb46605-8237-4778-baa9-87143d46d49e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197256584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.2197256584
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.3900529135
Short name T842
Test name
Test status
Simulation time 4370610072 ps
CPU time 4.02 seconds
Started Jul 11 06:38:00 PM PDT 24
Finished Jul 11 06:38:06 PM PDT 24
Peak memory 217260 kb
Host smart-441909ef-d736-478e-90ba-d1bcdd900ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900529135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.3900529135
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.2324301557
Short name T569
Test name
Test status
Simulation time 220955767 ps
CPU time 3.17 seconds
Started Jul 11 06:37:55 PM PDT 24
Finished Jul 11 06:37:59 PM PDT 24
Peak memory 216196 kb
Host smart-f5109438-343d-4cbc-b947-d2693094b5c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324301557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.2324301557
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.4079774716
Short name T771
Test name
Test status
Simulation time 54698785 ps
CPU time 0.83 seconds
Started Jul 11 06:37:56 PM PDT 24
Finished Jul 11 06:37:59 PM PDT 24
Peak memory 206000 kb
Host smart-510b1d19-37ed-40f2-9385-ef6d03ad9c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079774716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.4079774716
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.1654557168
Short name T389
Test name
Test status
Simulation time 10624462133 ps
CPU time 11 seconds
Started Jul 11 06:38:00 PM PDT 24
Finished Jul 11 06:38:13 PM PDT 24
Peak memory 238016 kb
Host smart-2943c5ce-90a6-4809-be02-c4d71addcfb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654557168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.1654557168
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.4191046359
Short name T433
Test name
Test status
Simulation time 12399793 ps
CPU time 0.68 seconds
Started Jul 11 06:38:05 PM PDT 24
Finished Jul 11 06:38:07 PM PDT 24
Peak memory 205524 kb
Host smart-279f011b-f2a3-4722-867f-8145493edfff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191046359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
4191046359
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.38785264
Short name T854
Test name
Test status
Simulation time 130352082 ps
CPU time 3.82 seconds
Started Jul 11 06:38:05 PM PDT 24
Finished Jul 11 06:38:10 PM PDT 24
Peak memory 232664 kb
Host smart-9afc0e3c-8d94-4782-9be3-553c55eccd43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38785264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.38785264
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.1117906664
Short name T326
Test name
Test status
Simulation time 21912365 ps
CPU time 0.84 seconds
Started Jul 11 06:37:59 PM PDT 24
Finished Jul 11 06:38:02 PM PDT 24
Peak memory 206940 kb
Host smart-5278c869-b0a2-4cc8-ace1-3dc51fba337f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117906664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.1117906664
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.4063493584
Short name T35
Test name
Test status
Simulation time 6575411435 ps
CPU time 92.62 seconds
Started Jul 11 06:38:05 PM PDT 24
Finished Jul 11 06:39:40 PM PDT 24
Peak memory 254796 kb
Host smart-98de9747-6587-44c6-8271-e8ec3a8a8ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063493584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.4063493584
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.98878877
Short name T753
Test name
Test status
Simulation time 2947718444 ps
CPU time 60.85 seconds
Started Jul 11 06:38:05 PM PDT 24
Finished Jul 11 06:39:08 PM PDT 24
Peak memory 252100 kb
Host smart-7c0a33d6-c56e-40e0-a065-0ea9228e4684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98878877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.98878877
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.2804883595
Short name T819
Test name
Test status
Simulation time 11429732621 ps
CPU time 95.97 seconds
Started Jul 11 06:38:03 PM PDT 24
Finished Jul 11 06:39:41 PM PDT 24
Peak memory 249288 kb
Host smart-319beb07-6692-43da-a6a5-906b2fd8df89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804883595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.2804883595
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.2436203553
Short name T727
Test name
Test status
Simulation time 5504833744 ps
CPU time 17.21 seconds
Started Jul 11 06:38:04 PM PDT 24
Finished Jul 11 06:38:23 PM PDT 24
Peak memory 248428 kb
Host smart-e6d9e6ac-2fcd-4d65-817e-b16ed43d2a66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436203553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.2436203553
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.3334714953
Short name T623
Test name
Test status
Simulation time 2143870041 ps
CPU time 17.55 seconds
Started Jul 11 06:38:05 PM PDT 24
Finished Jul 11 06:38:24 PM PDT 24
Peak memory 240868 kb
Host smart-ec501c42-a40a-4d24-9fd0-0d1205870fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334714953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmd
s.3334714953
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.3949919929
Short name T497
Test name
Test status
Simulation time 3227696338 ps
CPU time 16.61 seconds
Started Jul 11 06:37:55 PM PDT 24
Finished Jul 11 06:38:12 PM PDT 24
Peak memory 248952 kb
Host smart-155805a9-5cb0-494a-a29e-0050c68208e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949919929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.3949919929
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.1036515556
Short name T191
Test name
Test status
Simulation time 7103130015 ps
CPU time 11.27 seconds
Started Jul 11 06:38:02 PM PDT 24
Finished Jul 11 06:38:15 PM PDT 24
Peak memory 232768 kb
Host smart-d55d394d-8846-4bc8-a839-25eb550ef1ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036515556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.1036515556
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.2096266029
Short name T701
Test name
Test status
Simulation time 1296997158 ps
CPU time 7.98 seconds
Started Jul 11 06:38:04 PM PDT 24
Finished Jul 11 06:38:14 PM PDT 24
Peak memory 232648 kb
Host smart-c1ba4d81-509b-4808-8c92-1dff8564ab62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096266029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.2096266029
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.457000882
Short name T861
Test name
Test status
Simulation time 102023581 ps
CPU time 3.19 seconds
Started Jul 11 06:38:06 PM PDT 24
Finished Jul 11 06:38:10 PM PDT 24
Peak memory 219352 kb
Host smart-5607ca03-33ab-4277-b28c-3e25628001c8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=457000882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dire
ct.457000882
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.1504979564
Short name T113
Test name
Test status
Simulation time 31600559357 ps
CPU time 334.53 seconds
Started Jul 11 06:38:05 PM PDT 24
Finished Jul 11 06:43:41 PM PDT 24
Peak memory 265632 kb
Host smart-66e7d282-a2d3-4cef-a0ae-6d934a71b515
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504979564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.1504979564
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.2300555016
Short name T323
Test name
Test status
Simulation time 5067486989 ps
CPU time 9.04 seconds
Started Jul 11 06:38:01 PM PDT 24
Finished Jul 11 06:38:13 PM PDT 24
Peak memory 217524 kb
Host smart-604cd10d-4be2-405d-bcef-006eea1584a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300555016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.2300555016
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.1504588179
Short name T475
Test name
Test status
Simulation time 2013690772 ps
CPU time 3.25 seconds
Started Jul 11 06:38:03 PM PDT 24
Finished Jul 11 06:38:08 PM PDT 24
Peak memory 216268 kb
Host smart-073f017a-620a-473c-b774-00e10e9c17e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504588179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.1504588179
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.2435262019
Short name T764
Test name
Test status
Simulation time 25375152 ps
CPU time 1.14 seconds
Started Jul 11 06:38:05 PM PDT 24
Finished Jul 11 06:38:08 PM PDT 24
Peak memory 207688 kb
Host smart-0b8e1749-fd32-4e72-95a8-1e3696ab51da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435262019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.2435262019
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.2449224046
Short name T617
Test name
Test status
Simulation time 14029949 ps
CPU time 0.75 seconds
Started Jul 11 06:38:00 PM PDT 24
Finished Jul 11 06:38:04 PM PDT 24
Peak memory 205948 kb
Host smart-39d9c3b2-8503-44ba-b47d-76d7d471c217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449224046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.2449224046
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.3631157693
Short name T605
Test name
Test status
Simulation time 36246955236 ps
CPU time 29.06 seconds
Started Jul 11 06:38:01 PM PDT 24
Finished Jul 11 06:38:33 PM PDT 24
Peak memory 224572 kb
Host smart-a4f98a20-ab41-40f6-89f5-2a29f92f2238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631157693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.3631157693
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.507978303
Short name T551
Test name
Test status
Simulation time 23389325 ps
CPU time 0.71 seconds
Started Jul 11 06:38:13 PM PDT 24
Finished Jul 11 06:38:16 PM PDT 24
Peak memory 204880 kb
Host smart-232080b9-8d78-476a-ba5c-c0f0032622ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507978303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.507978303
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.2545677503
Short name T967
Test name
Test status
Simulation time 1611396488 ps
CPU time 6.67 seconds
Started Jul 11 06:38:10 PM PDT 24
Finished Jul 11 06:38:18 PM PDT 24
Peak memory 224424 kb
Host smart-c1d4b9ae-cf85-499d-847b-56a08e5483f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545677503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.2545677503
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.630086962
Short name T530
Test name
Test status
Simulation time 19212223 ps
CPU time 0.85 seconds
Started Jul 11 06:38:07 PM PDT 24
Finished Jul 11 06:38:09 PM PDT 24
Peak memory 206796 kb
Host smart-f202fbe9-42f3-4a32-b1b6-06d5c6d8da82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630086962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.630086962
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.1166998981
Short name T754
Test name
Test status
Simulation time 14039813057 ps
CPU time 106.49 seconds
Started Jul 11 06:38:10 PM PDT 24
Finished Jul 11 06:39:59 PM PDT 24
Peak memory 237380 kb
Host smart-32e13bd4-1c8c-4455-9bbc-3426202aa5ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166998981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.1166998981
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.485599429
Short name T802
Test name
Test status
Simulation time 301737494965 ps
CPU time 630.34 seconds
Started Jul 11 06:38:11 PM PDT 24
Finished Jul 11 06:48:42 PM PDT 24
Peak memory 256040 kb
Host smart-e7ca95d3-204a-41ae-9340-1a56cb0bfdb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485599429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.485599429
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.2296339695
Short name T708
Test name
Test status
Simulation time 30729688888 ps
CPU time 75.99 seconds
Started Jul 11 06:38:09 PM PDT 24
Finished Jul 11 06:39:27 PM PDT 24
Peak memory 257388 kb
Host smart-f8bf2c02-00ed-49f0-bec1-4ba94e92369b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296339695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.2296339695
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.59993278
Short name T438
Test name
Test status
Simulation time 2556199552 ps
CPU time 10.38 seconds
Started Jul 11 06:38:07 PM PDT 24
Finished Jul 11 06:38:19 PM PDT 24
Peak memory 224644 kb
Host smart-e35a4e6e-eccb-44ef-88d7-872b28491f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59993278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.59993278
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.508459505
Short name T832
Test name
Test status
Simulation time 74290187 ps
CPU time 0.89 seconds
Started Jul 11 06:38:09 PM PDT 24
Finished Jul 11 06:38:11 PM PDT 24
Peak memory 215952 kb
Host smart-20942261-775a-4ea0-bb59-1f2fb13d9041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508459505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmds
.508459505
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.1869440343
Short name T449
Test name
Test status
Simulation time 173226688 ps
CPU time 5.58 seconds
Started Jul 11 06:38:09 PM PDT 24
Finished Jul 11 06:38:16 PM PDT 24
Peak memory 219076 kb
Host smart-08525f90-78a4-4a14-86a4-c9e3f2353797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869440343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.1869440343
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.120323887
Short name T641
Test name
Test status
Simulation time 4817157289 ps
CPU time 45.82 seconds
Started Jul 11 06:38:09 PM PDT 24
Finished Jul 11 06:38:57 PM PDT 24
Peak memory 232832 kb
Host smart-03b78a47-043f-4d8f-b7e0-6e9ddd81c17b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120323887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.120323887
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.4036432128
Short name T518
Test name
Test status
Simulation time 10975510360 ps
CPU time 7.54 seconds
Started Jul 11 06:38:10 PM PDT 24
Finished Jul 11 06:38:19 PM PDT 24
Peak memory 232852 kb
Host smart-6e45984f-c318-4f8f-8c71-d16540767827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036432128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.4036432128
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.2022863311
Short name T194
Test name
Test status
Simulation time 63066882 ps
CPU time 2.46 seconds
Started Jul 11 06:38:07 PM PDT 24
Finished Jul 11 06:38:11 PM PDT 24
Peak memory 232648 kb
Host smart-414ae4bb-5a1e-4f9a-a924-f18e042ee256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022863311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.2022863311
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.2119457687
Short name T996
Test name
Test status
Simulation time 781097972 ps
CPU time 4.42 seconds
Started Jul 11 06:38:10 PM PDT 24
Finished Jul 11 06:38:16 PM PDT 24
Peak memory 222824 kb
Host smart-660dd26d-635d-48ae-872a-9677ede9b505
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2119457687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.2119457687
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.2950328115
Short name T276
Test name
Test status
Simulation time 2524374221 ps
CPU time 20.3 seconds
Started Jul 11 06:38:06 PM PDT 24
Finished Jul 11 06:38:27 PM PDT 24
Peak memory 216396 kb
Host smart-c9308add-837d-4a43-a85a-cc677de0372e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950328115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.2950328115
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.2109063777
Short name T382
Test name
Test status
Simulation time 5520137128 ps
CPU time 17.35 seconds
Started Jul 11 06:38:05 PM PDT 24
Finished Jul 11 06:38:24 PM PDT 24
Peak memory 216376 kb
Host smart-64fe46c7-a22f-4336-bcfb-af40183baecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109063777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.2109063777
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.1808712671
Short name T535
Test name
Test status
Simulation time 96004971 ps
CPU time 0.96 seconds
Started Jul 11 06:37:50 PM PDT 24
Finished Jul 11 06:37:51 PM PDT 24
Peak memory 207076 kb
Host smart-6a910d2d-83fc-4307-aa62-e92718503358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808712671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.1808712671
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.2098810891
Short name T622
Test name
Test status
Simulation time 108492640 ps
CPU time 0.82 seconds
Started Jul 11 06:38:04 PM PDT 24
Finished Jul 11 06:38:07 PM PDT 24
Peak memory 205972 kb
Host smart-2af117f4-70ca-4438-9c9f-b1bc858f4fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098810891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.2098810891
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.2935166952
Short name T948
Test name
Test status
Simulation time 1801105285 ps
CPU time 7.97 seconds
Started Jul 11 06:38:09 PM PDT 24
Finished Jul 11 06:38:18 PM PDT 24
Peak memory 232648 kb
Host smart-bd7a2496-9356-430c-af7e-13e744db8d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935166952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.2935166952
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.2299224280
Short name T303
Test name
Test status
Simulation time 27596214 ps
CPU time 0.74 seconds
Started Jul 11 06:38:16 PM PDT 24
Finished Jul 11 06:38:18 PM PDT 24
Peak memory 205512 kb
Host smart-87885440-0e11-4f41-8007-3a38c81ba557
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299224280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
2299224280
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.3672629068
Short name T407
Test name
Test status
Simulation time 1101962446 ps
CPU time 6.37 seconds
Started Jul 11 06:38:12 PM PDT 24
Finished Jul 11 06:38:20 PM PDT 24
Peak memory 224416 kb
Host smart-e50d0b8f-c9b8-47c5-98ed-74402c925469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672629068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.3672629068
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.1400218165
Short name T54
Test name
Test status
Simulation time 50841430 ps
CPU time 0.75 seconds
Started Jul 11 06:38:10 PM PDT 24
Finished Jul 11 06:38:12 PM PDT 24
Peak memory 205604 kb
Host smart-14244d40-9c64-4ec1-8d7c-50eaf1b9634b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400218165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.1400218165
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.410395301
Short name T296
Test name
Test status
Simulation time 37921573 ps
CPU time 0.75 seconds
Started Jul 11 06:38:14 PM PDT 24
Finished Jul 11 06:38:16 PM PDT 24
Peak memory 215772 kb
Host smart-6d6a87c2-3ab2-4dbf-89f4-491e33f5536b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410395301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.410395301
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.891694207
Short name T1004
Test name
Test status
Simulation time 5206314493 ps
CPU time 22.76 seconds
Started Jul 11 06:38:16 PM PDT 24
Finished Jul 11 06:38:40 PM PDT 24
Peak memory 249228 kb
Host smart-db6cf6df-838e-41eb-9e64-62c63ae1c267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891694207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.891694207
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.1388889872
Short name T620
Test name
Test status
Simulation time 19880636545 ps
CPU time 128.26 seconds
Started Jul 11 06:38:17 PM PDT 24
Finished Jul 11 06:40:27 PM PDT 24
Peak memory 249236 kb
Host smart-8d9dee94-e57f-4409-90a7-0b0bd7c20494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388889872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.1388889872
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_intercept.1301016553
Short name T775
Test name
Test status
Simulation time 511665239 ps
CPU time 7.55 seconds
Started Jul 11 06:38:10 PM PDT 24
Finished Jul 11 06:38:19 PM PDT 24
Peak memory 232604 kb
Host smart-0fd79928-2739-4e97-a1e7-61e1a2406e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301016553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.1301016553
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.3422198824
Short name T985
Test name
Test status
Simulation time 50169503776 ps
CPU time 26.7 seconds
Started Jul 11 06:38:13 PM PDT 24
Finished Jul 11 06:38:41 PM PDT 24
Peak memory 224560 kb
Host smart-12842813-17a0-460e-8d57-e1dcf35b1e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422198824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.3422198824
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.720092476
Short name T841
Test name
Test status
Simulation time 1664285273 ps
CPU time 8.56 seconds
Started Jul 11 06:38:10 PM PDT 24
Finished Jul 11 06:38:21 PM PDT 24
Peak memory 249700 kb
Host smart-0edc94ae-59a0-4d97-a465-efd8d09c0501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720092476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swap
.720092476
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.165562557
Short name T899
Test name
Test status
Simulation time 3366653278 ps
CPU time 4.29 seconds
Started Jul 11 06:38:13 PM PDT 24
Finished Jul 11 06:38:19 PM PDT 24
Peak memory 232744 kb
Host smart-3e1f3977-81b2-4010-85ab-fcaef98ba586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165562557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.165562557
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.2604812542
Short name T648
Test name
Test status
Simulation time 5739484387 ps
CPU time 10.16 seconds
Started Jul 11 06:38:14 PM PDT 24
Finished Jul 11 06:38:26 PM PDT 24
Peak memory 221704 kb
Host smart-547cdb34-bbfd-4326-b531-399924209a72
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2604812542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.2604812542
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.3770575064
Short name T160
Test name
Test status
Simulation time 41782918714 ps
CPU time 110.91 seconds
Started Jul 11 06:38:17 PM PDT 24
Finished Jul 11 06:40:10 PM PDT 24
Peak memory 263652 kb
Host smart-9f0214fe-80a9-43b1-95fa-f332d4988bb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770575064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.3770575064
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.3427203926
Short name T737
Test name
Test status
Simulation time 13044301882 ps
CPU time 11.28 seconds
Started Jul 11 06:38:12 PM PDT 24
Finished Jul 11 06:38:24 PM PDT 24
Peak memory 216304 kb
Host smart-f9c6e1e1-45d2-4f52-8fdd-4ed2f1dd4903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427203926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.3427203926
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.2669146816
Short name T718
Test name
Test status
Simulation time 5468657423 ps
CPU time 16.62 seconds
Started Jul 11 06:38:14 PM PDT 24
Finished Jul 11 06:38:32 PM PDT 24
Peak memory 216336 kb
Host smart-a4917835-7162-4e0a-a8d6-f8a1f31cdfcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669146816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.2669146816
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.1686540547
Short name T4
Test name
Test status
Simulation time 123686027 ps
CPU time 1.56 seconds
Started Jul 11 06:38:13 PM PDT 24
Finished Jul 11 06:38:16 PM PDT 24
Peak memory 216112 kb
Host smart-2d41e3a9-23dc-4557-86d8-cf0b2422986d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686540547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.1686540547
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.2822941338
Short name T298
Test name
Test status
Simulation time 98691835 ps
CPU time 0.92 seconds
Started Jul 11 06:38:13 PM PDT 24
Finished Jul 11 06:38:16 PM PDT 24
Peak memory 206236 kb
Host smart-f31a0694-403c-47e0-8550-262200c38ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822941338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.2822941338
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.1756266796
Short name T412
Test name
Test status
Simulation time 6842949658 ps
CPU time 21.31 seconds
Started Jul 11 06:38:13 PM PDT 24
Finished Jul 11 06:38:35 PM PDT 24
Peak memory 232820 kb
Host smart-976292b6-2f36-4cea-8dc5-d000d666cd9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756266796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.1756266796
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.3499125352
Short name T669
Test name
Test status
Simulation time 44792449 ps
CPU time 0.76 seconds
Started Jul 11 06:38:26 PM PDT 24
Finished Jul 11 06:38:27 PM PDT 24
Peak memory 205504 kb
Host smart-072d1e92-1bf2-4d23-87e2-f4d16cc95605
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499125352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
3499125352
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.565657569
Short name T695
Test name
Test status
Simulation time 29093158 ps
CPU time 2.18 seconds
Started Jul 11 06:38:17 PM PDT 24
Finished Jul 11 06:38:22 PM PDT 24
Peak memory 223968 kb
Host smart-858f56d5-1e40-44c2-9a5c-027641d8c6f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565657569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.565657569
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.4077055725
Short name T306
Test name
Test status
Simulation time 47725082 ps
CPU time 0.76 seconds
Started Jul 11 06:38:14 PM PDT 24
Finished Jul 11 06:38:16 PM PDT 24
Peak memory 205612 kb
Host smart-9693264b-7a08-47be-b992-260137136e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077055725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.4077055725
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.53764312
Short name T387
Test name
Test status
Simulation time 29231058 ps
CPU time 0.75 seconds
Started Jul 11 06:38:24 PM PDT 24
Finished Jul 11 06:38:26 PM PDT 24
Peak memory 215812 kb
Host smart-c6cece09-596a-48b9-a762-68dd3ed8121d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53764312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.53764312
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.3607759668
Short name T206
Test name
Test status
Simulation time 90369614174 ps
CPU time 429.5 seconds
Started Jul 11 06:38:23 PM PDT 24
Finished Jul 11 06:45:33 PM PDT 24
Peak memory 267744 kb
Host smart-fc71f999-a1c7-4c23-8879-8f9900054d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607759668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.3607759668
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.1029029561
Short name T634
Test name
Test status
Simulation time 9267965779 ps
CPU time 22.9 seconds
Started Jul 11 06:38:28 PM PDT 24
Finished Jul 11 06:38:51 PM PDT 24
Peak memory 219512 kb
Host smart-8ae7a408-6d60-4886-adca-7b24677010c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029029561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.1029029561
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.3159124216
Short name T267
Test name
Test status
Simulation time 204167026 ps
CPU time 8.17 seconds
Started Jul 11 06:38:17 PM PDT 24
Finished Jul 11 06:38:28 PM PDT 24
Peak memory 224460 kb
Host smart-28f79501-f0d7-4888-8d04-2a3a41722f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159124216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.3159124216
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.4144676307
Short name T13
Test name
Test status
Simulation time 14525781471 ps
CPU time 119.08 seconds
Started Jul 11 06:38:17 PM PDT 24
Finished Jul 11 06:40:18 PM PDT 24
Peak memory 254088 kb
Host smart-bed92e7c-7b7b-4f4b-a53a-238be3ef8bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144676307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmd
s.4144676307
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.2069087441
Short name T176
Test name
Test status
Simulation time 963698101 ps
CPU time 13.38 seconds
Started Jul 11 06:38:16 PM PDT 24
Finished Jul 11 06:38:30 PM PDT 24
Peak memory 232712 kb
Host smart-a04d20a2-7621-400e-8848-08e46270133c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069087441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.2069087441
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.1904430926
Short name T311
Test name
Test status
Simulation time 1677434393 ps
CPU time 12.22 seconds
Started Jul 11 06:38:19 PM PDT 24
Finished Jul 11 06:38:33 PM PDT 24
Peak memory 249796 kb
Host smart-6548cbd4-a822-4839-90b6-ad9056e65057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904430926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.1904430926
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.1971281792
Short name T239
Test name
Test status
Simulation time 398996095 ps
CPU time 7.42 seconds
Started Jul 11 06:38:19 PM PDT 24
Finished Jul 11 06:38:28 PM PDT 24
Peak memory 240904 kb
Host smart-920007ff-d1c2-4eec-8ca8-e153c19af8a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971281792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.1971281792
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.3302608217
Short name T499
Test name
Test status
Simulation time 6666183782 ps
CPU time 19.32 seconds
Started Jul 11 06:38:16 PM PDT 24
Finished Jul 11 06:38:36 PM PDT 24
Peak memory 232820 kb
Host smart-49fc3499-a2ee-4a93-8e51-208f4672c306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302608217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.3302608217
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.723351062
Short name T541
Test name
Test status
Simulation time 816924044 ps
CPU time 5.54 seconds
Started Jul 11 06:38:24 PM PDT 24
Finished Jul 11 06:38:30 PM PDT 24
Peak memory 223056 kb
Host smart-419543f8-7125-401e-a0aa-a1741834eb15
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=723351062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dire
ct.723351062
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.355789915
Short name T924
Test name
Test status
Simulation time 37413776083 ps
CPU time 199.63 seconds
Started Jul 11 06:38:26 PM PDT 24
Finished Jul 11 06:41:47 PM PDT 24
Peak memory 264088 kb
Host smart-c2b7d2bf-5b07-41ce-8db0-3ece1b01cb2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355789915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stres
s_all.355789915
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.1417091985
Short name T988
Test name
Test status
Simulation time 11685054 ps
CPU time 0.74 seconds
Started Jul 11 06:38:17 PM PDT 24
Finished Jul 11 06:38:20 PM PDT 24
Peak memory 206016 kb
Host smart-bad38d2d-0f30-4d7c-b64e-6f8a90b9458b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417091985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.1417091985
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.2969762424
Short name T863
Test name
Test status
Simulation time 13595865 ps
CPU time 0.71 seconds
Started Jul 11 06:38:17 PM PDT 24
Finished Jul 11 06:38:20 PM PDT 24
Peak memory 205760 kb
Host smart-d774ea98-469a-4426-ad8d-5764ef9c78d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969762424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.2969762424
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.3348200752
Short name T817
Test name
Test status
Simulation time 160296135 ps
CPU time 1.74 seconds
Started Jul 11 06:38:19 PM PDT 24
Finished Jul 11 06:38:23 PM PDT 24
Peak memory 216272 kb
Host smart-4984ca90-bd71-4e14-98ea-c159479f2b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348200752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.3348200752
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.2870558428
Short name T843
Test name
Test status
Simulation time 330507809 ps
CPU time 0.78 seconds
Started Jul 11 06:38:17 PM PDT 24
Finished Jul 11 06:38:19 PM PDT 24
Peak memory 206000 kb
Host smart-32ae603f-cf28-4301-b56b-f4bf6e0ed492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870558428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.2870558428
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.768260639
Short name T644
Test name
Test status
Simulation time 2124002025 ps
CPU time 4.84 seconds
Started Jul 11 06:38:18 PM PDT 24
Finished Jul 11 06:38:25 PM PDT 24
Peak memory 232592 kb
Host smart-f1b8b07d-eb55-4461-b546-1068a2440cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768260639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.768260639
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.303048529
Short name T788
Test name
Test status
Simulation time 17118929 ps
CPU time 0.73 seconds
Started Jul 11 06:38:43 PM PDT 24
Finished Jul 11 06:38:45 PM PDT 24
Peak memory 204976 kb
Host smart-da5d1b57-6863-49ab-bb5e-d95be3adaa23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303048529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.303048529
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.2053928397
Short name T347
Test name
Test status
Simulation time 84160008 ps
CPU time 3.5 seconds
Started Jul 11 06:38:46 PM PDT 24
Finished Jul 11 06:38:50 PM PDT 24
Peak memory 232692 kb
Host smart-88ed2191-031d-47a1-8ba6-e3865f6ab9e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053928397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.2053928397
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.1369214206
Short name T454
Test name
Test status
Simulation time 16072425 ps
CPU time 0.82 seconds
Started Jul 11 06:38:26 PM PDT 24
Finished Jul 11 06:38:28 PM PDT 24
Peak memory 206632 kb
Host smart-8257e03a-6f02-4e35-9438-1ce5ba76c04d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369214206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.1369214206
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.3159253480
Short name T196
Test name
Test status
Simulation time 14693739486 ps
CPU time 97.47 seconds
Started Jul 11 06:38:44 PM PDT 24
Finished Jul 11 06:40:23 PM PDT 24
Peak memory 249216 kb
Host smart-1c2608f8-710a-432b-8440-878fd7d98346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159253480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.3159253480
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.2569670085
Short name T110
Test name
Test status
Simulation time 163298373457 ps
CPU time 147.76 seconds
Started Jul 11 06:38:40 PM PDT 24
Finished Jul 11 06:41:09 PM PDT 24
Peak memory 262604 kb
Host smart-44014c55-00cb-4a6b-8b3b-1ff330c4f04d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569670085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.2569670085
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.1263573963
Short name T811
Test name
Test status
Simulation time 1554175977 ps
CPU time 14.94 seconds
Started Jul 11 06:38:39 PM PDT 24
Finished Jul 11 06:38:54 PM PDT 24
Peak memory 217644 kb
Host smart-1097c7bf-e1f8-4c7e-aebc-833bc35be56a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263573963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.1263573963
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.3002134700
Short name T271
Test name
Test status
Simulation time 5755891216 ps
CPU time 17.52 seconds
Started Jul 11 06:38:42 PM PDT 24
Finished Jul 11 06:39:01 PM PDT 24
Peak memory 235472 kb
Host smart-25bc5619-2f3d-496a-8eb1-be9dc0d1c621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002134700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.3002134700
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.2431083828
Short name T340
Test name
Test status
Simulation time 3487042320 ps
CPU time 33.3 seconds
Started Jul 11 06:38:40 PM PDT 24
Finished Jul 11 06:39:14 PM PDT 24
Peak memory 240788 kb
Host smart-c5b82164-9521-4168-93d7-b0fbd7b0aa69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431083828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmd
s.2431083828
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.2363349487
Short name T245
Test name
Test status
Simulation time 107415511 ps
CPU time 2.61 seconds
Started Jul 11 06:38:40 PM PDT 24
Finished Jul 11 06:38:43 PM PDT 24
Peak memory 232668 kb
Host smart-7dd7e977-0dc0-4455-9447-9d533b60d394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363349487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.2363349487
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.1293959085
Short name T777
Test name
Test status
Simulation time 9302303555 ps
CPU time 18.07 seconds
Started Jul 11 06:38:41 PM PDT 24
Finished Jul 11 06:39:00 PM PDT 24
Peak memory 240092 kb
Host smart-f4fab511-46af-450b-90a3-550859c23a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293959085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.1293959085
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.109108886
Short name T388
Test name
Test status
Simulation time 27782903185 ps
CPU time 16.1 seconds
Started Jul 11 06:38:41 PM PDT 24
Finished Jul 11 06:38:58 PM PDT 24
Peak memory 232720 kb
Host smart-27e4e966-0a02-4685-91e5-c367ff229bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109108886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swap
.109108886
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.390045376
Short name T945
Test name
Test status
Simulation time 41448980949 ps
CPU time 11.11 seconds
Started Jul 11 06:38:35 PM PDT 24
Finished Jul 11 06:38:47 PM PDT 24
Peak memory 224600 kb
Host smart-7863c750-408e-4f1e-857c-3a1abe88c0b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390045376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.390045376
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.1146514157
Short name T305
Test name
Test status
Simulation time 3309313755 ps
CPU time 4.69 seconds
Started Jul 11 06:38:38 PM PDT 24
Finished Jul 11 06:38:44 PM PDT 24
Peak memory 220312 kb
Host smart-bf17a5d4-67fd-4b7e-8a47-d5ef6e6f07b6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1146514157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.1146514157
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.626977318
Short name T950
Test name
Test status
Simulation time 10746644651 ps
CPU time 169.88 seconds
Started Jul 11 06:38:39 PM PDT 24
Finished Jul 11 06:41:30 PM PDT 24
Peak memory 261412 kb
Host smart-e4e7505c-b950-4476-85f4-a5e8db4161c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626977318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stres
s_all.626977318
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.2032569593
Short name T552
Test name
Test status
Simulation time 5972545685 ps
CPU time 23.76 seconds
Started Jul 11 06:38:33 PM PDT 24
Finished Jul 11 06:38:58 PM PDT 24
Peak memory 220924 kb
Host smart-39687ee7-27ac-499f-83ca-9c927438ef7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032569593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.2032569593
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.3457582888
Short name T678
Test name
Test status
Simulation time 16566583336 ps
CPU time 13.61 seconds
Started Jul 11 06:38:34 PM PDT 24
Finished Jul 11 06:38:48 PM PDT 24
Peak memory 216568 kb
Host smart-2ec02e79-2c53-480f-aeba-bffc1d76ace5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457582888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.3457582888
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.1241617023
Short name T477
Test name
Test status
Simulation time 77508846 ps
CPU time 0.82 seconds
Started Jul 11 06:38:41 PM PDT 24
Finished Jul 11 06:38:43 PM PDT 24
Peak memory 206020 kb
Host smart-ced75841-e033-4391-ae77-fe599cbafd10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241617023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.1241617023
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.3612798046
Short name T848
Test name
Test status
Simulation time 83350511 ps
CPU time 0.94 seconds
Started Jul 11 06:38:42 PM PDT 24
Finished Jul 11 06:38:44 PM PDT 24
Peak memory 206180 kb
Host smart-4974d974-c282-45d4-a237-72c871f06c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612798046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.3612798046
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.2192625804
Short name T813
Test name
Test status
Simulation time 359515910 ps
CPU time 4.72 seconds
Started Jul 11 06:38:38 PM PDT 24
Finished Jul 11 06:38:43 PM PDT 24
Peak memory 232732 kb
Host smart-6a63b9ce-0c66-4b05-9d52-e34c1b1cc14a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192625804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.2192625804
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.598894480
Short name T583
Test name
Test status
Simulation time 14048074 ps
CPU time 0.72 seconds
Started Jul 11 06:38:48 PM PDT 24
Finished Jul 11 06:38:49 PM PDT 24
Peak memory 205540 kb
Host smart-1a46cb8f-fbe8-4030-b1fd-b6ad87a8adf0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598894480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.598894480
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.2589863320
Short name T1009
Test name
Test status
Simulation time 2251991096 ps
CPU time 8.14 seconds
Started Jul 11 06:38:43 PM PDT 24
Finished Jul 11 06:38:53 PM PDT 24
Peak memory 232760 kb
Host smart-adbf70dc-12f9-4f12-9d92-915cdd2d86f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589863320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.2589863320
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.3518670698
Short name T979
Test name
Test status
Simulation time 20765559 ps
CPU time 0.81 seconds
Started Jul 11 06:38:47 PM PDT 24
Finished Jul 11 06:38:48 PM PDT 24
Peak memory 206564 kb
Host smart-05e32061-1c6f-408b-9e86-6107e5470a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518670698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.3518670698
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.3836495217
Short name T555
Test name
Test status
Simulation time 30700222098 ps
CPU time 68.57 seconds
Started Jul 11 06:38:48 PM PDT 24
Finished Jul 11 06:39:57 PM PDT 24
Peak memory 256184 kb
Host smart-747dbfc7-11c8-4e5d-872f-e5228fe282b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836495217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.3836495217
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.1844705423
Short name T553
Test name
Test status
Simulation time 9371670683 ps
CPU time 96.52 seconds
Started Jul 11 06:38:49 PM PDT 24
Finished Jul 11 06:40:26 PM PDT 24
Peak memory 254568 kb
Host smart-50235f52-97c6-4e90-a532-e0bf136b1d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844705423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.1844705423
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.1530535960
Short name T490
Test name
Test status
Simulation time 8787434901 ps
CPU time 54.34 seconds
Started Jul 11 06:38:50 PM PDT 24
Finished Jul 11 06:39:46 PM PDT 24
Peak memory 224816 kb
Host smart-55c6f7f0-bb81-44eb-8806-e24944682e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530535960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.1530535960
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.1249846551
Short name T849
Test name
Test status
Simulation time 22075519223 ps
CPU time 46.23 seconds
Started Jul 11 06:38:45 PM PDT 24
Finished Jul 11 06:39:32 PM PDT 24
Peak memory 234932 kb
Host smart-5efbf12d-dbb6-4d91-9546-2f8919785681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249846551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.1249846551
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.3754825305
Short name T262
Test name
Test status
Simulation time 7098638583 ps
CPU time 29.73 seconds
Started Jul 11 06:38:50 PM PDT 24
Finished Jul 11 06:39:21 PM PDT 24
Peak memory 241040 kb
Host smart-c56e3f9f-9b7e-44cd-9557-ac717c1ef10c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754825305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmd
s.3754825305
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.1871960078
Short name T393
Test name
Test status
Simulation time 399643542 ps
CPU time 2.24 seconds
Started Jul 11 06:38:44 PM PDT 24
Finished Jul 11 06:38:47 PM PDT 24
Peak memory 222960 kb
Host smart-708ec30e-366c-46b7-abd9-6b5f12e21e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871960078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.1871960078
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.2091450900
Short name T808
Test name
Test status
Simulation time 7209186756 ps
CPU time 28.19 seconds
Started Jul 11 06:38:43 PM PDT 24
Finished Jul 11 06:39:13 PM PDT 24
Peak memory 232808 kb
Host smart-2496cf8f-daaf-4089-9020-8fadf5e205ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091450900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.2091450900
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.1609792085
Short name T180
Test name
Test status
Simulation time 736174707 ps
CPU time 4.14 seconds
Started Jul 11 06:38:45 PM PDT 24
Finished Jul 11 06:38:50 PM PDT 24
Peak memory 224516 kb
Host smart-87a9d6ad-be54-4d42-b8ca-f03202456afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609792085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.1609792085
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.2831751775
Short name T592
Test name
Test status
Simulation time 383822606 ps
CPU time 3.71 seconds
Started Jul 11 06:38:44 PM PDT 24
Finished Jul 11 06:38:48 PM PDT 24
Peak memory 232632 kb
Host smart-c5f5eed4-eda7-4aaf-b4e4-75fd72fa945a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831751775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.2831751775
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.1793996032
Short name T312
Test name
Test status
Simulation time 516456166 ps
CPU time 5.84 seconds
Started Jul 11 06:38:50 PM PDT 24
Finished Jul 11 06:38:57 PM PDT 24
Peak memory 222576 kb
Host smart-c9d40cdf-bd14-47c5-8454-e1fc8a27c6b7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1793996032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.1793996032
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.2136058801
Short name T44
Test name
Test status
Simulation time 90289024978 ps
CPU time 879.43 seconds
Started Jul 11 06:38:50 PM PDT 24
Finished Jul 11 06:53:31 PM PDT 24
Peak memory 263400 kb
Host smart-b8dc2048-db28-488a-ba70-83424abfba1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136058801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.2136058801
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.1817167260
Short name T396
Test name
Test status
Simulation time 33490907470 ps
CPU time 26.75 seconds
Started Jul 11 06:38:44 PM PDT 24
Finished Jul 11 06:39:11 PM PDT 24
Peak memory 216340 kb
Host smart-430426bb-d4ab-41a0-ae19-31d863706b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817167260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.1817167260
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.2478699665
Short name T901
Test name
Test status
Simulation time 1090858824 ps
CPU time 7.57 seconds
Started Jul 11 06:38:44 PM PDT 24
Finished Jul 11 06:38:53 PM PDT 24
Peak memory 216264 kb
Host smart-77b48958-481e-45fe-8cbf-d38ff8b525fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478699665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.2478699665
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.35858821
Short name T902
Test name
Test status
Simulation time 409227864 ps
CPU time 1.51 seconds
Started Jul 11 06:38:47 PM PDT 24
Finished Jul 11 06:38:49 PM PDT 24
Peak memory 216148 kb
Host smart-00f8d36d-8877-41ce-baea-6c200cbdd87d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35858821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.35858821
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.3959193940
Short name T358
Test name
Test status
Simulation time 28400394 ps
CPU time 0.73 seconds
Started Jul 11 06:38:43 PM PDT 24
Finished Jul 11 06:38:44 PM PDT 24
Peak memory 205952 kb
Host smart-97582212-1c18-4752-9d3a-90467b877f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959193940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.3959193940
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.4092349179
Short name T714
Test name
Test status
Simulation time 408462908 ps
CPU time 2.07 seconds
Started Jul 11 06:38:45 PM PDT 24
Finished Jul 11 06:38:48 PM PDT 24
Peak memory 224156 kb
Host smart-96e29515-8f8c-43da-95ea-3bbe6811ea20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092349179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.4092349179
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.355053935
Short name T599
Test name
Test status
Simulation time 12397194 ps
CPU time 0.71 seconds
Started Jul 11 06:38:53 PM PDT 24
Finished Jul 11 06:38:54 PM PDT 24
Peak memory 205892 kb
Host smart-e7fc5623-88f2-446b-97a0-48e46d0be4e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355053935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.355053935
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.799970899
Short name T494
Test name
Test status
Simulation time 1089711411 ps
CPU time 10.52 seconds
Started Jul 11 06:38:53 PM PDT 24
Finished Jul 11 06:39:04 PM PDT 24
Peak memory 224520 kb
Host smart-6aae231c-7c00-43ae-be51-4097a54b37e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799970899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.799970899
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.1139802824
Short name T297
Test name
Test status
Simulation time 15415267 ps
CPU time 0.76 seconds
Started Jul 11 06:38:47 PM PDT 24
Finished Jul 11 06:38:48 PM PDT 24
Peak memory 205612 kb
Host smart-4e96f056-bd6c-4b0c-b973-b4be467ff106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139802824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.1139802824
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.2136181380
Short name T193
Test name
Test status
Simulation time 12949303976 ps
CPU time 83.56 seconds
Started Jul 11 06:38:53 PM PDT 24
Finished Jul 11 06:40:18 PM PDT 24
Peak memory 238648 kb
Host smart-207f18a4-3b32-43e6-9e08-f3ec9705c763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136181380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.2136181380
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.422354624
Short name T182
Test name
Test status
Simulation time 7286681340 ps
CPU time 93.62 seconds
Started Jul 11 06:38:51 PM PDT 24
Finished Jul 11 06:40:26 PM PDT 24
Peak memory 264780 kb
Host smart-064f4065-9570-4c7e-a058-fd56393f8c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422354624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.422354624
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.1206610405
Short name T45
Test name
Test status
Simulation time 31564048067 ps
CPU time 269.36 seconds
Started Jul 11 06:38:53 PM PDT 24
Finished Jul 11 06:43:23 PM PDT 24
Peak memory 249284 kb
Host smart-701cb3e2-a26f-4914-8e5d-c71d4bcd17fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206610405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.1206610405
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.1307667472
Short name T670
Test name
Test status
Simulation time 1252906009 ps
CPU time 7.98 seconds
Started Jul 11 06:38:53 PM PDT 24
Finished Jul 11 06:39:03 PM PDT 24
Peak memory 224452 kb
Host smart-b38c96d4-83f9-4cb1-9d1b-e94bac0460e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307667472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.1307667472
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.1545941698
Short name T292
Test name
Test status
Simulation time 29422620 ps
CPU time 0.74 seconds
Started Jul 11 06:38:56 PM PDT 24
Finished Jul 11 06:38:57 PM PDT 24
Peak memory 215812 kb
Host smart-e81130e4-151f-4e61-a4a4-91fd082c9b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545941698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmd
s.1545941698
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.1004147962
Short name T900
Test name
Test status
Simulation time 9308188470 ps
CPU time 16.92 seconds
Started Jul 11 06:39:32 PM PDT 24
Finished Jul 11 06:39:50 PM PDT 24
Peak memory 224548 kb
Host smart-3dca6eaf-e650-487f-a883-8ab5d0932036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004147962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.1004147962
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.1296990703
Short name T731
Test name
Test status
Simulation time 1353700634 ps
CPU time 18.39 seconds
Started Jul 11 06:38:48 PM PDT 24
Finished Jul 11 06:39:08 PM PDT 24
Peak memory 240772 kb
Host smart-1540929f-9244-4c4d-a6c7-89300de6698b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296990703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.1296990703
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.2896267497
Short name T488
Test name
Test status
Simulation time 29673170 ps
CPU time 2.56 seconds
Started Jul 11 06:38:49 PM PDT 24
Finished Jul 11 06:38:52 PM PDT 24
Peak memory 232308 kb
Host smart-e5a0589c-23b3-4fb0-a7f5-1fcb6b17ef11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896267497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.2896267497
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.2620553890
Short name T803
Test name
Test status
Simulation time 6190639804 ps
CPU time 10.78 seconds
Started Jul 11 06:38:50 PM PDT 24
Finished Jul 11 06:39:02 PM PDT 24
Peak memory 224612 kb
Host smart-980f1e4a-f500-4af7-ae07-3260dc05e31f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620553890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.2620553890
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.1612754327
Short name T864
Test name
Test status
Simulation time 944467798 ps
CPU time 6.47 seconds
Started Jul 11 06:38:53 PM PDT 24
Finished Jul 11 06:39:01 PM PDT 24
Peak memory 219108 kb
Host smart-bf5761b9-b3f5-4811-8a39-d672de23570d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1612754327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.1612754327
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.3758372353
Short name T778
Test name
Test status
Simulation time 49007319018 ps
CPU time 258.81 seconds
Started Jul 11 06:38:53 PM PDT 24
Finished Jul 11 06:43:13 PM PDT 24
Peak memory 256168 kb
Host smart-584eefc0-b20f-43c1-9c1b-832d6dad417d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758372353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.3758372353
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.273951469
Short name T674
Test name
Test status
Simulation time 7344236380 ps
CPU time 42.89 seconds
Started Jul 11 06:38:49 PM PDT 24
Finished Jul 11 06:39:33 PM PDT 24
Peak memory 216428 kb
Host smart-39c7e8ab-7114-484c-91bf-1262a95d61f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273951469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.273951469
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.656443499
Short name T636
Test name
Test status
Simulation time 3504848035 ps
CPU time 5.71 seconds
Started Jul 11 06:38:50 PM PDT 24
Finished Jul 11 06:38:56 PM PDT 24
Peak memory 216332 kb
Host smart-0cf2d27f-8af0-4b20-a715-739ea29759ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656443499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.656443499
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.3487478548
Short name T337
Test name
Test status
Simulation time 421050049 ps
CPU time 8.88 seconds
Started Jul 11 06:38:51 PM PDT 24
Finished Jul 11 06:39:01 PM PDT 24
Peak memory 216208 kb
Host smart-6424b6a0-07fd-42eb-8850-065f0ea10ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487478548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.3487478548
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.4131479102
Short name T564
Test name
Test status
Simulation time 77795483 ps
CPU time 0.71 seconds
Started Jul 11 06:38:47 PM PDT 24
Finished Jul 11 06:38:49 PM PDT 24
Peak memory 206000 kb
Host smart-12149738-cef7-417f-93f9-a8fbd406503d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131479102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.4131479102
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.722043786
Short name T463
Test name
Test status
Simulation time 10115245128 ps
CPU time 35.46 seconds
Started Jul 11 06:38:52 PM PDT 24
Finished Jul 11 06:39:29 PM PDT 24
Peak memory 250644 kb
Host smart-36fcbc48-bc73-4150-b182-af69a07bcfd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722043786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.722043786
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.1913309307
Short name T375
Test name
Test status
Simulation time 11323850 ps
CPU time 0.76 seconds
Started Jul 11 06:39:01 PM PDT 24
Finished Jul 11 06:39:03 PM PDT 24
Peak memory 205576 kb
Host smart-a7dca21c-0418-4ef5-ad93-30085f9c7bb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913309307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
1913309307
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.864824525
Short name T760
Test name
Test status
Simulation time 342542877 ps
CPU time 2.9 seconds
Started Jul 11 06:39:03 PM PDT 24
Finished Jul 11 06:39:07 PM PDT 24
Peak memory 224384 kb
Host smart-6cc9be11-0f3b-4e9e-8eba-9343e2b9878a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864824525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.864824525
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.3628208102
Short name T417
Test name
Test status
Simulation time 14368354 ps
CPU time 0.75 seconds
Started Jul 11 06:38:52 PM PDT 24
Finished Jul 11 06:38:54 PM PDT 24
Peak memory 206588 kb
Host smart-a8150f43-0079-4eab-824b-1532bf0d5f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628208102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.3628208102
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.2278730361
Short name T730
Test name
Test status
Simulation time 39733087693 ps
CPU time 157.45 seconds
Started Jul 11 06:38:57 PM PDT 24
Finished Jul 11 06:41:36 PM PDT 24
Peak memory 250200 kb
Host smart-7f479541-d6d7-4a9c-94cd-aa9ecd26ffac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278730361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.2278730361
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.1509264532
Short name T640
Test name
Test status
Simulation time 10130654227 ps
CPU time 83.8 seconds
Started Jul 11 06:38:57 PM PDT 24
Finished Jul 11 06:40:22 PM PDT 24
Peak memory 253232 kb
Host smart-fcac4e72-3a38-4f82-8e82-5a2d1cd6ce8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509264532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.1509264532
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.1039704595
Short name T343
Test name
Test status
Simulation time 2699627802 ps
CPU time 71.32 seconds
Started Jul 11 06:38:57 PM PDT 24
Finished Jul 11 06:40:09 PM PDT 24
Peak memory 257444 kb
Host smart-404388f0-13cb-4004-872f-49dc44be0385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039704595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.1039704595
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.2127439292
Short name T966
Test name
Test status
Simulation time 1240195711 ps
CPU time 20.51 seconds
Started Jul 11 06:38:57 PM PDT 24
Finished Jul 11 06:39:19 PM PDT 24
Peak memory 237172 kb
Host smart-c396697f-92d9-4d80-b5aa-28045ffdb561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127439292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.2127439292
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.214178901
Short name T208
Test name
Test status
Simulation time 44666109206 ps
CPU time 54.78 seconds
Started Jul 11 06:38:59 PM PDT 24
Finished Jul 11 06:39:55 PM PDT 24
Peak memory 237300 kb
Host smart-98cd91f3-d4bf-4e04-a96e-e90f2285a938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214178901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmds
.214178901
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.360004791
Short name T556
Test name
Test status
Simulation time 13020148554 ps
CPU time 39.05 seconds
Started Jul 11 06:38:56 PM PDT 24
Finished Jul 11 06:39:35 PM PDT 24
Peak memory 224600 kb
Host smart-ab7c408f-fd77-4d63-b061-d2e4bb26bb79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360004791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.360004791
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.1564241669
Short name T642
Test name
Test status
Simulation time 1477724076 ps
CPU time 8.15 seconds
Started Jul 11 06:38:57 PM PDT 24
Finished Jul 11 06:39:07 PM PDT 24
Peak memory 236704 kb
Host smart-af8ca5a0-bd28-4165-b6da-0203d7084259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564241669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.1564241669
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.3861376901
Short name T233
Test name
Test status
Simulation time 792408864 ps
CPU time 6.57 seconds
Started Jul 11 06:38:59 PM PDT 24
Finished Jul 11 06:39:07 PM PDT 24
Peak memory 240764 kb
Host smart-bec5e405-955d-48da-b56a-94e375b11cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861376901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.3861376901
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.3395608565
Short name T570
Test name
Test status
Simulation time 1601000536 ps
CPU time 2.36 seconds
Started Jul 11 06:38:55 PM PDT 24
Finished Jul 11 06:38:58 PM PDT 24
Peak memory 224388 kb
Host smart-e5d1a92c-15ac-4cf2-b843-5fb463cd013d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395608565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.3395608565
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.3133227946
Short name T505
Test name
Test status
Simulation time 1978535221 ps
CPU time 8.63 seconds
Started Jul 11 06:38:58 PM PDT 24
Finished Jul 11 06:39:07 PM PDT 24
Peak memory 223288 kb
Host smart-d3ebb341-d4e2-4983-bd29-0ea8eb8cfc4e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3133227946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.3133227946
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.317662483
Short name T138
Test name
Test status
Simulation time 4005452330 ps
CPU time 13.53 seconds
Started Jul 11 06:39:02 PM PDT 24
Finished Jul 11 06:39:17 PM PDT 24
Peak memory 239680 kb
Host smart-eae161c5-b39b-4af3-9a00-6447dba7a9b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317662483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stres
s_all.317662483
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.3828212981
Short name T447
Test name
Test status
Simulation time 1173380359 ps
CPU time 8.76 seconds
Started Jul 11 06:38:53 PM PDT 24
Finished Jul 11 06:39:03 PM PDT 24
Peak memory 216268 kb
Host smart-c8b9745d-ea41-44b3-8d26-7ecedd3a4d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828212981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.3828212981
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.3606917830
Short name T376
Test name
Test status
Simulation time 7587749100 ps
CPU time 3.93 seconds
Started Jul 11 06:38:52 PM PDT 24
Finished Jul 11 06:38:57 PM PDT 24
Peak memory 216332 kb
Host smart-ff377619-96e1-4494-bfee-9d1b06ada8ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606917830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.3606917830
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.3627548441
Short name T330
Test name
Test status
Simulation time 25289865 ps
CPU time 0.93 seconds
Started Jul 11 06:38:56 PM PDT 24
Finished Jul 11 06:38:58 PM PDT 24
Peak memory 207024 kb
Host smart-0b3401cb-6263-4c11-9896-4253b6ae90bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627548441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.3627548441
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.657357043
Short name T835
Test name
Test status
Simulation time 93598355 ps
CPU time 0.88 seconds
Started Jul 11 06:38:56 PM PDT 24
Finished Jul 11 06:38:58 PM PDT 24
Peak memory 206288 kb
Host smart-5a4d867c-e57a-4104-837e-b54b3a875eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657357043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.657357043
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.3682668546
Short name T559
Test name
Test status
Simulation time 2758993546 ps
CPU time 11.72 seconds
Started Jul 11 06:38:56 PM PDT 24
Finished Jul 11 06:39:09 PM PDT 24
Peak memory 239812 kb
Host smart-a5dba12c-693c-4232-83be-c3db278d1004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682668546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.3682668546
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.3469930852
Short name T418
Test name
Test status
Simulation time 138634254 ps
CPU time 0.72 seconds
Started Jul 11 06:34:57 PM PDT 24
Finished Jul 11 06:34:59 PM PDT 24
Peak memory 205536 kb
Host smart-fe7d148b-094c-40df-9b8e-2ba303590ab7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469930852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.3
469930852
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.1656252330
Short name T228
Test name
Test status
Simulation time 179158236 ps
CPU time 3.47 seconds
Started Jul 11 06:34:53 PM PDT 24
Finished Jul 11 06:34:58 PM PDT 24
Peak memory 232632 kb
Host smart-d26ac731-cd0f-4f2c-b570-bcccb17283d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656252330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.1656252330
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.3851939944
Short name T440
Test name
Test status
Simulation time 17846736 ps
CPU time 0.79 seconds
Started Jul 11 06:34:50 PM PDT 24
Finished Jul 11 06:34:52 PM PDT 24
Peak memory 206640 kb
Host smart-5a072d14-282e-4bbf-b026-1b7ec813f17e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851939944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.3851939944
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.2466733053
Short name T219
Test name
Test status
Simulation time 176604006395 ps
CPU time 323.78 seconds
Started Jul 11 06:34:57 PM PDT 24
Finished Jul 11 06:40:22 PM PDT 24
Peak memory 267028 kb
Host smart-6c4cfe24-83ba-4794-b8af-6f1c078ac608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466733053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.2466733053
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.778133014
Short name T259
Test name
Test status
Simulation time 114083748092 ps
CPU time 472.97 seconds
Started Jul 11 06:34:56 PM PDT 24
Finished Jul 11 06:42:50 PM PDT 24
Peak memory 263424 kb
Host smart-ef6aa9e4-46eb-40a5-ab7f-3ce1559d2a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778133014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.778133014
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.280367185
Short name T366
Test name
Test status
Simulation time 2356950232 ps
CPU time 38.77 seconds
Started Jul 11 06:34:56 PM PDT 24
Finished Jul 11 06:35:36 PM PDT 24
Peak memory 249276 kb
Host smart-04b54b0c-1cec-4bbe-9762-c0fa95b6c729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280367185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle.
280367185
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.2546804652
Short name T557
Test name
Test status
Simulation time 2505024604 ps
CPU time 6.96 seconds
Started Jul 11 06:34:52 PM PDT 24
Finished Jul 11 06:35:00 PM PDT 24
Peak memory 224588 kb
Host smart-eba91645-26eb-4f6e-83f5-a000324bda80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546804652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.2546804652
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.178839601
Short name T362
Test name
Test status
Simulation time 4261822232 ps
CPU time 37.98 seconds
Started Jul 11 06:34:54 PM PDT 24
Finished Jul 11 06:35:33 PM PDT 24
Peak memory 241000 kb
Host smart-f9716e37-e5d9-4dd6-9462-f3779c0415f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178839601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds.
178839601
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.2929798775
Short name T189
Test name
Test status
Simulation time 510558417 ps
CPU time 3.07 seconds
Started Jul 11 06:34:50 PM PDT 24
Finished Jul 11 06:34:54 PM PDT 24
Peak memory 224456 kb
Host smart-b88b075e-ea43-4b70-82a5-ab6460892b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929798775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.2929798775
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.704783026
Short name T992
Test name
Test status
Simulation time 3678678453 ps
CPU time 24.87 seconds
Started Jul 11 06:34:53 PM PDT 24
Finished Jul 11 06:35:19 PM PDT 24
Peak memory 232764 kb
Host smart-3f77571c-ecd6-4dfd-b280-d00c00fc39a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704783026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.704783026
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.1483392196
Short name T705
Test name
Test status
Simulation time 762018017 ps
CPU time 3.59 seconds
Started Jul 11 06:34:50 PM PDT 24
Finished Jul 11 06:34:55 PM PDT 24
Peak memory 232728 kb
Host smart-8b26f18a-902c-438b-ba09-001e62ce4a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483392196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.1483392196
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.1922760967
Short name T638
Test name
Test status
Simulation time 228281934 ps
CPU time 2.21 seconds
Started Jul 11 06:34:49 PM PDT 24
Finished Jul 11 06:34:53 PM PDT 24
Peak memory 223960 kb
Host smart-0d7b9186-12d7-40a1-a916-2092165fbc7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922760967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.1922760967
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.1687701218
Short name T741
Test name
Test status
Simulation time 622635661 ps
CPU time 7.73 seconds
Started Jul 11 06:34:53 PM PDT 24
Finished Jul 11 06:35:02 PM PDT 24
Peak memory 220552 kb
Host smart-45af9ad5-88d5-405a-8f14-c8d648c50202
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1687701218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.1687701218
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.365835489
Short name T829
Test name
Test status
Simulation time 71440030842 ps
CPU time 347.75 seconds
Started Jul 11 06:34:54 PM PDT 24
Finished Jul 11 06:40:43 PM PDT 24
Peak memory 240096 kb
Host smart-be6ed475-45b4-42a3-8824-5728aca7c08f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365835489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stress
_all.365835489
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.3096104404
Short name T400
Test name
Test status
Simulation time 60327896126 ps
CPU time 21.1 seconds
Started Jul 11 06:34:50 PM PDT 24
Finished Jul 11 06:35:13 PM PDT 24
Peak memory 216336 kb
Host smart-0f4f1063-53bb-45dc-aaf6-57c67a39aaa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096104404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.3096104404
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.546253251
Short name T467
Test name
Test status
Simulation time 709962299 ps
CPU time 5.25 seconds
Started Jul 11 06:34:49 PM PDT 24
Finished Jul 11 06:34:56 PM PDT 24
Peak memory 216244 kb
Host smart-1d070d3a-fd8a-4b8f-9aa4-ac38d29c0371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546253251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.546253251
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.784661660
Short name T683
Test name
Test status
Simulation time 760001595 ps
CPU time 3.93 seconds
Started Jul 11 06:34:49 PM PDT 24
Finished Jul 11 06:34:54 PM PDT 24
Peak memory 216260 kb
Host smart-d6e3750a-5c02-4928-baca-682e26a622e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784661660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.784661660
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.3775654679
Short name T500
Test name
Test status
Simulation time 352650257 ps
CPU time 0.82 seconds
Started Jul 11 06:34:49 PM PDT 24
Finished Jul 11 06:34:52 PM PDT 24
Peak memory 205976 kb
Host smart-f5c12eb4-9e50-4691-b53a-ac031d26043b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775654679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.3775654679
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.996071447
Short name T563
Test name
Test status
Simulation time 118787980 ps
CPU time 2.06 seconds
Started Jul 11 06:34:55 PM PDT 24
Finished Jul 11 06:34:58 PM PDT 24
Peak memory 224076 kb
Host smart-4db4ea41-b31e-40cb-9466-4ee79f792da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996071447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.996071447
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.1826075278
Short name T606
Test name
Test status
Simulation time 21763639 ps
CPU time 0.77 seconds
Started Jul 11 06:39:13 PM PDT 24
Finished Jul 11 06:39:14 PM PDT 24
Peak memory 204896 kb
Host smart-022d0cdb-31eb-49c0-8711-a1319e7ee74a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826075278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
1826075278
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.4252834919
Short name T699
Test name
Test status
Simulation time 1335038412 ps
CPU time 5.52 seconds
Started Jul 11 06:39:14 PM PDT 24
Finished Jul 11 06:39:20 PM PDT 24
Peak memory 232692 kb
Host smart-98a4338f-efea-44ff-ae1a-d3eaccc2fe06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252834919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.4252834919
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.2308437307
Short name T370
Test name
Test status
Simulation time 37978227 ps
CPU time 0.85 seconds
Started Jul 11 06:39:02 PM PDT 24
Finished Jul 11 06:39:03 PM PDT 24
Peak memory 206628 kb
Host smart-0579b757-810f-40ef-afa4-9a08290b2794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308437307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.2308437307
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.4186524885
Short name T532
Test name
Test status
Simulation time 59203376 ps
CPU time 0.79 seconds
Started Jul 11 06:39:06 PM PDT 24
Finished Jul 11 06:39:07 PM PDT 24
Peak memory 215780 kb
Host smart-05a2dcea-e820-4d6a-8f42-f90545bb1dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186524885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.4186524885
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.3811089457
Short name T710
Test name
Test status
Simulation time 7432569058 ps
CPU time 66.02 seconds
Started Jul 11 06:39:12 PM PDT 24
Finished Jul 11 06:40:19 PM PDT 24
Peak memory 235228 kb
Host smart-9e7f0e80-7000-4e01-addd-bd89461da33a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811089457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.3811089457
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.941653126
Short name T186
Test name
Test status
Simulation time 165659322218 ps
CPU time 364.57 seconds
Started Jul 11 06:39:14 PM PDT 24
Finished Jul 11 06:45:19 PM PDT 24
Peak memory 254900 kb
Host smart-648ed079-a60f-4f9a-a464-fe6f592245f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941653126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idle
.941653126
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.1383062386
Short name T51
Test name
Test status
Simulation time 160135173 ps
CPU time 5.65 seconds
Started Jul 11 06:39:14 PM PDT 24
Finished Jul 11 06:39:21 PM PDT 24
Peak memory 249084 kb
Host smart-d5b450c0-789a-472b-aec9-97e8485398ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383062386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.1383062386
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.101469385
Short name T850
Test name
Test status
Simulation time 17226177934 ps
CPU time 134.57 seconds
Started Jul 11 06:39:16 PM PDT 24
Finished Jul 11 06:41:31 PM PDT 24
Peak memory 256956 kb
Host smart-9d020ef9-d173-4056-bf53-5f39a801767e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101469385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmds
.101469385
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.4025065930
Short name T177
Test name
Test status
Simulation time 1782833851 ps
CPU time 16.99 seconds
Started Jul 11 06:39:06 PM PDT 24
Finished Jul 11 06:39:24 PM PDT 24
Peak memory 224508 kb
Host smart-7ec66622-fdf8-4201-a55f-1ffca124de9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025065930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.4025065930
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.1950286387
Short name T837
Test name
Test status
Simulation time 22360365205 ps
CPU time 150.36 seconds
Started Jul 11 06:39:06 PM PDT 24
Finished Jul 11 06:41:37 PM PDT 24
Peak memory 232804 kb
Host smart-77afcf71-ee97-461b-9b9d-37c24159aac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950286387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.1950286387
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.1698273118
Short name T607
Test name
Test status
Simulation time 109673868 ps
CPU time 2.52 seconds
Started Jul 11 06:39:12 PM PDT 24
Finished Jul 11 06:39:15 PM PDT 24
Peak memory 232328 kb
Host smart-a02609be-bb4d-4fef-87d3-54a2a8fcdad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698273118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.1698273118
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.2040459316
Short name T344
Test name
Test status
Simulation time 146465180 ps
CPU time 2.45 seconds
Started Jul 11 06:39:14 PM PDT 24
Finished Jul 11 06:39:18 PM PDT 24
Peak memory 232744 kb
Host smart-0ce95f62-8e8d-4996-8ecf-f4f45fe24d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040459316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.2040459316
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.2489316037
Short name T521
Test name
Test status
Simulation time 495783776 ps
CPU time 3.87 seconds
Started Jul 11 06:39:14 PM PDT 24
Finished Jul 11 06:39:19 PM PDT 24
Peak memory 218788 kb
Host smart-5d001a78-77a5-4898-8867-55e568b3cdef
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2489316037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.2489316037
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.783363213
Short name T862
Test name
Test status
Simulation time 344515963826 ps
CPU time 992.06 seconds
Started Jul 11 06:39:14 PM PDT 24
Finished Jul 11 06:55:47 PM PDT 24
Peak memory 281616 kb
Host smart-e22b9e1a-f998-4e94-b9bf-3e7c910790ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783363213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stres
s_all.783363213
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.2595317345
Short name T49
Test name
Test status
Simulation time 10264117830 ps
CPU time 17.11 seconds
Started Jul 11 06:39:02 PM PDT 24
Finished Jul 11 06:39:21 PM PDT 24
Peak memory 216320 kb
Host smart-4a6cc8d6-249b-4f87-911f-d3e8f94a2ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595317345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.2595317345
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.4190655223
Short name T504
Test name
Test status
Simulation time 26610516 ps
CPU time 0.68 seconds
Started Jul 11 06:39:01 PM PDT 24
Finished Jul 11 06:39:02 PM PDT 24
Peak memory 205716 kb
Host smart-285b4c5d-4a32-4f45-8666-e08677aa8ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190655223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.4190655223
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.4176901964
Short name T1005
Test name
Test status
Simulation time 484981183 ps
CPU time 1.6 seconds
Started Jul 11 06:39:03 PM PDT 24
Finished Jul 11 06:39:05 PM PDT 24
Peak memory 216268 kb
Host smart-3527c956-24d3-4a12-b3f1-e2a54d70d113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176901964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.4176901964
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.2222938214
Short name T529
Test name
Test status
Simulation time 34791324 ps
CPU time 0.71 seconds
Started Jul 11 06:39:02 PM PDT 24
Finished Jul 11 06:39:04 PM PDT 24
Peak memory 205672 kb
Host smart-8a627a79-7cad-4d16-87b8-4970e95d6278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222938214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.2222938214
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.1485803679
Short name T955
Test name
Test status
Simulation time 1654259138 ps
CPU time 7.46 seconds
Started Jul 11 06:39:12 PM PDT 24
Finished Jul 11 06:39:20 PM PDT 24
Peak memory 224460 kb
Host smart-c3015eb3-fe84-4857-b359-a1a5ad4b5132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485803679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.1485803679
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.2033597455
Short name T625
Test name
Test status
Simulation time 94407470 ps
CPU time 0.72 seconds
Started Jul 11 06:39:32 PM PDT 24
Finished Jul 11 06:39:33 PM PDT 24
Peak memory 205504 kb
Host smart-6ec56390-0dad-444c-999b-132e7b77500f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033597455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
2033597455
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.3807947314
Short name T744
Test name
Test status
Simulation time 168231786 ps
CPU time 3.91 seconds
Started Jul 11 06:39:24 PM PDT 24
Finished Jul 11 06:39:28 PM PDT 24
Peak memory 232692 kb
Host smart-4a612fe7-7a0f-4361-a60f-330f8b252b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807947314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.3807947314
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.3206245580
Short name T140
Test name
Test status
Simulation time 19293968 ps
CPU time 0.78 seconds
Started Jul 11 06:39:15 PM PDT 24
Finished Jul 11 06:39:17 PM PDT 24
Peak memory 206624 kb
Host smart-3a2b2353-d06d-4b97-9400-b5c129c99766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206245580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.3206245580
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.382219657
Short name T877
Test name
Test status
Simulation time 77972050159 ps
CPU time 186.39 seconds
Started Jul 11 06:39:23 PM PDT 24
Finished Jul 11 06:42:30 PM PDT 24
Peak memory 254472 kb
Host smart-e8d0146f-2a28-4903-a9f6-c6ca0ed30f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382219657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.382219657
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.1406890614
Short name T226
Test name
Test status
Simulation time 3140923948 ps
CPU time 28 seconds
Started Jul 11 06:39:24 PM PDT 24
Finished Jul 11 06:39:53 PM PDT 24
Peak memory 224616 kb
Host smart-95a11e44-1565-49b1-83ba-52865e3e35a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406890614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.1406890614
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.2499877613
Short name T836
Test name
Test status
Simulation time 12381374810 ps
CPU time 59.09 seconds
Started Jul 11 06:39:22 PM PDT 24
Finished Jul 11 06:40:22 PM PDT 24
Peak memory 252936 kb
Host smart-a3953005-addf-4308-941f-7a54da9e8e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499877613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.2499877613
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.2149810394
Short name T572
Test name
Test status
Simulation time 9084860828 ps
CPU time 31.07 seconds
Started Jul 11 06:39:20 PM PDT 24
Finished Jul 11 06:39:52 PM PDT 24
Peak memory 239832 kb
Host smart-460311ad-131d-4b31-9143-38231cb605f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149810394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.2149810394
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.2251633472
Short name T629
Test name
Test status
Simulation time 31640655521 ps
CPU time 50.17 seconds
Started Jul 11 06:39:18 PM PDT 24
Finished Jul 11 06:40:09 PM PDT 24
Peak memory 240988 kb
Host smart-2b205678-792f-4a5f-9f65-0903f219b5fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251633472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmd
s.2251633472
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.3349949625
Short name T736
Test name
Test status
Simulation time 983829272 ps
CPU time 11.41 seconds
Started Jul 11 06:39:19 PM PDT 24
Finished Jul 11 06:39:31 PM PDT 24
Peak memory 218796 kb
Host smart-d07f823f-fb4b-49bc-a99a-582c6678afaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349949625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.3349949625
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.2918597784
Short name T834
Test name
Test status
Simulation time 3675378092 ps
CPU time 15.77 seconds
Started Jul 11 06:39:19 PM PDT 24
Finished Jul 11 06:39:36 PM PDT 24
Peak memory 239796 kb
Host smart-6c86cd17-411a-4341-ab61-8656112c59b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918597784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.2918597784
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.378485284
Short name T484
Test name
Test status
Simulation time 2861291442 ps
CPU time 9.38 seconds
Started Jul 11 06:39:20 PM PDT 24
Finished Jul 11 06:39:30 PM PDT 24
Peak memory 248200 kb
Host smart-36677fac-7349-4214-bb47-b60fc84c4971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378485284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swap
.378485284
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.834553935
Short name T586
Test name
Test status
Simulation time 466777598 ps
CPU time 3.72 seconds
Started Jul 11 06:39:17 PM PDT 24
Finished Jul 11 06:39:21 PM PDT 24
Peak memory 232720 kb
Host smart-cd16552c-ba91-4245-b1e2-7db4c14f13aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834553935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.834553935
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.3432072606
Short name T785
Test name
Test status
Simulation time 346250865 ps
CPU time 5.42 seconds
Started Jul 11 06:39:17 PM PDT 24
Finished Jul 11 06:39:23 PM PDT 24
Peak memory 220512 kb
Host smart-49b4fc2b-5aa7-44ec-bdc0-c2d00ce7ca93
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3432072606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.3432072606
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.852694681
Short name T18
Test name
Test status
Simulation time 143611234002 ps
CPU time 504.42 seconds
Started Jul 11 06:39:23 PM PDT 24
Finished Jul 11 06:47:48 PM PDT 24
Peak memory 255544 kb
Host smart-6f97ab5b-bfb4-4635-b6d2-71f023d732db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852694681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stres
s_all.852694681
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.1362296851
Short name T588
Test name
Test status
Simulation time 26953766763 ps
CPU time 37.05 seconds
Started Jul 11 06:39:14 PM PDT 24
Finished Jul 11 06:39:52 PM PDT 24
Peak memory 216388 kb
Host smart-20879eae-6e49-4492-8712-7d52f733e9bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362296851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.1362296851
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.730594485
Short name T745
Test name
Test status
Simulation time 2197627365 ps
CPU time 4.18 seconds
Started Jul 11 06:39:17 PM PDT 24
Finished Jul 11 06:39:22 PM PDT 24
Peak memory 216328 kb
Host smart-e669c6d4-c853-4b3d-bafd-da751e813dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730594485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.730594485
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.3721760153
Short name T566
Test name
Test status
Simulation time 374942911 ps
CPU time 5.92 seconds
Started Jul 11 06:39:16 PM PDT 24
Finished Jul 11 06:39:22 PM PDT 24
Peak memory 216288 kb
Host smart-eda33171-0aef-4d40-a1ae-07b55a806bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721760153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.3721760153
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.2911191025
Short name T663
Test name
Test status
Simulation time 51614814 ps
CPU time 0.8 seconds
Started Jul 11 06:39:17 PM PDT 24
Finished Jul 11 06:39:19 PM PDT 24
Peak memory 206052 kb
Host smart-2d927b78-4781-4427-9b13-a74f9a1a654f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911191025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.2911191025
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.2861458744
Short name T934
Test name
Test status
Simulation time 240522233 ps
CPU time 3.88 seconds
Started Jul 11 06:39:18 PM PDT 24
Finished Jul 11 06:39:23 PM PDT 24
Peak memory 232640 kb
Host smart-8ee4717b-5184-426b-be21-2badebf146f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861458744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.2861458744
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.2643052182
Short name T560
Test name
Test status
Simulation time 13733447 ps
CPU time 0.76 seconds
Started Jul 11 06:39:28 PM PDT 24
Finished Jul 11 06:39:29 PM PDT 24
Peak memory 204896 kb
Host smart-42284fda-bab9-401d-aa07-0985d9b3fc70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643052182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
2643052182
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.3331127556
Short name T338
Test name
Test status
Simulation time 1044432066 ps
CPU time 11.27 seconds
Started Jul 11 06:39:30 PM PDT 24
Finished Jul 11 06:39:42 PM PDT 24
Peak memory 232620 kb
Host smart-1aa0f908-7b44-46b7-a540-5332ed3245bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331127556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.3331127556
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.865987458
Short name T415
Test name
Test status
Simulation time 16324086 ps
CPU time 0.75 seconds
Started Jul 11 06:39:23 PM PDT 24
Finished Jul 11 06:39:24 PM PDT 24
Peak memory 206892 kb
Host smart-999f04cd-0159-442e-b2ff-d4e81d85410d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865987458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.865987458
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.1078699308
Short name T549
Test name
Test status
Simulation time 25178662162 ps
CPU time 186.71 seconds
Started Jul 11 06:39:27 PM PDT 24
Finished Jul 11 06:42:34 PM PDT 24
Peak memory 250680 kb
Host smart-ac2def65-4d5a-4c09-8968-b5fcdbdcfd79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078699308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.1078699308
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.1480647934
Short name T591
Test name
Test status
Simulation time 14971443852 ps
CPU time 33.08 seconds
Started Jul 11 06:39:29 PM PDT 24
Finished Jul 11 06:40:03 PM PDT 24
Peak memory 232900 kb
Host smart-2bff17c0-75f1-474a-9940-034b0f0f5e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480647934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.1480647934
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.347213544
Short name T739
Test name
Test status
Simulation time 39117090050 ps
CPU time 221.88 seconds
Started Jul 11 06:39:30 PM PDT 24
Finished Jul 11 06:43:12 PM PDT 24
Peak memory 249280 kb
Host smart-2c9a16aa-4471-4503-b66c-98b6e3e1c8d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347213544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idle
.347213544
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.834512159
Short name T1008
Test name
Test status
Simulation time 1557436740 ps
CPU time 25.3 seconds
Started Jul 11 06:39:26 PM PDT 24
Finished Jul 11 06:39:52 PM PDT 24
Peak memory 240816 kb
Host smart-bae9525d-c1b1-4c60-90de-9bb085eb3b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834512159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.834512159
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.1898454603
Short name T514
Test name
Test status
Simulation time 6074444705 ps
CPU time 61.55 seconds
Started Jul 11 06:39:27 PM PDT 24
Finished Jul 11 06:40:29 PM PDT 24
Peak memory 252316 kb
Host smart-56fe2198-c0af-4435-8dac-69242ba324b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898454603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmd
s.1898454603
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.2107081200
Short name T828
Test name
Test status
Simulation time 165027547 ps
CPU time 3.36 seconds
Started Jul 11 06:39:28 PM PDT 24
Finished Jul 11 06:39:32 PM PDT 24
Peak memory 224396 kb
Host smart-3c99448e-b8ed-4ca0-8ee2-f9ce0653305a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107081200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.2107081200
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.2003437026
Short name T598
Test name
Test status
Simulation time 3782854441 ps
CPU time 36.06 seconds
Started Jul 11 06:39:24 PM PDT 24
Finished Jul 11 06:40:01 PM PDT 24
Peak memory 232828 kb
Host smart-3852690e-f3f9-4fb1-90ab-f98a39c70111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003437026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.2003437026
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.2130775086
Short name T421
Test name
Test status
Simulation time 108750570 ps
CPU time 2.37 seconds
Started Jul 11 06:39:25 PM PDT 24
Finished Jul 11 06:39:28 PM PDT 24
Peak memory 224088 kb
Host smart-c557059f-be4b-4c45-9a0e-56f3a5889fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130775086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.2130775086
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.353542967
Short name T209
Test name
Test status
Simulation time 49266494447 ps
CPU time 36.44 seconds
Started Jul 11 06:39:30 PM PDT 24
Finished Jul 11 06:40:08 PM PDT 24
Peak memory 250372 kb
Host smart-a4246447-ff12-4d41-a0c5-e7c1d8006e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353542967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.353542967
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.3095543832
Short name T394
Test name
Test status
Simulation time 2608966351 ps
CPU time 8.71 seconds
Started Jul 11 06:39:28 PM PDT 24
Finished Jul 11 06:39:38 PM PDT 24
Peak memory 223480 kb
Host smart-b3e2c808-b015-438a-90ba-6ff462f92369
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3095543832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.3095543832
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.492074548
Short name T770
Test name
Test status
Simulation time 1421811697 ps
CPU time 22.56 seconds
Started Jul 11 06:39:29 PM PDT 24
Finished Jul 11 06:39:53 PM PDT 24
Peak memory 217608 kb
Host smart-8f5ef266-83b8-4e7c-8211-0b91f6cbd912
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492074548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stres
s_all.492074548
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.1027954067
Short name T584
Test name
Test status
Simulation time 13434170 ps
CPU time 0.77 seconds
Started Jul 11 06:39:31 PM PDT 24
Finished Jul 11 06:39:33 PM PDT 24
Peak memory 205720 kb
Host smart-bbe2c230-5619-4c18-8cb2-32d394260761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027954067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.1027954067
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.4011093857
Short name T531
Test name
Test status
Simulation time 8298144516 ps
CPU time 19.46 seconds
Started Jul 11 06:39:24 PM PDT 24
Finished Jul 11 06:39:44 PM PDT 24
Peak memory 216404 kb
Host smart-df8343aa-d66a-427e-b578-6c6f5be82863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011093857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.4011093857
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.134001008
Short name T42
Test name
Test status
Simulation time 27332525 ps
CPU time 1 seconds
Started Jul 11 06:39:30 PM PDT 24
Finished Jul 11 06:39:32 PM PDT 24
Peak memory 207256 kb
Host smart-836037d0-272f-4322-9567-b1a90f614bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134001008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.134001008
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.2225089878
Short name T688
Test name
Test status
Simulation time 396239789 ps
CPU time 0.97 seconds
Started Jul 11 06:39:31 PM PDT 24
Finished Jul 11 06:39:33 PM PDT 24
Peak memory 207012 kb
Host smart-5ed04270-5ab0-43d1-9c0a-4d9ba7caf6cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225089878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.2225089878
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.3047432283
Short name T403
Test name
Test status
Simulation time 20126334818 ps
CPU time 16.11 seconds
Started Jul 11 06:39:29 PM PDT 24
Finished Jul 11 06:39:46 PM PDT 24
Peak memory 232828 kb
Host smart-fbc658c5-4252-4b8b-8d4b-208dc6f4590c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047432283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.3047432283
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.1095138055
Short name T798
Test name
Test status
Simulation time 124656741 ps
CPU time 0.75 seconds
Started Jul 11 06:39:38 PM PDT 24
Finished Jul 11 06:39:39 PM PDT 24
Peak memory 205492 kb
Host smart-6e1cfe30-c3ac-494a-9788-922ed176bc12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095138055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
1095138055
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.2839380635
Short name T360
Test name
Test status
Simulation time 5017276835 ps
CPU time 11.63 seconds
Started Jul 11 06:39:33 PM PDT 24
Finished Jul 11 06:39:45 PM PDT 24
Peak memory 224588 kb
Host smart-0c83528f-1466-4038-aad5-0d23160b1302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839380635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.2839380635
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.2378312919
Short name T702
Test name
Test status
Simulation time 17741654 ps
CPU time 0.75 seconds
Started Jul 11 06:39:29 PM PDT 24
Finished Jul 11 06:39:31 PM PDT 24
Peak memory 205748 kb
Host smart-63d60d93-a661-442e-bc5c-55b3a401ac63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378312919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.2378312919
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.4165713072
Short name T922
Test name
Test status
Simulation time 393487283018 ps
CPU time 181.89 seconds
Started Jul 11 06:39:38 PM PDT 24
Finished Jul 11 06:42:41 PM PDT 24
Peak memory 255632 kb
Host smart-555d3327-bb0a-4622-9cef-f583d2c0782c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165713072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.4165713072
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.1343719050
Short name T821
Test name
Test status
Simulation time 92875865007 ps
CPU time 499.11 seconds
Started Jul 11 06:39:40 PM PDT 24
Finished Jul 11 06:48:00 PM PDT 24
Peak memory 255248 kb
Host smart-e02a59f7-1eff-4051-95fe-e354de19c75c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343719050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.1343719050
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.370924963
Short name T195
Test name
Test status
Simulation time 95736921639 ps
CPU time 318.72 seconds
Started Jul 11 06:39:39 PM PDT 24
Finished Jul 11 06:44:58 PM PDT 24
Peak memory 273040 kb
Host smart-0f5c70ef-58bf-497a-8fde-a4e28a007b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370924963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idle
.370924963
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.2645369332
Short name T723
Test name
Test status
Simulation time 148767763 ps
CPU time 5.97 seconds
Started Jul 11 06:39:33 PM PDT 24
Finished Jul 11 06:39:40 PM PDT 24
Peak memory 224516 kb
Host smart-2521a7d4-971c-4ff4-8c2b-9235d78ea73d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645369332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.2645369332
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.2235176005
Short name T77
Test name
Test status
Simulation time 9690090338 ps
CPU time 54.58 seconds
Started Jul 11 06:39:33 PM PDT 24
Finished Jul 11 06:40:28 PM PDT 24
Peak memory 251876 kb
Host smart-a88ed3da-0b6c-465c-83f7-15370739b0e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235176005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmd
s.2235176005
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.676208957
Short name T595
Test name
Test status
Simulation time 1495188284 ps
CPU time 9.83 seconds
Started Jul 11 06:39:32 PM PDT 24
Finished Jul 11 06:39:43 PM PDT 24
Peak memory 220120 kb
Host smart-6a32677b-67d9-44f5-8cfe-d89542ee3212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676208957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.676208957
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.1050290020
Short name T1001
Test name
Test status
Simulation time 14008230503 ps
CPU time 120.91 seconds
Started Jul 11 06:39:32 PM PDT 24
Finished Jul 11 06:41:34 PM PDT 24
Peak memory 233872 kb
Host smart-09690cb0-f895-4d34-8894-2f5239ff4cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050290020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.1050290020
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.1654234701
Short name T567
Test name
Test status
Simulation time 320146833 ps
CPU time 3.28 seconds
Started Jul 11 06:39:36 PM PDT 24
Finished Jul 11 06:39:40 PM PDT 24
Peak memory 232636 kb
Host smart-15e3d96c-8f85-4528-ae1f-6e77657621ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654234701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.1654234701
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.3198142285
Short name T345
Test name
Test status
Simulation time 507202426 ps
CPU time 7.84 seconds
Started Jul 11 06:39:32 PM PDT 24
Finished Jul 11 06:39:41 PM PDT 24
Peak memory 232724 kb
Host smart-e65989e8-9770-4e61-961b-db5d4385628b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198142285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.3198142285
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.1009764918
Short name T825
Test name
Test status
Simulation time 6188543558 ps
CPU time 6.41 seconds
Started Jul 11 06:39:37 PM PDT 24
Finished Jul 11 06:39:45 PM PDT 24
Peak memory 220392 kb
Host smart-170a9650-f135-4bd3-bea4-f004e63e9e73
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1009764918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.1009764918
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.4086978549
Short name T520
Test name
Test status
Simulation time 2595028812 ps
CPU time 52.21 seconds
Started Jul 11 06:39:38 PM PDT 24
Finished Jul 11 06:40:31 PM PDT 24
Peak memory 253076 kb
Host smart-80cfa3af-0ec2-40b7-9dc6-a5e69b4c6f64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086978549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.4086978549
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.3747549724
Short name T277
Test name
Test status
Simulation time 13705292274 ps
CPU time 22.35 seconds
Started Jul 11 06:39:32 PM PDT 24
Finished Jul 11 06:39:56 PM PDT 24
Peak memory 216336 kb
Host smart-519b4d3f-3280-41c3-bec7-7b39ae2601ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747549724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.3747549724
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.2721816681
Short name T972
Test name
Test status
Simulation time 14272498408 ps
CPU time 10.41 seconds
Started Jul 11 06:39:31 PM PDT 24
Finished Jul 11 06:39:42 PM PDT 24
Peak memory 216324 kb
Host smart-a3c83ce3-00f1-46cd-a6e1-42410d3b3bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721816681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.2721816681
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.2388929228
Short name T481
Test name
Test status
Simulation time 116560045 ps
CPU time 1.32 seconds
Started Jul 11 06:39:33 PM PDT 24
Finished Jul 11 06:39:35 PM PDT 24
Peak memory 216156 kb
Host smart-3270db65-e7a4-4b77-814c-000d1f7e7837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388929228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.2388929228
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.929101629
Short name T627
Test name
Test status
Simulation time 37950409 ps
CPU time 0.81 seconds
Started Jul 11 06:39:32 PM PDT 24
Finished Jul 11 06:39:33 PM PDT 24
Peak memory 205996 kb
Host smart-faf53ff7-fafc-439d-aeaa-fc7ee47e23d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929101629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.929101629
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.2743410659
Short name T377
Test name
Test status
Simulation time 932863022 ps
CPU time 3.84 seconds
Started Jul 11 06:39:35 PM PDT 24
Finished Jul 11 06:39:40 PM PDT 24
Peak memory 224472 kb
Host smart-be376817-75a9-44ba-ba24-2419fa081d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743410659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.2743410659
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.300660231
Short name T442
Test name
Test status
Simulation time 32874553 ps
CPU time 0.73 seconds
Started Jul 11 06:39:48 PM PDT 24
Finished Jul 11 06:39:49 PM PDT 24
Peak memory 205832 kb
Host smart-b8ef66e8-cf24-4c1d-8e94-fcfb0e5f0ced
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300660231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.300660231
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.3658336633
Short name T383
Test name
Test status
Simulation time 41996901 ps
CPU time 2.78 seconds
Started Jul 11 06:39:42 PM PDT 24
Finished Jul 11 06:39:46 PM PDT 24
Peak memory 232836 kb
Host smart-8508a972-52ab-42de-83fd-756ed77de7c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658336633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.3658336633
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.3449656397
Short name T321
Test name
Test status
Simulation time 26101792 ps
CPU time 0.81 seconds
Started Jul 11 06:39:39 PM PDT 24
Finished Jul 11 06:39:41 PM PDT 24
Peak memory 206940 kb
Host smart-5fb041e9-4883-4674-8313-d575f280c413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449656397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.3449656397
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.3931770623
Short name T742
Test name
Test status
Simulation time 4871807837 ps
CPU time 33.4 seconds
Started Jul 11 06:39:42 PM PDT 24
Finished Jul 11 06:40:16 PM PDT 24
Peak memory 249144 kb
Host smart-7df33a9d-23ed-4e13-8ef9-f3e92d3c8e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931770623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.3931770623
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.4002299689
Short name T693
Test name
Test status
Simulation time 33293228769 ps
CPU time 239.8 seconds
Started Jul 11 06:39:46 PM PDT 24
Finished Jul 11 06:43:47 PM PDT 24
Peak memory 250968 kb
Host smart-5c0f72a0-89de-405b-a707-7ee604f39e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002299689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.4002299689
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.3912049398
Short name T757
Test name
Test status
Simulation time 19156750256 ps
CPU time 142.9 seconds
Started Jul 11 06:39:44 PM PDT 24
Finished Jul 11 06:42:07 PM PDT 24
Peak memory 267692 kb
Host smart-19546f9c-697e-4903-9d5c-04d1ffbdfbcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912049398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.3912049398
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.2725790890
Short name T876
Test name
Test status
Simulation time 1750071311 ps
CPU time 27.33 seconds
Started Jul 11 06:39:42 PM PDT 24
Finished Jul 11 06:40:11 PM PDT 24
Peak memory 240876 kb
Host smart-9066c8e1-d847-484b-98eb-e26ae0b2bf77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725790890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.2725790890
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.3784031211
Short name T804
Test name
Test status
Simulation time 3359563386 ps
CPU time 59.05 seconds
Started Jul 11 06:39:43 PM PDT 24
Finished Jul 11 06:40:43 PM PDT 24
Peak memory 257388 kb
Host smart-db23fba8-8d67-49b4-8a7a-9ada2df8de92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784031211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmd
s.3784031211
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.2131455366
Short name T844
Test name
Test status
Simulation time 347257019 ps
CPU time 5.41 seconds
Started Jul 11 06:39:41 PM PDT 24
Finished Jul 11 06:39:47 PM PDT 24
Peak memory 232728 kb
Host smart-87874e5c-ed5a-43ee-bfe1-93d90fbf8bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131455366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.2131455366
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.3831300164
Short name T426
Test name
Test status
Simulation time 1534638649 ps
CPU time 5.29 seconds
Started Jul 11 06:39:42 PM PDT 24
Finished Jul 11 06:39:48 PM PDT 24
Peak memory 232724 kb
Host smart-fe3b3e7a-ecfa-406d-980b-dc22c0fb86ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831300164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.3831300164
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.802862738
Short name T974
Test name
Test status
Simulation time 361598796 ps
CPU time 2.3 seconds
Started Jul 11 06:39:44 PM PDT 24
Finished Jul 11 06:39:47 PM PDT 24
Peak memory 224452 kb
Host smart-25cf664d-baa1-4d29-8bbf-3c1a2cce7467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802862738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swap
.802862738
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.133275214
Short name T942
Test name
Test status
Simulation time 16746584504 ps
CPU time 20.37 seconds
Started Jul 11 06:39:40 PM PDT 24
Finished Jul 11 06:40:01 PM PDT 24
Peak memory 224588 kb
Host smart-eac1ba16-07a2-4663-82ff-5850beadd853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133275214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.133275214
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.150800428
Short name T486
Test name
Test status
Simulation time 224077793 ps
CPU time 4.94 seconds
Started Jul 11 06:39:44 PM PDT 24
Finished Jul 11 06:39:50 PM PDT 24
Peak memory 218816 kb
Host smart-3584db5d-6373-4324-8742-38307303a405
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=150800428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dire
ct.150800428
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.2761165072
Short name T198
Test name
Test status
Simulation time 125822036383 ps
CPU time 300.62 seconds
Started Jul 11 06:39:41 PM PDT 24
Finished Jul 11 06:44:42 PM PDT 24
Peak memory 273872 kb
Host smart-42b4624a-0fe5-4843-9e4f-d4df792af39c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761165072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.2761165072
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.805279938
Short name T930
Test name
Test status
Simulation time 62418034138 ps
CPU time 30.29 seconds
Started Jul 11 06:39:39 PM PDT 24
Finished Jul 11 06:40:10 PM PDT 24
Peak memory 216324 kb
Host smart-a36b1daa-37a8-465f-91bc-769703db1bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805279938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.805279938
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.104184207
Short name T645
Test name
Test status
Simulation time 425677658 ps
CPU time 1.92 seconds
Started Jul 11 06:39:40 PM PDT 24
Finished Jul 11 06:39:43 PM PDT 24
Peak memory 207916 kb
Host smart-b0a0b789-6329-42fd-b21f-7ea4cc36f6dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104184207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.104184207
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.2612806418
Short name T392
Test name
Test status
Simulation time 280817768 ps
CPU time 2.29 seconds
Started Jul 11 06:39:42 PM PDT 24
Finished Jul 11 06:39:46 PM PDT 24
Peak memory 216196 kb
Host smart-bc4b5926-7345-4914-9954-b66ad84dd5c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612806418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.2612806418
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.345164745
Short name T510
Test name
Test status
Simulation time 13112993 ps
CPU time 0.68 seconds
Started Jul 11 06:39:37 PM PDT 24
Finished Jul 11 06:39:38 PM PDT 24
Peak memory 205660 kb
Host smart-a219f1f3-91c6-475a-81b6-e86361de6fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345164745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.345164745
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.2418103031
Short name T203
Test name
Test status
Simulation time 5122173110 ps
CPU time 5.68 seconds
Started Jul 11 06:39:40 PM PDT 24
Finished Jul 11 06:39:47 PM PDT 24
Peak memory 224656 kb
Host smart-c24fcc7c-2d09-4b0f-9470-a7c7181f88f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418103031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.2418103031
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.2100973684
Short name T577
Test name
Test status
Simulation time 10719215 ps
CPU time 0.72 seconds
Started Jul 11 06:39:58 PM PDT 24
Finished Jul 11 06:40:00 PM PDT 24
Peak memory 205796 kb
Host smart-d322ba0a-57f1-4d11-b8e1-ced2bd924252
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100973684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
2100973684
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.760525241
Short name T2
Test name
Test status
Simulation time 3414620667 ps
CPU time 13.65 seconds
Started Jul 11 06:39:51 PM PDT 24
Finished Jul 11 06:40:05 PM PDT 24
Peak memory 224600 kb
Host smart-baeaa88c-3efe-43db-8eba-1d793cbdda0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760525241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.760525241
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.3000351226
Short name T444
Test name
Test status
Simulation time 35411446 ps
CPU time 0.84 seconds
Started Jul 11 06:39:47 PM PDT 24
Finished Jul 11 06:39:48 PM PDT 24
Peak memory 206796 kb
Host smart-c06e3d88-6e7d-44de-ad62-79b7002b15b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000351226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.3000351226
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.194248638
Short name T184
Test name
Test status
Simulation time 3844813024 ps
CPU time 101.11 seconds
Started Jul 11 06:39:56 PM PDT 24
Finished Jul 11 06:41:38 PM PDT 24
Peak memory 265664 kb
Host smart-c5d302be-dd08-4199-9657-e30c367a0f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194248638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.194248638
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.713820468
Short name T476
Test name
Test status
Simulation time 4154007039 ps
CPU time 43.37 seconds
Started Jul 11 06:39:54 PM PDT 24
Finished Jul 11 06:40:39 PM PDT 24
Peak memory 249620 kb
Host smart-aae1a83d-9299-4efe-aac1-3172cc2721d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713820468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idle
.713820468
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.2101921328
Short name T898
Test name
Test status
Simulation time 424932105 ps
CPU time 4.74 seconds
Started Jul 11 06:39:51 PM PDT 24
Finished Jul 11 06:39:57 PM PDT 24
Peak memory 236364 kb
Host smart-83409d03-2765-45a2-9f33-47d2cc5dd6ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101921328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.2101921328
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.2870232918
Short name T814
Test name
Test status
Simulation time 3962774772 ps
CPU time 69.07 seconds
Started Jul 11 06:39:53 PM PDT 24
Finished Jul 11 06:41:03 PM PDT 24
Peak memory 252896 kb
Host smart-f81a7272-1d1b-4ef4-9b8e-6114218a41ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870232918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmd
s.2870232918
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.3815468410
Short name T907
Test name
Test status
Simulation time 2282106832 ps
CPU time 13.83 seconds
Started Jul 11 06:39:52 PM PDT 24
Finished Jul 11 06:40:07 PM PDT 24
Peak memory 224720 kb
Host smart-decb2718-43b3-4c0d-bebf-cb29f84be766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815468410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.3815468410
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.3612383256
Short name T751
Test name
Test status
Simulation time 417226269 ps
CPU time 2.62 seconds
Started Jul 11 06:39:51 PM PDT 24
Finished Jul 11 06:39:54 PM PDT 24
Peak memory 232728 kb
Host smart-edd1570b-0087-4112-9e44-c212426451c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612383256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.3612383256
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.3479013793
Short name T858
Test name
Test status
Simulation time 9667694606 ps
CPU time 11.44 seconds
Started Jul 11 06:39:52 PM PDT 24
Finished Jul 11 06:40:05 PM PDT 24
Peak memory 237644 kb
Host smart-1ea1d0fb-e757-4b51-a0d0-7e5f4c9374b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479013793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.3479013793
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.1846180224
Short name T582
Test name
Test status
Simulation time 1500545629 ps
CPU time 4.26 seconds
Started Jul 11 06:39:51 PM PDT 24
Finished Jul 11 06:39:55 PM PDT 24
Peak memory 224492 kb
Host smart-c4074179-cabe-4933-becf-de8fb2fe4545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846180224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.1846180224
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.3746686144
Short name T368
Test name
Test status
Simulation time 2092450325 ps
CPU time 7.25 seconds
Started Jul 11 06:39:52 PM PDT 24
Finished Jul 11 06:40:01 PM PDT 24
Peak memory 223008 kb
Host smart-423cbda0-45d9-485e-afde-290865d9b24f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3746686144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.3746686144
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.1804270413
Short name T847
Test name
Test status
Simulation time 16541236088 ps
CPU time 71.81 seconds
Started Jul 11 06:39:57 PM PDT 24
Finished Jul 11 06:41:10 PM PDT 24
Peak memory 249208 kb
Host smart-abea5ee0-1531-4002-a953-772bad7e7a39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804270413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.1804270413
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.3573032667
Short name T471
Test name
Test status
Simulation time 269370912 ps
CPU time 1.74 seconds
Started Jul 11 06:39:46 PM PDT 24
Finished Jul 11 06:39:49 PM PDT 24
Peak memory 216276 kb
Host smart-af96c14e-05cc-4cc5-b5a9-c704faeed853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573032667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.3573032667
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.3519425075
Short name T542
Test name
Test status
Simulation time 2049559623 ps
CPU time 3.29 seconds
Started Jul 11 06:39:46 PM PDT 24
Finished Jul 11 06:39:50 PM PDT 24
Peak memory 216196 kb
Host smart-e8a2774a-1c4e-4628-b7fd-5bfa49e02fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519425075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.3519425075
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.2172749996
Short name T1003
Test name
Test status
Simulation time 18163685 ps
CPU time 0.91 seconds
Started Jul 11 06:39:46 PM PDT 24
Finished Jul 11 06:39:48 PM PDT 24
Peak memory 206628 kb
Host smart-303aae5d-84e7-4867-a71a-b7b802394ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172749996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.2172749996
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.3994917179
Short name T472
Test name
Test status
Simulation time 139483922 ps
CPU time 0.93 seconds
Started Jul 11 06:39:46 PM PDT 24
Finished Jul 11 06:39:48 PM PDT 24
Peak memory 205992 kb
Host smart-89917b3f-3c75-4aa4-a165-dff651506dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994917179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.3994917179
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.4135386865
Short name T251
Test name
Test status
Simulation time 21072841882 ps
CPU time 17.76 seconds
Started Jul 11 06:39:50 PM PDT 24
Finished Jul 11 06:40:09 PM PDT 24
Peak memory 240936 kb
Host smart-79c6e515-ae5d-4282-a529-a17b5d4131c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135386865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.4135386865
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.1582299616
Short name T575
Test name
Test status
Simulation time 51705955 ps
CPU time 0.72 seconds
Started Jul 11 06:40:05 PM PDT 24
Finished Jul 11 06:40:06 PM PDT 24
Peak memory 204944 kb
Host smart-516b2098-b704-4c9e-8fd6-770978ecc2b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582299616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
1582299616
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.2799096484
Short name T422
Test name
Test status
Simulation time 978470054 ps
CPU time 2.42 seconds
Started Jul 11 06:40:01 PM PDT 24
Finished Jul 11 06:40:05 PM PDT 24
Peak memory 223996 kb
Host smart-3e08d5ed-12b0-4d65-a2d0-122957c1602d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799096484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.2799096484
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.1786009305
Short name T1006
Test name
Test status
Simulation time 16796168 ps
CPU time 0.79 seconds
Started Jul 11 06:39:58 PM PDT 24
Finished Jul 11 06:40:00 PM PDT 24
Peak memory 206876 kb
Host smart-74084e0a-ef77-48da-a33d-eb041894d824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786009305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.1786009305
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.292180768
Short name T637
Test name
Test status
Simulation time 3802420496 ps
CPU time 34.7 seconds
Started Jul 11 06:40:00 PM PDT 24
Finished Jul 11 06:40:36 PM PDT 24
Peak memory 249228 kb
Host smart-958d01ba-a11b-4ae9-9de9-5c89b44b1bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292180768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.292180768
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.830111894
Short name T258
Test name
Test status
Simulation time 8413530191 ps
CPU time 118.26 seconds
Started Jul 11 06:40:01 PM PDT 24
Finished Jul 11 06:42:00 PM PDT 24
Peak memory 254216 kb
Host smart-b9b1c822-f0af-4e52-9979-13768bdc2213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830111894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmds
.830111894
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.598788498
Short name T548
Test name
Test status
Simulation time 5470918130 ps
CPU time 18.2 seconds
Started Jul 11 06:40:00 PM PDT 24
Finished Jul 11 06:40:19 PM PDT 24
Peak memory 224568 kb
Host smart-49b66526-a8e6-442e-bdcc-9c8b9bbaa9d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598788498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.598788498
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.856566095
Short name T656
Test name
Test status
Simulation time 78589644 ps
CPU time 2.24 seconds
Started Jul 11 06:39:59 PM PDT 24
Finished Jul 11 06:40:02 PM PDT 24
Peak memory 223112 kb
Host smart-443087de-51de-42f8-9688-ce874e6fd7eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856566095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.856566095
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.1933151806
Short name T997
Test name
Test status
Simulation time 113399797 ps
CPU time 2.48 seconds
Started Jul 11 06:39:55 PM PDT 24
Finished Jul 11 06:39:58 PM PDT 24
Peak memory 232736 kb
Host smart-a3c43808-0b5e-477c-aa5a-da10b5b53d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933151806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.1933151806
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.700933732
Short name T840
Test name
Test status
Simulation time 9962807853 ps
CPU time 6.47 seconds
Started Jul 11 06:39:57 PM PDT 24
Finished Jul 11 06:40:05 PM PDT 24
Peak memory 224584 kb
Host smart-d70a5199-b9f7-4c2f-82e9-0932995cb5ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700933732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.700933732
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.1398407479
Short name T846
Test name
Test status
Simulation time 804129802 ps
CPU time 10.07 seconds
Started Jul 11 06:40:02 PM PDT 24
Finished Jul 11 06:40:13 PM PDT 24
Peak memory 222452 kb
Host smart-9e03f39e-bec4-4f12-9a06-8ae567552eda
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1398407479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.1398407479
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.1122972784
Short name T522
Test name
Test status
Simulation time 10876991544 ps
CPU time 51.39 seconds
Started Jul 11 06:40:05 PM PDT 24
Finished Jul 11 06:40:58 PM PDT 24
Peak memory 251568 kb
Host smart-2bcd7689-8146-4971-8666-1538eb75ddde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122972784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.1122972784
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.2746019251
Short name T838
Test name
Test status
Simulation time 16373976302 ps
CPU time 10.13 seconds
Started Jul 11 06:39:58 PM PDT 24
Finished Jul 11 06:40:09 PM PDT 24
Peak memory 216344 kb
Host smart-7eb3a4bd-8e09-44a6-bebf-c8d2b51939e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746019251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.2746019251
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.1836765306
Short name T48
Test name
Test status
Simulation time 1278787351 ps
CPU time 2.7 seconds
Started Jul 11 06:39:55 PM PDT 24
Finished Jul 11 06:39:59 PM PDT 24
Peak memory 216204 kb
Host smart-79cef35a-fdb1-4656-8c77-77e1b35dc700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836765306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.1836765306
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.108102575
Short name T916
Test name
Test status
Simulation time 451071805 ps
CPU time 2.99 seconds
Started Jul 11 06:39:58 PM PDT 24
Finished Jul 11 06:40:02 PM PDT 24
Peak memory 216236 kb
Host smart-f62d17c1-3642-4f24-9439-5651107f6846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108102575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.108102575
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.2192722509
Short name T717
Test name
Test status
Simulation time 129027147 ps
CPU time 0.81 seconds
Started Jul 11 06:39:55 PM PDT 24
Finished Jul 11 06:39:57 PM PDT 24
Peak memory 205992 kb
Host smart-4de2092f-48a7-4b84-84a4-bada9dc3bf74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192722509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.2192722509
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.1544509059
Short name T871
Test name
Test status
Simulation time 305577521 ps
CPU time 5.51 seconds
Started Jul 11 06:40:00 PM PDT 24
Finished Jul 11 06:40:06 PM PDT 24
Peak memory 232664 kb
Host smart-c5a1772e-2e82-4a42-86b0-b61cbb5cca25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544509059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.1544509059
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.1814509105
Short name T483
Test name
Test status
Simulation time 15291657 ps
CPU time 0.74 seconds
Started Jul 11 06:40:14 PM PDT 24
Finished Jul 11 06:40:16 PM PDT 24
Peak memory 204924 kb
Host smart-0716a939-2970-4723-887e-02879522c3ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814509105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
1814509105
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.1570271565
Short name T896
Test name
Test status
Simulation time 426028578 ps
CPU time 5.62 seconds
Started Jul 11 06:40:10 PM PDT 24
Finished Jul 11 06:40:17 PM PDT 24
Peak memory 224488 kb
Host smart-c65b59b7-5e85-4824-9b82-789ac8585b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570271565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.1570271565
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.540368381
Short name T390
Test name
Test status
Simulation time 119438059 ps
CPU time 0.82 seconds
Started Jul 11 06:40:04 PM PDT 24
Finished Jul 11 06:40:06 PM PDT 24
Peak memory 206624 kb
Host smart-1f159558-7e58-4f61-a7c2-2cd1ad727d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540368381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.540368381
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.3035316721
Short name T493
Test name
Test status
Simulation time 46448152662 ps
CPU time 116.19 seconds
Started Jul 11 06:40:10 PM PDT 24
Finished Jul 11 06:42:08 PM PDT 24
Peak memory 253824 kb
Host smart-45a12b2a-595b-4b6d-8874-0969449fe9d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035316721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.3035316721
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.2412276419
Short name T173
Test name
Test status
Simulation time 2725225200 ps
CPU time 51.53 seconds
Started Jul 11 06:40:16 PM PDT 24
Finished Jul 11 06:41:09 PM PDT 24
Peak memory 254872 kb
Host smart-bb55a8f2-ef51-4609-bfc5-3c687695e224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412276419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.2412276419
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.189303588
Short name T283
Test name
Test status
Simulation time 1618650962 ps
CPU time 30.56 seconds
Started Jul 11 06:40:16 PM PDT 24
Finished Jul 11 06:40:48 PM PDT 24
Peak memory 237156 kb
Host smart-48163606-b2d8-40df-8f02-3bc2cab780a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189303588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idle
.189303588
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.2561934013
Short name T124
Test name
Test status
Simulation time 867426628 ps
CPU time 10.46 seconds
Started Jul 11 06:40:09 PM PDT 24
Finished Jul 11 06:40:20 PM PDT 24
Peak memory 224512 kb
Host smart-b388704a-2965-43c8-a587-3ea71a24c4f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561934013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.2561934013
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.1585051795
Short name T713
Test name
Test status
Simulation time 353378958 ps
CPU time 2.25 seconds
Started Jul 11 06:40:11 PM PDT 24
Finished Jul 11 06:40:15 PM PDT 24
Peak memory 223900 kb
Host smart-4c4a0610-2f5a-405f-b1c8-59df2142b30b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585051795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.1585051795
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.51050475
Short name T473
Test name
Test status
Simulation time 304454412 ps
CPU time 9.22 seconds
Started Jul 11 06:40:09 PM PDT 24
Finished Jul 11 06:40:19 PM PDT 24
Peak memory 236104 kb
Host smart-a614308b-82ef-45f9-8a87-e27276c6028d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51050475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.51050475
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.2492375403
Short name T855
Test name
Test status
Simulation time 136844272 ps
CPU time 2.92 seconds
Started Jul 11 06:40:07 PM PDT 24
Finished Jul 11 06:40:10 PM PDT 24
Peak memory 232672 kb
Host smart-0bb73902-42c2-4b39-95e9-b7f71578f583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492375403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.2492375403
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.242394337
Short name T729
Test name
Test status
Simulation time 4183749524 ps
CPU time 9.15 seconds
Started Jul 11 06:40:10 PM PDT 24
Finished Jul 11 06:40:21 PM PDT 24
Peak memory 232792 kb
Host smart-c7a04e95-69d2-4aab-ad4f-8d45624e8272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242394337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.242394337
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.616970781
Short name T703
Test name
Test status
Simulation time 406908311 ps
CPU time 4.29 seconds
Started Jul 11 06:40:11 PM PDT 24
Finished Jul 11 06:40:17 PM PDT 24
Peak memory 223252 kb
Host smart-5dc247aa-d778-4fef-b652-69948980448e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=616970781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dire
ct.616970781
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.43086238
Short name T982
Test name
Test status
Simulation time 2937766621 ps
CPU time 70.05 seconds
Started Jul 11 06:40:13 PM PDT 24
Finished Jul 11 06:41:25 PM PDT 24
Peak memory 263788 kb
Host smart-f74c740b-ceab-490b-b99f-2095b9ccc8ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43086238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stress
_all.43086238
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.4182559139
Short name T282
Test name
Test status
Simulation time 12817175640 ps
CPU time 20.6 seconds
Started Jul 11 06:40:04 PM PDT 24
Finished Jul 11 06:40:25 PM PDT 24
Peak memory 216340 kb
Host smart-5e09b9d1-d8d4-446c-8b16-2c60bdbaf30b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182559139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.4182559139
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.1115391137
Short name T357
Test name
Test status
Simulation time 813690058 ps
CPU time 3.51 seconds
Started Jul 11 06:40:05 PM PDT 24
Finished Jul 11 06:40:10 PM PDT 24
Peak memory 216236 kb
Host smart-cdd003a9-041f-4097-b72d-0fc40ce5e205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115391137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.1115391137
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.3368313273
Short name T960
Test name
Test status
Simulation time 146792977 ps
CPU time 2.39 seconds
Started Jul 11 06:40:15 PM PDT 24
Finished Jul 11 06:40:19 PM PDT 24
Peak memory 208056 kb
Host smart-3254bacb-b349-4977-84bb-6fc09e5d20da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368313273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.3368313273
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.2769617453
Short name T800
Test name
Test status
Simulation time 489085786 ps
CPU time 0.93 seconds
Started Jul 11 06:40:05 PM PDT 24
Finished Jul 11 06:40:07 PM PDT 24
Peak memory 205928 kb
Host smart-f3bd6fb8-06d4-4f21-8c7d-6106fb466c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769617453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.2769617453
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.4037916045
Short name T342
Test name
Test status
Simulation time 138100114 ps
CPU time 2.47 seconds
Started Jul 11 06:40:16 PM PDT 24
Finished Jul 11 06:40:20 PM PDT 24
Peak memory 224440 kb
Host smart-a654f323-3333-4205-99fb-e1b3af1b6a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037916045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.4037916045
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.2895416426
Short name T822
Test name
Test status
Simulation time 11038623 ps
CPU time 0.75 seconds
Started Jul 11 06:40:25 PM PDT 24
Finished Jul 11 06:40:27 PM PDT 24
Peak memory 205968 kb
Host smart-f883518e-7213-4ba9-be73-62a16f0e8255
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895416426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
2895416426
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.3922868358
Short name T406
Test name
Test status
Simulation time 1182243484 ps
CPU time 3.61 seconds
Started Jul 11 06:40:18 PM PDT 24
Finished Jul 11 06:40:23 PM PDT 24
Peak memory 224680 kb
Host smart-24c2f815-2d3f-434a-b760-575b0806b031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922868358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.3922868358
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.1657903769
Short name T969
Test name
Test status
Simulation time 27981274 ps
CPU time 0.76 seconds
Started Jul 11 06:40:15 PM PDT 24
Finished Jul 11 06:40:16 PM PDT 24
Peak memory 205544 kb
Host smart-0cb5550b-ed03-44e8-badc-4186b7bec4c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657903769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.1657903769
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.2186139524
Short name T939
Test name
Test status
Simulation time 81919924131 ps
CPU time 322.1 seconds
Started Jul 11 06:40:19 PM PDT 24
Finished Jul 11 06:45:42 PM PDT 24
Peak memory 255412 kb
Host smart-108c8de4-d271-4526-bb4a-713b8f751f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186139524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.2186139524
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.2379789673
Short name T256
Test name
Test status
Simulation time 1481557869 ps
CPU time 47.11 seconds
Started Jul 11 06:40:18 PM PDT 24
Finished Jul 11 06:41:07 PM PDT 24
Peak memory 251284 kb
Host smart-de9bddfa-70b4-4fd8-9bfd-edb89f5bf0a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379789673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.2379789673
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.3412004836
Short name T200
Test name
Test status
Simulation time 9265141861 ps
CPU time 67.66 seconds
Started Jul 11 06:40:24 PM PDT 24
Finished Jul 11 06:41:32 PM PDT 24
Peak memory 254472 kb
Host smart-a2029add-7544-410b-ba63-1c56626d34e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412004836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.3412004836
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.573487831
Short name T269
Test name
Test status
Simulation time 42586782808 ps
CPU time 28.54 seconds
Started Jul 11 06:40:19 PM PDT 24
Finished Jul 11 06:40:49 PM PDT 24
Peak memory 236840 kb
Host smart-43897924-b118-408b-878a-183fb68cd735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573487831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.573487831
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.3371667167
Short name T315
Test name
Test status
Simulation time 151559728 ps
CPU time 0.88 seconds
Started Jul 11 06:40:19 PM PDT 24
Finished Jul 11 06:40:22 PM PDT 24
Peak memory 215948 kb
Host smart-a49b9547-5ec9-4668-9408-bb32c1e2d7e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371667167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmd
s.3371667167
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.2323679649
Short name T952
Test name
Test status
Simulation time 1969504732 ps
CPU time 5.64 seconds
Started Jul 11 06:40:21 PM PDT 24
Finished Jul 11 06:40:27 PM PDT 24
Peak memory 232612 kb
Host smart-c3902177-42d0-43b3-8639-acf052beacab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323679649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.2323679649
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.3452555669
Short name T881
Test name
Test status
Simulation time 1687596213 ps
CPU time 11.37 seconds
Started Jul 11 06:40:19 PM PDT 24
Finished Jul 11 06:40:31 PM PDT 24
Peak memory 232664 kb
Host smart-dcfa4697-b70d-4a1d-b914-8bf845a135f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452555669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.3452555669
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.2512688043
Short name T631
Test name
Test status
Simulation time 450554185 ps
CPU time 6.64 seconds
Started Jul 11 06:40:13 PM PDT 24
Finished Jul 11 06:40:21 PM PDT 24
Peak memory 232732 kb
Host smart-44cefe4c-ca6e-44fd-a40c-b6587aa97620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512688043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.2512688043
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.2532909045
Short name T759
Test name
Test status
Simulation time 5622936344 ps
CPU time 12.68 seconds
Started Jul 11 06:40:16 PM PDT 24
Finished Jul 11 06:40:30 PM PDT 24
Peak memory 232848 kb
Host smart-707dfee9-783e-432f-a62c-5c687d977cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532909045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.2532909045
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.2327195241
Short name T9
Test name
Test status
Simulation time 282112965 ps
CPU time 5.89 seconds
Started Jul 11 06:40:17 PM PDT 24
Finished Jul 11 06:40:24 PM PDT 24
Peak memory 223236 kb
Host smart-3bc62917-e5da-4736-ad53-d11508ca254e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2327195241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.2327195241
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.3102000384
Short name T873
Test name
Test status
Simulation time 300213614101 ps
CPU time 682.42 seconds
Started Jul 11 06:40:26 PM PDT 24
Finished Jul 11 06:51:50 PM PDT 24
Peak memory 265684 kb
Host smart-e00e85a1-40b6-4270-bad6-06a6a21bf5ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102000384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.3102000384
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.3540174565
Short name T711
Test name
Test status
Simulation time 8362962738 ps
CPU time 20.38 seconds
Started Jul 11 06:40:12 PM PDT 24
Finished Jul 11 06:40:34 PM PDT 24
Peak memory 216440 kb
Host smart-aafa1855-375d-4308-968d-479b3f191277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540174565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.3540174565
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.1080500519
Short name T69
Test name
Test status
Simulation time 2941583290 ps
CPU time 6.13 seconds
Started Jul 11 06:40:15 PM PDT 24
Finished Jul 11 06:40:23 PM PDT 24
Peak memory 216384 kb
Host smart-67b1d21f-d702-476d-b47d-5ac4b2c1f7f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080500519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.1080500519
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.525026507
Short name T921
Test name
Test status
Simulation time 124028225 ps
CPU time 1.26 seconds
Started Jul 11 06:40:16 PM PDT 24
Finished Jul 11 06:40:19 PM PDT 24
Peak memory 207980 kb
Host smart-3095121e-30bf-473a-b728-2ea69ccf6d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525026507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.525026507
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.1137137016
Short name T880
Test name
Test status
Simulation time 56425112 ps
CPU time 0.82 seconds
Started Jul 11 06:40:16 PM PDT 24
Finished Jul 11 06:40:18 PM PDT 24
Peak memory 205984 kb
Host smart-262c08eb-1f4f-4979-b781-75e6f1b9ed86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137137016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.1137137016
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.1170451980
Short name T827
Test name
Test status
Simulation time 99760525 ps
CPU time 3.2 seconds
Started Jul 11 06:40:18 PM PDT 24
Finished Jul 11 06:40:23 PM PDT 24
Peak memory 232664 kb
Host smart-ba42d04e-d639-4485-8919-e66b40e4b21d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170451980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.1170451980
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.1309005541
Short name T458
Test name
Test status
Simulation time 20047041 ps
CPU time 0.71 seconds
Started Jul 11 06:40:27 PM PDT 24
Finished Jul 11 06:40:29 PM PDT 24
Peak memory 205480 kb
Host smart-399ea643-2d9d-4c66-a424-a1e762f2dbf0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309005541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
1309005541
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.1397552855
Short name T915
Test name
Test status
Simulation time 182299459 ps
CPU time 5.11 seconds
Started Jul 11 06:40:23 PM PDT 24
Finished Jul 11 06:40:29 PM PDT 24
Peak memory 224516 kb
Host smart-3707235e-e435-42aa-8609-c24d539d80c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397552855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.1397552855
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.1429385465
Short name T709
Test name
Test status
Simulation time 146677284 ps
CPU time 0.78 seconds
Started Jul 11 06:40:26 PM PDT 24
Finished Jul 11 06:40:29 PM PDT 24
Peak memory 206576 kb
Host smart-4b9216ed-1190-4dbc-b3d4-39233603944e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429385465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.1429385465
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.2153250616
Short name T964
Test name
Test status
Simulation time 11530612091 ps
CPU time 12.26 seconds
Started Jul 11 06:40:27 PM PDT 24
Finished Jul 11 06:40:41 PM PDT 24
Peak memory 224624 kb
Host smart-7e27dcd6-964b-4741-8fe6-dd88e08c4c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153250616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.2153250616
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.2784263738
Short name T162
Test name
Test status
Simulation time 14670134474 ps
CPU time 48.43 seconds
Started Jul 11 06:40:26 PM PDT 24
Finished Jul 11 06:41:16 PM PDT 24
Peak memory 250872 kb
Host smart-6ca6fee9-50e4-4457-b662-eb6fcc4e70d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784263738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.2784263738
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.102354011
Short name T436
Test name
Test status
Simulation time 197159991 ps
CPU time 2.78 seconds
Started Jul 11 06:40:26 PM PDT 24
Finished Jul 11 06:40:31 PM PDT 24
Peak memory 224464 kb
Host smart-974a60c7-c5dd-4c9a-99eb-2a8f985b1ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102354011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.102354011
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.2821136308
Short name T399
Test name
Test status
Simulation time 953440347 ps
CPU time 15.5 seconds
Started Jul 11 06:40:27 PM PDT 24
Finished Jul 11 06:40:44 PM PDT 24
Peak memory 236788 kb
Host smart-6d87fbad-6c20-4fa9-96f2-5365af04364d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821136308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmd
s.2821136308
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.240488046
Short name T610
Test name
Test status
Simulation time 1402962036 ps
CPU time 15.19 seconds
Started Jul 11 06:40:25 PM PDT 24
Finished Jul 11 06:40:42 PM PDT 24
Peak memory 232808 kb
Host smart-67a6ae4f-390a-47c0-825d-dcb9ad413ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240488046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.240488046
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.3919733597
Short name T408
Test name
Test status
Simulation time 850965628 ps
CPU time 6.15 seconds
Started Jul 11 06:40:23 PM PDT 24
Finished Jul 11 06:40:30 PM PDT 24
Peak memory 224508 kb
Host smart-bbf96af6-22c8-45f5-85ce-f40425e6e27c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919733597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.3919733597
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.2294392429
Short name T651
Test name
Test status
Simulation time 1220696607 ps
CPU time 9.76 seconds
Started Jul 11 06:40:26 PM PDT 24
Finished Jul 11 06:40:37 PM PDT 24
Peak memory 224512 kb
Host smart-c42919a0-4323-4038-b365-6edff2a6dd28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294392429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.2294392429
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.3263783766
Short name T594
Test name
Test status
Simulation time 454146072 ps
CPU time 3.46 seconds
Started Jul 11 06:40:24 PM PDT 24
Finished Jul 11 06:40:28 PM PDT 24
Peak memory 232652 kb
Host smart-cee87f20-b76e-4acc-92b8-caa95f37afc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263783766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.3263783766
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.3976998853
Short name T455
Test name
Test status
Simulation time 2771880542 ps
CPU time 17.01 seconds
Started Jul 11 06:40:27 PM PDT 24
Finished Jul 11 06:40:46 PM PDT 24
Peak memory 222228 kb
Host smart-ff0a5819-de76-41d3-88fc-7cec4c108fe7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3976998853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.3976998853
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.3898419457
Short name T768
Test name
Test status
Simulation time 82782258904 ps
CPU time 413.18 seconds
Started Jul 11 06:40:28 PM PDT 24
Finished Jul 11 06:47:23 PM PDT 24
Peak memory 269452 kb
Host smart-fc9c344c-1ce6-4d81-aa4a-0471914ba732
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898419457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.3898419457
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.3389163608
Short name T647
Test name
Test status
Simulation time 2681651442 ps
CPU time 7.64 seconds
Started Jul 11 06:40:22 PM PDT 24
Finished Jul 11 06:40:31 PM PDT 24
Peak memory 216316 kb
Host smart-b65cbb3b-b46b-48b5-b4ce-82e402cf76fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389163608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.3389163608
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.112919185
Short name T758
Test name
Test status
Simulation time 6556257825 ps
CPU time 7.1 seconds
Started Jul 11 06:40:24 PM PDT 24
Finished Jul 11 06:40:32 PM PDT 24
Peak memory 216324 kb
Host smart-8ec3f4b4-2ec9-4cfc-9bf6-ce3711afa117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112919185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.112919185
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.4163369810
Short name T585
Test name
Test status
Simulation time 164237404 ps
CPU time 1.5 seconds
Started Jul 11 06:40:22 PM PDT 24
Finished Jul 11 06:40:25 PM PDT 24
Peak memory 216260 kb
Host smart-055d2cb6-1d19-48e6-831f-5559f900a7d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163369810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.4163369810
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.3927943294
Short name T734
Test name
Test status
Simulation time 273378437 ps
CPU time 0.89 seconds
Started Jul 11 06:40:24 PM PDT 24
Finished Jul 11 06:40:27 PM PDT 24
Peak memory 206084 kb
Host smart-dfaa14da-bce4-4369-aa07-11e43b3b22d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927943294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.3927943294
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.3995584064
Short name T1007
Test name
Test status
Simulation time 23461261275 ps
CPU time 33.88 seconds
Started Jul 11 06:40:22 PM PDT 24
Finished Jul 11 06:40:56 PM PDT 24
Peak memory 232800 kb
Host smart-bc450fa0-3653-4709-9aef-2d342d38490f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995584064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.3995584064
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.457601866
Short name T666
Test name
Test status
Simulation time 40387070 ps
CPU time 0.75 seconds
Started Jul 11 06:35:03 PM PDT 24
Finished Jul 11 06:35:04 PM PDT 24
Peak memory 205492 kb
Host smart-177d5c7c-12e0-4b9f-a1a6-34797dc6ebd6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457601866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.457601866
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.2953917517
Short name T792
Test name
Test status
Simulation time 659697972 ps
CPU time 9.2 seconds
Started Jul 11 06:34:57 PM PDT 24
Finished Jul 11 06:35:08 PM PDT 24
Peak memory 224524 kb
Host smart-8e3391af-e148-4ef7-a527-abf314bc992c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953917517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.2953917517
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.1827524613
Short name T450
Test name
Test status
Simulation time 66318063 ps
CPU time 0.78 seconds
Started Jul 11 06:34:58 PM PDT 24
Finished Jul 11 06:35:00 PM PDT 24
Peak memory 206636 kb
Host smart-43766195-df33-4781-a26d-49ec50018e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827524613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.1827524613
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.3309650367
Short name T39
Test name
Test status
Simulation time 13473880578 ps
CPU time 136.98 seconds
Started Jul 11 06:35:01 PM PDT 24
Finished Jul 11 06:37:19 PM PDT 24
Peak memory 271652 kb
Host smart-d9748ce5-4b3f-42e1-9930-0efc86b3e0e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309650367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.3309650367
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.2508377879
Short name T172
Test name
Test status
Simulation time 5751075675 ps
CPU time 96.92 seconds
Started Jul 11 06:35:01 PM PDT 24
Finished Jul 11 06:36:39 PM PDT 24
Peak memory 264796 kb
Host smart-f711b7f6-5136-47ec-9b93-3f9e8b0bf5c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508377879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.2508377879
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.3807608218
Short name T266
Test name
Test status
Simulation time 1164715054 ps
CPU time 18.67 seconds
Started Jul 11 06:35:04 PM PDT 24
Finished Jul 11 06:35:24 PM PDT 24
Peak memory 224440 kb
Host smart-76eaea3e-65d7-495f-8c26-a6adba7ad78c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807608218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.3807608218
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.2887030427
Short name T911
Test name
Test status
Simulation time 33368285506 ps
CPU time 217.02 seconds
Started Jul 11 06:35:02 PM PDT 24
Finished Jul 11 06:38:40 PM PDT 24
Peak memory 251364 kb
Host smart-e40060ba-bdf1-4996-a6cc-ac3a5a6246d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887030427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds
.2887030427
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.2615681691
Short name T395
Test name
Test status
Simulation time 28432187 ps
CPU time 2.07 seconds
Started Jul 11 06:34:59 PM PDT 24
Finished Jul 11 06:35:03 PM PDT 24
Peak memory 223844 kb
Host smart-ab7657a8-1b75-4e03-b4e4-3769efd4590b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615681691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.2615681691
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.1703477850
Short name T796
Test name
Test status
Simulation time 218670116 ps
CPU time 6.84 seconds
Started Jul 11 06:34:59 PM PDT 24
Finished Jul 11 06:35:07 PM PDT 24
Peak memory 224524 kb
Host smart-d1be1566-0831-4cc5-83b8-c723d1475533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703477850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.1703477850
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.3831533609
Short name T865
Test name
Test status
Simulation time 7303847020 ps
CPU time 10.19 seconds
Started Jul 11 06:34:56 PM PDT 24
Finished Jul 11 06:35:07 PM PDT 24
Peak memory 224592 kb
Host smart-72519129-2f8e-49d9-8e37-5a96bed98f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831533609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.3831533609
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.1052510487
Short name T175
Test name
Test status
Simulation time 1184557862 ps
CPU time 8.76 seconds
Started Jul 11 06:34:58 PM PDT 24
Finished Jul 11 06:35:08 PM PDT 24
Peak memory 224484 kb
Host smart-0f8adc86-d3cc-4e61-bf32-843e966d17ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052510487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.1052510487
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.4021544542
Short name T989
Test name
Test status
Simulation time 376147216 ps
CPU time 7.02 seconds
Started Jul 11 06:35:06 PM PDT 24
Finished Jul 11 06:35:15 PM PDT 24
Peak memory 223164 kb
Host smart-70290ee9-6be9-4a32-b7be-b03838faf9b5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4021544542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.4021544542
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.1785132095
Short name T63
Test name
Test status
Simulation time 228013304 ps
CPU time 1.11 seconds
Started Jul 11 06:35:03 PM PDT 24
Finished Jul 11 06:35:05 PM PDT 24
Peak memory 236564 kb
Host smart-432b4285-8cf7-4461-88e4-d776308c9952
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785132095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.1785132095
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.2713346919
Short name T554
Test name
Test status
Simulation time 549031515564 ps
CPU time 1057.9 seconds
Started Jul 11 06:35:03 PM PDT 24
Finished Jul 11 06:52:42 PM PDT 24
Peak memory 285400 kb
Host smart-e18c1848-f1c1-467d-accc-c57158f3885a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713346919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.2713346919
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.3246315410
Short name T951
Test name
Test status
Simulation time 284774627 ps
CPU time 5.61 seconds
Started Jul 11 06:34:58 PM PDT 24
Finished Jul 11 06:35:05 PM PDT 24
Peak memory 216252 kb
Host smart-9c504296-c207-422b-a581-54f3c042737d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246315410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.3246315410
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.4029714723
Short name T879
Test name
Test status
Simulation time 3739746926 ps
CPU time 12.72 seconds
Started Jul 11 06:34:59 PM PDT 24
Finished Jul 11 06:35:13 PM PDT 24
Peak memory 216308 kb
Host smart-70c08d82-d697-4c82-a029-1972beea6d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029714723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.4029714723
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.2043595859
Short name T654
Test name
Test status
Simulation time 129449030 ps
CPU time 1.73 seconds
Started Jul 11 06:34:59 PM PDT 24
Finished Jul 11 06:35:02 PM PDT 24
Peak memory 216200 kb
Host smart-df046c7e-f379-49a5-89a5-0f840db67a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043595859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.2043595859
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.2595969159
Short name T304
Test name
Test status
Simulation time 59765789 ps
CPU time 0.92 seconds
Started Jul 11 06:34:57 PM PDT 24
Finished Jul 11 06:34:59 PM PDT 24
Peak memory 205980 kb
Host smart-d5075aa1-5d96-4a69-aa54-0e585202e308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595969159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.2595969159
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.396466657
Short name T192
Test name
Test status
Simulation time 6578571329 ps
CPU time 20.86 seconds
Started Jul 11 06:34:59 PM PDT 24
Finished Jul 11 06:35:21 PM PDT 24
Peak memory 232800 kb
Host smart-271aabbb-968d-43dc-be63-9cf308be3bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396466657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.396466657
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.3652875119
Short name T747
Test name
Test status
Simulation time 42659504 ps
CPU time 0.77 seconds
Started Jul 11 06:40:37 PM PDT 24
Finished Jul 11 06:40:39 PM PDT 24
Peak memory 205700 kb
Host smart-f75dd473-781d-4008-b341-f00cc15ef560
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652875119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
3652875119
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.4067791608
Short name T482
Test name
Test status
Simulation time 112171922 ps
CPU time 2.55 seconds
Started Jul 11 06:40:31 PM PDT 24
Finished Jul 11 06:40:34 PM PDT 24
Peak memory 232680 kb
Host smart-b0fc7119-a3d9-4526-999c-d0913ed44d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067791608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.4067791608
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.1313614670
Short name T999
Test name
Test status
Simulation time 62866977 ps
CPU time 0.84 seconds
Started Jul 11 06:40:28 PM PDT 24
Finished Jul 11 06:40:30 PM PDT 24
Peak memory 206804 kb
Host smart-1da4a6b1-612d-4d71-b408-4c106ecc78fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313614670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.1313614670
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.823892008
Short name T211
Test name
Test status
Simulation time 133498565198 ps
CPU time 255.53 seconds
Started Jul 11 06:40:38 PM PDT 24
Finished Jul 11 06:44:55 PM PDT 24
Peak memory 249260 kb
Host smart-63ffc9ad-01c7-4af0-8c17-339d297d6014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823892008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.823892008
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.1046610756
Short name T686
Test name
Test status
Simulation time 1833692837 ps
CPU time 40.78 seconds
Started Jul 11 06:40:36 PM PDT 24
Finished Jul 11 06:41:17 PM PDT 24
Peak memory 251820 kb
Host smart-d651ddf3-c945-4bad-b549-1d85da2c83f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046610756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.1046610756
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.3468670536
Short name T372
Test name
Test status
Simulation time 29120146913 ps
CPU time 37.57 seconds
Started Jul 11 06:40:37 PM PDT 24
Finished Jul 11 06:41:15 PM PDT 24
Peak memory 239292 kb
Host smart-b750b09e-7057-42ee-9c8e-1d283cc8f38c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468670536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.3468670536
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.36646107
Short name T765
Test name
Test status
Simulation time 953670934 ps
CPU time 8.4 seconds
Started Jul 11 06:40:30 PM PDT 24
Finished Jul 11 06:40:39 PM PDT 24
Peak memory 234664 kb
Host smart-9a81f8c6-5312-4833-8968-de170ec5d0df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36646107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.36646107
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.2059827465
Short name T397
Test name
Test status
Simulation time 49158011254 ps
CPU time 51.06 seconds
Started Jul 11 06:40:36 PM PDT 24
Finished Jul 11 06:41:28 PM PDT 24
Peak memory 239348 kb
Host smart-d5ea479a-e35b-474a-82db-e0f426151f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059827465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmd
s.2059827465
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.227116380
Short name T547
Test name
Test status
Simulation time 1242698794 ps
CPU time 11.43 seconds
Started Jul 11 06:40:30 PM PDT 24
Finished Jul 11 06:40:43 PM PDT 24
Peak memory 232728 kb
Host smart-7549e8b7-6224-4d13-92b7-6196e526facb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227116380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.227116380
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.1620739411
Short name T839
Test name
Test status
Simulation time 30910941037 ps
CPU time 49.07 seconds
Started Jul 11 06:40:32 PM PDT 24
Finished Jul 11 06:41:22 PM PDT 24
Peak memory 240592 kb
Host smart-6bafde9d-6e53-4c81-bf9d-bef92dd854f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620739411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.1620739411
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.1046215230
Short name T970
Test name
Test status
Simulation time 1652061822 ps
CPU time 8.53 seconds
Started Jul 11 06:40:32 PM PDT 24
Finished Jul 11 06:40:42 PM PDT 24
Peak memory 239436 kb
Host smart-76c681d6-fcec-4a0a-a59a-fb7221cda564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046215230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.1046215230
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.2708221893
Short name T294
Test name
Test status
Simulation time 532172954 ps
CPU time 2.07 seconds
Started Jul 11 06:40:32 PM PDT 24
Finished Jul 11 06:40:35 PM PDT 24
Peak memory 224172 kb
Host smart-1bd0fd16-0362-4fba-87a0-a5ce8b1f8082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708221893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.2708221893
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.3983258028
Short name T123
Test name
Test status
Simulation time 318480079 ps
CPU time 3.61 seconds
Started Jul 11 06:40:35 PM PDT 24
Finished Jul 11 06:40:39 PM PDT 24
Peak memory 219388 kb
Host smart-ff94d08a-cf3f-47bc-856f-3c0fd62c6968
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3983258028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.3983258028
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.1924896018
Short name T508
Test name
Test status
Simulation time 11838946958 ps
CPU time 41.73 seconds
Started Jul 11 06:40:35 PM PDT 24
Finished Jul 11 06:41:18 PM PDT 24
Peak memory 232904 kb
Host smart-425423e7-38bc-40a9-97ec-05a938063a25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924896018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.1924896018
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.2487196553
Short name T290
Test name
Test status
Simulation time 157388316 ps
CPU time 3.17 seconds
Started Jul 11 06:40:25 PM PDT 24
Finished Jul 11 06:40:30 PM PDT 24
Peak memory 216352 kb
Host smart-d82480da-15bc-44fe-a6a3-edc4d81f5c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487196553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.2487196553
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.3211515504
Short name T23
Test name
Test status
Simulation time 35906318924 ps
CPU time 10.21 seconds
Started Jul 11 06:40:26 PM PDT 24
Finished Jul 11 06:40:39 PM PDT 24
Peak memory 217668 kb
Host smart-d6b0752f-84fd-44f6-815a-fb5904fe9457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211515504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.3211515504
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.3353909989
Short name T363
Test name
Test status
Simulation time 95447228 ps
CPU time 1.13 seconds
Started Jul 11 06:40:25 PM PDT 24
Finished Jul 11 06:40:27 PM PDT 24
Peak memory 207928 kb
Host smart-83b5aded-8188-4c6f-8516-8915072321c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353909989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.3353909989
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.2269284627
Short name T761
Test name
Test status
Simulation time 56435205 ps
CPU time 0.87 seconds
Started Jul 11 06:40:28 PM PDT 24
Finished Jul 11 06:40:30 PM PDT 24
Peak memory 206004 kb
Host smart-4d85275a-2551-49db-b8cd-98fba6629ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269284627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.2269284627
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.1539658466
Short name T888
Test name
Test status
Simulation time 1219881501 ps
CPU time 8.93 seconds
Started Jul 11 06:40:32 PM PDT 24
Finished Jul 11 06:40:42 PM PDT 24
Peak memory 249224 kb
Host smart-37313d20-5d23-4371-a992-fdb3545490fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539658466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.1539658466
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.490557629
Short name T565
Test name
Test status
Simulation time 19837531 ps
CPU time 0.73 seconds
Started Jul 11 06:40:46 PM PDT 24
Finished Jul 11 06:40:48 PM PDT 24
Peak memory 205556 kb
Host smart-5a256259-8792-4aa6-a1ca-c65faa1343b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490557629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.490557629
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.4289173714
Short name T507
Test name
Test status
Simulation time 947192694 ps
CPU time 3.65 seconds
Started Jul 11 06:40:40 PM PDT 24
Finished Jul 11 06:40:44 PM PDT 24
Peak memory 224524 kb
Host smart-1e87084d-85b2-4d92-a95b-99e9190fc070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289173714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.4289173714
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.1552805660
Short name T600
Test name
Test status
Simulation time 20539356 ps
CPU time 0.78 seconds
Started Jul 11 06:40:34 PM PDT 24
Finished Jul 11 06:40:36 PM PDT 24
Peak memory 205600 kb
Host smart-acf8fccd-619a-441f-863f-9f7a54be4a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552805660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.1552805660
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.2791436190
Short name T513
Test name
Test status
Simulation time 47299334737 ps
CPU time 133.76 seconds
Started Jul 11 06:40:40 PM PDT 24
Finished Jul 11 06:42:55 PM PDT 24
Peak memory 249220 kb
Host smart-2ae85e38-6894-4fb5-8257-e5d4f1d4ac68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791436190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.2791436190
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.260276998
Short name T278
Test name
Test status
Simulation time 31672507112 ps
CPU time 155.24 seconds
Started Jul 11 06:40:40 PM PDT 24
Finished Jul 11 06:43:17 PM PDT 24
Peak memory 240552 kb
Host smart-c1018eee-1da9-4655-a473-f1b790df2d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260276998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.260276998
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.1911211852
Short name T174
Test name
Test status
Simulation time 115747107551 ps
CPU time 344.29 seconds
Started Jul 11 06:40:45 PM PDT 24
Finished Jul 11 06:46:31 PM PDT 24
Peak memory 268532 kb
Host smart-ffc3fb36-e650-40bf-a148-864f83ca4300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911211852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.1911211852
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.3500890685
Short name T302
Test name
Test status
Simulation time 183529555 ps
CPU time 5.05 seconds
Started Jul 11 06:40:39 PM PDT 24
Finished Jul 11 06:40:45 PM PDT 24
Peak memory 232720 kb
Host smart-d4dc242f-5e19-49e5-8e89-c5b1d61ff2ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500890685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.3500890685
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.1940946901
Short name T159
Test name
Test status
Simulation time 29533007452 ps
CPU time 89.39 seconds
Started Jul 11 06:40:40 PM PDT 24
Finished Jul 11 06:42:11 PM PDT 24
Peak memory 265592 kb
Host smart-51dbc01e-9468-4c3b-a9f1-f39e614eee54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940946901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmd
s.1940946901
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.2253098191
Short name T79
Test name
Test status
Simulation time 7185985438 ps
CPU time 18.58 seconds
Started Jul 11 06:42:16 PM PDT 24
Finished Jul 11 06:42:35 PM PDT 24
Peak memory 224540 kb
Host smart-9951b8f1-dfd1-44cb-b752-ef4a2e8d6ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253098191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.2253098191
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.3668736447
Short name T435
Test name
Test status
Simulation time 2882773565 ps
CPU time 6.1 seconds
Started Jul 11 06:40:39 PM PDT 24
Finished Jul 11 06:40:47 PM PDT 24
Peak memory 232732 kb
Host smart-29c253e3-564a-4119-9e9b-a3bd78a4cd63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668736447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.3668736447
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.228800676
Short name T526
Test name
Test status
Simulation time 198014696 ps
CPU time 3.21 seconds
Started Jul 11 06:40:38 PM PDT 24
Finished Jul 11 06:40:43 PM PDT 24
Peak memory 232648 kb
Host smart-c8baa5c6-dc95-4847-9bcf-136249b27236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228800676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swap
.228800676
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.43125877
Short name T222
Test name
Test status
Simulation time 3356864335 ps
CPU time 13.92 seconds
Started Jul 11 06:40:40 PM PDT 24
Finished Jul 11 06:40:55 PM PDT 24
Peak memory 240888 kb
Host smart-a2d2eeec-f21f-48bb-a3d5-a2ff615ab906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43125877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.43125877
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.3189493692
Short name T908
Test name
Test status
Simulation time 1839296542 ps
CPU time 13.28 seconds
Started Jul 11 06:40:40 PM PDT 24
Finished Jul 11 06:40:55 PM PDT 24
Peak memory 219020 kb
Host smart-3d10a8dd-4b26-44f9-b778-2118512700cc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3189493692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.3189493692
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.2926323100
Short name T776
Test name
Test status
Simulation time 97975444 ps
CPU time 2.27 seconds
Started Jul 11 06:40:34 PM PDT 24
Finished Jul 11 06:40:37 PM PDT 24
Peak memory 216512 kb
Host smart-a3712ed3-1a53-4f7f-92d1-368c62af7395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926323100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.2926323100
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.2073145910
Short name T578
Test name
Test status
Simulation time 15399562888 ps
CPU time 24.27 seconds
Started Jul 11 06:40:35 PM PDT 24
Finished Jul 11 06:41:00 PM PDT 24
Peak memory 216316 kb
Host smart-eaa6397c-23b4-4ff9-9865-e91c68255d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073145910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.2073145910
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.3682539610
Short name T619
Test name
Test status
Simulation time 89388211 ps
CPU time 1.52 seconds
Started Jul 11 06:40:37 PM PDT 24
Finished Jul 11 06:40:39 PM PDT 24
Peak memory 216268 kb
Host smart-288b6ba9-a327-48c3-8cf9-d03386c95baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682539610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.3682539610
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.1746919557
Short name T732
Test name
Test status
Simulation time 1446256084 ps
CPU time 1.04 seconds
Started Jul 11 06:40:36 PM PDT 24
Finished Jul 11 06:40:39 PM PDT 24
Peak memory 207036 kb
Host smart-aa787561-cbdc-4f4e-8fc7-bb24a92164f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746919557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.1746919557
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.3548232781
Short name T797
Test name
Test status
Simulation time 7159623821 ps
CPU time 6.52 seconds
Started Jul 11 06:40:40 PM PDT 24
Finished Jul 11 06:40:48 PM PDT 24
Peak memory 224592 kb
Host smart-5fda4d39-d27f-4f80-ac9b-82d662aaf679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548232781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.3548232781
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.2975202373
Short name T941
Test name
Test status
Simulation time 35519966 ps
CPU time 0.7 seconds
Started Jul 11 06:40:53 PM PDT 24
Finished Jul 11 06:40:55 PM PDT 24
Peak memory 204964 kb
Host smart-7bf23cac-e6fc-4a14-aad4-90abe731e541
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975202373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
2975202373
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.799004568
Short name T698
Test name
Test status
Simulation time 7562558296 ps
CPU time 22.27 seconds
Started Jul 11 06:40:45 PM PDT 24
Finished Jul 11 06:41:08 PM PDT 24
Peak memory 232768 kb
Host smart-fb486629-291c-4d53-8a56-67e4b9ce3e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799004568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.799004568
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.2530936580
Short name T410
Test name
Test status
Simulation time 67184435 ps
CPU time 0.79 seconds
Started Jul 11 06:40:44 PM PDT 24
Finished Jul 11 06:40:45 PM PDT 24
Peak memory 205608 kb
Host smart-f0703cf3-6f09-4d22-8556-b92f348e99cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530936580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.2530936580
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.257779405
Short name T485
Test name
Test status
Simulation time 2340399569 ps
CPU time 16.79 seconds
Started Jul 11 06:40:50 PM PDT 24
Finished Jul 11 06:41:07 PM PDT 24
Peak memory 237104 kb
Host smart-556a0db4-e39a-43bf-9342-acfd94d84272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257779405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.257779405
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.2164124035
Short name T746
Test name
Test status
Simulation time 1383665105 ps
CPU time 21.38 seconds
Started Jul 11 06:40:49 PM PDT 24
Finished Jul 11 06:41:11 PM PDT 24
Peak memory 233860 kb
Host smart-6352fd1f-5040-4e11-a61b-86dd19edf55b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164124035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.2164124035
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.1289134372
Short name T456
Test name
Test status
Simulation time 927738329 ps
CPU time 14.56 seconds
Started Jul 11 06:40:51 PM PDT 24
Finished Jul 11 06:41:06 PM PDT 24
Peak memory 224604 kb
Host smart-6c38d824-e9e8-4dc3-97ed-87564540c922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289134372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.1289134372
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.3014231482
Short name T763
Test name
Test status
Simulation time 746463129 ps
CPU time 7.74 seconds
Started Jul 11 06:40:45 PM PDT 24
Finished Jul 11 06:40:54 PM PDT 24
Peak memory 232796 kb
Host smart-cc14dbd2-5a76-4518-8dfc-ee34056ddeee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014231482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.3014231482
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.3116995287
Short name T40
Test name
Test status
Simulation time 166698812909 ps
CPU time 562.71 seconds
Started Jul 11 06:40:49 PM PDT 24
Finished Jul 11 06:50:13 PM PDT 24
Peak memory 256592 kb
Host smart-ac4ecf99-2b6b-4c5c-a28c-b3f06e781c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116995287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmd
s.3116995287
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.2498857524
Short name T188
Test name
Test status
Simulation time 20307802962 ps
CPU time 23.36 seconds
Started Jul 11 06:40:45 PM PDT 24
Finished Jul 11 06:41:09 PM PDT 24
Peak memory 232780 kb
Host smart-fd810221-98a5-423f-929e-b5567a3ae995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498857524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.2498857524
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.14633986
Short name T538
Test name
Test status
Simulation time 37689517404 ps
CPU time 159 seconds
Started Jul 11 06:40:45 PM PDT 24
Finished Jul 11 06:43:26 PM PDT 24
Peak memory 249244 kb
Host smart-b89d94a8-0ef3-4403-8486-c759c537154d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14633986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.14633986
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.3380126516
Short name T774
Test name
Test status
Simulation time 1622020898 ps
CPU time 7.77 seconds
Started Jul 11 06:40:46 PM PDT 24
Finished Jul 11 06:40:55 PM PDT 24
Peak memory 232608 kb
Host smart-8ea5db44-8342-4fb8-8adb-6c64a1b5b2c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380126516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.3380126516
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.3422320709
Short name T621
Test name
Test status
Simulation time 12070655665 ps
CPU time 11.34 seconds
Started Jul 11 06:40:44 PM PDT 24
Finished Jul 11 06:40:57 PM PDT 24
Peak memory 232804 kb
Host smart-f547eac8-e135-4f90-9918-79e5743eee2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422320709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.3422320709
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.2780473888
Short name T587
Test name
Test status
Simulation time 7032621532 ps
CPU time 19.83 seconds
Started Jul 11 06:40:49 PM PDT 24
Finished Jul 11 06:41:10 PM PDT 24
Peak memory 221680 kb
Host smart-a596e08e-03f8-437b-b9e5-ea6e7a51b209
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2780473888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.2780473888
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.580035155
Short name T618
Test name
Test status
Simulation time 223313896 ps
CPU time 0.94 seconds
Started Jul 11 06:40:54 PM PDT 24
Finished Jul 11 06:40:56 PM PDT 24
Peak memory 207596 kb
Host smart-163900b4-535b-409d-8ae0-0da195d12504
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580035155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stres
s_all.580035155
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.2626587796
Short name T868
Test name
Test status
Simulation time 7328347139 ps
CPU time 17.19 seconds
Started Jul 11 06:40:44 PM PDT 24
Finished Jul 11 06:41:02 PM PDT 24
Peak memory 219972 kb
Host smart-c98608e3-610d-41ae-ad7b-353000e1740a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626587796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.2626587796
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.2202681675
Short name T682
Test name
Test status
Simulation time 768622914 ps
CPU time 2.63 seconds
Started Jul 11 06:40:46 PM PDT 24
Finished Jul 11 06:40:50 PM PDT 24
Peak memory 207896 kb
Host smart-31333b49-6a6d-4316-b016-16004db2e28e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202681675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.2202681675
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.2981568668
Short name T409
Test name
Test status
Simulation time 258594060 ps
CPU time 2.02 seconds
Started Jul 11 06:40:46 PM PDT 24
Finished Jul 11 06:40:49 PM PDT 24
Peak memory 216144 kb
Host smart-641a955b-241a-49b2-987f-2ad879281a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981568668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.2981568668
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.3602747532
Short name T373
Test name
Test status
Simulation time 30008763 ps
CPU time 0.78 seconds
Started Jul 11 06:40:45 PM PDT 24
Finished Jul 11 06:40:47 PM PDT 24
Peak memory 205988 kb
Host smart-eb1b4329-966f-474d-b6c2-e17598ee990f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602747532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.3602747532
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.1355467952
Short name T1010
Test name
Test status
Simulation time 15349572881 ps
CPU time 14.52 seconds
Started Jul 11 06:40:44 PM PDT 24
Finished Jul 11 06:40:59 PM PDT 24
Peak memory 224528 kb
Host smart-cb217ae9-d2e0-4d94-8c98-0e1b46194ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355467952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.1355467952
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.4209477623
Short name T692
Test name
Test status
Simulation time 11772966 ps
CPU time 0.72 seconds
Started Jul 11 06:40:59 PM PDT 24
Finished Jul 11 06:41:02 PM PDT 24
Peak memory 205820 kb
Host smart-c51ea644-91c7-42af-aebc-df506753d9cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209477623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
4209477623
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.3842584919
Short name T983
Test name
Test status
Simulation time 3642064633 ps
CPU time 12.61 seconds
Started Jul 11 06:40:55 PM PDT 24
Finished Jul 11 06:41:10 PM PDT 24
Peak memory 224544 kb
Host smart-a11309ae-6454-43ab-9e9a-f5cf80ed2275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842584919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.3842584919
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.2877316532
Short name T779
Test name
Test status
Simulation time 34774725 ps
CPU time 0.81 seconds
Started Jul 11 06:40:56 PM PDT 24
Finished Jul 11 06:40:59 PM PDT 24
Peak memory 207024 kb
Host smart-29465c6a-2fda-4878-9ab2-1f0feb4fbc49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877316532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.2877316532
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.3637309052
Short name T170
Test name
Test status
Simulation time 2933721831 ps
CPU time 42.21 seconds
Started Jul 11 06:40:58 PM PDT 24
Finished Jul 11 06:41:43 PM PDT 24
Peak memory 253320 kb
Host smart-63b6b4f1-1c6f-40e4-9304-a54e0d23dc1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637309052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.3637309052
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.1886954195
Short name T852
Test name
Test status
Simulation time 8383553746 ps
CPU time 47.07 seconds
Started Jul 11 06:40:58 PM PDT 24
Finished Jul 11 06:41:48 PM PDT 24
Peak memory 250384 kb
Host smart-1f6a0637-c000-44e8-96b3-fb15ec464977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886954195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.1886954195
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.2684846971
Short name T515
Test name
Test status
Simulation time 14946487621 ps
CPU time 90.94 seconds
Started Jul 11 06:40:57 PM PDT 24
Finished Jul 11 06:42:30 PM PDT 24
Peak memory 255256 kb
Host smart-33bca765-6159-465b-b971-6b6deeb9a3fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684846971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.2684846971
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.1221456409
Short name T369
Test name
Test status
Simulation time 164394342 ps
CPU time 3 seconds
Started Jul 11 06:40:57 PM PDT 24
Finished Jul 11 06:41:02 PM PDT 24
Peak memory 224508 kb
Host smart-9c8c77f1-df2e-405f-9740-040a0f0a0d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221456409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.1221456409
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.3066391731
Short name T748
Test name
Test status
Simulation time 4011558291 ps
CPU time 55.63 seconds
Started Jul 11 06:40:59 PM PDT 24
Finished Jul 11 06:41:57 PM PDT 24
Peak memory 257360 kb
Host smart-05f9d8e7-8f3c-4281-9e82-e96fb038841d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066391731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmd
s.3066391731
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.3432409567
Short name T141
Test name
Test status
Simulation time 33535939 ps
CPU time 2.24 seconds
Started Jul 11 06:40:55 PM PDT 24
Finished Jul 11 06:40:59 PM PDT 24
Peak memory 232408 kb
Host smart-3cdf8380-54d1-4845-8fc5-1ee8631780d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432409567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.3432409567
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.3155933712
Short name T971
Test name
Test status
Simulation time 2573258474 ps
CPU time 33.28 seconds
Started Jul 11 06:40:56 PM PDT 24
Finished Jul 11 06:41:31 PM PDT 24
Peak memory 248652 kb
Host smart-e0429acb-576a-4538-bfb9-49ca596d8b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155933712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.3155933712
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.2115648631
Short name T247
Test name
Test status
Simulation time 356752165 ps
CPU time 5.23 seconds
Started Jul 11 06:40:56 PM PDT 24
Finished Jul 11 06:41:03 PM PDT 24
Peak memory 224480 kb
Host smart-50c8510c-e0d6-4a6e-889f-d712dee3bdc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115648631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.2115648631
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.1149281839
Short name T677
Test name
Test status
Simulation time 2050843260 ps
CPU time 4.49 seconds
Started Jul 11 06:40:54 PM PDT 24
Finished Jul 11 06:40:59 PM PDT 24
Peak memory 232620 kb
Host smart-d7de46a3-aa89-4617-aa2a-d3e8a841d25a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149281839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.1149281839
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.3754908733
Short name T984
Test name
Test status
Simulation time 165613300 ps
CPU time 3.92 seconds
Started Jul 11 06:40:58 PM PDT 24
Finished Jul 11 06:41:03 PM PDT 24
Peak memory 218768 kb
Host smart-ead9783b-17b0-4532-8f46-eaf4c09cc1a3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3754908733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.3754908733
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.1433248386
Short name T145
Test name
Test status
Simulation time 58470084 ps
CPU time 1.2 seconds
Started Jul 11 06:40:59 PM PDT 24
Finished Jul 11 06:41:02 PM PDT 24
Peak memory 207676 kb
Host smart-239f5cc7-eeea-4832-a49b-28cf1d171f3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433248386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.1433248386
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.3996938756
Short name T341
Test name
Test status
Simulation time 11185400366 ps
CPU time 9.65 seconds
Started Jul 11 06:40:54 PM PDT 24
Finished Jul 11 06:41:04 PM PDT 24
Peak memory 216324 kb
Host smart-d7f89833-f56f-47ed-b431-b3769941e3d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996938756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.3996938756
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.830795547
Short name T875
Test name
Test status
Simulation time 65987332 ps
CPU time 0.89 seconds
Started Jul 11 06:40:54 PM PDT 24
Finished Jul 11 06:40:56 PM PDT 24
Peak memory 207012 kb
Host smart-872e817d-0efd-4ffd-99f8-1591e952e301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830795547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.830795547
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.1248931992
Short name T364
Test name
Test status
Simulation time 382457530 ps
CPU time 0.97 seconds
Started Jul 11 06:40:55 PM PDT 24
Finished Jul 11 06:40:58 PM PDT 24
Peak memory 207012 kb
Host smart-48b4d291-59dd-41b9-92b3-6869bb056cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248931992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.1248931992
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.2369413654
Short name T419
Test name
Test status
Simulation time 617354210 ps
CPU time 3.06 seconds
Started Jul 11 06:40:52 PM PDT 24
Finished Jul 11 06:40:55 PM PDT 24
Peak memory 224456 kb
Host smart-3098801f-a706-475f-926c-d63e05f4d0fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369413654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.2369413654
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.3561798880
Short name T309
Test name
Test status
Simulation time 16330849 ps
CPU time 0.73 seconds
Started Jul 11 06:41:02 PM PDT 24
Finished Jul 11 06:41:04 PM PDT 24
Peak memory 205860 kb
Host smart-488565e0-644d-438c-8106-97525374b52f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561798880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
3561798880
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.2567912377
Short name T946
Test name
Test status
Simulation time 387941160 ps
CPU time 3.61 seconds
Started Jul 11 06:41:02 PM PDT 24
Finished Jul 11 06:41:08 PM PDT 24
Peak memory 224520 kb
Host smart-55301dc8-a497-4843-9962-8e5541800417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567912377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.2567912377
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.239609972
Short name T457
Test name
Test status
Simulation time 25932962 ps
CPU time 0.78 seconds
Started Jul 11 06:40:58 PM PDT 24
Finished Jul 11 06:41:01 PM PDT 24
Peak memory 206640 kb
Host smart-0271c44d-4481-4336-9919-54a38e4423b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239609972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.239609972
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.2560551524
Short name T427
Test name
Test status
Simulation time 40769497 ps
CPU time 0.78 seconds
Started Jul 11 06:41:03 PM PDT 24
Finished Jul 11 06:41:06 PM PDT 24
Peak memory 215804 kb
Host smart-ece3623c-003f-48cd-bf1e-c4bf56f6e542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560551524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.2560551524
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.3490879875
Short name T728
Test name
Test status
Simulation time 25759325144 ps
CPU time 40.89 seconds
Started Jul 11 06:41:11 PM PDT 24
Finished Jul 11 06:41:53 PM PDT 24
Peak memory 250320 kb
Host smart-fc248766-8e36-40d3-ae60-6265576aed09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490879875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.3490879875
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.2645253037
Short name T459
Test name
Test status
Simulation time 73043234571 ps
CPU time 186.18 seconds
Started Jul 11 06:41:01 PM PDT 24
Finished Jul 11 06:44:09 PM PDT 24
Peak memory 250304 kb
Host smart-cb5f73be-f150-4e3f-b550-a77bdd497edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645253037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.2645253037
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.1618710913
Short name T696
Test name
Test status
Simulation time 96545712 ps
CPU time 3.51 seconds
Started Jul 11 06:41:03 PM PDT 24
Finished Jul 11 06:41:08 PM PDT 24
Peak memory 224504 kb
Host smart-28e3021c-8ab0-49ea-a861-a52b0d5d9c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618710913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.1618710913
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.686106304
Short name T810
Test name
Test status
Simulation time 41719694277 ps
CPU time 320.54 seconds
Started Jul 11 06:41:03 PM PDT 24
Finished Jul 11 06:46:25 PM PDT 24
Peak memory 254448 kb
Host smart-4708a62f-4eff-4549-a1b7-01d12f8bdaae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686106304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmds
.686106304
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.60760282
Short name T212
Test name
Test status
Simulation time 14843877358 ps
CPU time 13.68 seconds
Started Jul 11 06:40:58 PM PDT 24
Finished Jul 11 06:41:14 PM PDT 24
Peak memory 230468 kb
Host smart-1b4287c3-6a77-4700-bbd5-f64145d2ebc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60760282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.60760282
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.3216939341
Short name T890
Test name
Test status
Simulation time 1375759294 ps
CPU time 18.42 seconds
Started Jul 11 06:41:02 PM PDT 24
Finished Jul 11 06:41:23 PM PDT 24
Peak memory 232828 kb
Host smart-9ff6a447-7a09-4e72-b5c3-29df4f4b9e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216939341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.3216939341
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.328453367
Short name T238
Test name
Test status
Simulation time 1505503704 ps
CPU time 4.72 seconds
Started Jul 11 06:41:03 PM PDT 24
Finished Jul 11 06:41:10 PM PDT 24
Peak memory 224464 kb
Host smart-44d3d65a-0cf5-4c8b-8664-d17c2e348860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328453367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swap
.328453367
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.2831844798
Short name T793
Test name
Test status
Simulation time 3252665467 ps
CPU time 7.6 seconds
Started Jul 11 06:41:00 PM PDT 24
Finished Jul 11 06:41:10 PM PDT 24
Peak memory 232968 kb
Host smart-e77af168-b8b2-40de-8b71-e098df716de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831844798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.2831844798
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.3496361491
Short name T325
Test name
Test status
Simulation time 654279978 ps
CPU time 3.44 seconds
Started Jul 11 06:41:03 PM PDT 24
Finished Jul 11 06:41:08 PM PDT 24
Peak memory 218748 kb
Host smart-875bf78a-8b13-4da4-931c-28e8a4ca4c5e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3496361491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.3496361491
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.1180286389
Short name T405
Test name
Test status
Simulation time 19562390488 ps
CPU time 28.19 seconds
Started Jul 11 06:40:58 PM PDT 24
Finished Jul 11 06:41:29 PM PDT 24
Peak memory 216336 kb
Host smart-5be113df-60e5-4498-ae33-201bbcec1a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180286389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.1180286389
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.2443322711
Short name T501
Test name
Test status
Simulation time 13930451454 ps
CPU time 11.41 seconds
Started Jul 11 06:40:56 PM PDT 24
Finished Jul 11 06:41:09 PM PDT 24
Peak memory 216352 kb
Host smart-e8d2612e-5cc3-463c-b95d-5addc211d688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443322711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.2443322711
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.2296641761
Short name T993
Test name
Test status
Simulation time 138149135 ps
CPU time 1.24 seconds
Started Jul 11 06:40:58 PM PDT 24
Finished Jul 11 06:41:02 PM PDT 24
Peak memory 216272 kb
Host smart-5e094f1f-8a9b-4a5d-859b-e09028483789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296641761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.2296641761
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.1391107452
Short name T339
Test name
Test status
Simulation time 236894454 ps
CPU time 0.93 seconds
Started Jul 11 06:41:03 PM PDT 24
Finished Jul 11 06:41:06 PM PDT 24
Peak memory 205984 kb
Host smart-65dcf5a2-4aeb-4fd0-bff9-c681a2d68675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391107452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.1391107452
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.779254349
Short name T870
Test name
Test status
Simulation time 54440718 ps
CPU time 2.26 seconds
Started Jul 11 06:41:02 PM PDT 24
Finished Jul 11 06:41:06 PM PDT 24
Peak memory 224464 kb
Host smart-dfd32988-e8b1-4770-98c8-16f98f1b1c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779254349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.779254349
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.2105272676
Short name T318
Test name
Test status
Simulation time 16335815 ps
CPU time 0.76 seconds
Started Jul 11 06:41:07 PM PDT 24
Finished Jul 11 06:41:08 PM PDT 24
Peak memory 204968 kb
Host smart-46009598-ec5a-428e-a221-3d40bd8132a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105272676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
2105272676
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.2778699495
Short name T920
Test name
Test status
Simulation time 1180876475 ps
CPU time 5.15 seconds
Started Jul 11 06:41:07 PM PDT 24
Finished Jul 11 06:41:14 PM PDT 24
Peak memory 232808 kb
Host smart-5917662f-8b98-467d-ae1c-9c5a7fe14cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778699495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.2778699495
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.260512445
Short name T300
Test name
Test status
Simulation time 16680014 ps
CPU time 0.75 seconds
Started Jul 11 06:41:03 PM PDT 24
Finished Jul 11 06:41:06 PM PDT 24
Peak memory 205580 kb
Host smart-af4d80d8-b335-4463-974a-57ea8a1e57cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260512445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.260512445
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.1104603444
Short name T680
Test name
Test status
Simulation time 11324553520 ps
CPU time 76.41 seconds
Started Jul 11 06:41:07 PM PDT 24
Finished Jul 11 06:42:25 PM PDT 24
Peak memory 265608 kb
Host smart-2f8453d5-329f-472f-bd29-c4d93e3b9ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104603444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.1104603444
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.2563449692
Short name T187
Test name
Test status
Simulation time 63659039819 ps
CPU time 401.97 seconds
Started Jul 11 06:41:06 PM PDT 24
Finished Jul 11 06:47:49 PM PDT 24
Peak memory 281504 kb
Host smart-de6622ce-f20c-4fe6-9c6d-73ba1c146e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563449692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.2563449692
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.729311730
Short name T931
Test name
Test status
Simulation time 2559182210 ps
CPU time 15.82 seconds
Started Jul 11 06:41:08 PM PDT 24
Finished Jul 11 06:41:25 PM PDT 24
Peak memory 217748 kb
Host smart-abf0d75d-74ac-41da-b9df-663e8d17a9d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729311730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idle
.729311730
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.2391889156
Short name T613
Test name
Test status
Simulation time 9907065786 ps
CPU time 26.11 seconds
Started Jul 11 06:41:09 PM PDT 24
Finished Jul 11 06:41:37 PM PDT 24
Peak memory 232848 kb
Host smart-794dd2ba-0a04-498c-b60a-f4332af308f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391889156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.2391889156
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.1003153893
Short name T633
Test name
Test status
Simulation time 2156939710 ps
CPU time 8.3 seconds
Started Jul 11 06:41:07 PM PDT 24
Finished Jul 11 06:41:16 PM PDT 24
Peak memory 224576 kb
Host smart-bf067249-7199-41d2-93c4-0ee279733a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003153893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmd
s.1003153893
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.3472584551
Short name T661
Test name
Test status
Simulation time 1464701660 ps
CPU time 13.59 seconds
Started Jul 11 06:41:08 PM PDT 24
Finished Jul 11 06:41:24 PM PDT 24
Peak memory 224540 kb
Host smart-58867e51-82bc-48a6-94e8-829ccfab9c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472584551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.3472584551
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.3847023111
Short name T869
Test name
Test status
Simulation time 1452315951 ps
CPU time 16.23 seconds
Started Jul 11 06:41:08 PM PDT 24
Finished Jul 11 06:41:26 PM PDT 24
Peak memory 232672 kb
Host smart-ac15ccfd-2414-46b6-8c98-1b063131632e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847023111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.3847023111
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.2685625501
Short name T36
Test name
Test status
Simulation time 3271289178 ps
CPU time 5.23 seconds
Started Jul 11 06:41:05 PM PDT 24
Finished Jul 11 06:41:12 PM PDT 24
Peak memory 232768 kb
Host smart-5e7d6759-dadf-49ea-932e-a8d5190e6eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685625501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.2685625501
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.1980290057
Short name T981
Test name
Test status
Simulation time 19436798406 ps
CPU time 8.82 seconds
Started Jul 11 06:41:06 PM PDT 24
Finished Jul 11 06:41:16 PM PDT 24
Peak memory 240996 kb
Host smart-bcbc5fae-c027-40eb-8041-1dfb22306f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980290057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.1980290057
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.1691324528
Short name T121
Test name
Test status
Simulation time 212673578 ps
CPU time 5.06 seconds
Started Jul 11 06:41:09 PM PDT 24
Finished Jul 11 06:41:16 PM PDT 24
Peak memory 222588 kb
Host smart-fe16c091-f8eb-461b-8783-41438aa516d2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1691324528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.1691324528
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.3108536686
Short name T782
Test name
Test status
Simulation time 6156202814 ps
CPU time 25.27 seconds
Started Jul 11 06:41:09 PM PDT 24
Finished Jul 11 06:41:36 PM PDT 24
Peak memory 216392 kb
Host smart-7f98adc1-075e-4dab-afd5-009c7395589a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108536686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.3108536686
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.2753332637
Short name T460
Test name
Test status
Simulation time 1020447042 ps
CPU time 1.83 seconds
Started Jul 11 06:41:03 PM PDT 24
Finished Jul 11 06:41:07 PM PDT 24
Peak memory 207860 kb
Host smart-149b18a0-c8bb-4b30-a64c-e41707870099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753332637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.2753332637
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.889193492
Short name T860
Test name
Test status
Simulation time 231635133 ps
CPU time 3.52 seconds
Started Jul 11 06:41:11 PM PDT 24
Finished Jul 11 06:41:15 PM PDT 24
Peak memory 216272 kb
Host smart-bf86ceba-c2ad-4a38-84c1-22518cb0e522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889193492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.889193492
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.3924374778
Short name T738
Test name
Test status
Simulation time 64262299 ps
CPU time 0.83 seconds
Started Jul 11 06:41:09 PM PDT 24
Finished Jul 11 06:41:11 PM PDT 24
Peak memory 206004 kb
Host smart-ac6a0e4d-b003-476c-88e7-8638457f3c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924374778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.3924374778
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.3102883146
Short name T470
Test name
Test status
Simulation time 513804727 ps
CPU time 5.73 seconds
Started Jul 11 06:41:08 PM PDT 24
Finished Jul 11 06:41:15 PM PDT 24
Peak memory 232704 kb
Host smart-4d3b56ec-0fe6-47c8-af6e-c8568d363178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102883146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.3102883146
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.2941627250
Short name T818
Test name
Test status
Simulation time 14729835 ps
CPU time 0.74 seconds
Started Jul 11 06:41:17 PM PDT 24
Finished Jul 11 06:41:19 PM PDT 24
Peak memory 205544 kb
Host smart-4b3a74ae-26be-408d-aa86-78034036b6ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941627250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
2941627250
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.3772045700
Short name T689
Test name
Test status
Simulation time 1328775666 ps
CPU time 12.67 seconds
Started Jul 11 06:41:15 PM PDT 24
Finished Jul 11 06:41:29 PM PDT 24
Peak memory 224456 kb
Host smart-cf80a1f9-b733-4d2e-892c-3766a71e91e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772045700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.3772045700
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.1834900990
Short name T1011
Test name
Test status
Simulation time 24552886 ps
CPU time 0.78 seconds
Started Jul 11 06:41:12 PM PDT 24
Finished Jul 11 06:41:14 PM PDT 24
Peak memory 206584 kb
Host smart-a2d8ee2d-daf7-470f-8c2a-1aecc64a25ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834900990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.1834900990
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.2037766115
Short name T537
Test name
Test status
Simulation time 65220864051 ps
CPU time 188.99 seconds
Started Jul 11 06:41:15 PM PDT 24
Finished Jul 11 06:44:25 PM PDT 24
Peak memory 249212 kb
Host smart-bed15a91-d966-43af-b877-a5e3280a195f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037766115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.2037766115
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.650385178
Short name T169
Test name
Test status
Simulation time 12596493317 ps
CPU time 86.22 seconds
Started Jul 11 06:41:17 PM PDT 24
Finished Jul 11 06:42:44 PM PDT 24
Peak memory 253660 kb
Host smart-5c69351d-f7b8-483a-aa84-0b162676377a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650385178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.650385178
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.332137069
Short name T851
Test name
Test status
Simulation time 27218518100 ps
CPU time 106.94 seconds
Started Jul 11 06:41:16 PM PDT 24
Finished Jul 11 06:43:03 PM PDT 24
Peak memory 251292 kb
Host smart-12721674-0b00-4800-97d1-bc95eac06a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332137069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idle
.332137069
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.3624885465
Short name T448
Test name
Test status
Simulation time 457051163 ps
CPU time 8.76 seconds
Started Jul 11 06:41:16 PM PDT 24
Finished Jul 11 06:41:26 PM PDT 24
Peak memory 233752 kb
Host smart-1c1b9636-a71f-4616-806e-60a3fc6a3d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624885465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.3624885465
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.2953184133
Short name T257
Test name
Test status
Simulation time 17904695916 ps
CPU time 51.71 seconds
Started Jul 11 06:41:17 PM PDT 24
Finished Jul 11 06:42:10 PM PDT 24
Peak memory 266932 kb
Host smart-09dca88c-4dca-470c-8116-6778c1e5dbcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953184133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmd
s.2953184133
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.2962115841
Short name T635
Test name
Test status
Simulation time 272707822 ps
CPU time 4.52 seconds
Started Jul 11 06:41:12 PM PDT 24
Finished Jul 11 06:41:18 PM PDT 24
Peak memory 227844 kb
Host smart-dd135287-5662-4de0-880e-740c47fb7b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962115841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.2962115841
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.2552518458
Short name T954
Test name
Test status
Simulation time 491047245 ps
CPU time 9.7 seconds
Started Jul 11 06:41:17 PM PDT 24
Finished Jul 11 06:41:28 PM PDT 24
Peak memory 232728 kb
Host smart-63691397-c740-43fa-b06d-d78b92c28816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552518458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.2552518458
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.703413685
Short name T807
Test name
Test status
Simulation time 9288023688 ps
CPU time 27.89 seconds
Started Jul 11 06:41:11 PM PDT 24
Finished Jul 11 06:41:40 PM PDT 24
Peak memory 232748 kb
Host smart-e60e559d-c2d1-4f29-9ef4-3757d253a0d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703413685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swap
.703413685
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.2656071038
Short name T894
Test name
Test status
Simulation time 3200279567 ps
CPU time 5.11 seconds
Started Jul 11 06:41:11 PM PDT 24
Finished Jul 11 06:41:17 PM PDT 24
Peak memory 232736 kb
Host smart-6bb5584f-e573-45a6-a005-6ccc36845ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656071038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.2656071038
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.2620876752
Short name T867
Test name
Test status
Simulation time 993609643 ps
CPU time 9.47 seconds
Started Jul 11 06:41:16 PM PDT 24
Finished Jul 11 06:41:26 PM PDT 24
Peak memory 223244 kb
Host smart-df421743-a7d9-455a-aef2-31dc55ca7273
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2620876752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.2620876752
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.653086649
Short name T19
Test name
Test status
Simulation time 21510812351 ps
CPU time 122.73 seconds
Started Jul 11 06:41:17 PM PDT 24
Finished Jul 11 06:43:21 PM PDT 24
Peak memory 269988 kb
Host smart-b717ca94-5f89-481e-9ed4-03c9f4df8a2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653086649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stres
s_all.653086649
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.3879022164
Short name T281
Test name
Test status
Simulation time 1495658814 ps
CPU time 5.9 seconds
Started Jul 11 06:41:12 PM PDT 24
Finished Jul 11 06:41:19 PM PDT 24
Peak memory 216460 kb
Host smart-fd60220c-354a-4ca5-b0c1-6c1ee3788987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879022164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.3879022164
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.2544545799
Short name T544
Test name
Test status
Simulation time 5993292124 ps
CPU time 14.51 seconds
Started Jul 11 06:41:12 PM PDT 24
Finished Jul 11 06:41:28 PM PDT 24
Peak memory 216380 kb
Host smart-8d921a58-ce76-41c3-9cd7-03a17da0a1cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544545799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.2544545799
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.2447148
Short name T285
Test name
Test status
Simulation time 360770863 ps
CPU time 9.27 seconds
Started Jul 11 06:41:12 PM PDT 24
Finished Jul 11 06:41:22 PM PDT 24
Peak memory 216192 kb
Host smart-5ea8a497-8f47-47ae-87b4-cab527735df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.2447148
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.1742482503
Short name T68
Test name
Test status
Simulation time 266498241 ps
CPU time 0.91 seconds
Started Jul 11 06:41:11 PM PDT 24
Finished Jul 11 06:41:12 PM PDT 24
Peak memory 205980 kb
Host smart-651462c6-6180-40ec-a4d6-2745bd482246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742482503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.1742482503
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.1359982356
Short name T596
Test name
Test status
Simulation time 1790543729 ps
CPU time 7.81 seconds
Started Jul 11 06:41:16 PM PDT 24
Finished Jul 11 06:41:25 PM PDT 24
Peak memory 232716 kb
Host smart-f202e327-49e1-4016-b081-98a96a37b700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359982356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.1359982356
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.2480852426
Short name T914
Test name
Test status
Simulation time 11536816 ps
CPU time 0.7 seconds
Started Jul 11 06:41:28 PM PDT 24
Finished Jul 11 06:41:30 PM PDT 24
Peak memory 205612 kb
Host smart-16b40a81-ca59-489c-bed8-bf664f8095fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480852426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
2480852426
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.2530546403
Short name T733
Test name
Test status
Simulation time 28947492 ps
CPU time 0.77 seconds
Started Jul 11 06:41:16 PM PDT 24
Finished Jul 11 06:41:18 PM PDT 24
Peak memory 205900 kb
Host smart-f8b6d95c-4a70-47b0-9fb5-6fe694133cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530546403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.2530546403
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.2825839325
Short name T492
Test name
Test status
Simulation time 120737439 ps
CPU time 0.81 seconds
Started Jul 11 06:41:22 PM PDT 24
Finished Jul 11 06:41:23 PM PDT 24
Peak memory 215804 kb
Host smart-15b83885-637d-47b7-89f4-8ee2bdf7fe1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825839325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.2825839325
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.2527891373
Short name T32
Test name
Test status
Simulation time 64010178625 ps
CPU time 570.08 seconds
Started Jul 11 06:41:24 PM PDT 24
Finished Jul 11 06:50:55 PM PDT 24
Peak memory 254136 kb
Host smart-ce1ab694-d101-4017-a881-cf357ced0d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527891373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.2527891373
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.357506995
Short name T197
Test name
Test status
Simulation time 85606611341 ps
CPU time 243.13 seconds
Started Jul 11 06:41:24 PM PDT 24
Finished Jul 11 06:45:28 PM PDT 24
Peak memory 272104 kb
Host smart-deb3aad2-0f54-4f0b-aedc-2120ad80a16d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357506995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idle
.357506995
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.2364947619
Short name T272
Test name
Test status
Simulation time 394901821 ps
CPU time 8.74 seconds
Started Jul 11 06:41:20 PM PDT 24
Finished Jul 11 06:41:30 PM PDT 24
Peak memory 234056 kb
Host smart-106fe92f-cde0-4ca7-b0c0-919b581d9139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364947619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.2364947619
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.1377167667
Short name T589
Test name
Test status
Simulation time 57556001174 ps
CPU time 122.88 seconds
Started Jul 11 06:41:22 PM PDT 24
Finished Jul 11 06:43:25 PM PDT 24
Peak memory 249272 kb
Host smart-458205e8-6493-44cc-ba6e-f9080e7c6e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377167667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmd
s.1377167667
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.3493274146
Short name T50
Test name
Test status
Simulation time 270643579 ps
CPU time 6.53 seconds
Started Jul 11 06:41:21 PM PDT 24
Finished Jul 11 06:41:29 PM PDT 24
Peak memory 224456 kb
Host smart-05353fea-f955-40ef-a0d9-6c99484886cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493274146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.3493274146
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.4221570527
Short name T893
Test name
Test status
Simulation time 809557824 ps
CPU time 5.35 seconds
Started Jul 11 06:41:21 PM PDT 24
Finished Jul 11 06:41:27 PM PDT 24
Peak memory 232720 kb
Host smart-e73310ed-f2e9-4b51-a2aa-ff00e1fc827e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221570527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.4221570527
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.2026211299
Short name T602
Test name
Test status
Simulation time 35259246136 ps
CPU time 29.56 seconds
Started Jul 11 06:41:23 PM PDT 24
Finished Jul 11 06:41:53 PM PDT 24
Peak memory 237240 kb
Host smart-b67c07c8-642a-48f1-bb94-50e907a15da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026211299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.2026211299
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.1178977952
Short name T995
Test name
Test status
Simulation time 35188738977 ps
CPU time 21.51 seconds
Started Jul 11 06:41:22 PM PDT 24
Finished Jul 11 06:41:44 PM PDT 24
Peak memory 239636 kb
Host smart-c2ed335e-d4de-4587-b0d7-ff1b7f6417bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178977952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.1178977952
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.4124827791
Short name T402
Test name
Test status
Simulation time 1749381583 ps
CPU time 11.5 seconds
Started Jul 11 06:41:21 PM PDT 24
Finished Jul 11 06:41:34 PM PDT 24
Peak memory 222104 kb
Host smart-d51bbd32-61fa-44be-9ec6-a26ba5873911
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4124827791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.4124827791
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.1734336313
Short name T359
Test name
Test status
Simulation time 201958862 ps
CPU time 0.97 seconds
Started Jul 11 06:41:27 PM PDT 24
Finished Jul 11 06:41:29 PM PDT 24
Peak memory 206820 kb
Host smart-5fc910e2-9c64-4aa2-a40b-7605cf899d5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734336313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.1734336313
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.3684624478
Short name T603
Test name
Test status
Simulation time 1931015928 ps
CPU time 14.44 seconds
Started Jul 11 06:41:21 PM PDT 24
Finished Jul 11 06:41:37 PM PDT 24
Peak memory 216360 kb
Host smart-edc76155-ae27-4554-a4f1-e350a6c4415d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684624478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.3684624478
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.1995624545
Short name T612
Test name
Test status
Simulation time 2201799396 ps
CPU time 6.87 seconds
Started Jul 11 06:41:18 PM PDT 24
Finished Jul 11 06:41:26 PM PDT 24
Peak memory 216260 kb
Host smart-1bafff07-22fb-4558-b802-447a91d1a2e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995624545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.1995624545
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.3108944947
Short name T334
Test name
Test status
Simulation time 142868613 ps
CPU time 1.09 seconds
Started Jul 11 06:41:23 PM PDT 24
Finished Jul 11 06:41:25 PM PDT 24
Peak memory 207924 kb
Host smart-e5b5fb84-9220-4702-8131-98bbc428d407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108944947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.3108944947
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.2189875882
Short name T474
Test name
Test status
Simulation time 152431889 ps
CPU time 0.88 seconds
Started Jul 11 06:41:21 PM PDT 24
Finished Jul 11 06:41:23 PM PDT 24
Peak memory 206008 kb
Host smart-fccae0c8-1668-4312-9d86-513e07e987fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189875882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.2189875882
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.1875769838
Short name T579
Test name
Test status
Simulation time 7938243496 ps
CPU time 6.87 seconds
Started Jul 11 06:41:21 PM PDT 24
Finished Jul 11 06:41:28 PM PDT 24
Peak memory 224636 kb
Host smart-2a82eb8a-7fb8-4170-a83f-24f513a4b6a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875769838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.1875769838
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.2684109129
Short name T685
Test name
Test status
Simulation time 49994626 ps
CPU time 0.71 seconds
Started Jul 11 06:41:34 PM PDT 24
Finished Jul 11 06:41:36 PM PDT 24
Peak memory 205512 kb
Host smart-76155480-ae17-4e43-a117-a926342332ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684109129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
2684109129
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.1148121477
Short name T1000
Test name
Test status
Simulation time 229571489 ps
CPU time 2.67 seconds
Started Jul 11 06:41:30 PM PDT 24
Finished Jul 11 06:41:34 PM PDT 24
Peak memory 232300 kb
Host smart-0b66b719-6de7-44a2-b517-f8485d696059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148121477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.1148121477
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.3940249613
Short name T351
Test name
Test status
Simulation time 99810005 ps
CPU time 0.78 seconds
Started Jul 11 06:41:26 PM PDT 24
Finished Jul 11 06:41:27 PM PDT 24
Peak memory 205600 kb
Host smart-ceb773cb-615f-4395-b155-f37b73391647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940249613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.3940249613
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.270890583
Short name T772
Test name
Test status
Simulation time 11268776369 ps
CPU time 41.9 seconds
Started Jul 11 06:41:35 PM PDT 24
Finished Jul 11 06:42:19 PM PDT 24
Peak memory 250576 kb
Host smart-e8863d21-0936-491e-830f-456a9684e0cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270890583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.270890583
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.263091562
Short name T506
Test name
Test status
Simulation time 14770768652 ps
CPU time 110.1 seconds
Started Jul 11 06:41:35 PM PDT 24
Finished Jul 11 06:43:26 PM PDT 24
Peak memory 249236 kb
Host smart-cada8a99-1a14-4d60-b49e-b4ca53327ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263091562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idle
.263091562
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.1595192551
Short name T274
Test name
Test status
Simulation time 1163110189 ps
CPU time 7.26 seconds
Started Jul 11 06:41:35 PM PDT 24
Finished Jul 11 06:41:44 PM PDT 24
Peak memory 224464 kb
Host smart-b64534c2-3447-406d-9ec6-9852be6d8208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595192551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.1595192551
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.1273886371
Short name T202
Test name
Test status
Simulation time 74675088162 ps
CPU time 503.6 seconds
Started Jul 11 06:41:33 PM PDT 24
Finished Jul 11 06:49:58 PM PDT 24
Peak memory 257356 kb
Host smart-fa35951b-1fe5-48cc-ba1a-773fc6c641dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273886371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmd
s.1273886371
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.2808789868
Short name T229
Test name
Test status
Simulation time 1691619447 ps
CPU time 21.48 seconds
Started Jul 11 06:41:30 PM PDT 24
Finished Jul 11 06:41:53 PM PDT 24
Peak memory 224404 kb
Host smart-1a3a9cb7-3c17-41d8-aeb8-29110bdb7914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808789868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.2808789868
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.2600259973
Short name T956
Test name
Test status
Simulation time 5445379853 ps
CPU time 13.91 seconds
Started Jul 11 06:41:28 PM PDT 24
Finished Jul 11 06:41:43 PM PDT 24
Peak memory 249176 kb
Host smart-de71c461-2c68-40f3-8d6b-1ff9ab7ae8f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600259973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.2600259973
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.1045520924
Short name T465
Test name
Test status
Simulation time 165282806 ps
CPU time 3.11 seconds
Started Jul 11 06:41:31 PM PDT 24
Finished Jul 11 06:41:35 PM PDT 24
Peak memory 232648 kb
Host smart-6c77b1e2-1131-4983-a2de-3b17573861b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045520924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.1045520924
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.3731503907
Short name T404
Test name
Test status
Simulation time 761058210 ps
CPU time 3.45 seconds
Started Jul 11 06:41:29 PM PDT 24
Finished Jul 11 06:41:34 PM PDT 24
Peak memory 224468 kb
Host smart-c281cd73-1b78-4280-a3ea-3d43e68a95d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731503907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.3731503907
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.4071910891
Short name T938
Test name
Test status
Simulation time 1458744997 ps
CPU time 5.68 seconds
Started Jul 11 06:41:36 PM PDT 24
Finished Jul 11 06:41:43 PM PDT 24
Peak memory 222644 kb
Host smart-cbfa61f4-a144-410c-ad87-e3ac88366a6e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4071910891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.4071910891
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.1727907621
Short name T664
Test name
Test status
Simulation time 239073622 ps
CPU time 1.16 seconds
Started Jul 11 06:41:33 PM PDT 24
Finished Jul 11 06:41:34 PM PDT 24
Peak memory 206960 kb
Host smart-4893daea-a54a-45a1-96a1-16e60951d28c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727907621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.1727907621
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.3155935736
Short name T279
Test name
Test status
Simulation time 2223475820 ps
CPU time 15.54 seconds
Started Jul 11 06:41:25 PM PDT 24
Finished Jul 11 06:41:42 PM PDT 24
Peak memory 216404 kb
Host smart-258b5d2d-93cf-42f3-925b-72097d4462a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155935736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.3155935736
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.2483908853
Short name T411
Test name
Test status
Simulation time 3855925296 ps
CPU time 6.52 seconds
Started Jul 11 06:41:25 PM PDT 24
Finished Jul 11 06:41:33 PM PDT 24
Peak memory 216504 kb
Host smart-70119c0c-ad10-47d1-acfe-f08941eff349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483908853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.2483908853
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.585886283
Short name T22
Test name
Test status
Simulation time 126289913 ps
CPU time 1.81 seconds
Started Jul 11 06:41:29 PM PDT 24
Finished Jul 11 06:41:32 PM PDT 24
Peak memory 216220 kb
Host smart-79ea3796-bf78-47ac-8e91-1094bd351a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585886283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.585886283
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.3815603575
Short name T756
Test name
Test status
Simulation time 62726884 ps
CPU time 0.79 seconds
Started Jul 11 06:41:25 PM PDT 24
Finished Jul 11 06:41:27 PM PDT 24
Peak memory 206004 kb
Host smart-cb74a346-9221-4322-bd37-4d3fd8e10171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815603575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.3815603575
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.316796106
Short name T3
Test name
Test status
Simulation time 571481645 ps
CPU time 5.59 seconds
Started Jul 11 06:41:29 PM PDT 24
Finished Jul 11 06:41:36 PM PDT 24
Peak memory 224464 kb
Host smart-e21350d5-5dbf-40af-9823-df6fc8e92ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316796106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.316796106
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.1643769794
Short name T649
Test name
Test status
Simulation time 12578443 ps
CPU time 0.74 seconds
Started Jul 11 06:41:45 PM PDT 24
Finished Jul 11 06:41:47 PM PDT 24
Peak memory 205564 kb
Host smart-32f489e6-8f9f-4583-bde6-863786dd8e68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643769794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
1643769794
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.121959865
Short name T725
Test name
Test status
Simulation time 1813112326 ps
CPU time 7.39 seconds
Started Jul 11 06:41:38 PM PDT 24
Finished Jul 11 06:41:46 PM PDT 24
Peak memory 224468 kb
Host smart-6729bc90-103a-4b76-b1f6-976d74d975d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121959865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.121959865
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.3861494082
Short name T295
Test name
Test status
Simulation time 57960331 ps
CPU time 0.76 seconds
Started Jul 11 06:41:35 PM PDT 24
Finished Jul 11 06:41:36 PM PDT 24
Peak memory 205592 kb
Host smart-68579086-0db7-4196-a829-e086664006f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861494082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.3861494082
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.3631544020
Short name T413
Test name
Test status
Simulation time 49974205209 ps
CPU time 198.31 seconds
Started Jul 11 06:41:38 PM PDT 24
Finished Jul 11 06:44:58 PM PDT 24
Peak memory 250484 kb
Host smart-3610b4b2-7422-4427-b73a-3e00c1b832e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631544020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.3631544020
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.3962144307
Short name T430
Test name
Test status
Simulation time 8212583412 ps
CPU time 64.24 seconds
Started Jul 11 06:41:38 PM PDT 24
Finished Jul 11 06:42:43 PM PDT 24
Peak memory 252448 kb
Host smart-53adfc46-cd62-46d5-afa1-f84094673061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962144307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.3962144307
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.3659085309
Short name T7
Test name
Test status
Simulation time 7056952744 ps
CPU time 119.4 seconds
Started Jul 11 06:41:39 PM PDT 24
Finished Jul 11 06:43:39 PM PDT 24
Peak memory 257464 kb
Host smart-30616beb-d311-403f-af81-79bf4e3a4f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659085309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.3659085309
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.128435968
Short name T365
Test name
Test status
Simulation time 1230138008 ps
CPU time 6.23 seconds
Started Jul 11 06:41:38 PM PDT 24
Finished Jul 11 06:41:46 PM PDT 24
Peak memory 238224 kb
Host smart-8d1f5d59-036c-483c-a48d-cc4f1f8c7c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128435968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.128435968
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.1819145717
Short name T712
Test name
Test status
Simulation time 2688442634 ps
CPU time 18.61 seconds
Started Jul 11 06:41:36 PM PDT 24
Finished Jul 11 06:41:56 PM PDT 24
Peak memory 233808 kb
Host smart-bacd6890-8865-4e3b-9243-f6570fc8aeb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819145717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmd
s.1819145717
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.1184469849
Short name T12
Test name
Test status
Simulation time 1001703511 ps
CPU time 6.61 seconds
Started Jul 11 06:41:38 PM PDT 24
Finished Jul 11 06:41:45 PM PDT 24
Peak memory 224464 kb
Host smart-c45c37f5-a02a-4598-a357-cdf408f9c346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184469849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.1184469849
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.976876358
Short name T528
Test name
Test status
Simulation time 8468301683 ps
CPU time 15.98 seconds
Started Jul 11 06:41:38 PM PDT 24
Finished Jul 11 06:41:54 PM PDT 24
Peak memory 240068 kb
Host smart-afdde31b-9b0e-4a9b-8988-eba658a2720a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976876358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.976876358
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.4177783891
Short name T958
Test name
Test status
Simulation time 930092325 ps
CPU time 3.03 seconds
Started Jul 11 06:41:38 PM PDT 24
Finished Jul 11 06:41:41 PM PDT 24
Peak memory 224380 kb
Host smart-e98b5d24-871e-493f-8ffb-b35ef712eaac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177783891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.4177783891
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.2010559460
Short name T443
Test name
Test status
Simulation time 340668315 ps
CPU time 2.57 seconds
Started Jul 11 06:41:40 PM PDT 24
Finished Jul 11 06:41:44 PM PDT 24
Peak memory 224512 kb
Host smart-67598c7e-2819-4a26-937f-f2e9d42c96aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010559460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.2010559460
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.2700711583
Short name T673
Test name
Test status
Simulation time 658439644 ps
CPU time 10.01 seconds
Started Jul 11 06:41:39 PM PDT 24
Finished Jul 11 06:41:50 PM PDT 24
Peak memory 218928 kb
Host smart-ccf70d30-810e-443b-9603-195dcde462b9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2700711583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.2700711583
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.2121878629
Short name T142
Test name
Test status
Simulation time 30980675572 ps
CPU time 42.34 seconds
Started Jul 11 06:41:32 PM PDT 24
Finished Jul 11 06:42:15 PM PDT 24
Peak memory 216372 kb
Host smart-f26eb9d6-b24f-449c-8e5c-136ec0f34232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121878629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.2121878629
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.3621469187
Short name T866
Test name
Test status
Simulation time 577434885 ps
CPU time 2.95 seconds
Started Jul 11 06:41:36 PM PDT 24
Finished Jul 11 06:41:40 PM PDT 24
Peak memory 216184 kb
Host smart-e3b389be-8347-46b5-95a7-6da978979a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621469187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.3621469187
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.3165874355
Short name T889
Test name
Test status
Simulation time 38801695 ps
CPU time 1.31 seconds
Started Jul 11 06:41:34 PM PDT 24
Finished Jul 11 06:41:37 PM PDT 24
Peak memory 216224 kb
Host smart-2e0a80fd-9c3c-4d4f-b93a-99f7c7f39d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165874355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.3165874355
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.421616063
Short name T853
Test name
Test status
Simulation time 162985413 ps
CPU time 0.97 seconds
Started Jul 11 06:41:35 PM PDT 24
Finished Jul 11 06:41:37 PM PDT 24
Peak memory 207024 kb
Host smart-204e1662-9d5c-4547-9b24-b57ac819ca18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421616063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.421616063
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.1814955162
Short name T464
Test name
Test status
Simulation time 149698972 ps
CPU time 2.5 seconds
Started Jul 11 06:41:39 PM PDT 24
Finished Jul 11 06:41:43 PM PDT 24
Peak memory 224448 kb
Host smart-abf09bad-6919-4865-9216-55cdefd84c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814955162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.1814955162
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.3479009248
Short name T675
Test name
Test status
Simulation time 41877742 ps
CPU time 0.74 seconds
Started Jul 11 06:35:14 PM PDT 24
Finished Jul 11 06:35:15 PM PDT 24
Peak memory 205972 kb
Host smart-6acacea6-d0e4-4958-9422-a566b5f299d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479009248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.3
479009248
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.1563130048
Short name T987
Test name
Test status
Simulation time 798158320 ps
CPU time 4.98 seconds
Started Jul 11 06:35:13 PM PDT 24
Finished Jul 11 06:35:18 PM PDT 24
Peak memory 232900 kb
Host smart-1763c853-1a9e-4fdd-9d2f-fb1249663f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563130048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.1563130048
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.2257506777
Short name T667
Test name
Test status
Simulation time 15340695 ps
CPU time 0.8 seconds
Started Jul 11 06:35:02 PM PDT 24
Finished Jul 11 06:35:04 PM PDT 24
Peak memory 206644 kb
Host smart-15d5acd6-a600-412c-a753-a6f15c6cf6d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257506777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.2257506777
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.580021406
Short name T884
Test name
Test status
Simulation time 5270506436 ps
CPU time 68.23 seconds
Started Jul 11 06:35:15 PM PDT 24
Finished Jul 11 06:36:24 PM PDT 24
Peak memory 253224 kb
Host smart-c2bbbdde-ab22-41ee-8e58-8bb651ea5703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580021406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.580021406
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.4162217523
Short name T231
Test name
Test status
Simulation time 929983203811 ps
CPU time 645.53 seconds
Started Jul 11 06:35:15 PM PDT 24
Finished Jul 11 06:46:02 PM PDT 24
Peak memory 270796 kb
Host smart-28469f7f-7fb9-47af-94fa-dbe28b6d4523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162217523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.4162217523
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.253616394
Short name T179
Test name
Test status
Simulation time 9850590165 ps
CPU time 138.35 seconds
Started Jul 11 06:35:15 PM PDT 24
Finished Jul 11 06:37:35 PM PDT 24
Peak memory 254472 kb
Host smart-8ef8d199-428d-4db7-b661-a95af61cc4a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253616394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle.
253616394
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.3021155283
Short name T820
Test name
Test status
Simulation time 371445202 ps
CPU time 6.21 seconds
Started Jul 11 06:35:10 PM PDT 24
Finished Jul 11 06:35:17 PM PDT 24
Peak memory 249092 kb
Host smart-1a7a6efe-5a7d-490e-8708-2c702c92d454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021155283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.3021155283
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.3079204751
Short name T74
Test name
Test status
Simulation time 10585460566 ps
CPU time 46.76 seconds
Started Jul 11 06:35:11 PM PDT 24
Finished Jul 11 06:35:58 PM PDT 24
Peak memory 250720 kb
Host smart-2b522cf5-5f20-4e39-a01a-af29b48ed649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079204751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds
.3079204751
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.2138430967
Short name T740
Test name
Test status
Simulation time 97002274 ps
CPU time 2.85 seconds
Started Jul 11 06:35:11 PM PDT 24
Finished Jul 11 06:35:14 PM PDT 24
Peak memory 218796 kb
Host smart-33685164-e52a-4bc3-afe3-a7d0781dbaf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138430967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.2138430967
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.2225766863
Short name T242
Test name
Test status
Simulation time 403225204 ps
CPU time 5.01 seconds
Started Jul 11 06:35:11 PM PDT 24
Finished Jul 11 06:35:16 PM PDT 24
Peak memory 224464 kb
Host smart-e803ae65-2908-44c3-8fd4-3ee3ad7a7e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225766863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.2225766863
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.3959011661
Short name T263
Test name
Test status
Simulation time 648384457 ps
CPU time 5.78 seconds
Started Jul 11 06:35:11 PM PDT 24
Finished Jul 11 06:35:17 PM PDT 24
Peak memory 224460 kb
Host smart-ec06a7b5-06ec-40c6-a080-7f5e05c0a810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959011661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.3959011661
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.4242065676
Short name T795
Test name
Test status
Simulation time 181740190 ps
CPU time 2.19 seconds
Started Jul 11 06:35:05 PM PDT 24
Finished Jul 11 06:35:08 PM PDT 24
Peak memory 223756 kb
Host smart-8ddc24c0-926c-48b7-a288-42a671e9d657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242065676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.4242065676
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.4221908913
Short name T716
Test name
Test status
Simulation time 3378231977 ps
CPU time 8.76 seconds
Started Jul 11 06:35:12 PM PDT 24
Finished Jul 11 06:35:21 PM PDT 24
Peak memory 222212 kb
Host smart-0c6598b5-73af-4f6e-bd57-76888fa6677c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4221908913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.4221908913
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.2184378225
Short name T628
Test name
Test status
Simulation time 2233281214 ps
CPU time 14.48 seconds
Started Jul 11 06:35:16 PM PDT 24
Finished Jul 11 06:35:32 PM PDT 24
Peak memory 224604 kb
Host smart-a3e34f4d-6664-4e43-87fe-f7d399bf01f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184378225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.2184378225
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.347555918
Short name T498
Test name
Test status
Simulation time 8631453958 ps
CPU time 30.03 seconds
Started Jul 11 06:35:03 PM PDT 24
Finished Jul 11 06:35:34 PM PDT 24
Peak memory 216540 kb
Host smart-a1a20eed-7c1f-4f79-91d3-871c132833ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347555918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.347555918
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.1860367709
Short name T301
Test name
Test status
Simulation time 1883095263 ps
CPU time 7.22 seconds
Started Jul 11 06:35:03 PM PDT 24
Finished Jul 11 06:35:11 PM PDT 24
Peak memory 216264 kb
Host smart-1f3fc503-ee33-4b3d-b024-0bfe94f327b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860367709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.1860367709
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.3177449428
Short name T534
Test name
Test status
Simulation time 95185517 ps
CPU time 1.34 seconds
Started Jul 11 06:35:07 PM PDT 24
Finished Jul 11 06:35:09 PM PDT 24
Peak memory 216220 kb
Host smart-ac4663ad-a664-431f-87c2-211b24ca71ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177449428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.3177449428
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.3127489952
Short name T385
Test name
Test status
Simulation time 68861809 ps
CPU time 0.92 seconds
Started Jul 11 06:35:06 PM PDT 24
Finished Jul 11 06:35:08 PM PDT 24
Peak memory 207032 kb
Host smart-c32d4d41-da5f-414a-bd4b-cc385a9d4680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127489952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.3127489952
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.2218228703
Short name T912
Test name
Test status
Simulation time 2463076801 ps
CPU time 7.97 seconds
Started Jul 11 06:35:12 PM PDT 24
Finished Jul 11 06:35:21 PM PDT 24
Peak memory 224592 kb
Host smart-4ee17539-5d00-4d3e-b181-809d772a7273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218228703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.2218228703
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.107562395
Short name T313
Test name
Test status
Simulation time 38486218 ps
CPU time 0.73 seconds
Started Jul 11 06:35:25 PM PDT 24
Finished Jul 11 06:35:27 PM PDT 24
Peak memory 205832 kb
Host smart-a50249aa-7a81-47b6-9412-463b48265a37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107562395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.107562395
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.3245262439
Short name T248
Test name
Test status
Simulation time 3062522995 ps
CPU time 9.71 seconds
Started Jul 11 06:35:24 PM PDT 24
Finished Jul 11 06:35:35 PM PDT 24
Peak memory 224520 kb
Host smart-43d4e096-cbb6-448f-b443-90dd0c9e8ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245262439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.3245262439
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.1566065865
Short name T735
Test name
Test status
Simulation time 16563505 ps
CPU time 0.81 seconds
Started Jul 11 06:35:18 PM PDT 24
Finished Jul 11 06:35:20 PM PDT 24
Peak memory 206924 kb
Host smart-7fa4d1b1-cbb8-4264-aff5-5d97cc834d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566065865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.1566065865
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.3496656963
Short name T246
Test name
Test status
Simulation time 577832171559 ps
CPU time 609.93 seconds
Started Jul 11 06:35:31 PM PDT 24
Finished Jul 11 06:45:41 PM PDT 24
Peak memory 265612 kb
Host smart-c0793591-621f-4386-8ad3-d89c5e188944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496656963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.3496656963
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.2005994215
Short name T766
Test name
Test status
Simulation time 118225140961 ps
CPU time 302.94 seconds
Started Jul 11 06:35:23 PM PDT 24
Finished Jul 11 06:40:27 PM PDT 24
Peak memory 257472 kb
Host smart-6b02c9aa-74c3-4632-9833-0cdf499b355b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005994215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.2005994215
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.3321894106
Short name T288
Test name
Test status
Simulation time 39882469952 ps
CPU time 58.45 seconds
Started Jul 11 06:35:26 PM PDT 24
Finished Jul 11 06:36:26 PM PDT 24
Peak memory 238772 kb
Host smart-036fc217-8ec3-406c-88a7-552e2fe150c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321894106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.3321894106
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.3922649214
Short name T275
Test name
Test status
Simulation time 4454477180 ps
CPU time 9.54 seconds
Started Jul 11 06:35:26 PM PDT 24
Finished Jul 11 06:35:36 PM PDT 24
Peak memory 233420 kb
Host smart-78be8f69-8292-482a-a01b-b082de42382d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922649214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.3922649214
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.2167027997
Short name T973
Test name
Test status
Simulation time 6338297638 ps
CPU time 57.04 seconds
Started Jul 11 06:35:30 PM PDT 24
Finished Jul 11 06:36:28 PM PDT 24
Peak memory 251484 kb
Host smart-a2f8d5c0-3fe8-4662-9710-2438e925685f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167027997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds
.2167027997
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.318007634
Short name T749
Test name
Test status
Simulation time 1920938378 ps
CPU time 6.28 seconds
Started Jul 11 06:35:25 PM PDT 24
Finished Jul 11 06:35:32 PM PDT 24
Peak memory 232712 kb
Host smart-aa0d7145-76c6-4804-838b-4a6b4b79eaf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318007634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.318007634
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.89969118
Short name T53
Test name
Test status
Simulation time 15245113646 ps
CPU time 78.24 seconds
Started Jul 11 06:35:24 PM PDT 24
Finished Jul 11 06:36:43 PM PDT 24
Peak memory 232792 kb
Host smart-932d21c4-143e-4030-b0ee-9530c0557789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89969118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.89969118
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.1243906156
Short name T639
Test name
Test status
Simulation time 748780610 ps
CPU time 8.46 seconds
Started Jul 11 06:35:19 PM PDT 24
Finished Jul 11 06:35:29 PM PDT 24
Peak memory 238944 kb
Host smart-b9098356-34f2-46ce-a473-12af290cdd7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243906156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.1243906156
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.1172555042
Short name T243
Test name
Test status
Simulation time 100531172 ps
CPU time 3.39 seconds
Started Jul 11 06:35:20 PM PDT 24
Finished Jul 11 06:35:24 PM PDT 24
Peak memory 224476 kb
Host smart-2303f60a-f866-40cd-8dce-609c3a11d62a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172555042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.1172555042
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.2728089535
Short name T333
Test name
Test status
Simulation time 10316395454 ps
CPU time 14.99 seconds
Started Jul 11 06:35:25 PM PDT 24
Finished Jul 11 06:35:41 PM PDT 24
Peak memory 223188 kb
Host smart-ec568abf-f3bf-44ab-a62b-5533f9ed2c00
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2728089535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.2728089535
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.2623531944
Short name T284
Test name
Test status
Simulation time 17249531052 ps
CPU time 14.98 seconds
Started Jul 11 06:35:16 PM PDT 24
Finished Jul 11 06:35:33 PM PDT 24
Peak memory 216532 kb
Host smart-1e43a45e-fbf9-48e9-bf2f-36f955f07c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623531944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.2623531944
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.2240535222
Short name T769
Test name
Test status
Simulation time 27046098 ps
CPU time 0.7 seconds
Started Jul 11 06:35:15 PM PDT 24
Finished Jul 11 06:35:17 PM PDT 24
Peak memory 205724 kb
Host smart-4096405d-1f6e-40c1-af8d-300dc44ae389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240535222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.2240535222
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.1718788111
Short name T662
Test name
Test status
Simulation time 172284024 ps
CPU time 1.55 seconds
Started Jul 11 06:35:17 PM PDT 24
Finished Jul 11 06:35:19 PM PDT 24
Peak memory 216244 kb
Host smart-f63ff480-5ec0-4b43-b0bf-7b3d0865ffdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718788111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.1718788111
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.211619595
Short name T424
Test name
Test status
Simulation time 15269215 ps
CPU time 0.72 seconds
Started Jul 11 06:35:18 PM PDT 24
Finished Jul 11 06:35:20 PM PDT 24
Peak memory 205984 kb
Host smart-89fccc12-3569-4ee1-b200-1c20518b0b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211619595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.211619595
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.2528668752
Short name T646
Test name
Test status
Simulation time 7396454068 ps
CPU time 18.33 seconds
Started Jul 11 06:35:24 PM PDT 24
Finished Jul 11 06:35:43 PM PDT 24
Peak memory 224652 kb
Host smart-0f7b6d8f-c023-41eb-8177-95ddc5a2db12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528668752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.2528668752
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.258752320
Short name T815
Test name
Test status
Simulation time 36689129 ps
CPU time 0.72 seconds
Started Jul 11 06:35:33 PM PDT 24
Finished Jul 11 06:35:34 PM PDT 24
Peak memory 204976 kb
Host smart-e3d87516-5307-44e5-b8ff-44b0a5a3dc97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258752320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.258752320
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.3818920799
Short name T225
Test name
Test status
Simulation time 133252998 ps
CPU time 3.49 seconds
Started Jul 11 06:35:28 PM PDT 24
Finished Jul 11 06:35:33 PM PDT 24
Peak memory 232668 kb
Host smart-923e8bf9-49af-4b17-aa22-e1f3c1c9ece7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818920799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.3818920799
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.1922779136
Short name T659
Test name
Test status
Simulation time 17989661 ps
CPU time 0.8 seconds
Started Jul 11 06:35:24 PM PDT 24
Finished Jul 11 06:35:26 PM PDT 24
Peak memory 206616 kb
Host smart-3cb1fcf9-9af8-4c93-8d1c-f2730d6f327a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922779136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.1922779136
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.3702632612
Short name T721
Test name
Test status
Simulation time 23535558274 ps
CPU time 85.6 seconds
Started Jul 11 06:35:28 PM PDT 24
Finished Jul 11 06:36:54 PM PDT 24
Peak memory 249192 kb
Host smart-8914bdf6-3d7b-41a4-94af-f489bb2d24ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702632612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.3702632612
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.2541219585
Short name T743
Test name
Test status
Simulation time 483690440392 ps
CPU time 436.46 seconds
Started Jul 11 06:35:32 PM PDT 24
Finished Jul 11 06:42:49 PM PDT 24
Peak memory 250704 kb
Host smart-7ced2103-c643-4344-85d1-869987fc192e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541219585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.2541219585
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.3421078282
Short name T289
Test name
Test status
Simulation time 6799367075 ps
CPU time 30.87 seconds
Started Jul 11 06:35:34 PM PDT 24
Finished Jul 11 06:36:06 PM PDT 24
Peak memory 224804 kb
Host smart-523d1c02-419b-464f-a2ac-9e03657d498b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421078282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.3421078282
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.508106765
Short name T453
Test name
Test status
Simulation time 8870250087 ps
CPU time 46.87 seconds
Started Jul 11 06:35:26 PM PDT 24
Finished Jul 11 06:36:14 PM PDT 24
Peak memory 232820 kb
Host smart-9bd4a135-58b2-484b-9b94-ec678e863b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508106765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.508106765
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.1424368812
Short name T784
Test name
Test status
Simulation time 6395258581 ps
CPU time 24.34 seconds
Started Jul 11 06:35:28 PM PDT 24
Finished Jul 11 06:35:54 PM PDT 24
Peak memory 249152 kb
Host smart-b8f1677b-e921-42b8-991b-771ecb150c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424368812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds
.1424368812
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.3432175382
Short name T694
Test name
Test status
Simulation time 1324602150 ps
CPU time 5.88 seconds
Started Jul 11 06:35:29 PM PDT 24
Finished Jul 11 06:35:36 PM PDT 24
Peak memory 232660 kb
Host smart-66248777-6b41-4f53-84c6-30ec4fe510e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432175382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.3432175382
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.3666871546
Short name T25
Test name
Test status
Simulation time 35362751032 ps
CPU time 55.51 seconds
Started Jul 11 06:35:31 PM PDT 24
Finished Jul 11 06:36:27 PM PDT 24
Peak memory 224700 kb
Host smart-b11b9051-3714-4f0d-ae09-ae8a5e5ad408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666871546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.3666871546
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.1504975762
Short name T687
Test name
Test status
Simulation time 198087013 ps
CPU time 2.47 seconds
Started Jul 11 06:35:29 PM PDT 24
Finished Jul 11 06:35:32 PM PDT 24
Peak memory 223944 kb
Host smart-47bb1ea8-05b6-4f2f-b2f0-188c5a42312b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504975762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.1504975762
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.1936787068
Short name T681
Test name
Test status
Simulation time 560626758 ps
CPU time 3.07 seconds
Started Jul 11 06:35:26 PM PDT 24
Finished Jul 11 06:35:31 PM PDT 24
Peak memory 224476 kb
Host smart-2b5a24f0-0b0e-4cf1-b034-40b5b2f075bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936787068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.1936787068
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.1301894328
Short name T962
Test name
Test status
Simulation time 5786190566 ps
CPU time 14.74 seconds
Started Jul 11 06:35:31 PM PDT 24
Finished Jul 11 06:35:46 PM PDT 24
Peak memory 222360 kb
Host smart-bd6351ce-1076-4ef2-9270-f8431a226c0b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1301894328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.1301894328
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.2332793026
Short name T947
Test name
Test status
Simulation time 44194278 ps
CPU time 1.01 seconds
Started Jul 11 06:35:34 PM PDT 24
Finished Jul 11 06:35:36 PM PDT 24
Peak memory 206852 kb
Host smart-5b125d54-d5cf-4ddd-9438-e20801ff349e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332793026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.2332793026
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.3366655395
Short name T928
Test name
Test status
Simulation time 4338421588 ps
CPU time 9.21 seconds
Started Jul 11 06:35:31 PM PDT 24
Finished Jul 11 06:35:42 PM PDT 24
Peak memory 219764 kb
Host smart-7111d414-abdd-4cd2-a6f7-52a874728325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366655395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.3366655395
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.1668761442
Short name T348
Test name
Test status
Simulation time 21889428 ps
CPU time 0.71 seconds
Started Jul 11 06:35:27 PM PDT 24
Finished Jul 11 06:35:29 PM PDT 24
Peak memory 205724 kb
Host smart-79ee88f0-c0e3-49d8-926c-54765a12c88d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668761442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.1668761442
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.2234654289
Short name T314
Test name
Test status
Simulation time 186807544 ps
CPU time 1.16 seconds
Started Jul 11 06:35:28 PM PDT 24
Finished Jul 11 06:35:30 PM PDT 24
Peak memory 216128 kb
Host smart-f3c852e5-7c4f-435d-b0ba-b35c2fb62d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234654289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.2234654289
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.861467646
Short name T790
Test name
Test status
Simulation time 69008787 ps
CPU time 0.78 seconds
Started Jul 11 06:35:29 PM PDT 24
Finished Jul 11 06:35:31 PM PDT 24
Peak memory 206004 kb
Host smart-a535fad0-5b84-48c4-ad87-4936c3d9d111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861467646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.861467646
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.1796073210
Short name T892
Test name
Test status
Simulation time 586329501 ps
CPU time 7.77 seconds
Started Jul 11 06:35:28 PM PDT 24
Finished Jul 11 06:35:37 PM PDT 24
Peak memory 248220 kb
Host smart-b7404b75-3a72-4a1a-b078-7f1bc432e8f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796073210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.1796073210
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.315031927
Short name T615
Test name
Test status
Simulation time 14064593 ps
CPU time 0.75 seconds
Started Jul 11 06:35:44 PM PDT 24
Finished Jul 11 06:35:46 PM PDT 24
Peak memory 205888 kb
Host smart-c8e73842-308f-4d5d-82a8-3ad402c742c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315031927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.315031927
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.3970775052
Short name T1
Test name
Test status
Simulation time 1478744550 ps
CPU time 6.5 seconds
Started Jul 11 06:35:45 PM PDT 24
Finished Jul 11 06:35:52 PM PDT 24
Peak memory 224512 kb
Host smart-95a5869f-8b7e-441f-8d4f-45dbb795bf13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970775052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.3970775052
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.3877203441
Short name T937
Test name
Test status
Simulation time 23550553 ps
CPU time 0.81 seconds
Started Jul 11 06:35:33 PM PDT 24
Finished Jul 11 06:35:35 PM PDT 24
Peak memory 206640 kb
Host smart-ad8edb99-800b-4830-9177-4fb35d7bed11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877203441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.3877203441
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.2205855063
Short name T809
Test name
Test status
Simulation time 72403767664 ps
CPU time 116.51 seconds
Started Jul 11 06:35:44 PM PDT 24
Finished Jul 11 06:37:41 PM PDT 24
Peak memory 239944 kb
Host smart-1dc90159-32c0-48f5-8a21-f756c0df8b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205855063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.2205855063
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.2941729116
Short name T904
Test name
Test status
Simulation time 32376724011 ps
CPU time 81.36 seconds
Started Jul 11 06:35:44 PM PDT 24
Finished Jul 11 06:37:06 PM PDT 24
Peak memory 249256 kb
Host smart-1c186fba-b64a-4079-b278-8ff3a13c0ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941729116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.2941729116
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.4071498851
Short name T826
Test name
Test status
Simulation time 4133459859 ps
CPU time 23 seconds
Started Jul 11 06:35:44 PM PDT 24
Finished Jul 11 06:36:08 PM PDT 24
Peak memory 217804 kb
Host smart-9d9fb035-8055-4279-8e43-7ed77d799c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071498851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.4071498851
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.1551399741
Short name T527
Test name
Test status
Simulation time 853540219 ps
CPU time 13.78 seconds
Started Jul 11 06:35:43 PM PDT 24
Finished Jul 11 06:35:57 PM PDT 24
Peak memory 257156 kb
Host smart-d03e050b-bd60-4e17-ae19-bf6ce49da5e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551399741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.1551399741
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.2366889681
Short name T655
Test name
Test status
Simulation time 265612563 ps
CPU time 5.35 seconds
Started Jul 11 06:35:38 PM PDT 24
Finished Jul 11 06:35:44 PM PDT 24
Peak memory 224460 kb
Host smart-68934544-1e42-4198-bbb0-3124a2c32467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366889681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.2366889681
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.3609639282
Short name T546
Test name
Test status
Simulation time 171235773 ps
CPU time 2.57 seconds
Started Jul 11 06:35:44 PM PDT 24
Finished Jul 11 06:35:48 PM PDT 24
Peak memory 232344 kb
Host smart-c03d12c4-f965-404f-91aa-8fef36428f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609639282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.3609639282
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.3468725176
Short name T420
Test name
Test status
Simulation time 1217783280 ps
CPU time 7.88 seconds
Started Jul 11 06:35:38 PM PDT 24
Finished Jul 11 06:35:47 PM PDT 24
Peak memory 232700 kb
Host smart-62787a2a-698c-4b3f-b8cc-e3644a5dd96d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468725176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.3468725176
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.4066682612
Short name T38
Test name
Test status
Simulation time 5214117036 ps
CPU time 18.9 seconds
Started Jul 11 06:35:43 PM PDT 24
Finished Jul 11 06:36:03 PM PDT 24
Peak memory 248612 kb
Host smart-57c1145d-fb65-40c1-9696-bc434f975efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066682612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.4066682612
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.524828940
Short name T936
Test name
Test status
Simulation time 2600707043 ps
CPU time 9.53 seconds
Started Jul 11 06:35:44 PM PDT 24
Finished Jul 11 06:35:55 PM PDT 24
Peak memory 223272 kb
Host smart-07571e8e-c98e-488d-be76-dccd3f07ed8e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=524828940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_direc
t.524828940
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.2547897766
Short name T136
Test name
Test status
Simulation time 70554415 ps
CPU time 1.14 seconds
Started Jul 11 06:35:48 PM PDT 24
Finished Jul 11 06:35:51 PM PDT 24
Peak memory 207172 kb
Host smart-9cc4c6c8-8c8b-43d9-bb34-1db2efd659d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547897766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.2547897766
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.7108908
Short name T626
Test name
Test status
Simulation time 2084119588 ps
CPU time 20.62 seconds
Started Jul 11 06:35:34 PM PDT 24
Finished Jul 11 06:35:56 PM PDT 24
Peak memory 216456 kb
Host smart-6a3ca64f-b908-4dad-8338-4137415271f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7108908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.7108908
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.2954612246
Short name T874
Test name
Test status
Simulation time 1468914491 ps
CPU time 3.11 seconds
Started Jul 11 06:35:34 PM PDT 24
Finished Jul 11 06:35:38 PM PDT 24
Peak memory 216240 kb
Host smart-ac6f4af9-b8d3-4f19-b4be-53d222c385c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954612246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.2954612246
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.1278389274
Short name T611
Test name
Test status
Simulation time 23752104 ps
CPU time 0.78 seconds
Started Jul 11 06:35:39 PM PDT 24
Finished Jul 11 06:35:41 PM PDT 24
Peak memory 205980 kb
Host smart-1f000735-c3c0-4145-8327-797d52002868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278389274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.1278389274
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.2009550644
Short name T349
Test name
Test status
Simulation time 184896041 ps
CPU time 0.81 seconds
Started Jul 11 06:35:37 PM PDT 24
Finished Jul 11 06:35:38 PM PDT 24
Peak memory 206012 kb
Host smart-352b83d3-45c9-4e49-9154-0b1a0ca05a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009550644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.2009550644
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.1610554715
Short name T241
Test name
Test status
Simulation time 7200079192 ps
CPU time 7.84 seconds
Started Jul 11 06:35:40 PM PDT 24
Finished Jul 11 06:35:48 PM PDT 24
Peak memory 224552 kb
Host smart-c7ffcc31-318f-4aed-9815-60d38c7edee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610554715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.1610554715
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.987775897
Short name T891
Test name
Test status
Simulation time 14492504 ps
CPU time 0.77 seconds
Started Jul 11 06:35:48 PM PDT 24
Finished Jul 11 06:35:50 PM PDT 24
Peak memory 205540 kb
Host smart-10cb2a5e-af84-4bb1-8b42-8bf9f26df7ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987775897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.987775897
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.3032218248
Short name T445
Test name
Test status
Simulation time 66558988 ps
CPU time 3.15 seconds
Started Jul 11 06:35:48 PM PDT 24
Finished Jul 11 06:35:53 PM PDT 24
Peak memory 232684 kb
Host smart-edcfddc9-93e8-4964-a9c8-989ce0052478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032218248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.3032218248
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.3997514037
Short name T380
Test name
Test status
Simulation time 21097877 ps
CPU time 0.85 seconds
Started Jul 11 06:35:46 PM PDT 24
Finished Jul 11 06:35:47 PM PDT 24
Peak memory 206636 kb
Host smart-d1b6ea88-6060-49d4-8a35-1ba66a760282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997514037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.3997514037
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.2624630612
Short name T43
Test name
Test status
Simulation time 4383210391 ps
CPU time 25.19 seconds
Started Jul 11 06:35:47 PM PDT 24
Finished Jul 11 06:36:14 PM PDT 24
Peak memory 232832 kb
Host smart-6ebeb728-6222-461f-a59a-0d05f8abe533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624630612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.2624630612
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.3968807729
Short name T913
Test name
Test status
Simulation time 106545252361 ps
CPU time 384.73 seconds
Started Jul 11 06:35:47 PM PDT 24
Finished Jul 11 06:42:14 PM PDT 24
Peak memory 257464 kb
Host smart-6af064fe-d504-4852-a8e4-24becac3fa3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968807729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.3968807729
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.4098640080
Short name T616
Test name
Test status
Simulation time 125041395 ps
CPU time 3.19 seconds
Started Jul 11 06:35:48 PM PDT 24
Finished Jul 11 06:35:53 PM PDT 24
Peak memory 232712 kb
Host smart-066a394b-b8f4-4fa6-8441-4a461d3d9ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098640080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.4098640080
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.3633123213
Short name T207
Test name
Test status
Simulation time 12670969046 ps
CPU time 44.81 seconds
Started Jul 11 06:35:47 PM PDT 24
Finished Jul 11 06:36:33 PM PDT 24
Peak memory 248644 kb
Host smart-0f5e213c-f43c-44f2-b0f0-2d140cb0154a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633123213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds
.3633123213
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.1359265399
Short name T214
Test name
Test status
Simulation time 2874636723 ps
CPU time 22.01 seconds
Started Jul 11 06:35:46 PM PDT 24
Finished Jul 11 06:36:09 PM PDT 24
Peak memory 224596 kb
Host smart-6d02cb31-9007-46a7-84c1-fd30de8f2d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359265399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.1359265399
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.2319862520
Short name T479
Test name
Test status
Simulation time 8475233996 ps
CPU time 78.23 seconds
Started Jul 11 06:35:48 PM PDT 24
Finished Jul 11 06:37:08 PM PDT 24
Peak memory 239988 kb
Host smart-ab9763a1-9ef8-43ef-b90a-c5cb5fdd5f49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319862520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.2319862520
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.3005430285
Short name T235
Test name
Test status
Simulation time 448403021 ps
CPU time 2.52 seconds
Started Jul 11 06:35:42 PM PDT 24
Finished Jul 11 06:35:46 PM PDT 24
Peak memory 224472 kb
Host smart-db81e787-6e77-4ced-8354-c4634e202b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005430285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.3005430285
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.697381734
Short name T230
Test name
Test status
Simulation time 754083569 ps
CPU time 7.7 seconds
Started Jul 11 06:35:45 PM PDT 24
Finished Jul 11 06:35:54 PM PDT 24
Peak memory 232656 kb
Host smart-00cf85f5-c39c-4855-9508-b36951c2ebe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697381734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.697381734
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.322072783
Short name T416
Test name
Test status
Simulation time 2531791029 ps
CPU time 10.51 seconds
Started Jul 11 06:35:48 PM PDT 24
Finished Jul 11 06:36:01 PM PDT 24
Peak memory 223436 kb
Host smart-137d187f-c29b-4556-bf5d-fa9b93b5f7c5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=322072783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_direc
t.322072783
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.3441702615
Short name T137
Test name
Test status
Simulation time 20702536573 ps
CPU time 62.95 seconds
Started Jul 11 06:35:50 PM PDT 24
Finished Jul 11 06:36:54 PM PDT 24
Peak memory 249328 kb
Host smart-3b85c9ec-206f-4b2d-83b0-0fded2d612b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441702615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.3441702615
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.4002297061
Short name T316
Test name
Test status
Simulation time 282898383 ps
CPU time 0.75 seconds
Started Jul 11 06:35:43 PM PDT 24
Finished Jul 11 06:35:45 PM PDT 24
Peak memory 205748 kb
Host smart-7174d5c8-10cc-4062-862c-462d8a02a6aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002297061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.4002297061
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.1075403817
Short name T425
Test name
Test status
Simulation time 21422047681 ps
CPU time 16.89 seconds
Started Jul 11 06:35:43 PM PDT 24
Finished Jul 11 06:36:01 PM PDT 24
Peak memory 217708 kb
Host smart-e55e456d-5a64-4284-8877-6ff4c5d2dc8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075403817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.1075403817
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.2523620528
Short name T439
Test name
Test status
Simulation time 127873715 ps
CPU time 2 seconds
Started Jul 11 06:35:42 PM PDT 24
Finished Jul 11 06:35:45 PM PDT 24
Peak memory 216224 kb
Host smart-f72fdfe6-8b0f-445d-b894-7cc3d72703fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523620528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.2523620528
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.2920284150
Short name T752
Test name
Test status
Simulation time 180249532 ps
CPU time 0.85 seconds
Started Jul 11 06:35:49 PM PDT 24
Finished Jul 11 06:35:52 PM PDT 24
Peak memory 206004 kb
Host smart-bcd75ea0-e769-4132-b34f-668e0b7b1574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920284150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.2920284150
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.1304846216
Short name T146
Test name
Test status
Simulation time 6902956087 ps
CPU time 22.9 seconds
Started Jul 11 06:35:48 PM PDT 24
Finished Jul 11 06:36:13 PM PDT 24
Peak memory 232792 kb
Host smart-c58b1047-7ccb-4806-84fc-1e68be965082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304846216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.1304846216
Directory /workspace/9.spi_device_upload/latest
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