Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2622379	1			T1	5902		T2	1		T3	9039
all_values[1]	2622379	1			T1	5902		T2	1		T3	9039
all_values[2]	2622379	1			T1	5902		T2	1		T3	9039
all_values[3]	2622379	1			T1	5902		T2	1		T3	9039
all_values[4]	2622379	1			T1	5902		T2	1		T3	9039
all_values[5]	2622379	1			T1	5902		T2	1		T3	9039
all_values[6]	2622379	1			T1	5902		T2	1		T3	9039
all_values[7]	2622379	1			T1	5902		T2	1		T3	9039

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20150316

1

T1

47216

T2

8

T3

72312

auto[1]

828716

1

T11

67

T17

34

T18

69

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20951103

1

T1

47216

T2

8

T3

72113

auto[1]

27929

1

T3

199

T11

40

T17

572

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2547533	1			T1	5902		T2	1		T3	8877
all_values[0]	auto[0]	auto[1]	12973	1			T3	162		T17	251		T26	91
all_values[0]	auto[1]	auto[0]	61400	1			T11	2		T17	2		T18	8
all_values[0]	auto[1]	auto[1]	473	1			T11	2		T18	2		T19	2
all_values[1]	auto[0]	auto[0]	2524626	1			T1	5902		T2	1		T3	9002
all_values[1]	auto[0]	auto[1]	8733	1			T3	37		T11	4		T17	205
all_values[1]	auto[1]	auto[0]	88735	1			T11	6		T17	5		T18	11
all_values[1]	auto[1]	auto[1]	285	1			T11	2		T17	1		T18	2
all_values[2]	auto[0]	auto[0]	2483982	1			T1	5902		T2	1		T3	9039
all_values[2]	auto[0]	auto[1]	3271	1			T11	2		T17	97		T26	47
all_values[2]	auto[1]	auto[0]	134873	1			T11	4		T17	1		T18	3
all_values[2]	auto[1]	auto[1]	253	1			T11	1		T17	4		T18	3
all_values[3]	auto[0]	auto[0]	2513514	1			T1	5902		T2	1		T3	9039
all_values[3]	auto[0]	auto[1]	188	1			T11	1		T18	5		T20	4
all_values[3]	auto[1]	auto[0]	108490	1			T11	10		T17	1		T18	2
all_values[3]	auto[1]	auto[1]	187	1			T11	2		T17	3		T18	4
all_values[4]	auto[0]	auto[0]	2483976	1			T1	5902		T2	1		T3	9039
all_values[4]	auto[0]	auto[1]	192	1			T11	2		T17	1		T18	4
all_values[4]	auto[1]	auto[0]	137999	1			T11	8		T17	3		T18	2
all_values[4]	auto[1]	auto[1]	212	1			T11	2		T18	4		T20	3
all_values[5]	auto[0]	auto[0]	2483754	1			T1	5902		T2	1		T3	9039
all_values[5]	auto[0]	auto[1]	178	1			T11	3		T17	1		T18	4
all_values[5]	auto[1]	auto[0]	138256	1			T11	6		T17	6		T18	9
all_values[5]	auto[1]	auto[1]	191	1			T11	3		T17	2		T18	2
all_values[6]	auto[0]	auto[0]	2477102	1			T1	5902		T2	1		T3	9039
all_values[6]	auto[0]	auto[1]	186	1			T11	7		T17	1		T18	3
all_values[6]	auto[1]	auto[0]	144888	1			T11	3		T17	3		T18	2
all_values[6]	auto[1]	auto[1]	203	1			T11	1		T18	3		T20	5
all_values[7]	auto[0]	auto[0]	2609913	1			T1	5902		T2	1		T3	9039
all_values[7]	auto[0]	auto[1]	195	1			T11	1		T17	4		T18	2
all_values[7]	auto[1]	auto[0]	12062	1			T11	8		T17	1		T18	9
all_values[7]	auto[1]	auto[1]	209	1			T11	7		T17	2		T18	3