Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	36100	1			T2	6		T3	115		T5	149
auto[SpiFlashAddrCfg]	8044	1			T2	2		T3	21		T5	24
auto[SpiFlashAddr3b]	9797	1			T3	48		T5	20		T7	2
auto[SpiFlashAddr4b]	8090	1			T2	2		T3	42		T5	29

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34465

1

T2

10

T3

71

T5

107

auto[1]

27566

1

T3

155

T5

115

T13

384

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33969

1

T2

6

T3

143

T5

76

auto[1]

28062

1

T2

4

T3

83

T5

146

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	41187	1			T2	6		T3	135		T5	168
values[1]	1290	1			T3	3		T5	2		T12	2
values[2]	1531	1			T3	7		T5	4		T13	8
values[3]	1468	1			T3	9		T7	2		T13	7
values[4]	1640	1			T3	2		T5	2		T13	10
values[5]	1520	1			T3	6		T5	4		T13	3
values[6]	1676	1			T2	2		T3	10		T5	7
values[7]	1479	1			T3	9		T5	4		T12	2
values[8]	10240	1			T2	2		T3	45		T5	31

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32674

1

T2

10

T3

226

T5

222

auto[1]

29357

1

T10

2

T13

687

T16

447

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

58496

1

T2

10

T3

214

T5

210

write

3535

1

T3

12

T5

12

T12

4

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

20633

1

T2

4

T3

84

T5

64

valids[0x1]

41398

1

T2

6

T3

142

T5

158

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1639	1			T2	4		T3	6		T5	3
internal_process_ops[0x5a]	1674	1			T3	4		T5	1		T13	7
internal_process_ops[0x05]	21156	1			T2	2		T3	70		T5	105
internal_process_ops[0x35]	1723	1			T3	5		T5	6		T13	11
internal_process_ops[0x15]	1683	1			T3	2		T5	6		T13	6
internal_process_ops[0x03]	1116	1			T3	5		T5	7		T10	1
internal_process_ops[0x0b]	1067	1			T3	5		T5	4		T13	2
internal_process_ops[0x3b]	1084	1			T3	5		T5	1		T12	2
internal_process_ops[0x6b]	1140	1			T2	2		T3	8		T5	4
internal_process_ops[0xbb]	1104	1			T2	2		T3	6		T5	2
internal_process_ops[0xeb]	1134	1			T3	5		T5	7		T13	3

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

60322

1

T2

10

T3

219

T5

215

auto[1]

1709

1

T3

7

T5

7

T13

6

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

59470

1

T2

10

T3

215

T5

214

auto[1]

2561

1

T3

11

T5

8

T12

2

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10713

1

T2

6

T3

30

T5

67

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6678

1

T3

84

T5

80

T15

8

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2204

1

T2

2

T3

10

T5

12

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1931

1

T3

10

T5

9

T15

8

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2759

1

T3

16

T5

10

T7

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2351

1

T3

28

T5

8

T15

10

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2207

1

T2

2

T3

12

T5

12

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

2053

1

T3

24

T5

12

T15

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

126

1

T34

2

T40

1

T41

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

87

1

T3

1

T26

3

T20

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

124

1

T17

2

T26

5

T34

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

121

1

T5

2

T26

1

T20

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

93

1

T5

2

T12

2

T26

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

97

1

T26

2

T40

1

T155

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

131

1

T3

1

T5

1

T26

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

120

1

T17

1

T26

2

T34

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

132

1

T3

1

T12

2

T26

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

81

1

T3

1

T34

3

T20

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

89

1

T3

2

T5

2

T37

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

105

1

T42

2

T20

1

T37

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

129

1

T34

2

T37

1

T156

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

101

1

T5

4

T17

2

T34

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

113

1

T3

1

T17

1

T26

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

129

1

T3

5

T5

1

T34

3

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9857

1

T13

230

T16

204

T17

96

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7962

1

T13

325

T16

124

T17

57

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1586

1

T10

2

T13

18

T16

14

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1443

1

T13

18

T16

9

T17

13

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1957

1

T13

29

T16

26

T17

29

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1913

1

T13

19

T16

19

T17

17

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1425

1

T13

12

T16

14

T17

19

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1457

1

T13

16

T16

15

T17

17

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

126

1

T13

5

T16

2

T17

4

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

99

1

T16

4

T19

2

T20

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

95

1

T17

1

T23

6

T24

4

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

112

1

T16

1

T19

6

T20

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

96

1

T13

1

T19

1

T20

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

119

1

T13

2

T17

1

T25

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

120

1

T17

2

T25

1

T20

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

104

1

T16

2

T17

2

T19

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

117

1

T13

2

T17

1

T20

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

102

1

T16

3

T17

1

T23

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

111

1

T16

1

T25

1

T23

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

80

1

T13

1

T17

2

T148

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

123

1

T13

3

T16

1

T17

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

129

1

T13

1

T16

1

T17

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

101

1

T13

3

T16

1

T17

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

123

1

T13

2

T16

6

T17

9

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	4288	1			T3	25		T5	27		T12	2
auto[0]	values[0]	valids[0x1]	16286	1			T2	6		T3	110		T5	141
auto[0]	values[1]	valids[0x1]	681	1			T3	3		T5	2		T12	2
auto[0]	values[2]	valids[0x0]	542	1			T3	7		T5	1		T17	5
auto[0]	values[2]	valids[0x1]	302	1			T5	3		T17	3		T26	3
auto[0]	values[3]	valids[0x0]	538	1			T3	3		T7	2		T15	4
auto[0]	values[3]	valids[0x1]	302	1			T3	6		T17	4		T26	6
auto[0]	values[4]	valids[0x0]	588	1			T3	2		T5	1		T26	5
auto[0]	values[4]	valids[0x1]	347	1			T5	1		T17	4		T26	1
auto[0]	values[5]	valids[0x0]	610	1			T3	4		T5	3		T17	5
auto[0]	values[5]	valids[0x1]	303	1			T3	2		T5	1		T17	1
auto[0]	values[6]	valids[0x0]	674	1			T2	2		T3	9		T5	5
auto[0]	values[6]	valids[0x1]	326	1			T3	1		T5	2		T17	1
auto[0]	values[7]	valids[0x0]	542	1			T3	5		T5	4		T12	2
auto[0]	values[7]	valids[0x1]	304	1			T3	4		T17	1		T26	2
auto[0]	values[8]	valids[0x0]	3809	1			T2	2		T3	29		T5	23
auto[0]	values[8]	valids[0x1]	2232	1			T3	16		T5	8		T15	2
auto[1]	values[0]	valids[0x0]	4181	1			T13	41		T16	58		T17	37
auto[1]	values[0]	valids[0x1]	16432	1			T10	1		T13	548		T16	307
auto[1]	values[1]	valids[0x1]	609	1			T13	10		T16	10		T17	16
auto[1]	values[2]	valids[0x0]	386	1			T13	4		T16	3		T17	2
auto[1]	values[2]	valids[0x1]	301	1			T13	4		T16	4		T17	6
auto[1]	values[3]	valids[0x0]	380	1			T13	5		T16	5		T17	7
auto[1]	values[3]	valids[0x1]	248	1			T13	2		T17	3		T19	2
auto[1]	values[4]	valids[0x0]	441	1			T13	7		T16	1		T17	5
auto[1]	values[4]	valids[0x1]	264	1			T13	3		T16	1		T17	3
auto[1]	values[5]	valids[0x0]	369	1			T13	3		T16	4		T25	1
auto[1]	values[5]	valids[0x1]	238	1			T16	1		T17	3		T19	3
auto[1]	values[6]	valids[0x0]	400	1			T13	2		T16	2		T17	4
auto[1]	values[6]	valids[0x1]	276	1			T13	5		T16	5		T17	5
auto[1]	values[7]	valids[0x0]	382	1			T13	5		T16	1		T17	5
auto[1]	values[7]	valids[0x1]	251	1			T13	1		T16	2		T17	4
auto[1]	values[8]	valids[0x0]	2503	1			T10	1		T13	38		T16	29
auto[1]	values[8]	valids[0x1]	1696	1			T13	9		T16	14		T17	24