Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3662636

1

T1

1

T2

8215

T3

9193

auto[1]

35514

1

T3

66

T5

102

T12

51

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

894443

1

T1

1

T2

8215

T3

51

auto[1]

2803707

1

T3

9208

T5

8995

T12

51

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	665589	1			T1	1		T2	2014		T3	268
auto[524288:1048575]	457855	1			T2	14		T3	2527		T5	1316
auto[1048576:1572863]	407216	1			T2	2649		T3	533		T5	3
auto[1572864:2097151]	434008	1			T2	2319		T3	10		T7	830
auto[2097152:2621439]	438280	1			T3	2874		T5	9		T13	42
auto[2621440:3145727]	439267	1			T2	335		T3	270		T5	3530
auto[3145728:3670015]	424504	1			T2	880		T3	515		T5	543
auto[3670016:4194303]	431431	1			T2	4		T3	2262		T5	3383

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2840900

1

T1

1

T2

22

T3

9259

auto[1]

857250

1

T2

8193

T5

12

T7

4249

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3158391

1

T1

1

T2

8215

T3

4509

auto[1]

539759

1

T3

4750

T5

551

T13

1581

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	165970	1			T1	1		T2	2014		T3	5
auto[0]	auto[0]	auto[0:524287]	auto[1]	416116	1			T3	256		T5	256		T12	2
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	98516	1			T2	14		T3	7		T5	7
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	279650	1			T3	261		T5	1282		T13	643
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	85806	1			T2	2649		T3	7		T5	2
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	254864	1			T3	514		T5	1		T13	1772
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	117434	1			T2	2319		T3	2		T7	830
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	254005	1			T3	1		T13	5068		T16	1483
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	102330	1			T3	2		T5	2		T13	4
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	266437	1			T3	2614		T5	1		T13	4
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	106097	1			T2	335		T3	2		T5	11
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	257439	1			T3	257		T5	3501		T13	2
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	113401	1			T2	880		T3	3		T5	3
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	251350	1			T3	512		T5	2		T13	1605
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	86532	1			T2	4		T3	3		T5	5
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	273250	1			T3	1		T5	3340		T13	649
auto[0]	auto[1]	auto[0:524287]	auto[0]	2788	1			T3	2		T13	3		T16	2
auto[0]	auto[1]	auto[0:524287]	auto[1]	76789	1			T3	1		T13	84		T16	527
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	3913	1			T5	1		T13	2		T16	1
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	71239	1			T3	2228		T5	5		T13	3
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	1137	1			T17	8		T25	1		T34	3
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	58644	1			T17	2967		T20	2		T51	2233
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	1146	1			T3	3		T13	1		T16	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	57211	1			T13	513		T34	256		T21	128
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	892	1			T3	2		T17	5		T34	48
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	65145	1			T3	256		T17	7690		T34	218
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	641	1			T3	1		T5	2		T17	2
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	70600	1			T17	257		T25	549		T20	1118
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	2483	1			T5	1		T13	6		T17	5
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	53433	1			T5	512		T13	937		T17	256
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	790	1			T3	1		T5	3		T13	1
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	66588	1			T3	2252		T5	1		T13	2
auto[1]	auto[0]	auto[0:524287]	auto[0]	500	1			T12	2		T13	3		T16	2
auto[1]	auto[0]	auto[0:524287]	auto[1]	2870	1			T12	49		T13	80		T16	16
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	453	1			T3	5		T5	2		T13	2
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	2822	1			T3	26		T5	19		T13	32
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	584	1			T3	2		T13	1		T17	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	5347	1			T3	10		T13	5		T17	3
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	471	1			T3	1		T13	3		T16	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	3127	1			T3	3		T13	121		T16	12
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	432	1			T5	1		T13	2		T16	2
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2488	1			T5	5		T13	32		T16	33
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	441	1			T3	1		T5	1		T13	2
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2411	1			T3	9		T5	15		T13	40
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	379	1			T5	2		T13	5		T16	2
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	3110	1			T5	23		T13	76		T16	18
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	464	1			T3	1		T5	1		T13	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	3295	1			T3	4		T5	7		T13	53
auto[1]	auto[1]	auto[0:524287]	auto[0]	106	1			T3	1		T16	1		T19	2
auto[1]	auto[1]	auto[0:524287]	auto[1]	450	1			T3	3		T16	8		T19	6
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	103	1			T13	1		T16	1		T19	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	1159	1			T13	20		T16	5		T19	8
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	81	1			T17	2		T20	2		T30	2
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	753	1			T17	9		T20	2		T30	2
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	109	1			T13	1		T38	1		T24	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	505	1			T13	7		T24	1		T184	21
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	110	1			T34	16		T40	1		T24	2
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	446	1			T40	4		T24	1		T30	3
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	151	1			T17	1		T20	1		T38	2
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	1487	1			T38	1		T24	2		T51	29
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	87	1			T34	3		T41	3		T23	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	261	1			T23	12		T31	10		T191	12
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	96	1			T5	1		T16	1		T17	3
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	416	1			T5	25		T16	10		T17	18

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	2281191	1			T1	1		T2	22		T3	4447
auto[0]	auto[0]	auto[1]	848006	1			T2	8193		T5	4		T7	4249
auto[0]	auto[1]	auto[0]	524984	1			T3	4746		T5	524		T13	1551
auto[0]	auto[1]	auto[1]	8455	1			T5	1		T13	1		T16	2
auto[1]	auto[0]	auto[0]	28557	1			T3	62		T5	70		T12	51
auto[1]	auto[0]	auto[1]	637	1			T5	6		T13	2		T16	2
auto[1]	auto[1]	auto[0]	6168	1			T3	4		T5	25		T13	28
auto[1]	auto[1]	auto[1]	152	1			T5	1		T13	1		T16	1