Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2622379	1			T1	5902		T2	1		T3	9039
all_pins[1]	2622379	1			T1	5902		T2	1		T3	9039
all_pins[2]	2622379	1			T1	5902		T2	1		T3	9039
all_pins[3]	2622379	1			T1	5902		T2	1		T3	9039
all_pins[4]	2622379	1			T1	5902		T2	1		T3	9039
all_pins[5]	2622379	1			T1	5902		T2	1		T3	9039
all_pins[6]	2622379	1			T1	5902		T2	1		T3	9039
all_pins[7]	2622379	1			T1	5902		T2	1		T3	9039

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	20830699	1			T1	47216		T2	8		T3	72312
values[0x1]	148333	1			T11	20		T17	12		T18	23
transitions[0x0=>0x1]	147012	1			T11	14		T17	8		T18	18
transitions[0x1=>0x0]	147024	1			T11	14		T17	8		T18	18

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2621871	1			T1	5902		T2	1		T3	9039
all_pins[0]	values[0x1]	508	1			T11	2		T18	2		T19	2
all_pins[0]	transitions[0x0=>0x1]	451	1			T11	1		T18	2		T19	2
all_pins[0]	transitions[0x1=>0x0]	242	1			T11	1		T17	1		T18	2
all_pins[1]	values[0x0]	2622080	1			T1	5902		T2	1		T3	9039
all_pins[1]	values[0x1]	299	1			T11	2		T17	1		T18	2
all_pins[1]	transitions[0x0=>0x1]	208	1			T11	1		T18	2		T20	2
all_pins[1]	transitions[0x1=>0x0]	169	1			T17	3		T18	3		T20	20
all_pins[2]	values[0x0]	2622119	1			T1	5902		T2	1		T3	9039
all_pins[2]	values[0x1]	260	1			T11	1		T17	4		T18	3
all_pins[2]	transitions[0x0=>0x1]	211	1			T11	1		T17	1		T18	1
all_pins[2]	transitions[0x1=>0x0]	138	1			T11	2		T18	2		T19	3
all_pins[3]	values[0x0]	2622192	1			T1	5902		T2	1		T3	9039
all_pins[3]	values[0x1]	187	1			T11	2		T17	3		T18	4
all_pins[3]	transitions[0x0=>0x1]	128	1			T11	2		T17	3		T18	4
all_pins[3]	transitions[0x1=>0x0]	153	1			T11	2		T18	4		T20	3
all_pins[4]	values[0x0]	2622167	1			T1	5902		T2	1		T3	9039
all_pins[4]	values[0x1]	212	1			T11	2		T18	4		T20	3
all_pins[4]	transitions[0x0=>0x1]	167	1			T11	1		T18	3		T20	3
all_pins[4]	transitions[0x1=>0x0]	2034	1			T11	2		T17	2		T18	1
all_pins[5]	values[0x0]	2620300	1			T1	5902		T2	1		T3	9039
all_pins[5]	values[0x1]	2079	1			T11	3		T17	2		T18	2
all_pins[5]	transitions[0x0=>0x1]	1158	1			T11	3		T17	2		T18	2
all_pins[5]	transitions[0x1=>0x0]	143658	1			T11	1		T18	3		T20	44776
all_pins[6]	values[0x0]	2477800	1			T1	5902		T2	1		T3	9039
all_pins[6]	values[0x1]	144579	1			T11	1		T18	3		T20	45096
all_pins[6]	transitions[0x0=>0x1]	144533	1			T18	2		T20	45096		T21	2
all_pins[6]	transitions[0x1=>0x0]	163	1			T11	6		T17	2		T18	2
all_pins[7]	values[0x0]	2622170	1			T1	5902		T2	1		T3	9039
all_pins[7]	values[0x1]	209	1			T11	7		T17	2		T18	3
all_pins[7]	transitions[0x0=>0x1]	156	1			T11	5		T17	2		T18	2
all_pins[7]	transitions[0x1=>0x0]	467	1			T18	1		T19	2		T20	163