Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18729

1

T2

10

T3

71

T5

107

auto[1]

13945

1

T3

155

T5

115

T15

28

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4027	1			T34	20		T42	4		T20	50
values[1]	4699	1			T3	61		T5	26		T17	87
values[2]	3840	1			T20	25		T37	20		T38	24
values[3]	4098	1			T3	46		T12	69		T26	65
values[4]	3631	1			T5	55		T17	20		T26	20
values[5]	4231	1			T3	79		T5	76		T7	4
values[6]	4584	1			T5	45		T17	85		T26	194
values[7]	3564	1			T2	10		T3	40		T5	20

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4283	1			T3	61		T15	28		T17	50
values[1]	3817	1			T3	46		T5	85		T17	40
values[2]	4033	1			T3	20		T26	129		T32	14
values[3]	3739	1			T5	72		T34	20		T42	4
values[4]	4440	1			T2	10		T3	44		T5	45
values[5]	3574	1			T3	35		T12	69		T26	224
values[6]	4609	1			T3	20		T5	20		T14	4
values[7]	4179	1			T7	4		T17	65		T26	45

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	286	1			T40	11		T183	10		T184	13
auto[0]	values[0]	values[1]	408	1			T34	6		T155	13		T147	10
auto[0]	values[0]	values[2]	318	1			T24	14		T51	42		T167	7
auto[0]	values[0]	values[3]	467	1			T169	13		T193	32		T31	12
auto[0]	values[0]	values[4]	297	1			T156	26		T169	14		T193	13
auto[0]	values[0]	values[5]	128	1			T37	39		T189	6		T208	13
auto[0]	values[0]	values[6]	376	1			T183	14		T128	10		T31	74
auto[0]	values[0]	values[7]	262	1			T20	34		T43	9		T155	14
auto[0]	values[1]	values[0]	278	1			T3	21		T30	9		T167	13
auto[0]	values[1]	values[1]	267	1			T17	13		T209	24		T31	13
auto[0]	values[1]	values[2]	262	1			T26	101		T188	12		T210	7
auto[0]	values[1]	values[3]	115	1			T5	21		T34	13		T191	25
auto[0]	values[1]	values[4]	407	1			T17	12		T183	28		T188	15
auto[0]	values[1]	values[5]	198	1			T188	16		T169	14		T193	12
auto[0]	values[1]	values[6]	526	1			T17	10		T41	13		T169	13
auto[0]	values[1]	values[7]	497	1			T26	17		T184	56		T169	13
auto[0]	values[2]	values[0]	245	1			T128	11		T191	32		T211	18
auto[0]	values[2]	values[1]	220	1			T37	11		T198	8		T84	16
auto[0]	values[2]	values[2]	456	1			T40	18		T188	5		T184	34
auto[0]	values[2]	values[3]	231	1			T24	13		T188	14		T147	14
auto[0]	values[2]	values[4]	245	1			T24	12		T212	8		T187	12
auto[0]	values[2]	values[5]	247	1			T38	17		T190	6		T213	15
auto[0]	values[2]	values[6]	240	1			T40	13		T51	17		T184	15
auto[0]	values[2]	values[7]	317	1			T20	19		T182	20		T188	50
auto[0]	values[3]	values[0]	324	1			T38	14		T54	6		T206	14
auto[0]	values[3]	values[1]	220	1			T3	5		T26	9		T24	14
auto[0]	values[3]	values[2]	294	1			T26	12		T34	9		T20	35
auto[0]	values[3]	values[3]	321	1			T37	15		T38	9		T76	14
auto[0]	values[3]	values[4]	314	1			T34	14		T40	32		T193	14
auto[0]	values[3]	values[5]	346	1			T12	69		T183	28		T168	10
auto[0]	values[3]	values[6]	403	1			T26	11		T34	13		T40	8
auto[0]	values[3]	values[7]	300	1			T109	20		T43	9		T146	11
auto[0]	values[4]	values[0]	228	1			T94	18		T43	13		T191	15
auto[0]	values[4]	values[1]	324	1			T5	16		T17	12		T34	13
auto[0]	values[4]	values[2]	120	1			T37	7		T31	10		T168	14
auto[0]	values[4]	values[3]	248	1			T169	10		T210	35		T149	9
auto[0]	values[4]	values[4]	358	1			T214	6		T155	8		T193	12
auto[0]	values[4]	values[5]	220	1			T51	9		T184	9		T167	12
auto[0]	values[4]	values[6]	212	1			T198	14		T215	8		T194	6
auto[0]	values[4]	values[7]	210	1			T26	8		T155	16		T51	6
auto[0]	values[5]	values[0]	243	1			T26	14		T34	13		T24	17
auto[0]	values[5]	values[1]	193	1			T5	12		T41	12		T43	9
auto[0]	values[5]	values[2]	345	1			T3	7		T34	11		T188	23
auto[0]	values[5]	values[3]	313	1			T5	37		T40	49		T31	8
auto[0]	values[5]	values[4]	325	1			T3	10		T37	18		T43	7
auto[0]	values[5]	values[5]	315	1			T3	15		T26	10		T34	9
auto[0]	values[5]	values[6]	242	1			T14	4		T17	7		T26	16
auto[0]	values[5]	values[7]	348	1			T7	4		T155	9		T51	86
auto[0]	values[6]	values[0]	389	1			T17	11		T43	16		T24	18
auto[0]	values[6]	values[1]	331	1			T216	6		T183	26		T155	11
auto[0]	values[6]	values[2]	360	1			T32	14		T202	10		T40	32
auto[0]	values[6]	values[3]	422	1			T40	8		T24	4		T51	12
auto[0]	values[6]	values[4]	345	1			T5	11		T184	18		T167	13
auto[0]	values[6]	values[5]	267	1			T26	72		T34	16		T40	9
auto[0]	values[6]	values[6]	283	1			T20	14		T40	8		T128	15
auto[0]	values[6]	values[7]	260	1			T17	7		T24	17		T51	11
auto[0]	values[7]	values[0]	172	1			T17	18		T217	4		T184	7
auto[0]	values[7]	values[1]	247	1			T155	15		T203	22		T168	14
auto[0]	values[7]	values[2]	245	1			T218	10		T197	10		T219	16
auto[0]	values[7]	values[3]	258	1			T45	30		T149	50		T220	18
auto[0]	values[7]	values[4]	256	1			T2	10		T3	4		T20	13
auto[0]	values[7]	values[5]	343	1			T183	16		T155	14		T221	6
auto[0]	values[7]	values[6]	279	1			T3	9		T5	10		T93	18
auto[0]	values[7]	values[7]	213	1			T73	14		T128	12		T168	24
auto[1]	values[0]	values[0]	225	1			T40	9		T183	39		T184	7
auto[1]	values[0]	values[1]	189	1			T34	14		T155	27		T147	10
auto[1]	values[0]	values[2]	202	1			T24	10		T51	9		T167	13
auto[1]	values[0]	values[3]	171	1			T42	4		T169	7		T193	6
auto[1]	values[0]	values[4]	144	1			T169	6		T193	7		T187	7
auto[1]	values[0]	values[5]	121	1			T37	35		T208	7		T222	5
auto[1]	values[0]	values[6]	158	1			T183	6		T128	10		T31	20
auto[1]	values[0]	values[7]	275	1			T20	16		T43	11		T155	6
auto[1]	values[1]	values[0]	417	1			T3	40		T30	89		T167	7
auto[1]	values[1]	values[1]	140	1			T17	7		T31	7		T146	12
auto[1]	values[1]	values[2]	192	1			T26	8		T188	12		T210	13
auto[1]	values[1]	values[3]	92	1			T5	5		T34	7		T191	8
auto[1]	values[1]	values[4]	362	1			T17	8		T183	12		T188	11
auto[1]	values[1]	values[5]	162	1			T188	9		T169	6		T193	21
auto[1]	values[1]	values[6]	537	1			T17	37		T41	7		T169	7
auto[1]	values[1]	values[7]	247	1			T26	8		T184	14		T169	7
auto[1]	values[2]	values[0]	324	1			T128	12		T191	90		T223	17
auto[1]	values[2]	values[1]	186	1			T37	9		T198	12		T84	4
auto[1]	values[2]	values[2]	269	1			T40	13		T188	17		T184	8
auto[1]	values[2]	values[3]	233	1			T24	7		T188	6		T147	8
auto[1]	values[2]	values[4]	167	1			T24	10		T187	8		T45	5
auto[1]	values[2]	values[5]	152	1			T38	7		T205	24		T190	14
auto[1]	values[2]	values[6]	189	1			T40	8		T51	5		T184	5
auto[1]	values[2]	values[7]	119	1			T20	6		T188	5		T178	19
auto[1]	values[3]	values[0]	270	1			T38	6		T206	6		T224	6
auto[1]	values[3]	values[1]	155	1			T3	41		T26	11		T24	10
auto[1]	values[3]	values[2]	159	1			T26	8		T34	11		T20	16
auto[1]	values[3]	values[3]	199	1			T37	5		T38	20		T184	11
auto[1]	values[3]	values[4]	150	1			T34	6		T40	18		T193	6
auto[1]	values[3]	values[5]	116	1			T183	17		T168	10		T198	11
auto[1]	values[3]	values[6]	255	1			T26	14		T34	7		T40	12
auto[1]	values[3]	values[7]	272	1			T43	11		T146	9		T147	14
auto[1]	values[4]	values[0]	174	1			T43	7		T195	10		T191	5
auto[1]	values[4]	values[1]	350	1			T5	39		T17	8		T34	7
auto[1]	values[4]	values[2]	108	1			T37	17		T31	10		T168	6
auto[1]	values[4]	values[3]	106	1			T169	10		T210	5		T149	11
auto[1]	values[4]	values[4]	308	1			T155	12		T193	8		T31	122
auto[1]	values[4]	values[5]	260	1			T51	11		T184	37		T167	8
auto[1]	values[4]	values[6]	224	1			T225	20		T198	6		T215	89
auto[1]	values[4]	values[7]	181	1			T26	12		T155	4		T51	40
auto[1]	values[5]	values[0]	235	1			T15	28		T26	21		T34	7
auto[1]	values[5]	values[1]	152	1			T5	18		T41	8		T43	11
auto[1]	values[5]	values[2]	292	1			T3	13		T34	9		T126	6
auto[1]	values[5]	values[3]	167	1			T5	9		T40	12		T31	12
auto[1]	values[5]	values[4]	360	1			T3	14		T37	8		T43	13
auto[1]	values[5]	values[5]	195	1			T3	20		T26	20		T34	11
auto[1]	values[5]	values[6]	271	1			T17	13		T26	4		T155	5
auto[1]	values[5]	values[7]	235	1			T155	11		T51	18		T30	4
auto[1]	values[6]	values[0]	250	1			T17	9		T43	4		T24	6
auto[1]	values[6]	values[1]	207	1			T183	6		T155	9		T24	12
auto[1]	values[6]	values[2]	276	1			T40	6		T193	17		T146	3
auto[1]	values[6]	values[3]	195	1			T40	17		T24	18		T51	8
auto[1]	values[6]	values[4]	160	1			T5	34		T184	10		T167	7
auto[1]	values[6]	values[5]	252	1			T26	122		T34	4		T40	17
auto[1]	values[6]	values[6]	248	1			T20	7		T40	12		T128	5
auto[1]	values[6]	values[7]	339	1			T17	58		T24	6		T51	9
auto[1]	values[7]	values[0]	223	1			T17	12		T184	52		T207	11
auto[1]	values[7]	values[1]	228	1			T155	5		T168	6		T206	7
auto[1]	values[7]	values[2]	135	1			T197	13		T219	7		T224	8
auto[1]	values[7]	values[3]	201	1			T45	16		T149	8		T215	26
auto[1]	values[7]	values[4]	242	1			T3	16		T20	9		T183	8
auto[1]	values[7]	values[5]	252	1			T183	4		T155	6		T191	4
auto[1]	values[7]	values[6]	166	1			T3	11		T5	10		T45	14
auto[1]	values[7]	values[7]	104	1			T128	12		T168	16		T206	13