Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	429	1			T3	3		T5	4		T7	2
auto[ReadAddrCrossIntoMailbox]	328	1			T3	3		T5	2		T17	2
auto[ReadAddrCrossOutOfMailbox]	324	1			T3	1		T5	2		T17	1
auto[ReadAddrCrossAllMailbox]	214	1			T3	1		T5	3		T26	1
auto[ReadAddrOutsideMailbox]	3796	1			T2	4		T3	26		T5	14

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2506

1

T2

2

T3

17

T5

9

auto[1]

2585

1

T2

2

T3

17

T5

16

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	851	1			T3	5		T5	7		T12	2
read_ops[0x0b]	832	1			T3	5		T5	4		T17	5
read_ops[0x3b]	822	1			T3	5		T5	1		T12	2
read_ops[0x6b]	885	1			T2	2		T3	8		T5	4
read_ops[0xbb]	836	1			T2	2		T3	6		T5	2
read_ops[0xeb]	865	1			T3	5		T5	7		T14	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	30	1			T3	1		T51	1		T30	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	37	1			T17	1		T26	2		T20	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	25	1			T184	1		T146	2		T178	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	25	1			T26	1		T34	1		T41	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	25	1			T183	1		T30	1		T147	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	27	1			T5	1		T34	1		T183	2
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	21	1			T184	1		T193	1		T191	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	23	1			T5	3		T24	1		T188	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	335	1			T3	4		T5	2		T12	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	303	1			T5	1		T12	1		T15	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	36	1			T40	1		T188	1		T169	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	38	1			T3	1		T5	1		T34	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	21	1			T155	2		T147	2		T198	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	17	1			T5	1		T34	3		T193	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T40	2		T193	1		T128	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	22	1			T38	1		T183	1		T30	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	10	1			T183	1		T226	1		T153	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T3	1		T187	3		T197	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	343	1			T3	3		T5	2		T17	4
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	309	1			T17	1		T26	4		T34	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	47	1			T3	1		T183	1		T155	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	31	1			T40	1		T188	1		T169	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	37	1			T40	1		T155	1		T51	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	19	1			T17	1		T26	1		T40	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	26	1			T51	1		T193	1		T31	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	27	1			T17	1		T183	2		T24	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T26	1		T193	1		T128	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T24	2		T188	1		T226	3
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	299	1			T3	2		T12	1		T15	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	301	1			T3	2		T5	1		T12	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	38	1			T5	2		T7	1		T17	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	47	1			T7	1		T37	1		T40	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T17	1		T41	1		T183	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	30	1			T3	1		T34	1		T51	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	26	1			T40	1		T183	1		T51	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	40	1			T20	1		T41	1		T51	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T200	1		T191	1		T84	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T200	1		T146	1		T206	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	297	1			T2	1		T3	1		T5	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	345	1			T2	1		T3	6		T5	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	27	1			T155	1		T51	1		T184	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	37	1			T188	2		T30	1		T193	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	29	1			T183	2		T54	1		T184	2
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	45	1			T3	1		T26	1		T34	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T40	1		T54	2		T178	3
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	37	1			T5	1		T26	1		T34	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T43	1		T183	1		T184	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	22	1			T20	1		T40	1		T51	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	293	1			T2	1		T3	1		T15	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	307	1			T2	1		T3	4		T5	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	34	1			T14	1		T34	2		T20	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	27	1			T5	1		T14	1		T37	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	23	1			T3	1		T30	1		T147	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	31	1			T5	1		T26	1		T41	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	26	1			T188	1		T31	1		T147	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	24	1			T3	1		T41	1		T128	2
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	21	1			T184	1		T169	2		T31	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T191	1		T45	1		T149	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	317	1			T3	3		T5	2		T17	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	347	1			T5	3		T17	4		T26	5