Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4228	1			T3	61		T7	4		T26	219
values[1]	3899	1			T17	65		T34	20		T20	44
values[2]	3951	1			T3	55		T5	26		T17	20
values[3]	4239	1			T3	24		T15	28		T17	20
values[4]	3937	1			T2	10		T5	46		T17	20
values[5]	4310	1			T3	20		T5	45		T17	77
values[6]	3628	1			T3	66		T5	105		T26	30
values[7]	4482	1			T12	69		T14	4		T17	40

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4530	1			T14	4		T17	47		T34	20
values[1]	3736	1			T3	81		T5	45		T17	65
values[2]	4032	1			T2	10		T3	20		T5	20
values[3]	3879	1			T3	20		T5	26		T15	28
values[4]	4152	1			T3	48		T5	131		T12	69
values[5]	4613	1			T17	70		T26	25		T20	43
values[6]	3373	1			T3	37		T26	55		T34	40
values[7]	4359	1			T3	20		T7	4		T17	20

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31833

1

T2

10

T3

219

T5

215

auto[1]

841

1

T3

7

T5

7

T17

3

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	625	1			T34	17		T24	24		T188	52
auto[0]	values[0]	values[1]	414	1			T26	29		T193	19		T168	17
auto[0]	values[0]	values[2]	679	1			T26	123		T38	20		T183	20
auto[0]	values[0]	values[3]	625	1			T34	20		T169	20		T167	39
auto[0]	values[0]	values[4]	348	1			T3	23		T26	19		T20	24
auto[0]	values[0]	values[5]	626	1			T26	25		T41	19		T183	25
auto[0]	values[0]	values[6]	310	1			T3	36		T26	19		T34	17
auto[0]	values[0]	values[7]	498	1			T7	4		T34	20		T156	26
auto[0]	values[1]	values[0]	721	1			T40	41		T24	22		T169	20
auto[0]	values[1]	values[1]	409	1			T17	65		T40	18		T155	20
auto[0]	values[1]	values[2]	368	1			T34	20		T37	20		T227	2
auto[0]	values[1]	values[3]	520	1			T20	20		T188	26		T228	2
auto[0]	values[1]	values[4]	427	1			T93	18		T155	36		T24	20
auto[0]	values[1]	values[5]	368	1			T20	20		T54	6		T167	19
auto[0]	values[1]	values[6]	480	1			T183	30		T31	18		T167	19
auto[0]	values[1]	values[7]	499	1			T43	19		T51	82		T184	39
auto[0]	values[2]	values[0]	450	1			T51	20		T178	22		T45	21
auto[0]	values[2]	values[1]	499	1			T3	35		T37	25		T183	66
auto[0]	values[2]	values[2]	447	1			T183	20		T128	20		T31	20
auto[0]	values[2]	values[3]	401	1			T5	24		T24	24		T188	24
auto[0]	values[2]	values[4]	619	1			T40	20		T167	19		T198	18
auto[0]	values[2]	values[5]	559	1			T17	20		T20	21		T184	43
auto[0]	values[2]	values[6]	430	1			T34	20		T155	20		T51	51
auto[0]	values[2]	values[7]	434	1			T3	19		T184	20		T147	19
auto[0]	values[3]	values[0]	446	1			T59	10		T184	25		T191	48
auto[0]	values[3]	values[1]	593	1			T126	6		T128	43		T31	22
auto[0]	values[3]	values[2]	478	1			T182	20		T155	20		T51	89
auto[0]	values[3]	values[3]	431	1			T15	28		T34	19		T184	20
auto[0]	values[3]	values[4]	473	1			T3	23		T40	19		T24	22
auto[0]	values[3]	values[5]	636	1			T229	8		T146	38		T230	4
auto[0]	values[3]	values[6]	570	1			T217	4		T184	48		T169	19
auto[0]	values[3]	values[7]	481	1			T17	20		T26	58		T42	2
auto[0]	values[4]	values[0]	439	1			T183	32		T191	31		T84	20
auto[0]	values[4]	values[1]	500	1			T155	20		T24	40		T169	20
auto[0]	values[4]	values[2]	437	1			T2	10		T17	19		T32	14
auto[0]	values[4]	values[3]	334	1			T183	20		T57	2		T169	18
auto[0]	values[4]	values[4]	565	1			T5	46		T73	14		T51	35
auto[0]	values[4]	values[5]	455	1			T38	25		T188	30		T187	36
auto[0]	values[4]	values[6]	487	1			T26	35		T24	22		T206	20
auto[0]	values[4]	values[7]	633	1			T26	25		T37	28		T40	21
auto[0]	values[5]	values[0]	454	1			T17	47		T212	8		T193	20
auto[0]	values[5]	values[1]	314	1			T5	43		T193	20		T128	20
auto[0]	values[5]	values[2]	675	1			T3	20		T26	108		T20	28
auto[0]	values[5]	values[3]	663	1			T51	45		T188	18		T167	20
auto[0]	values[5]	values[4]	561	1			T40	37		T155	20		T231	18
auto[0]	values[5]	values[5]	533	1			T17	30		T202	10		T38	22
auto[0]	values[5]	values[6]	276	1			T40	20		T155	18		T128	24
auto[0]	values[5]	values[7]	734	1			T34	20		T40	25		T76	14
auto[0]	values[6]	values[0]	677	1			T191	105		T167	20		T45	20
auto[0]	values[6]	values[1]	458	1			T3	43		T40	30		T41	18
auto[0]	values[6]	values[2]	380	1			T5	20		T26	29		T20	25
auto[0]	values[6]	values[3]	491	1			T3	20		T34	20		T40	35
auto[0]	values[6]	values[4]	331	1			T5	82		T109	20		T184	20
auto[0]	values[6]	values[5]	445	1			T37	44		T43	19		T24	24
auto[0]	values[6]	values[6]	469	1			T20	24		T43	20		T31	20
auto[0]	values[6]	values[7]	293	1			T187	19		T232	2		T233	6
auto[0]	values[7]	values[0]	602	1			T14	4		T188	20		T184	26
auto[0]	values[7]	values[1]	450	1			T216	6		T183	20		T147	23
auto[0]	values[7]	values[2]	468	1			T94	18		T191	19		T178	40
auto[0]	values[7]	values[3]	336	1			T17	20		T26	20		T40	24
auto[0]	values[7]	values[4]	718	1			T12	69		T37	26		T40	30
auto[0]	values[7]	values[5]	885	1			T17	18		T184	55		T191	18
auto[0]	values[7]	values[6]	253	1			T187	20		T234	14		T235	28
auto[0]	values[7]	values[7]	653	1			T155	19		T51	153		T189	6
auto[1]	values[0]	values[0]	13	1			T34	3		T188	3		T181	2
auto[1]	values[0]	values[1]	16	1			T26	1		T193	1		T168	3
auto[1]	values[0]	values[2]	14	1			T26	1		T147	5		T207	1
auto[1]	values[0]	values[3]	14	1			T167	1		T236	2		T237	1
auto[1]	values[0]	values[4]	11	1			T3	1		T26	1		T20	1
auto[1]	values[0]	values[5]	9	1			T41	1		T193	1		T238	1
auto[1]	values[0]	values[6]	9	1			T3	1		T26	1		T34	3
auto[1]	values[0]	values[7]	17	1			T24	1		T188	1		T191	1
auto[1]	values[1]	values[0]	20	1			T210	2		T84	1		T149	3
auto[1]	values[1]	values[1]	10	1			T40	2		T224	2		T174	2
auto[1]	values[1]	values[2]	4	1			T36	1		T239	1		T240	2
auto[1]	values[1]	values[3]	14	1			T20	2		T168	2		T207	3
auto[1]	values[1]	values[4]	14	1			T155	4		T31	4		T174	3
auto[1]	values[1]	values[5]	12	1			T20	2		T167	1		T178	1
auto[1]	values[1]	values[6]	13	1			T31	2		T167	1		T241	1
auto[1]	values[1]	values[7]	20	1			T43	1		T51	2		T184	3
auto[1]	values[2]	values[0]	8	1			T45	2		T242	2		T243	2
auto[1]	values[2]	values[1]	15	1			T37	1		T183	3		T51	1
auto[1]	values[2]	values[2]	10	1			T168	1		T215	1		T174	3
auto[1]	values[2]	values[3]	10	1			T5	2		T188	1		T187	1
auto[1]	values[2]	values[4]	23	1			T167	1		T198	2		T84	2
auto[1]	values[2]	values[5]	17	1			T184	3		T169	2		T193	1
auto[1]	values[2]	values[6]	11	1			T187	3		T244	1		T235	1
auto[1]	values[2]	values[7]	18	1			T3	1		T147	1		T194	1
auto[1]	values[3]	values[0]	13	1			T184	1		T191	1		T198	1
auto[1]	values[3]	values[1]	12	1			T31	1		T167	1		T84	1
auto[1]	values[3]	values[2]	21	1			T51	2		T128	1		T167	4
auto[1]	values[3]	values[3]	6	1			T34	1		T169	1		T210	2
auto[1]	values[3]	values[4]	22	1			T3	1		T40	1		T24	1
auto[1]	values[3]	values[5]	17	1			T146	1		T208	1		T235	1
auto[1]	values[3]	values[6]	25	1			T184	2		T169	1		T178	1
auto[1]	values[3]	values[7]	15	1			T26	2		T42	2		T51	3
auto[1]	values[4]	values[0]	1	1			T245	1		-	-		-	-
auto[1]	values[4]	values[1]	8	1			T238	2		T246	2		T247	2
auto[1]	values[4]	values[2]	11	1			T17	1		T34	1		T128	1
auto[1]	values[4]	values[3]	9	1			T169	2		T187	4		T244	1
auto[1]	values[4]	values[4]	10	1			T51	2		T179	1		T204	2
auto[1]	values[4]	values[5]	16	1			T38	4		T188	3		T187	1
auto[1]	values[4]	values[6]	12	1			T248	4		T249	6		T250	2
auto[1]	values[4]	values[7]	20	1			T178	3		T174	1		T251	1
auto[1]	values[5]	values[0]	10	1			T198	2		T174	1		T252	1
auto[1]	values[5]	values[1]	10	1			T5	2		T253	3		T254	4
auto[1]	values[5]	values[2]	18	1			T26	1		T193	3		T168	3
auto[1]	values[5]	values[3]	16	1			T51	1		T188	2		T219	1
auto[1]	values[5]	values[4]	15	1			T40	1		T231	2		T207	4
auto[1]	values[5]	values[5]	11	1			T38	2		T193	1		T190	1
auto[1]	values[5]	values[6]	9	1			T155	2		T147	1		T190	3
auto[1]	values[5]	values[7]	11	1			T255	2		T198	2		T197	1
auto[1]	values[6]	values[0]	29	1			T191	1		T45	1		T238	1
auto[1]	values[6]	values[1]	17	1			T3	3		T41	2		T43	1
auto[1]	values[6]	values[2]	9	1			T26	1		T20	1		T31	2
auto[1]	values[6]	values[3]	2	1			T256	1		T257	1		-	-
auto[1]	values[6]	values[4]	5	1			T5	3		T193	1		T258	1
auto[1]	values[6]	values[5]	2	1			T43	1		T149	1		-	-
auto[1]	values[6]	values[6]	8	1			T20	1		T236	1		T208	2
auto[1]	values[6]	values[7]	12	1			T187	1		T232	2		T153	2
auto[1]	values[7]	values[0]	22	1			T184	2		T169	2		T30	3
auto[1]	values[7]	values[1]	11	1			T215	1		T243	1		T259	3
auto[1]	values[7]	values[2]	13	1			T191	1		T186	3		T222	2
auto[1]	values[7]	values[3]	7	1			T40	2		T45	2		T176	1
auto[1]	values[7]	values[4]	10	1			T40	1		T31	4		T45	1
auto[1]	values[7]	values[5]	22	1			T17	2		T184	4		T191	2
auto[1]	values[7]	values[6]	11	1			T187	2		T204	2		T260	4
auto[1]	values[7]	values[7]	21	1			T155	1		T51	4		T128	2