Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	856	1			T11	11		T17	8		T18	14
all_values[1]	856	1			T11	11		T17	8		T18	14
all_values[2]	856	1			T11	11		T17	8		T18	14
all_values[3]	856	1			T11	11		T17	8		T18	14
all_values[4]	856	1			T11	11		T17	8		T18	14
all_values[5]	856	1			T11	11		T17	8		T18	14
all_values[6]	856	1			T11	11		T17	8		T18	14
all_values[7]	856	1			T11	11		T17	8		T18	14

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3611

1

T11

48

T17

44

T18

70

auto[1]

3237

1

T11

40

T17

20

T18

42

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2822

1

T11

46

T17

40

T18

46

auto[1]

4026

1

T11

42

T17

24

T18

66

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3935

1

T11

59

T17

45

T18

66

auto[1]

2913

1

T11

29

T17

19

T18

46

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	192	1			T11	8		T17	3		T18	2
all_values[0]	auto[0]	auto[0]	auto[1]	90	1			T17	1		T18	3		T20	1
all_values[0]	auto[0]	auto[1]	auto[0]	155	1			T11	1		T17	2		T18	2
all_values[0]	auto[0]	auto[1]	auto[1]	64	1			T11	1		T18	1		T19	1
all_values[0]	auto[1]	auto[0]	auto[1]	192	1			T11	1		T17	2		T18	3
all_values[0]	auto[1]	auto[1]	auto[1]	163	1			T18	3		T19	1		T20	2
all_values[1]	auto[0]	auto[0]	auto[0]	192	1			T17	5		T18	5		T19	2
all_values[1]	auto[0]	auto[0]	auto[1]	82	1			T11	2		T19	1		T20	1
all_values[1]	auto[0]	auto[1]	auto[0]	164	1			T11	4		T17	2		T18	5
all_values[1]	auto[0]	auto[1]	auto[1]	76	1			T11	1		T18	2		T20	2
all_values[1]	auto[1]	auto[0]	auto[1]	195	1			T11	3		T19	4		T20	2
all_values[1]	auto[1]	auto[1]	auto[1]	147	1			T11	1		T17	1		T18	2
all_values[2]	auto[0]	auto[0]	auto[0]	172	1			T11	6		T17	3		T18	3
all_values[2]	auto[0]	auto[0]	auto[1]	78	1			T11	1		T18	1		T20	1
all_values[2]	auto[0]	auto[1]	auto[0]	140	1			T11	2		T18	1		T19	5
all_values[2]	auto[0]	auto[1]	auto[1]	77	1			T17	1		T18	1		T24	1
all_values[2]	auto[1]	auto[0]	auto[1]	202	1			T11	1		T17	2		T18	6
all_values[2]	auto[1]	auto[1]	auto[1]	187	1			T11	1		T17	2		T18	2
all_values[3]	auto[0]	auto[0]	auto[0]	200	1			T11	2		T17	5		T18	3
all_values[3]	auto[0]	auto[0]	auto[1]	71	1			T18	1		T20	2		T23	1
all_values[3]	auto[0]	auto[1]	auto[0]	143	1			T11	5		T19	1		T21	1
all_values[3]	auto[0]	auto[1]	auto[1]	72	1			T17	1		T18	2		T19	1
all_values[3]	auto[1]	auto[0]	auto[1]	195	1			T11	2		T17	1		T18	8
all_values[3]	auto[1]	auto[1]	auto[1]	175	1			T11	2		T17	1		T19	3
all_values[4]	auto[0]	auto[0]	auto[0]	171	1			T11	3		T17	5		T18	4
all_values[4]	auto[0]	auto[0]	auto[1]	82	1			T11	1		T18	2		T20	1
all_values[4]	auto[0]	auto[1]	auto[0]	140	1			T11	4		T17	2		T21	1
all_values[4]	auto[0]	auto[1]	auto[1]	88	1			T18	2		T20	2		T23	1
all_values[4]	auto[1]	auto[0]	auto[1]	196	1			T11	1		T17	1		T18	3
all_values[4]	auto[1]	auto[1]	auto[1]	179	1			T11	2		T18	3		T19	3
all_values[5]	auto[0]	auto[0]	auto[0]	243	1			T11	2		T17	2		T18	4
all_values[5]	auto[0]	auto[1]	auto[0]	244	1			T11	3		T17	3		T18	4
all_values[5]	auto[1]	auto[0]	auto[1]	192	1			T11	4		T17	2		T18	4
all_values[5]	auto[1]	auto[1]	auto[1]	177	1			T11	2		T17	1		T18	2
all_values[6]	auto[0]	auto[0]	auto[0]	174	1			T11	2		T17	4		T18	3
all_values[6]	auto[0]	auto[0]	auto[1]	71	1			T11	3		T18	2		T23	1
all_values[6]	auto[0]	auto[1]	auto[0]	169	1			T11	1		T17	2		T18	3
all_values[6]	auto[0]	auto[1]	auto[1]	97	1			T11	1		T20	3		T21	1
all_values[6]	auto[1]	auto[0]	auto[1]	182	1			T11	4		T17	2		T18	4
all_values[6]	auto[1]	auto[1]	auto[1]	163	1			T18	2		T20	2		T21	1
all_values[7]	auto[0]	auto[0]	auto[0]	172	1			T11	1		T17	2		T18	5
all_values[7]	auto[0]	auto[0]	auto[1]	77	1			T17	1		T18	1		T19	3
all_values[7]	auto[0]	auto[1]	auto[0]	151	1			T11	2		T18	2		T23	2
all_values[7]	auto[0]	auto[1]	auto[1]	88	1			T11	3		T17	1		T18	2
all_values[7]	auto[1]	auto[0]	auto[1]	190	1			T11	1		T17	3		T18	3
all_values[7]	auto[1]	auto[1]	auto[1]	178	1			T11	4		T17	1		T18	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal