Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1615

1

T1

8

T3

8

T8

15

auto[1]

1702

1

T1

13

T3

9

T8

17

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1814

1

T1

21

T3

9

T16

2

auto[1]

1503

1

T3

8

T8

32

T16

1

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2611

1

T1

12

T3

12

T8

32

auto[1]

706

1

T1

9

T3

5

T16

2

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	613	1			T1	5		T3	2		T8	2
valid[1]	697	1			T1	7		T3	3		T8	5
valid[2]	665	1			T1	3		T3	6		T8	9
valid[3]	696	1			T1	5		T3	3		T8	11
valid[4]	646	1			T1	1		T3	3		T8	5

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	97	1			T37	2		T44	1		T38	1
auto[0]	auto[0]	valid[0]	auto[1]	127	1			T8	1		T26	1		T28	2
auto[0]	auto[0]	valid[1]	auto[0]	107	1			T20	1		T37	1		T44	2
auto[0]	auto[0]	valid[1]	auto[1]	176	1			T8	4		T26	1		T19	1
auto[0]	auto[0]	valid[2]	auto[0]	82	1			T1	2		T3	1		T19	1
auto[0]	auto[0]	valid[2]	auto[1]	159	1			T3	1		T8	6		T28	6
auto[0]	auto[0]	valid[3]	auto[0]	119	1			T1	2		T3	2		T17	2
auto[0]	auto[0]	valid[3]	auto[1]	136	1			T3	1		T8	2		T26	1
auto[0]	auto[0]	valid[4]	auto[0]	113	1			T1	1		T17	3		T19	1
auto[0]	auto[0]	valid[4]	auto[1]	133	1			T8	2		T19	2		T28	6
auto[0]	auto[1]	valid[0]	auto[0]	130	1			T1	2		T26	1		T20	1
auto[0]	auto[1]	valid[0]	auto[1]	133	1			T3	1		T8	1		T28	3
auto[0]	auto[1]	valid[1]	auto[0]	121	1			T1	5		T17	2		T26	1
auto[0]	auto[1]	valid[1]	auto[1]	152	1			T3	3		T8	1		T16	1
auto[0]	auto[1]	valid[2]	auto[0]	127	1			T3	1		T17	1		T26	3
auto[0]	auto[1]	valid[2]	auto[1]	164	1			T3	1		T8	3		T28	4
auto[0]	auto[1]	valid[3]	auto[0]	107	1			T26	1		T19	3		T37	1
auto[0]	auto[1]	valid[3]	auto[1]	175	1			T8	9		T28	9		T82	1
auto[0]	auto[1]	valid[4]	auto[0]	105	1			T19	1		T37	2		T44	3
auto[0]	auto[1]	valid[4]	auto[1]	148	1			T3	1		T8	3		T19	1
auto[1]	auto[0]	valid[0]	auto[0]	77	1			T1	2		T3	1		T16	1
auto[1]	auto[0]	valid[1]	auto[0]	71	1			T26	2		T19	1		T20	1
auto[1]	auto[0]	valid[2]	auto[0]	64	1			T1	1		T3	1		T20	1
auto[1]	auto[0]	valid[3]	auto[0]	82	1			T17	1		T37	1		T38	1
auto[1]	auto[0]	valid[4]	auto[0]	72	1			T3	1		T19	1		T20	1
auto[1]	auto[1]	valid[0]	auto[0]	49	1			T1	1		T17	1		T19	1
auto[1]	auto[1]	valid[1]	auto[0]	70	1			T1	2		T17	1		T19	1
auto[1]	auto[1]	valid[2]	auto[0]	69	1			T3	1		T20	1		T38	1
auto[1]	auto[1]	valid[3]	auto[0]	77	1			T1	3		T17	2		T20	1
auto[1]	auto[1]	valid[4]	auto[0]	75	1			T3	1		T16	1		T20	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal