Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

46106

1

T1

491

T3

362

T16

57

auto[1]

15898

1

T3

106

T8

427

T16

28

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

44952

1

T1

334

T3

303

T8

427

auto[1]

17052

1

T1

157

T3

165

T16

30

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	31858	1			T1	273		T3	229		T8	228
others[1]	5225	1			T1	42		T3	38		T8	32
others[2]	5269	1			T1	39		T3	40		T8	45
others[3]	5994	1			T1	41		T3	62		T8	42
interest[1]	3452	1			T1	30		T3	29		T8	17
interest[4]	20770	1			T1	180		T3	137		T8	145
interest[64]	10206	1			T1	66		T3	70		T8	63

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	14890	1			T1	185		T3	101		T16	13
auto[0]	auto[0]	others[1]	2522	1			T1	31		T3	12		T16	2
auto[0]	auto[0]	others[2]	2446	1			T1	23		T3	15		T16	1
auto[0]	auto[0]	others[3]	2829	1			T1	28		T3	28		T16	6
auto[0]	auto[0]	interest[1]	1641	1			T1	24		T3	9		T16	3
auto[0]	auto[0]	interest[4]	9656	1			T1	117		T3	54		T16	10
auto[0]	auto[0]	interest[64]	4726	1			T1	43		T3	32		T16	2
auto[0]	auto[1]	others[0]	8266	1			T3	50		T8	228		T16	16
auto[0]	auto[1]	others[1]	1293	1			T3	8		T8	32		T16	1
auto[0]	auto[1]	others[2]	1367	1			T3	6		T8	45		T16	1
auto[0]	auto[1]	others[3]	1504	1			T3	17		T8	42		T16	2
auto[0]	auto[1]	interest[1]	859	1			T3	9		T8	17		T16	1
auto[0]	auto[1]	interest[4]	5523	1			T3	34		T8	145		T16	10
auto[0]	auto[1]	interest[64]	2609	1			T3	16		T8	63		T16	7
auto[1]	auto[0]	others[0]	8702	1			T1	88		T3	78		T16	14
auto[1]	auto[0]	others[1]	1410	1			T1	11		T3	18		T16	2
auto[1]	auto[0]	others[2]	1456	1			T1	16		T3	19		T16	5
auto[1]	auto[0]	others[3]	1661	1			T1	13		T3	17		T16	2
auto[1]	auto[0]	interest[1]	952	1			T1	6		T3	11		T16	2
auto[1]	auto[0]	interest[4]	5591	1			T1	63		T3	49		T16	11
auto[1]	auto[0]	interest[64]	2871	1			T1	23		T3	22		T16	5

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal