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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.04 98.38 93.99 98.62 89.36 97.19 95.45 99.26


Total test records in report: 1131
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html
T101 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1298647677 Jul 12 06:43:03 PM PDT 24 Jul 12 06:43:09 PM PDT 24 83599449 ps
T116 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.2271343133 Jul 12 06:42:45 PM PDT 24 Jul 12 06:43:07 PM PDT 24 1373764271 ps
T1035 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.4227256929 Jul 12 06:43:07 PM PDT 24 Jul 12 06:43:13 PM PDT 24 48135541 ps
T117 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1693916215 Jul 12 06:43:06 PM PDT 24 Jul 12 06:43:32 PM PDT 24 1405972811 ps
T1036 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.565275360 Jul 12 06:42:58 PM PDT 24 Jul 12 06:43:02 PM PDT 24 35593389 ps
T96 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.244921344 Jul 12 06:43:00 PM PDT 24 Jul 12 06:43:07 PM PDT 24 78668912 ps
T1037 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3577306258 Jul 12 06:43:09 PM PDT 24 Jul 12 06:43:15 PM PDT 24 76450414 ps
T79 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2252125448 Jul 12 06:42:48 PM PDT 24 Jul 12 06:42:51 PM PDT 24 320670544 ps
T1038 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3158111626 Jul 12 06:42:59 PM PDT 24 Jul 12 06:43:06 PM PDT 24 165294525 ps
T143 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.231517204 Jul 12 06:43:00 PM PDT 24 Jul 12 06:43:06 PM PDT 24 761909291 ps
T118 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.2544009827 Jul 12 06:42:57 PM PDT 24 Jul 12 06:43:02 PM PDT 24 506923233 ps
T1039 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1943574327 Jul 12 06:43:24 PM PDT 24 Jul 12 06:43:26 PM PDT 24 13646371 ps
T1040 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3707405597 Jul 12 06:43:07 PM PDT 24 Jul 12 06:43:15 PM PDT 24 235071073 ps
T120 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3865576535 Jul 12 06:42:50 PM PDT 24 Jul 12 06:43:28 PM PDT 24 7532019169 ps
T1041 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.4179982663 Jul 12 06:43:02 PM PDT 24 Jul 12 06:43:07 PM PDT 24 13564620 ps
T1042 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1116410176 Jul 12 06:42:49 PM PDT 24 Jul 12 06:42:54 PM PDT 24 195278487 ps
T1043 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2720813044 Jul 12 06:42:58 PM PDT 24 Jul 12 06:43:02 PM PDT 24 18498116 ps
T103 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3439567568 Jul 12 06:42:51 PM PDT 24 Jul 12 06:42:57 PM PDT 24 41779182 ps
T1044 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.566697260 Jul 12 06:43:02 PM PDT 24 Jul 12 06:43:08 PM PDT 24 40339563 ps
T144 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.2075310056 Jul 12 06:43:04 PM PDT 24 Jul 12 06:43:11 PM PDT 24 141876016 ps
T1045 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.3212249369 Jul 12 06:42:58 PM PDT 24 Jul 12 06:43:02 PM PDT 24 15399447 ps
T1046 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1145510956 Jul 12 06:42:51 PM PDT 24 Jul 12 06:42:56 PM PDT 24 29728024 ps
T166 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3945206460 Jul 12 06:43:03 PM PDT 24 Jul 12 06:43:13 PM PDT 24 108676268 ps
T123 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2873964394 Jul 12 06:42:49 PM PDT 24 Jul 12 06:42:53 PM PDT 24 112284202 ps
T1047 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.988055571 Jul 12 06:42:57 PM PDT 24 Jul 12 06:43:02 PM PDT 24 82678982 ps
T80 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.374453798 Jul 12 06:42:36 PM PDT 24 Jul 12 06:42:41 PM PDT 24 20550936 ps
T1048 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.145377018 Jul 12 06:43:09 PM PDT 24 Jul 12 06:43:14 PM PDT 24 58759350 ps
T1049 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.177778374 Jul 12 06:42:56 PM PDT 24 Jul 12 06:42:58 PM PDT 24 16859931 ps
T1050 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.2055497958 Jul 12 06:43:05 PM PDT 24 Jul 12 06:43:09 PM PDT 24 76889949 ps
T1051 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.1897639209 Jul 12 06:42:43 PM PDT 24 Jul 12 06:42:46 PM PDT 24 12648347 ps
T1052 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3213500667 Jul 12 06:42:47 PM PDT 24 Jul 12 06:42:51 PM PDT 24 198764388 ps
T161 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1802014911 Jul 12 06:43:07 PM PDT 24 Jul 12 06:43:30 PM PDT 24 601860542 ps
T162 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.1040565057 Jul 12 06:42:55 PM PDT 24 Jul 12 06:43:17 PM PDT 24 4222503707 ps
T119 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.4163178130 Jul 12 06:42:53 PM PDT 24 Jul 12 06:42:58 PM PDT 24 75357792 ps
T1053 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3326648293 Jul 12 06:42:53 PM PDT 24 Jul 12 06:43:00 PM PDT 24 219193963 ps
T121 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.4019497880 Jul 12 06:42:52 PM PDT 24 Jul 12 06:43:28 PM PDT 24 935274686 ps
T1054 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3210122678 Jul 12 06:42:48 PM PDT 24 Jul 12 06:42:53 PM PDT 24 85304390 ps
T98 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.3666102561 Jul 12 06:42:59 PM PDT 24 Jul 12 06:43:04 PM PDT 24 315342595 ps
T145 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.3782890859 Jul 12 06:42:59 PM PDT 24 Jul 12 06:43:03 PM PDT 24 73194080 ps
T1055 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1144497310 Jul 12 06:43:01 PM PDT 24 Jul 12 06:43:05 PM PDT 24 20610447 ps
T154 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.762832210 Jul 12 06:42:53 PM PDT 24 Jul 12 06:42:58 PM PDT 24 172135763 ps
T1056 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3073278759 Jul 12 06:42:53 PM PDT 24 Jul 12 06:42:58 PM PDT 24 74488311 ps
T1057 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2042135148 Jul 12 06:42:59 PM PDT 24 Jul 12 06:43:03 PM PDT 24 42610680 ps
T1058 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2384781516 Jul 12 06:43:08 PM PDT 24 Jul 12 06:43:13 PM PDT 24 20575991 ps
T1059 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1294521834 Jul 12 06:42:54 PM PDT 24 Jul 12 06:43:04 PM PDT 24 1141023077 ps
T1060 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3561130300 Jul 12 06:43:09 PM PDT 24 Jul 12 06:43:14 PM PDT 24 34290192 ps
T158 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2727193255 Jul 12 06:42:51 PM PDT 24 Jul 12 06:43:05 PM PDT 24 107998058 ps
T124 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3674698240 Jul 12 06:43:01 PM PDT 24 Jul 12 06:43:28 PM PDT 24 2390573404 ps
T1061 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.2488803433 Jul 12 06:43:07 PM PDT 24 Jul 12 06:43:12 PM PDT 24 14461663 ps
T1062 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3266029012 Jul 12 06:42:54 PM PDT 24 Jul 12 06:42:57 PM PDT 24 49135288 ps
T1063 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.2401215546 Jul 12 06:42:47 PM PDT 24 Jul 12 06:42:50 PM PDT 24 18024380 ps
T164 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.3264294300 Jul 12 06:43:08 PM PDT 24 Jul 12 06:43:20 PM PDT 24 768481099 ps
T122 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.237125140 Jul 12 06:42:51 PM PDT 24 Jul 12 06:42:56 PM PDT 24 309501865 ps
T1064 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1660200470 Jul 12 06:42:51 PM PDT 24 Jul 12 06:43:03 PM PDT 24 330494582 ps
T1065 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.3885895663 Jul 12 06:43:06 PM PDT 24 Jul 12 06:43:11 PM PDT 24 12728362 ps
T99 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.4027476425 Jul 12 06:43:05 PM PDT 24 Jul 12 06:43:11 PM PDT 24 63059511 ps
T1066 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1706940074 Jul 12 06:42:58 PM PDT 24 Jul 12 06:43:03 PM PDT 24 213497263 ps
T1067 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1416074623 Jul 12 06:42:36 PM PDT 24 Jul 12 06:42:41 PM PDT 24 65059405 ps
T1068 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2842476745 Jul 12 06:43:02 PM PDT 24 Jul 12 06:43:06 PM PDT 24 20498369 ps
T97 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1871236866 Jul 12 06:42:51 PM PDT 24 Jul 12 06:42:57 PM PDT 24 164064451 ps
T1069 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2363688345 Jul 12 06:43:04 PM PDT 24 Jul 12 06:43:11 PM PDT 24 951913875 ps
T1070 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.791599631 Jul 12 06:42:48 PM PDT 24 Jul 12 06:42:51 PM PDT 24 122731310 ps
T1071 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.438266583 Jul 12 06:43:07 PM PDT 24 Jul 12 06:43:12 PM PDT 24 29701856 ps
T1072 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1260631494 Jul 12 06:42:52 PM PDT 24 Jul 12 06:42:56 PM PDT 24 73149138 ps
T102 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.345851545 Jul 12 06:42:52 PM PDT 24 Jul 12 06:42:58 PM PDT 24 192478650 ps
T1073 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2339079025 Jul 12 06:42:55 PM PDT 24 Jul 12 06:42:58 PM PDT 24 20961304 ps
T1074 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.3533617174 Jul 12 06:42:58 PM PDT 24 Jul 12 06:43:02 PM PDT 24 37692180 ps
T163 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.2313394371 Jul 12 06:43:06 PM PDT 24 Jul 12 06:43:16 PM PDT 24 311087308 ps
T1075 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.4215581645 Jul 12 06:43:03 PM PDT 24 Jul 12 06:43:23 PM PDT 24 691618470 ps
T159 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3231044035 Jul 12 06:42:50 PM PDT 24 Jul 12 06:43:14 PM PDT 24 5401289025 ps
T1076 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.3498392127 Jul 12 06:43:00 PM PDT 24 Jul 12 06:43:04 PM PDT 24 11060873 ps
T1077 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.406416263 Jul 12 06:43:02 PM PDT 24 Jul 12 06:43:08 PM PDT 24 76229708 ps
T100 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1739160445 Jul 12 06:43:10 PM PDT 24 Jul 12 06:43:18 PM PDT 24 1785503836 ps
T1078 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3585918156 Jul 12 06:42:55 PM PDT 24 Jul 12 06:42:58 PM PDT 24 12833920 ps
T81 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3369329676 Jul 12 06:42:47 PM PDT 24 Jul 12 06:42:50 PM PDT 24 21014469 ps
T1079 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.990245981 Jul 12 06:42:56 PM PDT 24 Jul 12 06:43:03 PM PDT 24 73167223 ps
T165 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1581084737 Jul 12 06:42:48 PM PDT 24 Jul 12 06:43:07 PM PDT 24 1156217939 ps
T1080 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.957526903 Jul 12 06:43:08 PM PDT 24 Jul 12 06:43:15 PM PDT 24 82540446 ps
T160 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.3896018974 Jul 12 06:42:52 PM PDT 24 Jul 12 06:43:07 PM PDT 24 405690011 ps
T1081 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1968475726 Jul 12 06:43:07 PM PDT 24 Jul 12 06:43:12 PM PDT 24 15333314 ps
T1082 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.190336441 Jul 12 06:42:46 PM PDT 24 Jul 12 06:42:49 PM PDT 24 19228381 ps
T1083 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.2014798669 Jul 12 06:43:02 PM PDT 24 Jul 12 06:43:20 PM PDT 24 2855170081 ps
T1084 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2991616193 Jul 12 06:42:48 PM PDT 24 Jul 12 06:42:53 PM PDT 24 241936758 ps
T1085 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.4112621357 Jul 12 06:42:37 PM PDT 24 Jul 12 06:42:42 PM PDT 24 13565298 ps
T1086 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3710099442 Jul 12 06:42:55 PM PDT 24 Jul 12 06:43:00 PM PDT 24 578028726 ps
T1087 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.514872497 Jul 12 06:42:53 PM PDT 24 Jul 12 06:42:57 PM PDT 24 53875596 ps
T1088 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.849789646 Jul 12 06:42:58 PM PDT 24 Jul 12 06:43:03 PM PDT 24 46217603 ps
T1089 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2696882629 Jul 12 06:42:55 PM PDT 24 Jul 12 06:43:18 PM PDT 24 995068466 ps
T1090 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.961019333 Jul 12 06:42:49 PM PDT 24 Jul 12 06:42:54 PM PDT 24 178045743 ps
T1091 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1471220183 Jul 12 06:42:58 PM PDT 24 Jul 12 06:43:05 PM PDT 24 106582652 ps
T1092 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2373673377 Jul 12 06:42:51 PM PDT 24 Jul 12 06:42:56 PM PDT 24 113085736 ps
T1093 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.112097683 Jul 12 06:43:06 PM PDT 24 Jul 12 06:43:12 PM PDT 24 73522200 ps
T1094 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.152877779 Jul 12 06:42:56 PM PDT 24 Jul 12 06:43:04 PM PDT 24 807147719 ps
T1095 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.3745798719 Jul 12 06:43:04 PM PDT 24 Jul 12 06:43:08 PM PDT 24 50753159 ps
T1096 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.1468876813 Jul 12 06:43:06 PM PDT 24 Jul 12 06:43:15 PM PDT 24 16048148 ps
T1097 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.4248565304 Jul 12 06:43:05 PM PDT 24 Jul 12 06:43:10 PM PDT 24 56249741 ps
T1098 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3462481279 Jul 12 06:43:02 PM PDT 24 Jul 12 06:43:06 PM PDT 24 37749802 ps
T1099 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.938180935 Jul 12 06:43:02 PM PDT 24 Jul 12 06:43:08 PM PDT 24 125960297 ps
T1100 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.302773381 Jul 12 06:43:03 PM PDT 24 Jul 12 06:43:11 PM PDT 24 951615125 ps
T1101 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3478333142 Jul 12 06:42:56 PM PDT 24 Jul 12 06:42:59 PM PDT 24 13058387 ps
T1102 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3628545955 Jul 12 06:43:00 PM PDT 24 Jul 12 06:43:03 PM PDT 24 48268959 ps
T1103 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2973812508 Jul 12 06:43:06 PM PDT 24 Jul 12 06:43:11 PM PDT 24 49057479 ps
T1104 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.603649184 Jul 12 06:43:03 PM PDT 24 Jul 12 06:43:24 PM PDT 24 289485840 ps
T1105 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1920000417 Jul 12 06:42:43 PM PDT 24 Jul 12 06:42:47 PM PDT 24 133503208 ps
T1106 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.2274392746 Jul 12 06:43:27 PM PDT 24 Jul 12 06:43:29 PM PDT 24 40701602 ps
T1107 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3908147072 Jul 12 06:43:09 PM PDT 24 Jul 12 06:43:14 PM PDT 24 23854294 ps
T1108 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.776460853 Jul 12 06:42:54 PM PDT 24 Jul 12 06:43:04 PM PDT 24 147378066 ps
T1109 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.4268336626 Jul 12 06:43:04 PM PDT 24 Jul 12 06:43:11 PM PDT 24 348438886 ps
T1110 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.3432802983 Jul 12 06:43:02 PM PDT 24 Jul 12 06:43:09 PM PDT 24 224633194 ps
T1111 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1411915366 Jul 12 06:42:49 PM PDT 24 Jul 12 06:42:53 PM PDT 24 95358819 ps
T1112 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.3192827223 Jul 12 06:43:24 PM PDT 24 Jul 12 06:43:26 PM PDT 24 42119788 ps
T1113 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.968138477 Jul 12 06:42:59 PM PDT 24 Jul 12 06:43:02 PM PDT 24 55639182 ps
T1114 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1319087548 Jul 12 06:43:04 PM PDT 24 Jul 12 06:43:15 PM PDT 24 1068267361 ps
T1115 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.690535364 Jul 12 06:43:04 PM PDT 24 Jul 12 06:43:20 PM PDT 24 782206437 ps
T1116 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.549764512 Jul 12 06:43:20 PM PDT 24 Jul 12 06:43:21 PM PDT 24 47762294 ps
T157 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.4231430924 Jul 12 06:42:47 PM PDT 24 Jul 12 06:42:53 PM PDT 24 77447583 ps
T1117 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3779619391 Jul 12 06:42:48 PM PDT 24 Jul 12 06:42:58 PM PDT 24 993522398 ps
T1118 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.179858368 Jul 12 06:43:02 PM PDT 24 Jul 12 06:43:08 PM PDT 24 242761968 ps
T1119 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3788926176 Jul 12 06:42:47 PM PDT 24 Jul 12 06:42:50 PM PDT 24 42134538 ps
T1120 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.962750175 Jul 12 06:43:00 PM PDT 24 Jul 12 06:43:04 PM PDT 24 23959773 ps
T1121 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2930037265 Jul 12 06:42:50 PM PDT 24 Jul 12 06:42:54 PM PDT 24 188231309 ps
T1122 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2837149026 Jul 12 06:43:11 PM PDT 24 Jul 12 06:43:15 PM PDT 24 23299799 ps
T1123 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.4077693164 Jul 12 06:42:52 PM PDT 24 Jul 12 06:42:55 PM PDT 24 21457104 ps
T1124 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.1267423204 Jul 12 06:42:48 PM PDT 24 Jul 12 06:43:12 PM PDT 24 1697465161 ps
T1125 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1528668502 Jul 12 06:42:59 PM PDT 24 Jul 12 06:43:04 PM PDT 24 45271829 ps
T1126 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.932502830 Jul 12 06:43:04 PM PDT 24 Jul 12 06:43:08 PM PDT 24 18497608 ps
T1127 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.727857155 Jul 12 06:43:09 PM PDT 24 Jul 12 06:43:15 PM PDT 24 56585221 ps
T1128 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1933399902 Jul 12 06:43:05 PM PDT 24 Jul 12 06:43:16 PM PDT 24 257243904 ps
T1129 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.2634846141 Jul 12 06:42:56 PM PDT 24 Jul 12 06:43:03 PM PDT 24 269392627 ps
T1130 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3229807132 Jul 12 06:43:03 PM PDT 24 Jul 12 06:43:07 PM PDT 24 14686362 ps
T1131 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.393532816 Jul 12 06:42:50 PM PDT 24 Jul 12 06:42:55 PM PDT 24 305670011 ps

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.3165689481
Short name T3
Test name
Test status
Simulation time 15986849164 ps
CPU time 126.67 seconds
Started Jul 12 06:33:38 PM PDT 24
Finished Jul 12 06:35:46 PM PDT 24
Peak memory 264324 kb
Host smart-f3648e24-cf46-4df1-9178-58d2b0fadea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165689481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.3165689481
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.544028116
Short name T37
Test name
Test status
Simulation time 29646939246 ps
CPU time 316.68 seconds
Started Jul 12 06:32:19 PM PDT 24
Finished Jul 12 06:37:36 PM PDT 24
Peak memory 250804 kb
Host smart-29d441ae-d8eb-45ac-933b-546a704831bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544028116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idle
.544028116
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.299919278
Short name T17
Test name
Test status
Simulation time 31844679614 ps
CPU time 204.53 seconds
Started Jul 12 06:33:33 PM PDT 24
Finished Jul 12 06:36:59 PM PDT 24
Peak memory 267808 kb
Host smart-4b049096-c3ea-45ed-ac7c-dd2b26f9021a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299919278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stres
s_all.299919278
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.1451074132
Short name T90
Test name
Test status
Simulation time 4283635318 ps
CPU time 22.62 seconds
Started Jul 12 06:42:56 PM PDT 24
Finished Jul 12 06:43:22 PM PDT 24
Peak memory 215712 kb
Host smart-70be46c3-5213-4a70-8ea7-44c5aaee915c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451074132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.1451074132
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.59851687
Short name T24
Test name
Test status
Simulation time 472425670151 ps
CPU time 613.79 seconds
Started Jul 12 06:31:07 PM PDT 24
Finished Jul 12 06:41:22 PM PDT 24
Peak memory 281928 kb
Host smart-b03d93a8-4062-4ab3-ad58-c1310938a139
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59851687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stress_
all.59851687
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.562479796
Short name T64
Test name
Test status
Simulation time 48363207 ps
CPU time 0.77 seconds
Started Jul 12 06:30:45 PM PDT 24
Finished Jul 12 06:30:47 PM PDT 24
Peak memory 215992 kb
Host smart-b4d3ef23-2bf1-4b98-81cd-6bcd45a13f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562479796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.562479796
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.3569565227
Short name T40
Test name
Test status
Simulation time 229085651360 ps
CPU time 497.33 seconds
Started Jul 12 06:31:01 PM PDT 24
Finished Jul 12 06:39:21 PM PDT 24
Peak memory 250912 kb
Host smart-4a3defc3-9f6d-4f72-b7e9-9eb7085ca963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569565227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.3569565227
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.3312243911
Short name T178
Test name
Test status
Simulation time 9950392098 ps
CPU time 169.25 seconds
Started Jul 12 06:34:37 PM PDT 24
Finished Jul 12 06:37:28 PM PDT 24
Peak memory 249264 kb
Host smart-1f7ecec4-0ec9-4d5c-a024-7b69208505ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312243911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.3312243911
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3145385358
Short name T61
Test name
Test status
Simulation time 64472263 ps
CPU time 3.99 seconds
Started Jul 12 06:42:55 PM PDT 24
Finished Jul 12 06:43:01 PM PDT 24
Peak memory 215984 kb
Host smart-216ef02d-9dba-4574-bb19-8f4d57f36db1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145385358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
3145385358
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.3772113994
Short name T31
Test name
Test status
Simulation time 5330427634 ps
CPU time 128.98 seconds
Started Jul 12 06:34:20 PM PDT 24
Finished Jul 12 06:36:32 PM PDT 24
Peak memory 255836 kb
Host smart-273b90b1-e5a8-4f93-bf06-4ba609845532
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772113994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.3772113994
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.1303038255
Short name T22
Test name
Test status
Simulation time 133451565 ps
CPU time 1 seconds
Started Jul 12 06:31:04 PM PDT 24
Finished Jul 12 06:31:06 PM PDT 24
Peak memory 235888 kb
Host smart-49a687cb-9dbc-45a7-9b0c-224aed8011a4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303038255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.1303038255
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.2976379009
Short name T191
Test name
Test status
Simulation time 104869866205 ps
CPU time 395.01 seconds
Started Jul 12 06:34:54 PM PDT 24
Finished Jul 12 06:41:31 PM PDT 24
Peak memory 273640 kb
Host smart-2e4e9a45-a851-4df2-8a69-6a13a41a5832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976379009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.2976379009
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.3904083514
Short name T33
Test name
Test status
Simulation time 447060810 ps
CPU time 6.68 seconds
Started Jul 12 06:34:55 PM PDT 24
Finished Jul 12 06:35:03 PM PDT 24
Peak memory 224480 kb
Host smart-26065a6f-50b2-4c34-92d0-17083219918e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904083514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.3904083514
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.794795962
Short name T51
Test name
Test status
Simulation time 8975043981 ps
CPU time 126.61 seconds
Started Jul 12 06:32:25 PM PDT 24
Finished Jul 12 06:34:33 PM PDT 24
Peak memory 253732 kb
Host smart-7342f7c8-65ef-45d3-a888-ab4167ab7fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794795962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.794795962
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.858037152
Short name T149
Test name
Test status
Simulation time 209429415165 ps
CPU time 540.08 seconds
Started Jul 12 06:31:03 PM PDT 24
Finished Jul 12 06:40:05 PM PDT 24
Peak memory 283460 kb
Host smart-07a92de2-1409-44e2-b5d8-57e304665835
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858037152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stress
_all.858037152
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3743389128
Short name T111
Test name
Test status
Simulation time 82008470 ps
CPU time 2.41 seconds
Started Jul 12 06:43:04 PM PDT 24
Finished Jul 12 06:43:09 PM PDT 24
Peak memory 215632 kb
Host smart-9cbc292d-784b-4a70-a214-7a164919b443
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743389128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
3743389128
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.2272311576
Short name T153
Test name
Test status
Simulation time 5190333358 ps
CPU time 126.59 seconds
Started Jul 12 06:35:18 PM PDT 24
Finished Jul 12 06:37:26 PM PDT 24
Peak memory 268652 kb
Host smart-99e628d2-2f75-41a1-8bbc-c6442be8b5d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272311576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.2272311576
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.2703361198
Short name T193
Test name
Test status
Simulation time 33117500220 ps
CPU time 131.18 seconds
Started Jul 12 06:31:20 PM PDT 24
Finished Jul 12 06:33:33 PM PDT 24
Peak memory 255896 kb
Host smart-276efab8-6aae-45a7-a688-2cbbe87b0c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703361198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.2703361198
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.2463271229
Short name T19
Test name
Test status
Simulation time 11704831689 ps
CPU time 103.89 seconds
Started Jul 12 06:30:59 PM PDT 24
Finished Jul 12 06:32:44 PM PDT 24
Peak memory 249244 kb
Host smart-bffc2d73-634a-40b7-a1c5-fef9bc82bb19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463271229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.2463271229
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.771073836
Short name T84
Test name
Test status
Simulation time 4099451243 ps
CPU time 88.87 seconds
Started Jul 12 06:31:00 PM PDT 24
Finished Jul 12 06:32:30 PM PDT 24
Peak memory 257324 kb
Host smart-cf397ae4-b68d-4341-bcc3-a8a3558c8e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771073836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds.
771073836
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.1069855814
Short name T224
Test name
Test status
Simulation time 28392039750 ps
CPU time 183.42 seconds
Started Jul 12 06:30:52 PM PDT 24
Finished Jul 12 06:33:56 PM PDT 24
Peak memory 263940 kb
Host smart-cd646019-96b6-4c51-bcdb-ceca15e54fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069855814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds
.1069855814
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.3918586075
Short name T215
Test name
Test status
Simulation time 1009911352022 ps
CPU time 440.24 seconds
Started Jul 12 06:34:26 PM PDT 24
Finished Jul 12 06:41:47 PM PDT 24
Peak memory 269060 kb
Host smart-c43a1ca7-e93e-40cb-b519-9c15de86d0fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918586075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.3918586075
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.918787152
Short name T187
Test name
Test status
Simulation time 42845666576 ps
CPU time 163.76 seconds
Started Jul 12 06:32:06 PM PDT 24
Finished Jul 12 06:34:52 PM PDT 24
Peak memory 265916 kb
Host smart-18bb4d45-86ed-4127-b437-77ff1e4c3100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918787152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.918787152
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.874706163
Short name T146
Test name
Test status
Simulation time 17882347870 ps
CPU time 204.82 seconds
Started Jul 12 06:32:48 PM PDT 24
Finished Jul 12 06:36:15 PM PDT 24
Peak memory 255996 kb
Host smart-195f3394-4918-42f1-88df-29d6bde2b9b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874706163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stres
s_all.874706163
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.951887180
Short name T58
Test name
Test status
Simulation time 41896746 ps
CPU time 0.78 seconds
Started Jul 12 06:30:44 PM PDT 24
Finished Jul 12 06:30:46 PM PDT 24
Peak memory 204912 kb
Host smart-29158b30-0962-4b20-b037-d9b43221559d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951887180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.951887180
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.3246093648
Short name T194
Test name
Test status
Simulation time 11032903892 ps
CPU time 110.79 seconds
Started Jul 12 06:33:09 PM PDT 24
Finished Jul 12 06:35:01 PM PDT 24
Peak memory 257392 kb
Host smart-a81fb5db-586e-4e2c-87b1-20a4f186da4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246093648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.3246093648
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.1146877769
Short name T13
Test name
Test status
Simulation time 4307882425 ps
CPU time 61.85 seconds
Started Jul 12 06:31:00 PM PDT 24
Finished Jul 12 06:32:02 PM PDT 24
Peak memory 251228 kb
Host smart-e670194d-6ba9-464d-bbcf-a5f487ca15f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146877769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.1146877769
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.2708840436
Short name T181
Test name
Test status
Simulation time 191600079184 ps
CPU time 326.91 seconds
Started Jul 12 06:33:11 PM PDT 24
Finished Jul 12 06:38:39 PM PDT 24
Peak memory 265604 kb
Host smart-5afd0725-7bd6-4ed9-83ee-12946c3f6242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708840436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.2708840436
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1739160445
Short name T100
Test name
Test status
Simulation time 1785503836 ps
CPU time 4.17 seconds
Started Jul 12 06:43:10 PM PDT 24
Finished Jul 12 06:43:18 PM PDT 24
Peak memory 216096 kb
Host smart-17d13534-adfb-4b28-8861-1537f437ef40
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739160445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
1739160445
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.3104740211
Short name T20
Test name
Test status
Simulation time 80835273323 ps
CPU time 819.7 seconds
Started Jul 12 06:34:40 PM PDT 24
Finished Jul 12 06:48:21 PM PDT 24
Peak memory 273500 kb
Host smart-f22a9214-67f6-4bb3-ab5d-34a48b4dd1cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104740211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.3104740211
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3231044035
Short name T159
Test name
Test status
Simulation time 5401289025 ps
CPU time 22.28 seconds
Started Jul 12 06:42:50 PM PDT 24
Finished Jul 12 06:43:14 PM PDT 24
Peak memory 215808 kb
Host smart-55863015-43b6-45a5-87b8-34e2732b28ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231044035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.3231044035
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.3706705107
Short name T45
Test name
Test status
Simulation time 83943823031 ps
CPU time 427.7 seconds
Started Jul 12 06:31:53 PM PDT 24
Finished Jul 12 06:39:02 PM PDT 24
Peak memory 251052 kb
Host smart-d618bae1-a7bf-481f-a500-352e31bbb11f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706705107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.3706705107
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.4155647455
Short name T734
Test name
Test status
Simulation time 23243030991 ps
CPU time 238.13 seconds
Started Jul 12 06:33:01 PM PDT 24
Finished Jul 12 06:37:00 PM PDT 24
Peak memory 273200 kb
Host smart-9ec0ed59-0dd3-4b19-a5ee-1aed28d7daba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155647455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.4155647455
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.1510511360
Short name T239
Test name
Test status
Simulation time 10588362636 ps
CPU time 121.09 seconds
Started Jul 12 06:31:51 PM PDT 24
Finished Jul 12 06:33:53 PM PDT 24
Peak memory 263536 kb
Host smart-fc4401d7-30f0-4d5e-bdc8-dcab754dc08d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510511360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.1510511360
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.715535985
Short name T263
Test name
Test status
Simulation time 6769928977 ps
CPU time 26.92 seconds
Started Jul 12 06:32:24 PM PDT 24
Finished Jul 12 06:32:53 PM PDT 24
Peak memory 236104 kb
Host smart-85526e90-5a95-491b-bf65-3ac72881ea85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715535985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.715535985
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.1528639197
Short name T34
Test name
Test status
Simulation time 28254441142 ps
CPU time 141.94 seconds
Started Jul 12 06:32:35 PM PDT 24
Finished Jul 12 06:34:58 PM PDT 24
Peak memory 268672 kb
Host smart-2ca7799c-c4a8-4e48-ad5e-8b72fc0e60ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528639197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.1528639197
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.4123766511
Short name T425
Test name
Test status
Simulation time 45563086680 ps
CPU time 164.45 seconds
Started Jul 12 06:33:08 PM PDT 24
Finished Jul 12 06:35:53 PM PDT 24
Peak memory 273748 kb
Host smart-1b30a2bd-7c9c-4bac-be3b-3c01419ff1d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123766511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.4123766511
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.3023054646
Short name T266
Test name
Test status
Simulation time 2392328249 ps
CPU time 11.05 seconds
Started Jul 12 06:33:59 PM PDT 24
Finished Jul 12 06:34:11 PM PDT 24
Peak memory 232752 kb
Host smart-bbafc0a3-1a70-4efc-96ff-a533f16021e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023054646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.3023054646
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.3790123108
Short name T87
Test name
Test status
Simulation time 1234052941 ps
CPU time 17 seconds
Started Jul 12 06:42:54 PM PDT 24
Finished Jul 12 06:43:13 PM PDT 24
Peak memory 215768 kb
Host smart-3f76eabe-bd92-4e4c-906f-eb35108ba93e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790123108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.3790123108
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.1040565057
Short name T162
Test name
Test status
Simulation time 4222503707 ps
CPU time 19.86 seconds
Started Jul 12 06:42:55 PM PDT 24
Finished Jul 12 06:43:17 PM PDT 24
Peak memory 216160 kb
Host smart-41ef6411-1b78-451d-a8ba-a0ae2ea3bbec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040565057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.1040565057
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.94055480
Short name T253
Test name
Test status
Simulation time 35967346398 ps
CPU time 306.77 seconds
Started Jul 12 06:30:42 PM PDT 24
Finished Jul 12 06:35:50 PM PDT 24
Peak memory 253876 kb
Host smart-9b172dd8-1214-432c-9a27-9e4f925c3eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94055480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.94055480
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.3336486504
Short name T269
Test name
Test status
Simulation time 5087086792 ps
CPU time 31.93 seconds
Started Jul 12 06:30:45 PM PDT 24
Finished Jul 12 06:31:18 PM PDT 24
Peak memory 240928 kb
Host smart-b8b62a3c-584c-4b7a-9dc7-fa37c8bc31a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336486504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.3336486504
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.2532852053
Short name T249
Test name
Test status
Simulation time 15885132164 ps
CPU time 63.23 seconds
Started Jul 12 06:31:42 PM PDT 24
Finished Jul 12 06:32:46 PM PDT 24
Peak memory 253524 kb
Host smart-e8b66ac3-4c26-4d15-88f6-98c6db5e42e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532852053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.2532852053
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.4095629134
Short name T247
Test name
Test status
Simulation time 34000415834 ps
CPU time 339.7 seconds
Started Jul 12 06:31:57 PM PDT 24
Finished Jul 12 06:37:37 PM PDT 24
Peak memory 256180 kb
Host smart-fcfd2ad8-fae1-48e6-87fc-49ed3eb2d709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095629134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.4095629134
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.1697112032
Short name T257
Test name
Test status
Simulation time 367721174309 ps
CPU time 343.7 seconds
Started Jul 12 06:32:39 PM PDT 24
Finished Jul 12 06:38:23 PM PDT 24
Peak memory 265524 kb
Host smart-bb835ba4-cbcb-4ff6-a2a0-51e208f6dec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697112032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.1697112032
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.817317395
Short name T245
Test name
Test status
Simulation time 15434796688 ps
CPU time 45.57 seconds
Started Jul 12 06:32:49 PM PDT 24
Finished Jul 12 06:33:37 PM PDT 24
Peak memory 249104 kb
Host smart-87721979-a769-4af6-8777-38ab73a6c776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817317395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.817317395
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.2333287589
Short name T279
Test name
Test status
Simulation time 131595937450 ps
CPU time 96.95 seconds
Started Jul 12 06:33:11 PM PDT 24
Finished Jul 12 06:34:49 PM PDT 24
Peak memory 249220 kb
Host smart-487b3c8e-e494-475a-8bf5-aa801d21db0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333287589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.2333287589
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.2779945571
Short name T175
Test name
Test status
Simulation time 4163043656 ps
CPU time 4.9 seconds
Started Jul 12 06:35:08 PM PDT 24
Finished Jul 12 06:35:15 PM PDT 24
Peak memory 224440 kb
Host smart-2a121368-7943-4f76-b987-254db55fa805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779945571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.2779945571
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.1321699726
Short name T83
Test name
Test status
Simulation time 3490967505 ps
CPU time 15.99 seconds
Started Jul 12 06:31:43 PM PDT 24
Finished Jul 12 06:32:01 PM PDT 24
Peak memory 232592 kb
Host smart-dafc999b-370b-4bdd-b279-c5ee79546ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321699726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.1321699726
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.1104108572
Short name T182
Test name
Test status
Simulation time 255990480 ps
CPU time 5.42 seconds
Started Jul 12 06:31:57 PM PDT 24
Finished Jul 12 06:32:03 PM PDT 24
Peak memory 232552 kb
Host smart-9e2754fe-cc30-4b3f-9230-c8ceb4630a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104108572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.1104108572
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.3102491233
Short name T136
Test name
Test status
Simulation time 385397093 ps
CPU time 8.78 seconds
Started Jul 12 06:32:14 PM PDT 24
Finished Jul 12 06:32:23 PM PDT 24
Peak memory 232592 kb
Host smart-40b3b7a3-b087-4b14-b848-d92295568e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102491233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.3102491233
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3369329676
Short name T81
Test name
Test status
Simulation time 21014469 ps
CPU time 1.15 seconds
Started Jul 12 06:42:47 PM PDT 24
Finished Jul 12 06:42:50 PM PDT 24
Peak memory 207432 kb
Host smart-9fbbc91c-52d1-4b8c-b71c-902220ab2323
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369329676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.3369329676
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.302773381
Short name T1100
Test name
Test status
Simulation time 951615125 ps
CPU time 4.95 seconds
Started Jul 12 06:43:03 PM PDT 24
Finished Jul 12 06:43:11 PM PDT 24
Peak memory 216980 kb
Host smart-9563947c-794e-46cc-aaac-ceb6981590a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302773381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.302773381
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.2271343133
Short name T116
Test name
Test status
Simulation time 1373764271 ps
CPU time 21.74 seconds
Started Jul 12 06:42:45 PM PDT 24
Finished Jul 12 06:43:07 PM PDT 24
Peak memory 215696 kb
Host smart-37cf277f-e069-46e0-baa9-47e34f4ca3cd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271343133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.2271343133
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1702722774
Short name T1028
Test name
Test status
Simulation time 725435028 ps
CPU time 12.48 seconds
Started Jul 12 06:42:45 PM PDT 24
Finished Jul 12 06:42:58 PM PDT 24
Peak memory 207416 kb
Host smart-96c01b48-504d-48b9-a767-59d0a0262abc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702722774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.1702722774
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.374453798
Short name T80
Test name
Test status
Simulation time 20550936 ps
CPU time 1.23 seconds
Started Jul 12 06:42:36 PM PDT 24
Finished Jul 12 06:42:41 PM PDT 24
Peak memory 215676 kb
Host smart-9c747b43-6c72-4a63-bdbe-f57735259a86
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374453798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_hw_reset.374453798
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3210122678
Short name T1054
Test name
Test status
Simulation time 85304390 ps
CPU time 2.63 seconds
Started Jul 12 06:42:48 PM PDT 24
Finished Jul 12 06:42:53 PM PDT 24
Peak memory 218028 kb
Host smart-42ec4454-8858-4753-85e5-f738f59f40ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210122678 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.3210122678
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.190336441
Short name T1082
Test name
Test status
Simulation time 19228381 ps
CPU time 1.31 seconds
Started Jul 12 06:42:46 PM PDT 24
Finished Jul 12 06:42:49 PM PDT 24
Peak memory 207540 kb
Host smart-80fc8701-0f62-4096-a0c9-9ec1ea46e7cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190336441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.190336441
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.1897639209
Short name T1051
Test name
Test status
Simulation time 12648347 ps
CPU time 0.71 seconds
Started Jul 12 06:42:43 PM PDT 24
Finished Jul 12 06:42:46 PM PDT 24
Peak memory 204336 kb
Host smart-49554023-8d1e-4f29-b18f-83254450e189
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897639209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.1
897639209
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1416074623
Short name T1067
Test name
Test status
Simulation time 65059405 ps
CPU time 1.29 seconds
Started Jul 12 06:42:36 PM PDT 24
Finished Jul 12 06:42:41 PM PDT 24
Peak memory 215700 kb
Host smart-6774932d-43aa-47cc-999e-3279b52ea51e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416074623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.1416074623
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.4112621357
Short name T1085
Test name
Test status
Simulation time 13565298 ps
CPU time 0.68 seconds
Started Jul 12 06:42:37 PM PDT 24
Finished Jul 12 06:42:42 PM PDT 24
Peak memory 204424 kb
Host smart-aa20b9a7-3f65-4aa4-8766-bf84d7c707bb
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112621357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.4112621357
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3158111626
Short name T1038
Test name
Test status
Simulation time 165294525 ps
CPU time 4.4 seconds
Started Jul 12 06:42:59 PM PDT 24
Finished Jul 12 06:43:06 PM PDT 24
Peak memory 215736 kb
Host smart-967a92e4-130e-49b3-957f-f200d45373c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158111626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.3158111626
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.289820992
Short name T91
Test name
Test status
Simulation time 167445801 ps
CPU time 2.85 seconds
Started Jul 12 06:42:37 PM PDT 24
Finished Jul 12 06:42:44 PM PDT 24
Peak memory 216168 kb
Host smart-4f07db38-0f55-4130-a22c-ca9e1bb31570
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289820992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.289820992
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.2696286712
Short name T113
Test name
Test status
Simulation time 113169110 ps
CPU time 7.76 seconds
Started Jul 12 06:42:48 PM PDT 24
Finished Jul 12 06:42:57 PM PDT 24
Peak memory 215644 kb
Host smart-83c18aab-2d5d-42d8-9cc1-a59563536303
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696286712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.2696286712
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.4019497880
Short name T121
Test name
Test status
Simulation time 935274686 ps
CPU time 33.89 seconds
Started Jul 12 06:42:52 PM PDT 24
Finished Jul 12 06:43:28 PM PDT 24
Peak memory 207432 kb
Host smart-7ebae8e2-7280-4d83-a1f8-f93b1da708e9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019497880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.4019497880
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.482324213
Short name T107
Test name
Test status
Simulation time 151281407 ps
CPU time 2.59 seconds
Started Jul 12 06:42:47 PM PDT 24
Finished Jul 12 06:42:52 PM PDT 24
Peak memory 217572 kb
Host smart-eab71d6f-4cdb-4dcd-90ec-4e33b5af203e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482324213 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.482324213
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.647641046
Short name T110
Test name
Test status
Simulation time 334719082 ps
CPU time 2.76 seconds
Started Jul 12 06:42:43 PM PDT 24
Finished Jul 12 06:42:48 PM PDT 24
Peak memory 215740 kb
Host smart-5e798d02-a665-4703-9413-9ac8fb778942
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647641046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.647641046
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.1746424520
Short name T1023
Test name
Test status
Simulation time 70912299 ps
CPU time 0.74 seconds
Started Jul 12 06:43:04 PM PDT 24
Finished Jul 12 06:43:08 PM PDT 24
Peak memory 204284 kb
Host smart-c7206ac8-5989-4051-a581-a72179bd3e8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746424520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.1
746424520
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2873964394
Short name T123
Test name
Test status
Simulation time 112284202 ps
CPU time 1.28 seconds
Started Jul 12 06:42:49 PM PDT 24
Finished Jul 12 06:42:53 PM PDT 24
Peak memory 215772 kb
Host smart-e928280f-fc21-4707-8be4-7fa3b8a80454
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873964394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.2873964394
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.177778374
Short name T1049
Test name
Test status
Simulation time 16859931 ps
CPU time 0.69 seconds
Started Jul 12 06:42:56 PM PDT 24
Finished Jul 12 06:42:58 PM PDT 24
Peak memory 204096 kb
Host smart-4050603b-5e2f-4435-b399-f01b5a360d03
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177778374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem
_walk.177778374
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.910707103
Short name T1034
Test name
Test status
Simulation time 110648501 ps
CPU time 1.77 seconds
Started Jul 12 06:42:49 PM PDT 24
Finished Jul 12 06:42:53 PM PDT 24
Peak memory 207588 kb
Host smart-6658eb86-1f59-4c05-915e-d5a34b6a8fa9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910707103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sp
i_device_same_csr_outstanding.910707103
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2008423924
Short name T95
Test name
Test status
Simulation time 69301058 ps
CPU time 2.07 seconds
Started Jul 12 06:42:57 PM PDT 24
Finished Jul 12 06:43:02 PM PDT 24
Peak memory 216128 kb
Host smart-87297c5a-0f2e-4d65-8a82-7a689d6123ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008423924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.2
008423924
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3439567568
Short name T103
Test name
Test status
Simulation time 41779182 ps
CPU time 2.85 seconds
Started Jul 12 06:42:51 PM PDT 24
Finished Jul 12 06:42:57 PM PDT 24
Peak memory 217276 kb
Host smart-3eddcdba-0b99-42a5-9ad5-d4b13820d06c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439567568 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.3439567568
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.406416263
Short name T1077
Test name
Test status
Simulation time 76229708 ps
CPU time 2.62 seconds
Started Jul 12 06:43:02 PM PDT 24
Finished Jul 12 06:43:08 PM PDT 24
Peak memory 215656 kb
Host smart-71cae7d1-df8e-433e-bc43-96d065bc0c03
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406416263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.406416263
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2339079025
Short name T1073
Test name
Test status
Simulation time 20961304 ps
CPU time 0.71 seconds
Started Jul 12 06:42:55 PM PDT 24
Finished Jul 12 06:42:58 PM PDT 24
Peak memory 204612 kb
Host smart-17122e5c-70da-45bb-b09e-5e33c4a60982
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339079025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
2339079025
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.152877779
Short name T1094
Test name
Test status
Simulation time 807147719 ps
CPU time 4.38 seconds
Started Jul 12 06:42:56 PM PDT 24
Finished Jul 12 06:43:04 PM PDT 24
Peak memory 215700 kb
Host smart-4e516895-8b0b-4bb5-8bb5-7c9e0b012a96
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152877779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.s
pi_device_same_csr_outstanding.152877779
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.514872497
Short name T1087
Test name
Test status
Simulation time 53875596 ps
CPU time 1.71 seconds
Started Jul 12 06:42:53 PM PDT 24
Finished Jul 12 06:42:57 PM PDT 24
Peak memory 216748 kb
Host smart-2fd3263f-e1ae-494d-8ec1-f0806e419e32
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514872497 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.514872497
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.762832210
Short name T154
Test name
Test status
Simulation time 172135763 ps
CPU time 2.22 seconds
Started Jul 12 06:42:53 PM PDT 24
Finished Jul 12 06:42:58 PM PDT 24
Peak memory 215748 kb
Host smart-08b262b5-a5e6-428e-b716-b1c86d7cc5bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762832210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.762832210
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.3885895663
Short name T1065
Test name
Test status
Simulation time 12728362 ps
CPU time 0.72 seconds
Started Jul 12 06:43:06 PM PDT 24
Finished Jul 12 06:43:11 PM PDT 24
Peak memory 204600 kb
Host smart-7af40dc3-9be3-4ca3-8728-ce55f6679681
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885895663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
3885895663
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3073278759
Short name T1056
Test name
Test status
Simulation time 74488311 ps
CPU time 2.74 seconds
Started Jul 12 06:42:53 PM PDT 24
Finished Jul 12 06:42:58 PM PDT 24
Peak memory 215700 kb
Host smart-98461979-405a-4307-87f3-46e28f3b9b95
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073278759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.3073278759
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2696882629
Short name T1089
Test name
Test status
Simulation time 995068466 ps
CPU time 21.15 seconds
Started Jul 12 06:42:55 PM PDT 24
Finished Jul 12 06:43:18 PM PDT 24
Peak memory 215540 kb
Host smart-a5efcc87-21bb-4a75-a407-3544d87b89a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696882629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.2696882629
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.282358590
Short name T108
Test name
Test status
Simulation time 227668563 ps
CPU time 1.84 seconds
Started Jul 12 06:43:08 PM PDT 24
Finished Jul 12 06:43:14 PM PDT 24
Peak memory 215880 kb
Host smart-62fad03e-cc74-4595-a4c9-f1089945bd0d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282358590 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.282358590
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.957526903
Short name T1080
Test name
Test status
Simulation time 82540446 ps
CPU time 1.96 seconds
Started Jul 12 06:43:08 PM PDT 24
Finished Jul 12 06:43:15 PM PDT 24
Peak memory 215716 kb
Host smart-7713cd5d-9678-4efe-9865-b22ee33b8f14
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957526903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.957526903
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3266029012
Short name T1062
Test name
Test status
Simulation time 49135288 ps
CPU time 0.74 seconds
Started Jul 12 06:42:54 PM PDT 24
Finished Jul 12 06:42:57 PM PDT 24
Peak memory 204280 kb
Host smart-198b4b38-b433-4c1b-987f-d42025e344b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266029012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
3266029012
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3710099442
Short name T1086
Test name
Test status
Simulation time 578028726 ps
CPU time 2.99 seconds
Started Jul 12 06:42:55 PM PDT 24
Finished Jul 12 06:43:00 PM PDT 24
Peak memory 215560 kb
Host smart-a1334b28-b45a-4225-ba44-c48de36dfb48
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710099442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.3710099442
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.4027476425
Short name T99
Test name
Test status
Simulation time 63059511 ps
CPU time 1.82 seconds
Started Jul 12 06:43:05 PM PDT 24
Finished Jul 12 06:43:11 PM PDT 24
Peak memory 216036 kb
Host smart-dc5e0767-6b0b-420e-a1f1-0e8134bc8b26
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027476425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
4027476425
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1294521834
Short name T1059
Test name
Test status
Simulation time 1141023077 ps
CPU time 7.5 seconds
Started Jul 12 06:42:54 PM PDT 24
Finished Jul 12 06:43:04 PM PDT 24
Peak memory 216224 kb
Host smart-4f201fef-76ac-42fd-aafc-243eb64787d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294521834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.1294521834
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.3919231193
Short name T106
Test name
Test status
Simulation time 573326358 ps
CPU time 1.83 seconds
Started Jul 12 06:43:03 PM PDT 24
Finished Jul 12 06:43:08 PM PDT 24
Peak memory 215780 kb
Host smart-8bbc86fb-d9ab-4e0d-996e-36f3583e95de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919231193 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.3919231193
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.776460853
Short name T1108
Test name
Test status
Simulation time 147378066 ps
CPU time 2.68 seconds
Started Jul 12 06:42:54 PM PDT 24
Finished Jul 12 06:43:04 PM PDT 24
Peak memory 215592 kb
Host smart-00101e9f-d6ac-400b-92d9-6d7db0dd0ad6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776460853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.776460853
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.438266583
Short name T1071
Test name
Test status
Simulation time 29701856 ps
CPU time 0.74 seconds
Started Jul 12 06:43:07 PM PDT 24
Finished Jul 12 06:43:12 PM PDT 24
Peak memory 204208 kb
Host smart-c4370b80-68ad-47c4-9213-fed5eebbd964
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438266583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.438266583
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3326648293
Short name T1053
Test name
Test status
Simulation time 219193963 ps
CPU time 3.74 seconds
Started Jul 12 06:42:53 PM PDT 24
Finished Jul 12 06:43:00 PM PDT 24
Peak memory 207608 kb
Host smart-c5fb335e-eb02-4122-a289-d7e6f24cede0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326648293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.3326648293
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.990245981
Short name T1079
Test name
Test status
Simulation time 73167223 ps
CPU time 4.73 seconds
Started Jul 12 06:42:56 PM PDT 24
Finished Jul 12 06:43:03 PM PDT 24
Peak memory 215992 kb
Host smart-5e0ac64c-0acc-4c56-ba51-442e828f0cb4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990245981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.990245981
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.2014798669
Short name T1083
Test name
Test status
Simulation time 2855170081 ps
CPU time 14.55 seconds
Started Jul 12 06:43:02 PM PDT 24
Finished Jul 12 06:43:20 PM PDT 24
Peak memory 217244 kb
Host smart-773fc0b6-d95c-4b64-9fff-bba498597d66
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014798669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.2014798669
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1706940074
Short name T1066
Test name
Test status
Simulation time 213497263 ps
CPU time 1.81 seconds
Started Jul 12 06:42:58 PM PDT 24
Finished Jul 12 06:43:03 PM PDT 24
Peak memory 215748 kb
Host smart-eeae06e4-d35a-41f6-bd15-7d2adf5af064
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706940074 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.1706940074
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.849789646
Short name T1088
Test name
Test status
Simulation time 46217603 ps
CPU time 1.55 seconds
Started Jul 12 06:42:58 PM PDT 24
Finished Jul 12 06:43:03 PM PDT 24
Peak memory 215688 kb
Host smart-91441b18-7410-4467-8a5b-4af9e72a6d53
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849789646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.849789646
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.1468876813
Short name T1096
Test name
Test status
Simulation time 16048148 ps
CPU time 0.73 seconds
Started Jul 12 06:43:06 PM PDT 24
Finished Jul 12 06:43:15 PM PDT 24
Peak memory 204276 kb
Host smart-24e39dd9-1ddd-4264-8a37-4990f14cc1aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468876813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
1468876813
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.938180935
Short name T1099
Test name
Test status
Simulation time 125960297 ps
CPU time 2.92 seconds
Started Jul 12 06:43:02 PM PDT 24
Finished Jul 12 06:43:08 PM PDT 24
Peak memory 215796 kb
Host smart-62139405-3200-431f-ba48-3630d083c6aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938180935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.s
pi_device_same_csr_outstanding.938180935
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.4268336626
Short name T1109
Test name
Test status
Simulation time 348438886 ps
CPU time 2.66 seconds
Started Jul 12 06:43:04 PM PDT 24
Finished Jul 12 06:43:11 PM PDT 24
Peak memory 216076 kb
Host smart-ff6bce5d-aafb-4d43-a947-07041b5c54ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268336626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
4268336626
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.179858368
Short name T1118
Test name
Test status
Simulation time 242761968 ps
CPU time 1.73 seconds
Started Jul 12 06:43:02 PM PDT 24
Finished Jul 12 06:43:08 PM PDT 24
Peak memory 215928 kb
Host smart-1d14df3c-e056-415c-8a87-47b9f2f1a5e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179858368 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.179858368
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.2412551314
Short name T112
Test name
Test status
Simulation time 129062239 ps
CPU time 1.97 seconds
Started Jul 12 06:43:07 PM PDT 24
Finished Jul 12 06:43:13 PM PDT 24
Peak memory 207532 kb
Host smart-50b563b3-403d-4e57-91c5-090130910240
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412551314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
2412551314
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3628545955
Short name T1102
Test name
Test status
Simulation time 48268959 ps
CPU time 0.73 seconds
Started Jul 12 06:43:00 PM PDT 24
Finished Jul 12 06:43:03 PM PDT 24
Peak memory 204316 kb
Host smart-34d7371c-1cf7-48d5-8192-331297356d49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628545955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
3628545955
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3707405597
Short name T1040
Test name
Test status
Simulation time 235071073 ps
CPU time 3.86 seconds
Started Jul 12 06:43:07 PM PDT 24
Finished Jul 12 06:43:15 PM PDT 24
Peak memory 215800 kb
Host smart-3634d8dd-e983-465e-8a69-ecc8259dd558
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707405597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.3707405597
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.244921344
Short name T96
Test name
Test status
Simulation time 78668912 ps
CPU time 4.66 seconds
Started Jul 12 06:43:00 PM PDT 24
Finished Jul 12 06:43:07 PM PDT 24
Peak memory 216012 kb
Host smart-f001f440-64b8-4e2b-9be0-7f3236fdd82b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244921344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.244921344
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3945206460
Short name T166
Test name
Test status
Simulation time 108676268 ps
CPU time 6.84 seconds
Started Jul 12 06:43:03 PM PDT 24
Finished Jul 12 06:43:13 PM PDT 24
Peak memory 215564 kb
Host smart-ddaf5dbd-ac55-42c2-8435-9d1daff7901b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945206460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.3945206460
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3756522895
Short name T62
Test name
Test status
Simulation time 298046281 ps
CPU time 2.87 seconds
Started Jul 12 06:43:08 PM PDT 24
Finished Jul 12 06:43:15 PM PDT 24
Peak memory 216840 kb
Host smart-8486e727-f112-47e5-888c-a9b129445857
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756522895 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.3756522895
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.3782890859
Short name T145
Test name
Test status
Simulation time 73194080 ps
CPU time 1.23 seconds
Started Jul 12 06:42:59 PM PDT 24
Finished Jul 12 06:43:03 PM PDT 24
Peak memory 207556 kb
Host smart-cb510abb-06f1-4595-be3d-d9645c9b4aa8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782890859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
3782890859
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3462481279
Short name T1098
Test name
Test status
Simulation time 37749802 ps
CPU time 0.74 seconds
Started Jul 12 06:43:02 PM PDT 24
Finished Jul 12 06:43:06 PM PDT 24
Peak memory 204600 kb
Host smart-0650c611-ebe8-4d80-bedd-03fcd6961ff6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462481279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
3462481279
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.2075310056
Short name T144
Test name
Test status
Simulation time 141876016 ps
CPU time 3.08 seconds
Started Jul 12 06:43:04 PM PDT 24
Finished Jul 12 06:43:11 PM PDT 24
Peak memory 215820 kb
Host smart-c1a98b48-c204-417f-9c5b-3b5ab1bd8d40
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075310056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.2075310056
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.727857155
Short name T1127
Test name
Test status
Simulation time 56585221 ps
CPU time 1.84 seconds
Started Jul 12 06:43:09 PM PDT 24
Finished Jul 12 06:43:15 PM PDT 24
Peak memory 215932 kb
Host smart-a2beb986-daf8-4ec2-b764-25d017b9df23
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727857155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.727857155
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1933399902
Short name T1128
Test name
Test status
Simulation time 257243904 ps
CPU time 6.73 seconds
Started Jul 12 06:43:05 PM PDT 24
Finished Jul 12 06:43:16 PM PDT 24
Peak memory 216040 kb
Host smart-1c8b40c1-111d-4297-82d9-6e762b6846ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933399902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.1933399902
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.4248565304
Short name T1097
Test name
Test status
Simulation time 56249741 ps
CPU time 1.67 seconds
Started Jul 12 06:43:05 PM PDT 24
Finished Jul 12 06:43:10 PM PDT 24
Peak memory 215784 kb
Host smart-64960cb0-1a39-487c-92ca-b53a655c5ad7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248565304 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.4248565304
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.2544009827
Short name T118
Test name
Test status
Simulation time 506923233 ps
CPU time 2.31 seconds
Started Jul 12 06:42:57 PM PDT 24
Finished Jul 12 06:43:02 PM PDT 24
Peak memory 215700 kb
Host smart-d057fbcc-a616-410d-8070-138bae596f6c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544009827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
2544009827
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.3745798719
Short name T1095
Test name
Test status
Simulation time 50753159 ps
CPU time 0.74 seconds
Started Jul 12 06:43:04 PM PDT 24
Finished Jul 12 06:43:08 PM PDT 24
Peak memory 204264 kb
Host smart-2131ed70-d507-46e7-bc7f-9163fb85aff0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745798719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
3745798719
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.842918025
Short name T141
Test name
Test status
Simulation time 547508061 ps
CPU time 3.02 seconds
Started Jul 12 06:43:07 PM PDT 24
Finished Jul 12 06:43:14 PM PDT 24
Peak memory 215648 kb
Host smart-4b600c52-3e30-4b78-8740-5f7c1d7f484a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842918025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.s
pi_device_same_csr_outstanding.842918025
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.2634846141
Short name T1129
Test name
Test status
Simulation time 269392627 ps
CPU time 3.51 seconds
Started Jul 12 06:42:56 PM PDT 24
Finished Jul 12 06:43:03 PM PDT 24
Peak memory 216032 kb
Host smart-bc3a2488-eb10-4edc-a161-f213adce277e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634846141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
2634846141
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.2313394371
Short name T163
Test name
Test status
Simulation time 311087308 ps
CPU time 5.93 seconds
Started Jul 12 06:43:06 PM PDT 24
Finished Jul 12 06:43:16 PM PDT 24
Peak memory 215748 kb
Host smart-e158b0af-401b-4da3-9e00-254af0b6a2bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313394371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.2313394371
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2508924389
Short name T88
Test name
Test status
Simulation time 88917854 ps
CPU time 1.89 seconds
Started Jul 12 06:42:57 PM PDT 24
Finished Jul 12 06:43:02 PM PDT 24
Peak memory 216784 kb
Host smart-2065ba2a-1c84-49cc-b3cc-29f003e801b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508924389 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.2508924389
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.962750175
Short name T1120
Test name
Test status
Simulation time 23959773 ps
CPU time 1.5 seconds
Started Jul 12 06:43:00 PM PDT 24
Finished Jul 12 06:43:04 PM PDT 24
Peak memory 215720 kb
Host smart-378f18bd-4966-4555-8e42-b7f39547cad1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962750175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.962750175
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.2488803433
Short name T1061
Test name
Test status
Simulation time 14461663 ps
CPU time 0.68 seconds
Started Jul 12 06:43:07 PM PDT 24
Finished Jul 12 06:43:12 PM PDT 24
Peak memory 204292 kb
Host smart-8b04a28c-87e1-4b5f-a9ea-7c15b515e97d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488803433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
2488803433
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2363688345
Short name T1069
Test name
Test status
Simulation time 951913875 ps
CPU time 3.89 seconds
Started Jul 12 06:43:04 PM PDT 24
Finished Jul 12 06:43:11 PM PDT 24
Peak memory 215872 kb
Host smart-ab44b183-1c28-4d30-a52c-7214cf0f2a3e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363688345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.2363688345
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.3264294300
Short name T164
Test name
Test status
Simulation time 768481099 ps
CPU time 7.76 seconds
Started Jul 12 06:43:08 PM PDT 24
Finished Jul 12 06:43:20 PM PDT 24
Peak memory 216796 kb
Host smart-609d556f-32ae-4e0d-8115-29d3b982b48e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264294300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.3264294300
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3577306258
Short name T1037
Test name
Test status
Simulation time 76450414 ps
CPU time 1.6 seconds
Started Jul 12 06:43:09 PM PDT 24
Finished Jul 12 06:43:15 PM PDT 24
Peak memory 215812 kb
Host smart-17996ab3-ea0b-4b9d-b1f3-44e35f73b860
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577306258 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.3577306258
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1144497310
Short name T1055
Test name
Test status
Simulation time 20610447 ps
CPU time 0.76 seconds
Started Jul 12 06:43:01 PM PDT 24
Finished Jul 12 06:43:05 PM PDT 24
Peak memory 204296 kb
Host smart-bc504fdc-9dbf-4ef1-8843-33f015557359
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144497310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
1144497310
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.3432802983
Short name T1110
Test name
Test status
Simulation time 224633194 ps
CPU time 3.7 seconds
Started Jul 12 06:43:02 PM PDT 24
Finished Jul 12 06:43:09 PM PDT 24
Peak memory 216184 kb
Host smart-07dbf16d-8de2-4dcf-bd31-824649847d9e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432802983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.3432802983
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2042135148
Short name T1057
Test name
Test status
Simulation time 42610680 ps
CPU time 1.65 seconds
Started Jul 12 06:42:59 PM PDT 24
Finished Jul 12 06:43:03 PM PDT 24
Peak memory 217028 kb
Host smart-f663d19d-aaf6-4d2a-a44e-b1259bb45c52
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042135148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
2042135148
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1802014911
Short name T161
Test name
Test status
Simulation time 601860542 ps
CPU time 18.61 seconds
Started Jul 12 06:43:07 PM PDT 24
Finished Jul 12 06:43:30 PM PDT 24
Peak memory 215856 kb
Host smart-a4fd34ea-1063-451b-9d8b-db9a0103c3d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802014911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.1802014911
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3779619391
Short name T1117
Test name
Test status
Simulation time 993522398 ps
CPU time 7.7 seconds
Started Jul 12 06:42:48 PM PDT 24
Finished Jul 12 06:42:58 PM PDT 24
Peak memory 207516 kb
Host smart-2e91e305-e613-4cc7-bc3f-17780e9a54ef
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779619391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.3779619391
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3865576535
Short name T120
Test name
Test status
Simulation time 7532019169 ps
CPU time 35.74 seconds
Started Jul 12 06:42:50 PM PDT 24
Finished Jul 12 06:43:28 PM PDT 24
Peak memory 207644 kb
Host smart-e159d8be-7de4-4dae-af0b-feb793f65093
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865576535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.3865576535
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2676270494
Short name T78
Test name
Test status
Simulation time 14942643 ps
CPU time 0.93 seconds
Started Jul 12 06:42:49 PM PDT 24
Finished Jul 12 06:42:52 PM PDT 24
Peak memory 207204 kb
Host smart-bd6b7b53-2839-4263-b6d6-a8eb40b9bb0a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676270494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.2676270494
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2472021782
Short name T104
Test name
Test status
Simulation time 188812554 ps
CPU time 3.69 seconds
Started Jul 12 06:42:49 PM PDT 24
Finished Jul 12 06:42:55 PM PDT 24
Peak memory 218604 kb
Host smart-95d98ac1-50f2-4d3e-b51c-24af571a1f9a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472021782 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.2472021782
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.237125140
Short name T122
Test name
Test status
Simulation time 309501865 ps
CPU time 2.15 seconds
Started Jul 12 06:42:51 PM PDT 24
Finished Jul 12 06:42:56 PM PDT 24
Peak memory 207520 kb
Host smart-8cff1ede-bb1c-4e46-93d9-2f5a6873691f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237125140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.237125140
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.4077693164
Short name T1123
Test name
Test status
Simulation time 21457104 ps
CPU time 0.68 seconds
Started Jul 12 06:42:52 PM PDT 24
Finished Jul 12 06:42:55 PM PDT 24
Peak memory 204616 kb
Host smart-610073a4-5269-408f-aba2-f02756980fc2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077693164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.4
077693164
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2628977885
Short name T115
Test name
Test status
Simulation time 244626241 ps
CPU time 2.37 seconds
Started Jul 12 06:42:48 PM PDT 24
Finished Jul 12 06:42:52 PM PDT 24
Peak memory 215744 kb
Host smart-8ceb1aab-33cb-4caa-8fe9-d152ee3e012b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628977885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.2628977885
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3585918156
Short name T1078
Test name
Test status
Simulation time 12833920 ps
CPU time 0.68 seconds
Started Jul 12 06:42:55 PM PDT 24
Finished Jul 12 06:42:58 PM PDT 24
Peak memory 204040 kb
Host smart-b510d189-c4e1-4807-b0e5-2666a162deb5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585918156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.3585918156
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.210462573
Short name T1022
Test name
Test status
Simulation time 1218619348 ps
CPU time 2.83 seconds
Started Jul 12 06:43:02 PM PDT 24
Finished Jul 12 06:43:08 PM PDT 24
Peak memory 215676 kb
Host smart-f907250e-1349-4702-8662-694b3615326b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210462573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sp
i_device_same_csr_outstanding.210462573
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1871236866
Short name T97
Test name
Test status
Simulation time 164064451 ps
CPU time 3.8 seconds
Started Jul 12 06:42:51 PM PDT 24
Finished Jul 12 06:42:57 PM PDT 24
Peak memory 215980 kb
Host smart-3e422639-25f4-4964-aea2-c1cc7f9161b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871236866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.1
871236866
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.3896018974
Short name T160
Test name
Test status
Simulation time 405690011 ps
CPU time 12.59 seconds
Started Jul 12 06:42:52 PM PDT 24
Finished Jul 12 06:43:07 PM PDT 24
Peak memory 215772 kb
Host smart-dd63ea60-e3d3-4d88-af8b-ac7c8907160a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896018974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.3896018974
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2384781516
Short name T1058
Test name
Test status
Simulation time 20575991 ps
CPU time 0.72 seconds
Started Jul 12 06:43:08 PM PDT 24
Finished Jul 12 06:43:13 PM PDT 24
Peak memory 204308 kb
Host smart-ff49d3fb-4f9a-48f0-8c04-fe519393c382
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384781516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
2384781516
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2973812508
Short name T1103
Test name
Test status
Simulation time 49057479 ps
CPU time 0.75 seconds
Started Jul 12 06:43:06 PM PDT 24
Finished Jul 12 06:43:11 PM PDT 24
Peak memory 204648 kb
Host smart-556992a9-b94c-4413-9f05-7ea570645014
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973812508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
2973812508
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3561130300
Short name T1060
Test name
Test status
Simulation time 34290192 ps
CPU time 0.71 seconds
Started Jul 12 06:43:09 PM PDT 24
Finished Jul 12 06:43:14 PM PDT 24
Peak memory 204284 kb
Host smart-e6b500d7-5c46-478d-acf5-21fb2d33df65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561130300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
3561130300
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1132690979
Short name T1032
Test name
Test status
Simulation time 31411874 ps
CPU time 0.68 seconds
Started Jul 12 06:43:00 PM PDT 24
Finished Jul 12 06:43:03 PM PDT 24
Peak memory 204308 kb
Host smart-7c19918e-f108-48bf-8554-97b797af59fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132690979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
1132690979
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.565275360
Short name T1036
Test name
Test status
Simulation time 35593389 ps
CPU time 0.72 seconds
Started Jul 12 06:42:58 PM PDT 24
Finished Jul 12 06:43:02 PM PDT 24
Peak memory 204300 kb
Host smart-fcdfc111-ba4a-46b9-a1ae-7e409e1121ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565275360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.565275360
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.379621639
Short name T1030
Test name
Test status
Simulation time 24123213 ps
CPU time 0.75 seconds
Started Jul 12 06:43:08 PM PDT 24
Finished Jul 12 06:43:13 PM PDT 24
Peak memory 204296 kb
Host smart-81c95301-b780-4746-ae2b-a665f423dcf0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379621639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.379621639
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2773446405
Short name T1020
Test name
Test status
Simulation time 77984990 ps
CPU time 0.73 seconds
Started Jul 12 06:43:09 PM PDT 24
Finished Jul 12 06:43:14 PM PDT 24
Peak memory 204268 kb
Host smart-e3261f93-8376-43fc-b7db-6cbdb0373733
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773446405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
2773446405
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.2981523295
Short name T1029
Test name
Test status
Simulation time 11204971 ps
CPU time 0.71 seconds
Started Jul 12 06:43:02 PM PDT 24
Finished Jul 12 06:43:06 PM PDT 24
Peak memory 204304 kb
Host smart-f70a5884-8d79-425e-97b4-0ac722dec15a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981523295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
2981523295
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1959515117
Short name T1027
Test name
Test status
Simulation time 68426493 ps
CPU time 0.7 seconds
Started Jul 12 06:43:06 PM PDT 24
Finished Jul 12 06:43:10 PM PDT 24
Peak memory 204300 kb
Host smart-fb813d1e-cac7-4103-9767-71a7aee6de3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959515117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
1959515117
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3229807132
Short name T1130
Test name
Test status
Simulation time 14686362 ps
CPU time 0.73 seconds
Started Jul 12 06:43:03 PM PDT 24
Finished Jul 12 06:43:07 PM PDT 24
Peak memory 204300 kb
Host smart-5f065ca6-efd3-42fb-af8c-f80b17315a97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229807132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
3229807132
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1660200470
Short name T1064
Test name
Test status
Simulation time 330494582 ps
CPU time 8.78 seconds
Started Jul 12 06:42:51 PM PDT 24
Finished Jul 12 06:43:03 PM PDT 24
Peak memory 215628 kb
Host smart-d484db2f-3784-437c-b4da-420c9dd398b3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660200470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.1660200470
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.690535364
Short name T1115
Test name
Test status
Simulation time 782206437 ps
CPU time 12.41 seconds
Started Jul 12 06:43:04 PM PDT 24
Finished Jul 12 06:43:20 PM PDT 24
Peak memory 215660 kb
Host smart-09e831e1-07b1-4043-9fb8-4dd0241fb23c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690535364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_bit_bash.690535364
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.4138054006
Short name T77
Test name
Test status
Simulation time 48400800 ps
CPU time 0.93 seconds
Started Jul 12 06:42:49 PM PDT 24
Finished Jul 12 06:42:52 PM PDT 24
Peak memory 207220 kb
Host smart-cd08eabe-9705-4274-a0a1-1234185f4266
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138054006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.4138054006
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.393532816
Short name T1131
Test name
Test status
Simulation time 305670011 ps
CPU time 2.99 seconds
Started Jul 12 06:42:50 PM PDT 24
Finished Jul 12 06:42:55 PM PDT 24
Peak memory 216856 kb
Host smart-f151f357-13c2-423e-8a6c-2d7adaf4aa54
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393532816 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.393532816
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1920000417
Short name T1105
Test name
Test status
Simulation time 133503208 ps
CPU time 1.9 seconds
Started Jul 12 06:42:43 PM PDT 24
Finished Jul 12 06:42:47 PM PDT 24
Peak memory 215668 kb
Host smart-539eb2b7-9e03-4931-b71b-90773304ff4a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920000417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.1
920000417
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3478333142
Short name T1101
Test name
Test status
Simulation time 13058387 ps
CPU time 0.9 seconds
Started Jul 12 06:42:56 PM PDT 24
Finished Jul 12 06:42:59 PM PDT 24
Peak memory 204432 kb
Host smart-ce7d5d72-e8be-4165-8d0b-f3dc438dd68e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478333142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.3
478333142
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.112097683
Short name T1093
Test name
Test status
Simulation time 73522200 ps
CPU time 1.75 seconds
Started Jul 12 06:43:06 PM PDT 24
Finished Jul 12 06:43:12 PM PDT 24
Peak memory 215768 kb
Host smart-17d3feeb-7061-4fe4-af53-1dc6f12a8986
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112097683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_
device_mem_partial_access.112097683
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.3590375354
Short name T1031
Test name
Test status
Simulation time 17618806 ps
CPU time 0.66 seconds
Started Jul 12 06:42:47 PM PDT 24
Finished Jul 12 06:42:48 PM PDT 24
Peak memory 204092 kb
Host smart-8a5fdade-62dc-4f3f-905b-4d23b917b952
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590375354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.3590375354
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1145510956
Short name T1046
Test name
Test status
Simulation time 29728024 ps
CPU time 1.71 seconds
Started Jul 12 06:42:51 PM PDT 24
Finished Jul 12 06:42:56 PM PDT 24
Peak memory 215688 kb
Host smart-928caee0-d3ca-4f74-911a-812b42fcefa8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145510956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.1145510956
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.988055571
Short name T1047
Test name
Test status
Simulation time 82678982 ps
CPU time 1.67 seconds
Started Jul 12 06:42:57 PM PDT 24
Finished Jul 12 06:43:02 PM PDT 24
Peak memory 216080 kb
Host smart-39afeb73-c035-422b-bb6c-bc0c6eb15c9d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988055571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.988055571
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.603649184
Short name T1104
Test name
Test status
Simulation time 289485840 ps
CPU time 18.41 seconds
Started Jul 12 06:43:03 PM PDT 24
Finished Jul 12 06:43:24 PM PDT 24
Peak memory 215640 kb
Host smart-4e0b8ff1-7298-4ad3-af5f-7b0fcaa68caa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603649184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_
tl_intg_err.603649184
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2720813044
Short name T1043
Test name
Test status
Simulation time 18498116 ps
CPU time 0.7 seconds
Started Jul 12 06:42:58 PM PDT 24
Finished Jul 12 06:43:02 PM PDT 24
Peak memory 204308 kb
Host smart-385a30e1-7468-4986-addf-7d9aa2005cd1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720813044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
2720813044
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3891218825
Short name T1018
Test name
Test status
Simulation time 24461840 ps
CPU time 0.76 seconds
Started Jul 12 06:43:03 PM PDT 24
Finished Jul 12 06:43:07 PM PDT 24
Peak memory 204280 kb
Host smart-95fa1684-49fc-4026-9529-d2f5dcc27b0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891218825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
3891218825
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.145377018
Short name T1048
Test name
Test status
Simulation time 58759350 ps
CPU time 0.76 seconds
Started Jul 12 06:43:09 PM PDT 24
Finished Jul 12 06:43:14 PM PDT 24
Peak memory 204580 kb
Host smart-a062a1fd-fd06-4523-b3fe-9bf1f7aedc4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145377018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.145377018
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.3533617174
Short name T1074
Test name
Test status
Simulation time 37692180 ps
CPU time 0.73 seconds
Started Jul 12 06:42:58 PM PDT 24
Finished Jul 12 06:43:02 PM PDT 24
Peak memory 204624 kb
Host smart-41543886-8404-4a74-b0c0-78a7a87a327d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533617174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
3533617174
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.4227256929
Short name T1035
Test name
Test status
Simulation time 48135541 ps
CPU time 0.83 seconds
Started Jul 12 06:43:07 PM PDT 24
Finished Jul 12 06:43:13 PM PDT 24
Peak memory 204624 kb
Host smart-a50f5357-c65a-43f3-a6cb-1ef682fc7b03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227256929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
4227256929
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1968475726
Short name T1081
Test name
Test status
Simulation time 15333314 ps
CPU time 0.7 seconds
Started Jul 12 06:43:07 PM PDT 24
Finished Jul 12 06:43:12 PM PDT 24
Peak memory 204284 kb
Host smart-b2f355d9-0c1a-47c9-8c72-7562b07e7e26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968475726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
1968475726
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.3212249369
Short name T1045
Test name
Test status
Simulation time 15399447 ps
CPU time 0.76 seconds
Started Jul 12 06:42:58 PM PDT 24
Finished Jul 12 06:43:02 PM PDT 24
Peak memory 204272 kb
Host smart-b011096e-30b6-4203-892d-a4b36d714834
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212249369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
3212249369
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.2055497958
Short name T1050
Test name
Test status
Simulation time 76889949 ps
CPU time 0.8 seconds
Started Jul 12 06:43:05 PM PDT 24
Finished Jul 12 06:43:09 PM PDT 24
Peak memory 204292 kb
Host smart-d6537a65-441d-4a63-b0eb-781cdcdd604f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055497958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
2055497958
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.968138477
Short name T1113
Test name
Test status
Simulation time 55639182 ps
CPU time 0.76 seconds
Started Jul 12 06:42:59 PM PDT 24
Finished Jul 12 06:43:02 PM PDT 24
Peak memory 204636 kb
Host smart-bfe55fb3-5f04-4675-a136-d5bd6c003e12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968138477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.968138477
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.2809777914
Short name T1033
Test name
Test status
Simulation time 22517435 ps
CPU time 0.7 seconds
Started Jul 12 06:43:13 PM PDT 24
Finished Jul 12 06:43:16 PM PDT 24
Peak memory 204296 kb
Host smart-f0005f9f-4737-4eb7-b9ef-ff4dfd6f29bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809777914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
2809777914
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3674698240
Short name T124
Test name
Test status
Simulation time 2390573404 ps
CPU time 24.02 seconds
Started Jul 12 06:43:01 PM PDT 24
Finished Jul 12 06:43:28 PM PDT 24
Peak memory 215788 kb
Host smart-1e0939f2-7f10-43f6-9522-7259acef48af
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674698240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.3674698240
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1693916215
Short name T117
Test name
Test status
Simulation time 1405972811 ps
CPU time 22.39 seconds
Started Jul 12 06:43:06 PM PDT 24
Finished Jul 12 06:43:32 PM PDT 24
Peak memory 207456 kb
Host smart-6da01174-1904-4923-8b37-c1f6cf139cc7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693916215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.1693916215
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2252125448
Short name T79
Test name
Test status
Simulation time 320670544 ps
CPU time 1 seconds
Started Jul 12 06:42:48 PM PDT 24
Finished Jul 12 06:42:51 PM PDT 24
Peak memory 207248 kb
Host smart-fa25b1ed-0e57-4f01-90e7-c38895d0e4dd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252125448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.2252125448
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.566697260
Short name T1044
Test name
Test status
Simulation time 40339563 ps
CPU time 2.98 seconds
Started Jul 12 06:43:02 PM PDT 24
Finished Jul 12 06:43:08 PM PDT 24
Peak memory 218452 kb
Host smart-fb688357-9cfe-4daf-98bf-a21c36845315
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566697260 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.566697260
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1260631494
Short name T1072
Test name
Test status
Simulation time 73149138 ps
CPU time 2.47 seconds
Started Jul 12 06:42:52 PM PDT 24
Finished Jul 12 06:42:56 PM PDT 24
Peak memory 215640 kb
Host smart-73afad5c-157c-4f8d-b899-d80b4b27d1da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260631494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.1
260631494
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3258683663
Short name T1021
Test name
Test status
Simulation time 15279217 ps
CPU time 0.72 seconds
Started Jul 12 06:42:51 PM PDT 24
Finished Jul 12 06:42:54 PM PDT 24
Peak memory 204300 kb
Host smart-5bc06964-cb88-4a63-8bf3-48e1dec7243e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258683663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.3
258683663
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.791599631
Short name T1070
Test name
Test status
Simulation time 122731310 ps
CPU time 1.78 seconds
Started Jul 12 06:42:48 PM PDT 24
Finished Jul 12 06:42:51 PM PDT 24
Peak memory 215708 kb
Host smart-a69b3146-c2a1-46a3-8cb3-7221ee266451
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791599631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_
device_mem_partial_access.791599631
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.4179982663
Short name T1041
Test name
Test status
Simulation time 13564620 ps
CPU time 0.69 seconds
Started Jul 12 06:43:02 PM PDT 24
Finished Jul 12 06:43:07 PM PDT 24
Peak memory 204096 kb
Host smart-ed4b090d-c472-490e-8dad-6a04cb495593
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179982663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.4179982663
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1471220183
Short name T1091
Test name
Test status
Simulation time 106582652 ps
CPU time 2.86 seconds
Started Jul 12 06:42:58 PM PDT 24
Finished Jul 12 06:43:05 PM PDT 24
Peak memory 215764 kb
Host smart-c46b5f2d-d508-45f4-ba02-37697d3c0f03
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471220183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.1471220183
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2695475817
Short name T63
Test name
Test status
Simulation time 138589118 ps
CPU time 3.3 seconds
Started Jul 12 06:42:48 PM PDT 24
Finished Jul 12 06:42:54 PM PDT 24
Peak memory 216000 kb
Host smart-c9d2f6a8-1354-4833-852c-c4e71dcaa1d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695475817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.2
695475817
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.1267423204
Short name T1124
Test name
Test status
Simulation time 1697465161 ps
CPU time 22.28 seconds
Started Jul 12 06:42:48 PM PDT 24
Finished Jul 12 06:43:12 PM PDT 24
Peak memory 223924 kb
Host smart-753c38bd-ec31-4a3e-a8ec-e6e709bc7c67
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267423204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.1267423204
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2974935707
Short name T1019
Test name
Test status
Simulation time 78812534 ps
CPU time 0.75 seconds
Started Jul 12 06:43:15 PM PDT 24
Finished Jul 12 06:43:18 PM PDT 24
Peak memory 204304 kb
Host smart-e1a3198f-b77c-4bdc-80be-3382183cf3a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974935707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
2974935707
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.327603310
Short name T1024
Test name
Test status
Simulation time 41101368 ps
CPU time 0.74 seconds
Started Jul 12 06:43:07 PM PDT 24
Finished Jul 12 06:43:12 PM PDT 24
Peak memory 204292 kb
Host smart-22bc6a94-1abe-4505-83c1-baab761e3329
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327603310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.327603310
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.2274392746
Short name T1106
Test name
Test status
Simulation time 40701602 ps
CPU time 0.7 seconds
Started Jul 12 06:43:27 PM PDT 24
Finished Jul 12 06:43:29 PM PDT 24
Peak memory 204324 kb
Host smart-e15fec60-d1f0-44b0-b1aa-fbde2ba1cabd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274392746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
2274392746
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.3905473190
Short name T1025
Test name
Test status
Simulation time 37643012 ps
CPU time 0.68 seconds
Started Jul 12 06:43:03 PM PDT 24
Finished Jul 12 06:43:07 PM PDT 24
Peak memory 204224 kb
Host smart-4a669b88-2d18-4be0-949f-42b716860f69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905473190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
3905473190
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.549764512
Short name T1116
Test name
Test status
Simulation time 47762294 ps
CPU time 0.72 seconds
Started Jul 12 06:43:20 PM PDT 24
Finished Jul 12 06:43:21 PM PDT 24
Peak memory 204296 kb
Host smart-a1755bb8-45af-453d-a2b6-29627560dba6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549764512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.549764512
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3908147072
Short name T1107
Test name
Test status
Simulation time 23854294 ps
CPU time 0.71 seconds
Started Jul 12 06:43:09 PM PDT 24
Finished Jul 12 06:43:14 PM PDT 24
Peak memory 204288 kb
Host smart-d0c7b7e7-676c-4231-9dc4-5de18a5bc426
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908147072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
3908147072
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1943574327
Short name T1039
Test name
Test status
Simulation time 13646371 ps
CPU time 0.77 seconds
Started Jul 12 06:43:24 PM PDT 24
Finished Jul 12 06:43:26 PM PDT 24
Peak memory 204604 kb
Host smart-4c7193d8-b89c-4350-9a38-fb3f8549f615
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943574327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
1943574327
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.932502830
Short name T1126
Test name
Test status
Simulation time 18497608 ps
CPU time 0.78 seconds
Started Jul 12 06:43:04 PM PDT 24
Finished Jul 12 06:43:08 PM PDT 24
Peak memory 204572 kb
Host smart-aa037233-a05e-4a52-8869-7651947d3d31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932502830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.932502830
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2837149026
Short name T1122
Test name
Test status
Simulation time 23299799 ps
CPU time 0.75 seconds
Started Jul 12 06:43:11 PM PDT 24
Finished Jul 12 06:43:15 PM PDT 24
Peak memory 204280 kb
Host smart-100c98ec-67b7-4999-99fc-26b0ffec1be1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837149026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
2837149026
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.3192827223
Short name T1112
Test name
Test status
Simulation time 42119788 ps
CPU time 0.72 seconds
Started Jul 12 06:43:24 PM PDT 24
Finished Jul 12 06:43:26 PM PDT 24
Peak memory 204312 kb
Host smart-d5acb2e1-032d-46aa-a1f1-321cc1ce578c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192827223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
3192827223
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1116410176
Short name T1042
Test name
Test status
Simulation time 195278487 ps
CPU time 2.88 seconds
Started Jul 12 06:42:49 PM PDT 24
Finished Jul 12 06:42:54 PM PDT 24
Peak memory 217808 kb
Host smart-990ebe2d-30bb-498b-9f0d-6a0fda4c9ccd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116410176 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.1116410176
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1375550000
Short name T114
Test name
Test status
Simulation time 35804260 ps
CPU time 2.3 seconds
Started Jul 12 06:43:02 PM PDT 24
Finished Jul 12 06:43:08 PM PDT 24
Peak memory 215656 kb
Host smart-5a7063bc-c15c-478b-81f5-018b7eb673bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375550000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.1
375550000
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.2620435827
Short name T1026
Test name
Test status
Simulation time 25326258 ps
CPU time 0.73 seconds
Started Jul 12 06:42:50 PM PDT 24
Finished Jul 12 06:42:53 PM PDT 24
Peak memory 204288 kb
Host smart-d7cb64de-05b7-475a-b5c4-76ec37eba8b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620435827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.2
620435827
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1915083585
Short name T139
Test name
Test status
Simulation time 757251886 ps
CPU time 3.04 seconds
Started Jul 12 06:42:45 PM PDT 24
Finished Jul 12 06:42:49 PM PDT 24
Peak memory 215720 kb
Host smart-de9e5109-caf3-4f11-9557-53c78e415ee1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915083585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.1915083585
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.961019333
Short name T1090
Test name
Test status
Simulation time 178045743 ps
CPU time 2.66 seconds
Started Jul 12 06:42:49 PM PDT 24
Finished Jul 12 06:42:54 PM PDT 24
Peak memory 216004 kb
Host smart-55df8660-4f9b-4e1f-9042-504765cbf432
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961019333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.961019333
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.4215581645
Short name T1075
Test name
Test status
Simulation time 691618470 ps
CPU time 16.2 seconds
Started Jul 12 06:43:03 PM PDT 24
Finished Jul 12 06:43:23 PM PDT 24
Peak memory 223948 kb
Host smart-a88b5d32-5f00-4755-886b-5381e53f902e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215581645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.4215581645
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2669356427
Short name T105
Test name
Test status
Simulation time 38444716 ps
CPU time 2.51 seconds
Started Jul 12 06:42:46 PM PDT 24
Finished Jul 12 06:42:50 PM PDT 24
Peak memory 217448 kb
Host smart-dbe25295-f8ab-4981-9507-c1841b972ce2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669356427 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.2669356427
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2373673377
Short name T1092
Test name
Test status
Simulation time 113085736 ps
CPU time 1.85 seconds
Started Jul 12 06:42:51 PM PDT 24
Finished Jul 12 06:42:56 PM PDT 24
Peak memory 207420 kb
Host smart-b1b6b576-fd74-462d-a4f6-64a505d0fb3b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373673377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.2
373673377
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.3498392127
Short name T1076
Test name
Test status
Simulation time 11060873 ps
CPU time 0.73 seconds
Started Jul 12 06:43:00 PM PDT 24
Finished Jul 12 06:43:04 PM PDT 24
Peak memory 204252 kb
Host smart-a5f62550-d943-40ee-8c52-a6fd50607484
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498392127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.3
498392127
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1040188905
Short name T138
Test name
Test status
Simulation time 215591301 ps
CPU time 4.17 seconds
Started Jul 12 06:42:58 PM PDT 24
Finished Jul 12 06:43:06 PM PDT 24
Peak memory 215680 kb
Host smart-ab9233b8-2d9a-4740-891c-1ef33a49f1c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040188905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.1040188905
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2991616193
Short name T1084
Test name
Test status
Simulation time 241936758 ps
CPU time 3.39 seconds
Started Jul 12 06:42:48 PM PDT 24
Finished Jul 12 06:42:53 PM PDT 24
Peak memory 216032 kb
Host smart-f795788f-af85-4386-8240-474e8a1580cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991616193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.2
991616193
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2727193255
Short name T158
Test name
Test status
Simulation time 107998058 ps
CPU time 6.63 seconds
Started Jul 12 06:42:51 PM PDT 24
Finished Jul 12 06:43:05 PM PDT 24
Peak memory 215712 kb
Host smart-b2c37a3a-c438-4140-8312-22680c802472
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727193255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.2727193255
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.231517204
Short name T143
Test name
Test status
Simulation time 761909291 ps
CPU time 2.76 seconds
Started Jul 12 06:43:00 PM PDT 24
Finished Jul 12 06:43:06 PM PDT 24
Peak memory 218656 kb
Host smart-e5ed19fb-f969-4d9e-99d5-f9f713494bc0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231517204 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.231517204
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1528668502
Short name T1125
Test name
Test status
Simulation time 45271829 ps
CPU time 1.85 seconds
Started Jul 12 06:42:59 PM PDT 24
Finished Jul 12 06:43:04 PM PDT 24
Peak memory 215728 kb
Host smart-910ac7e9-11a9-41cd-86fc-04c6284c9159
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528668502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.1
528668502
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.2401215546
Short name T1063
Test name
Test status
Simulation time 18024380 ps
CPU time 0.78 seconds
Started Jul 12 06:42:47 PM PDT 24
Finished Jul 12 06:42:50 PM PDT 24
Peak memory 204248 kb
Host smart-3fb901a1-b08e-42ce-966a-102682d84569
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401215546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.2
401215546
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.822880118
Short name T142
Test name
Test status
Simulation time 98247634 ps
CPU time 1.81 seconds
Started Jul 12 06:42:51 PM PDT 24
Finished Jul 12 06:42:55 PM PDT 24
Peak memory 215704 kb
Host smart-c5a42d80-917f-4c75-a900-b60747bfa9be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822880118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sp
i_device_same_csr_outstanding.822880118
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.4231430924
Short name T157
Test name
Test status
Simulation time 77447583 ps
CPU time 4.72 seconds
Started Jul 12 06:42:47 PM PDT 24
Finished Jul 12 06:42:53 PM PDT 24
Peak memory 216100 kb
Host smart-a6368e62-0935-4618-ad67-165866cf94ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231430924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.4
231430924
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.2844580994
Short name T89
Test name
Test status
Simulation time 605176752 ps
CPU time 18.59 seconds
Started Jul 12 06:43:00 PM PDT 24
Finished Jul 12 06:43:21 PM PDT 24
Peak memory 216076 kb
Host smart-7a738cda-dc49-41ee-ae95-b63bbe41adb3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844580994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.2844580994
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2930037265
Short name T1121
Test name
Test status
Simulation time 188231309 ps
CPU time 1.74 seconds
Started Jul 12 06:42:50 PM PDT 24
Finished Jul 12 06:42:54 PM PDT 24
Peak memory 215836 kb
Host smart-3b9ace63-e476-429c-9058-d7af7918b9c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930037265 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.2930037265
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1411915366
Short name T1111
Test name
Test status
Simulation time 95358819 ps
CPU time 1.68 seconds
Started Jul 12 06:42:49 PM PDT 24
Finished Jul 12 06:42:53 PM PDT 24
Peak memory 215616 kb
Host smart-2ecbaf67-3778-483f-a4b1-89681d733994
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411915366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.1
411915366
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3788926176
Short name T1119
Test name
Test status
Simulation time 42134538 ps
CPU time 0.83 seconds
Started Jul 12 06:42:47 PM PDT 24
Finished Jul 12 06:42:50 PM PDT 24
Peak memory 204628 kb
Host smart-2d8ceaa4-a8a0-476a-97f2-7f1c464e6176
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788926176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.3
788926176
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3213500667
Short name T1052
Test name
Test status
Simulation time 198764388 ps
CPU time 2.96 seconds
Started Jul 12 06:42:47 PM PDT 24
Finished Jul 12 06:42:51 PM PDT 24
Peak memory 215732 kb
Host smart-3aaec325-26aa-44e5-86fa-c29dc1af314a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213500667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.3213500667
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.345851545
Short name T102
Test name
Test status
Simulation time 192478650 ps
CPU time 3.12 seconds
Started Jul 12 06:42:52 PM PDT 24
Finished Jul 12 06:42:58 PM PDT 24
Peak memory 216300 kb
Host smart-f5ccbb50-99aa-42cc-b1bb-c1a05b28e6fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345851545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.345851545
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1581084737
Short name T165
Test name
Test status
Simulation time 1156217939 ps
CPU time 17.67 seconds
Started Jul 12 06:42:48 PM PDT 24
Finished Jul 12 06:43:07 PM PDT 24
Peak memory 223832 kb
Host smart-76131efa-711e-495c-abb5-3d4ed3fae4b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581084737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.1581084737
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1298647677
Short name T101
Test name
Test status
Simulation time 83599449 ps
CPU time 2.51 seconds
Started Jul 12 06:43:03 PM PDT 24
Finished Jul 12 06:43:09 PM PDT 24
Peak memory 217788 kb
Host smart-131a7da7-66e5-4d86-a0e0-6e4a1ec6c290
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298647677 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.1298647677
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.4163178130
Short name T119
Test name
Test status
Simulation time 75357792 ps
CPU time 2.48 seconds
Started Jul 12 06:42:53 PM PDT 24
Finished Jul 12 06:42:58 PM PDT 24
Peak memory 215620 kb
Host smart-81a3784b-1edc-4fc9-9f67-1308c6f8f568
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163178130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.4
163178130
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2842476745
Short name T1068
Test name
Test status
Simulation time 20498369 ps
CPU time 0.71 seconds
Started Jul 12 06:43:02 PM PDT 24
Finished Jul 12 06:43:06 PM PDT 24
Peak memory 204612 kb
Host smart-bb9257e4-f561-41af-9b4b-ddb3a1742a72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842476745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.2
842476745
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.564650383
Short name T140
Test name
Test status
Simulation time 83996275 ps
CPU time 2.1 seconds
Started Jul 12 06:42:53 PM PDT 24
Finished Jul 12 06:42:58 PM PDT 24
Peak memory 215816 kb
Host smart-f493a961-2019-4b04-af1f-5d9965c016ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564650383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sp
i_device_same_csr_outstanding.564650383
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.3666102561
Short name T98
Test name
Test status
Simulation time 315342595 ps
CPU time 2.19 seconds
Started Jul 12 06:42:59 PM PDT 24
Finished Jul 12 06:43:04 PM PDT 24
Peak memory 215984 kb
Host smart-73146063-0c17-471f-9a29-5f07525bca98
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666102561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.3
666102561
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1319087548
Short name T1114
Test name
Test status
Simulation time 1068267361 ps
CPU time 7.84 seconds
Started Jul 12 06:43:04 PM PDT 24
Finished Jul 12 06:43:15 PM PDT 24
Peak memory 215772 kb
Host smart-ff07b799-cd6d-4422-b20f-4282ce7d8526
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319087548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.1319087548
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.3786633795
Short name T379
Test name
Test status
Simulation time 89542257 ps
CPU time 2.87 seconds
Started Jul 12 06:30:42 PM PDT 24
Finished Jul 12 06:30:46 PM PDT 24
Peak memory 232596 kb
Host smart-0887001c-424a-4010-88dd-b72a3d908cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786633795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.3786633795
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.2106776611
Short name T289
Test name
Test status
Simulation time 127370462 ps
CPU time 0.8 seconds
Started Jul 12 06:30:46 PM PDT 24
Finished Jul 12 06:30:48 PM PDT 24
Peak memory 206552 kb
Host smart-b6a3c250-224c-4714-9189-0e641e116916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106776611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.2106776611
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.1617520966
Short name T1
Test name
Test status
Simulation time 6012971793 ps
CPU time 41.58 seconds
Started Jul 12 06:30:45 PM PDT 24
Finished Jul 12 06:31:28 PM PDT 24
Peak memory 219324 kb
Host smart-330ab2b0-ddd4-41b8-b20f-6756f844e304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617520966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.1617520966
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.2958373560
Short name T16
Test name
Test status
Simulation time 19295277916 ps
CPU time 80.33 seconds
Started Jul 12 06:30:44 PM PDT 24
Finished Jul 12 06:32:06 PM PDT 24
Peak memory 262384 kb
Host smart-4671b1af-8804-4368-af86-d4b7a8308847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958373560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.2958373560
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.3033766268
Short name T168
Test name
Test status
Simulation time 3093884255 ps
CPU time 67.23 seconds
Started Jul 12 06:30:44 PM PDT 24
Finished Jul 12 06:31:53 PM PDT 24
Peak memory 261100 kb
Host smart-7cbf0fc4-d12e-4be3-ba17-1ff561bc0b77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033766268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds
.3033766268
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_intercept.3248164533
Short name T216
Test name
Test status
Simulation time 727273464 ps
CPU time 9.95 seconds
Started Jul 12 06:30:44 PM PDT 24
Finished Jul 12 06:30:55 PM PDT 24
Peak memory 232572 kb
Host smart-e4cd9ac8-5605-4240-8078-1d4847384c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248164533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.3248164533
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.473717161
Short name T127
Test name
Test status
Simulation time 14226176338 ps
CPU time 26.75 seconds
Started Jul 12 06:30:44 PM PDT 24
Finished Jul 12 06:31:13 PM PDT 24
Peak memory 232664 kb
Host smart-ec8ed459-9d39-4fb8-99bc-47407591a047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473717161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.473717161
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.1457523012
Short name T526
Test name
Test status
Simulation time 11554567590 ps
CPU time 9.88 seconds
Started Jul 12 06:30:41 PM PDT 24
Finished Jul 12 06:30:51 PM PDT 24
Peak memory 240924 kb
Host smart-c3dd1676-7c8e-47dd-8362-040845002207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457523012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.1457523012
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.1070883565
Short name T959
Test name
Test status
Simulation time 1942313841 ps
CPU time 8.39 seconds
Started Jul 12 06:30:42 PM PDT 24
Finished Jul 12 06:30:52 PM PDT 24
Peak memory 240512 kb
Host smart-c6e0ebfc-bf77-41e0-9234-1efc378faf04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070883565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.1070883565
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.3570015732
Short name T307
Test name
Test status
Simulation time 282382222 ps
CPU time 3.81 seconds
Started Jul 12 06:30:45 PM PDT 24
Finished Jul 12 06:30:50 PM PDT 24
Peak memory 219756 kb
Host smart-2661707d-183f-4dca-bab2-f8f721efcb04
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3570015732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.3570015732
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.2915055033
Short name T67
Test name
Test status
Simulation time 237408086 ps
CPU time 1.09 seconds
Started Jul 12 06:30:45 PM PDT 24
Finished Jul 12 06:30:47 PM PDT 24
Peak memory 235468 kb
Host smart-38bb31e9-5c1f-4580-acc8-fc990e2dac3e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915055033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.2915055033
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.1247802937
Short name T676
Test name
Test status
Simulation time 56480782665 ps
CPU time 318.1 seconds
Started Jul 12 06:30:44 PM PDT 24
Finished Jul 12 06:36:04 PM PDT 24
Peak memory 255480 kb
Host smart-bb5f304f-bf00-45cc-8944-8bd650eb8999
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247802937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.1247802937
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.1638846320
Short name T633
Test name
Test status
Simulation time 8438022579 ps
CPU time 38.37 seconds
Started Jul 12 06:30:44 PM PDT 24
Finished Jul 12 06:31:24 PM PDT 24
Peak memory 216340 kb
Host smart-dc9d9097-4cca-4f54-8835-82337d3657a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638846320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.1638846320
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.2559050929
Short name T466
Test name
Test status
Simulation time 29661933 ps
CPU time 0.72 seconds
Started Jul 12 06:30:43 PM PDT 24
Finished Jul 12 06:30:45 PM PDT 24
Peak memory 205660 kb
Host smart-99cc7665-3172-4f00-91b7-9803a0ce0391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559050929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.2559050929
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.1071947743
Short name T822
Test name
Test status
Simulation time 81355236 ps
CPU time 1.47 seconds
Started Jul 12 06:30:44 PM PDT 24
Finished Jul 12 06:30:46 PM PDT 24
Peak memory 216080 kb
Host smart-3474bef4-c7e7-42ee-a477-2ce59a72c17c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071947743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.1071947743
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.1723245929
Short name T483
Test name
Test status
Simulation time 233842322 ps
CPU time 0.96 seconds
Started Jul 12 06:30:42 PM PDT 24
Finished Jul 12 06:30:44 PM PDT 24
Peak memory 205908 kb
Host smart-fb271d2b-df8d-4e13-a2f7-9148b3d67a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723245929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.1723245929
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.1285907252
Short name T763
Test name
Test status
Simulation time 1713516087 ps
CPU time 5.41 seconds
Started Jul 12 06:30:46 PM PDT 24
Finished Jul 12 06:30:53 PM PDT 24
Peak memory 232564 kb
Host smart-66333829-f474-40fb-9a0c-77ace8cd7ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285907252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.1285907252
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.869207375
Short name T296
Test name
Test status
Simulation time 73419384 ps
CPU time 0.8 seconds
Started Jul 12 06:31:06 PM PDT 24
Finished Jul 12 06:31:07 PM PDT 24
Peak memory 205788 kb
Host smart-45cbf7ce-7e15-455b-bedc-9cef5b1fa726
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869207375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.869207375
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.3938677077
Short name T856
Test name
Test status
Simulation time 896061700 ps
CPU time 3.72 seconds
Started Jul 12 06:30:55 PM PDT 24
Finished Jul 12 06:31:00 PM PDT 24
Peak memory 224340 kb
Host smart-c009a21a-0cc3-496e-b171-5ea503242760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938677077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.3938677077
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.208782191
Short name T1007
Test name
Test status
Simulation time 56157767 ps
CPU time 0.78 seconds
Started Jul 12 06:30:43 PM PDT 24
Finished Jul 12 06:30:45 PM PDT 24
Peak memory 205792 kb
Host smart-4548a4c9-2569-4234-a3d3-d373c8bf6170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208782191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.208782191
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.274481983
Short name T397
Test name
Test status
Simulation time 54114373 ps
CPU time 0.76 seconds
Started Jul 12 06:30:56 PM PDT 24
Finished Jul 12 06:30:57 PM PDT 24
Peak memory 215732 kb
Host smart-6f37c415-027e-4ea9-8754-0451654e662f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274481983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.274481983
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.2819796269
Short name T370
Test name
Test status
Simulation time 74718801129 ps
CPU time 296.56 seconds
Started Jul 12 06:31:04 PM PDT 24
Finished Jul 12 06:36:02 PM PDT 24
Peak memory 257380 kb
Host smart-5a4c85f6-3dd0-4416-8797-b435c544e697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819796269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.2819796269
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.968984409
Short name T275
Test name
Test status
Simulation time 2526410104 ps
CPU time 20.69 seconds
Started Jul 12 06:31:02 PM PDT 24
Finished Jul 12 06:31:24 PM PDT 24
Peak memory 238456 kb
Host smart-238cb39e-9c5f-4a27-8e9f-9cc7acbbb230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968984409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle.
968984409
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.4253806774
Short name T728
Test name
Test status
Simulation time 220756333 ps
CPU time 6.26 seconds
Started Jul 12 06:30:51 PM PDT 24
Finished Jul 12 06:30:59 PM PDT 24
Peak memory 224372 kb
Host smart-04b1ee19-eccd-453d-a2d3-dc1289674ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253806774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.4253806774
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_intercept.3712935793
Short name T57
Test name
Test status
Simulation time 40513100 ps
CPU time 2.59 seconds
Started Jul 12 06:30:50 PM PDT 24
Finished Jul 12 06:30:54 PM PDT 24
Peak memory 227028 kb
Host smart-357a0e53-9008-40da-bd85-99af5a29c7bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712935793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.3712935793
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.1620298452
Short name T976
Test name
Test status
Simulation time 122350163465 ps
CPU time 111.33 seconds
Started Jul 12 06:30:51 PM PDT 24
Finished Jul 12 06:32:44 PM PDT 24
Peak memory 233784 kb
Host smart-2bc7b6ce-3edb-460f-8d20-18c18e1c222a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620298452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.1620298452
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.4108253521
Short name T837
Test name
Test status
Simulation time 474898218 ps
CPU time 7.08 seconds
Started Jul 12 06:30:51 PM PDT 24
Finished Jul 12 06:30:59 PM PDT 24
Peak memory 232532 kb
Host smart-d069241e-e2f2-49b6-a570-f43480544c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108253521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.4108253521
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.1056683742
Short name T670
Test name
Test status
Simulation time 74026592 ps
CPU time 2.25 seconds
Started Jul 12 06:30:51 PM PDT 24
Finished Jul 12 06:30:54 PM PDT 24
Peak memory 224412 kb
Host smart-5c8a1eec-d481-4cc0-adcb-bf1562ec66b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056683742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.1056683742
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.229219165
Short name T967
Test name
Test status
Simulation time 365842745 ps
CPU time 3.61 seconds
Started Jul 12 06:30:51 PM PDT 24
Finished Jul 12 06:30:56 PM PDT 24
Peak memory 220652 kb
Host smart-a2ebe523-62fa-4fcc-a334-f60b82bc137d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=229219165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_direc
t.229219165
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.3268729961
Short name T451
Test name
Test status
Simulation time 269479037 ps
CPU time 5.31 seconds
Started Jul 12 06:30:53 PM PDT 24
Finished Jul 12 06:30:59 PM PDT 24
Peak memory 219304 kb
Host smart-b63f4861-33f3-4401-8dde-6901cbb1b9e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268729961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.3268729961
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.4091206284
Short name T301
Test name
Test status
Simulation time 529653270 ps
CPU time 3.02 seconds
Started Jul 12 06:30:46 PM PDT 24
Finished Jul 12 06:30:50 PM PDT 24
Peak memory 216128 kb
Host smart-266c0850-28a3-40f1-8f34-70eb1c58358e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091206284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.4091206284
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.2022067464
Short name T971
Test name
Test status
Simulation time 56500171 ps
CPU time 1.39 seconds
Started Jul 12 06:30:51 PM PDT 24
Finished Jul 12 06:30:54 PM PDT 24
Peak memory 216144 kb
Host smart-b46ea438-abcb-448a-b54a-d71d83ff2cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022067464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.2022067464
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.780362224
Short name T443
Test name
Test status
Simulation time 42390782 ps
CPU time 0.82 seconds
Started Jul 12 06:30:52 PM PDT 24
Finished Jul 12 06:30:53 PM PDT 24
Peak memory 206336 kb
Host smart-e0e758f4-2d3a-451a-bd27-3c995e9f29e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780362224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.780362224
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.4264401095
Short name T109
Test name
Test status
Simulation time 9890616623 ps
CPU time 9.49 seconds
Started Jul 12 06:30:55 PM PDT 24
Finished Jul 12 06:31:06 PM PDT 24
Peak memory 224432 kb
Host smart-b86a78b7-3f22-49ce-b210-b5b0ceb39fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264401095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.4264401095
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.2875794667
Short name T1013
Test name
Test status
Simulation time 23263860 ps
CPU time 0.75 seconds
Started Jul 12 06:31:42 PM PDT 24
Finished Jul 12 06:31:44 PM PDT 24
Peak memory 205444 kb
Host smart-c290958d-96a5-434c-a751-7e48603b56b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875794667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
2875794667
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.3947038352
Short name T373
Test name
Test status
Simulation time 175805662 ps
CPU time 3.49 seconds
Started Jul 12 06:31:47 PM PDT 24
Finished Jul 12 06:31:52 PM PDT 24
Peak memory 224432 kb
Host smart-45526b2f-83bb-4324-9c92-2c8f2321e80d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947038352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.3947038352
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.3860753785
Short name T303
Test name
Test status
Simulation time 22193362 ps
CPU time 0.77 seconds
Started Jul 12 06:31:37 PM PDT 24
Finished Jul 12 06:31:39 PM PDT 24
Peak memory 206548 kb
Host smart-85974c0b-af3b-4b5f-b45e-c571a0539a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860753785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.3860753785
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.328078848
Short name T855
Test name
Test status
Simulation time 21021647151 ps
CPU time 155.76 seconds
Started Jul 12 06:31:47 PM PDT 24
Finished Jul 12 06:34:23 PM PDT 24
Peak memory 240948 kb
Host smart-558e3102-c237-46f6-a1cb-44f1a9d9e47b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328078848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.328078848
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.4024383601
Short name T772
Test name
Test status
Simulation time 9316564741 ps
CPU time 56.95 seconds
Started Jul 12 06:31:45 PM PDT 24
Finished Jul 12 06:32:43 PM PDT 24
Peak memory 249220 kb
Host smart-c290340b-4663-4669-b18e-fde73142d8aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024383601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.4024383601
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.949287084
Short name T998
Test name
Test status
Simulation time 4207222687 ps
CPU time 21.74 seconds
Started Jul 12 06:31:43 PM PDT 24
Finished Jul 12 06:32:06 PM PDT 24
Peak memory 237420 kb
Host smart-ea459467-551d-4e64-a396-d37fb6acaef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949287084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmds
.949287084
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.645167111
Short name T654
Test name
Test status
Simulation time 278643793 ps
CPU time 4.17 seconds
Started Jul 12 06:31:35 PM PDT 24
Finished Jul 12 06:31:40 PM PDT 24
Peak memory 232628 kb
Host smart-67d390b1-198e-4d77-a4bc-2842a41023d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645167111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.645167111
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.1537134455
Short name T839
Test name
Test status
Simulation time 1142311162 ps
CPU time 4.69 seconds
Started Jul 12 06:31:35 PM PDT 24
Finished Jul 12 06:31:41 PM PDT 24
Peak memory 224460 kb
Host smart-04a71416-30ae-4df9-8e48-62bebf32b2a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537134455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.1537134455
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.1155849192
Short name T260
Test name
Test status
Simulation time 17659845785 ps
CPU time 51.4 seconds
Started Jul 12 06:31:35 PM PDT 24
Finished Jul 12 06:32:27 PM PDT 24
Peak memory 233608 kb
Host smart-0b8bda7a-096f-4e54-b0c0-a9bd8db34b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155849192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.1155849192
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.525228558
Short name T1014
Test name
Test status
Simulation time 36498332 ps
CPU time 2.62 seconds
Started Jul 12 06:31:35 PM PDT 24
Finished Jul 12 06:31:39 PM PDT 24
Peak memory 232232 kb
Host smart-4bf4ddfa-1e2e-49db-a4b4-a0fb951f313a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525228558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.525228558
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.3371285409
Short name T336
Test name
Test status
Simulation time 1991326960 ps
CPU time 17.72 seconds
Started Jul 12 06:31:43 PM PDT 24
Finished Jul 12 06:32:02 PM PDT 24
Peak memory 223060 kb
Host smart-0fe75a71-ca3e-4c85-b629-dc18cb6ceaef
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3371285409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.3371285409
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.1661507659
Short name T545
Test name
Test status
Simulation time 119007995 ps
CPU time 0.87 seconds
Started Jul 12 06:31:40 PM PDT 24
Finished Jul 12 06:31:43 PM PDT 24
Peak memory 207352 kb
Host smart-6f738f0f-f5b6-42a6-bc11-0ffd41476300
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661507659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.1661507659
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.2787795775
Short name T995
Test name
Test status
Simulation time 6652880134 ps
CPU time 9.99 seconds
Started Jul 12 06:31:35 PM PDT 24
Finished Jul 12 06:31:46 PM PDT 24
Peak memory 216408 kb
Host smart-ab5de4cc-46fb-40a9-a99a-fa5d2f3dc1f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787795775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.2787795775
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.3437698556
Short name T514
Test name
Test status
Simulation time 39838278 ps
CPU time 0.77 seconds
Started Jul 12 06:31:35 PM PDT 24
Finished Jul 12 06:31:37 PM PDT 24
Peak memory 205644 kb
Host smart-0c298144-cecf-46b5-9710-a237e577bfeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437698556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.3437698556
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.2127830033
Short name T371
Test name
Test status
Simulation time 56270716 ps
CPU time 1.02 seconds
Started Jul 12 06:31:37 PM PDT 24
Finished Jul 12 06:31:39 PM PDT 24
Peak memory 207480 kb
Host smart-39bc5e73-1be7-4a33-9373-44f41c6bda10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127830033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.2127830033
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.1954012466
Short name T449
Test name
Test status
Simulation time 16053408 ps
CPU time 0.73 seconds
Started Jul 12 06:31:37 PM PDT 24
Finished Jul 12 06:31:39 PM PDT 24
Peak memory 205920 kb
Host smart-78d0d7fc-20b4-49d3-a7f7-cf2fd8ae1114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954012466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.1954012466
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.22665811
Short name T964
Test name
Test status
Simulation time 425616721 ps
CPU time 2.55 seconds
Started Jul 12 06:31:43 PM PDT 24
Finished Jul 12 06:31:47 PM PDT 24
Peak memory 232548 kb
Host smart-5e27bec3-3660-44be-a248-20edf701d495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22665811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.22665811
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.1368385765
Short name T556
Test name
Test status
Simulation time 15426049 ps
CPU time 0.84 seconds
Started Jul 12 06:31:51 PM PDT 24
Finished Jul 12 06:31:53 PM PDT 24
Peak memory 204888 kb
Host smart-e53644f2-ed02-4559-a603-11bf5f6698ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368385765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
1368385765
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.1775333578
Short name T685
Test name
Test status
Simulation time 305898401 ps
CPU time 4.08 seconds
Started Jul 12 06:31:53 PM PDT 24
Finished Jul 12 06:31:58 PM PDT 24
Peak memory 232540 kb
Host smart-52063656-de50-4543-a27a-1312de517ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775333578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.1775333578
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.3921712868
Short name T889
Test name
Test status
Simulation time 12856340 ps
CPU time 0.77 seconds
Started Jul 12 06:31:44 PM PDT 24
Finished Jul 12 06:31:46 PM PDT 24
Peak memory 206536 kb
Host smart-b338da57-1c13-4cc4-b226-c61105cff0a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921712868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.3921712868
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.2068553672
Short name T894
Test name
Test status
Simulation time 62161550878 ps
CPU time 123.58 seconds
Started Jul 12 06:31:53 PM PDT 24
Finished Jul 12 06:33:57 PM PDT 24
Peak memory 254896 kb
Host smart-560696f7-566f-4d0c-99b2-4c80cdb7bf29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068553672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.2068553672
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.1034578662
Short name T208
Test name
Test status
Simulation time 10984113532 ps
CPU time 148.87 seconds
Started Jul 12 06:31:52 PM PDT 24
Finished Jul 12 06:34:22 PM PDT 24
Peak memory 271432 kb
Host smart-6d2ade91-0f73-40a4-9e91-21671c209626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034578662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.1034578662
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.1695722954
Short name T985
Test name
Test status
Simulation time 454474328 ps
CPU time 11.22 seconds
Started Jul 12 06:31:52 PM PDT 24
Finished Jul 12 06:32:04 PM PDT 24
Peak memory 224440 kb
Host smart-14f4e768-e4d9-4f41-83ab-427660fd53a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695722954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.1695722954
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.3570107052
Short name T223
Test name
Test status
Simulation time 112286828690 ps
CPU time 161.5 seconds
Started Jul 12 06:31:51 PM PDT 24
Finished Jul 12 06:34:33 PM PDT 24
Peak memory 253508 kb
Host smart-23ac4b6a-02f5-4ee7-b80f-13bacfcc0d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570107052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd
s.3570107052
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.3334705616
Short name T7
Test name
Test status
Simulation time 1400762936 ps
CPU time 13.56 seconds
Started Jul 12 06:31:40 PM PDT 24
Finished Jul 12 06:31:55 PM PDT 24
Peak memory 232560 kb
Host smart-18056602-b2f7-41f9-adca-cbc1536b1456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334705616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.3334705616
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.1381859497
Short name T199
Test name
Test status
Simulation time 7266175577 ps
CPU time 8.87 seconds
Started Jul 12 06:31:41 PM PDT 24
Finished Jul 12 06:31:51 PM PDT 24
Peak memory 224440 kb
Host smart-0ca679e8-915c-4d69-b63a-4e01fcd08aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381859497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.1381859497
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.1407096003
Short name T910
Test name
Test status
Simulation time 18268728566 ps
CPU time 23.31 seconds
Started Jul 12 06:31:51 PM PDT 24
Finished Jul 12 06:32:15 PM PDT 24
Peak memory 240896 kb
Host smart-97b91ee1-621e-40f6-b7e9-12655aa78219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407096003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.1407096003
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.3547761549
Short name T220
Test name
Test status
Simulation time 5115667227 ps
CPU time 16.5 seconds
Started Jul 12 06:31:48 PM PDT 24
Finished Jul 12 06:32:05 PM PDT 24
Peak memory 232716 kb
Host smart-f9bd2493-526b-44ca-a1eb-4d0e3db58839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547761549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.3547761549
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.3521107408
Short name T753
Test name
Test status
Simulation time 972775128 ps
CPU time 3.64 seconds
Started Jul 12 06:31:51 PM PDT 24
Finished Jul 12 06:31:56 PM PDT 24
Peak memory 218420 kb
Host smart-1462b3ae-2e2b-43f7-bea6-e0354f9c4552
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3521107408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.3521107408
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.636386164
Short name T273
Test name
Test status
Simulation time 17754282645 ps
CPU time 36.07 seconds
Started Jul 12 06:31:51 PM PDT 24
Finished Jul 12 06:32:28 PM PDT 24
Peak memory 217544 kb
Host smart-80cd3586-4f31-4d2e-b123-4e0f72c1ed74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636386164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stres
s_all.636386164
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.2461278575
Short name T750
Test name
Test status
Simulation time 50797242585 ps
CPU time 34.13 seconds
Started Jul 12 06:31:40 PM PDT 24
Finished Jul 12 06:32:15 PM PDT 24
Peak memory 216264 kb
Host smart-633ee6ab-463d-4519-b1dc-d714b2b08d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461278575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.2461278575
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.3561887930
Short name T586
Test name
Test status
Simulation time 673691109 ps
CPU time 4.55 seconds
Started Jul 12 06:31:41 PM PDT 24
Finished Jul 12 06:31:47 PM PDT 24
Peak memory 216148 kb
Host smart-7dffdf20-760f-4f83-bfa0-b0dcfc57ddf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561887930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.3561887930
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.3120572402
Short name T345
Test name
Test status
Simulation time 147023987 ps
CPU time 1.79 seconds
Started Jul 12 06:31:47 PM PDT 24
Finished Jul 12 06:31:49 PM PDT 24
Peak memory 207924 kb
Host smart-521ea186-feb0-4b16-9bf7-40272be5f978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120572402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.3120572402
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.1177206011
Short name T791
Test name
Test status
Simulation time 29378152 ps
CPU time 0.69 seconds
Started Jul 12 06:31:41 PM PDT 24
Finished Jul 12 06:31:43 PM PDT 24
Peak memory 205516 kb
Host smart-688e8005-b359-49c2-8a75-76bcde21ea12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177206011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.1177206011
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.519978848
Short name T832
Test name
Test status
Simulation time 812280405 ps
CPU time 3.3 seconds
Started Jul 12 06:31:43 PM PDT 24
Finished Jul 12 06:31:48 PM PDT 24
Peak memory 232616 kb
Host smart-89e05373-c2ae-43cd-858a-aad8e8426466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519978848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.519978848
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.2921650571
Short name T387
Test name
Test status
Simulation time 44419726 ps
CPU time 0.7 seconds
Started Jul 12 06:31:51 PM PDT 24
Finished Jul 12 06:31:53 PM PDT 24
Peak memory 204936 kb
Host smart-aaf24ab0-a1b2-4910-8d49-889267881058
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921650571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
2921650571
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.481024328
Short name T597
Test name
Test status
Simulation time 3728452515 ps
CPU time 8.37 seconds
Started Jul 12 06:31:52 PM PDT 24
Finished Jul 12 06:32:02 PM PDT 24
Peak memory 224516 kb
Host smart-0a928ee6-b954-4535-8970-0013a6a199ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481024328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.481024328
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.3465336810
Short name T310
Test name
Test status
Simulation time 59301285 ps
CPU time 0.75 seconds
Started Jul 12 06:31:52 PM PDT 24
Finished Jul 12 06:31:54 PM PDT 24
Peak memory 205548 kb
Host smart-a180dbf3-bf67-47ff-b746-fc5f663a0643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465336810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.3465336810
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.4274814408
Short name T180
Test name
Test status
Simulation time 135017088499 ps
CPU time 228.09 seconds
Started Jul 12 06:31:54 PM PDT 24
Finished Jul 12 06:35:43 PM PDT 24
Peak memory 263124 kb
Host smart-d0afed04-9bf2-4d25-9bce-a8af0a854b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274814408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.4274814408
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.1144585199
Short name T495
Test name
Test status
Simulation time 5286056463 ps
CPU time 107.64 seconds
Started Jul 12 06:31:52 PM PDT 24
Finished Jul 12 06:33:41 PM PDT 24
Peak memory 250336 kb
Host smart-543ec6f9-74ab-4872-853e-969375f87ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144585199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.1144585199
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.3826388748
Short name T765
Test name
Test status
Simulation time 1425070920 ps
CPU time 8.43 seconds
Started Jul 12 06:31:50 PM PDT 24
Finished Jul 12 06:31:59 PM PDT 24
Peak memory 224412 kb
Host smart-c489621d-2333-426c-b80a-3ef9fc85ffdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826388748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.3826388748
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.4063983569
Short name T618
Test name
Test status
Simulation time 20358247 ps
CPU time 0.75 seconds
Started Jul 12 06:31:52 PM PDT 24
Finished Jul 12 06:31:54 PM PDT 24
Peak memory 215672 kb
Host smart-ccc22617-7998-4e9e-b1ce-42bf8e1e275b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063983569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmd
s.4063983569
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_intercept.1757343986
Short name T782
Test name
Test status
Simulation time 1088710571 ps
CPU time 13.37 seconds
Started Jul 12 06:31:50 PM PDT 24
Finished Jul 12 06:32:05 PM PDT 24
Peak memory 232568 kb
Host smart-076be9cb-239a-4da1-989c-3990fb24c34e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757343986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.1757343986
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.2330357022
Short name T875
Test name
Test status
Simulation time 9989050910 ps
CPU time 56.96 seconds
Started Jul 12 06:31:53 PM PDT 24
Finished Jul 12 06:32:51 PM PDT 24
Peak memory 232768 kb
Host smart-929d4eff-5c39-4f7f-aabb-9c0debc1d539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330357022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.2330357022
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.1015037398
Short name T650
Test name
Test status
Simulation time 69433716017 ps
CPU time 27.42 seconds
Started Jul 12 06:31:53 PM PDT 24
Finished Jul 12 06:32:22 PM PDT 24
Peak memory 224508 kb
Host smart-399ac566-0ace-4d52-a300-8253cc538abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015037398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.1015037398
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.1500154970
Short name T599
Test name
Test status
Simulation time 509654637 ps
CPU time 5.69 seconds
Started Jul 12 06:31:53 PM PDT 24
Finished Jul 12 06:32:00 PM PDT 24
Peak memory 224440 kb
Host smart-26aaa7fe-da57-48a1-8fde-d2c426da1b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500154970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.1500154970
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.953451696
Short name T909
Test name
Test status
Simulation time 2477101934 ps
CPU time 11.36 seconds
Started Jul 12 06:31:51 PM PDT 24
Finished Jul 12 06:32:04 PM PDT 24
Peak memory 218912 kb
Host smart-145a845e-5ea5-4a44-bcf5-c2241538060f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=953451696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dire
ct.953451696
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.3587261397
Short name T700
Test name
Test status
Simulation time 30840150192 ps
CPU time 100.88 seconds
Started Jul 12 06:31:50 PM PDT 24
Finished Jul 12 06:33:32 PM PDT 24
Peak memory 264704 kb
Host smart-fde72041-d4b7-47c2-9f95-60faaf14407e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587261397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.3587261397
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.3986718622
Short name T698
Test name
Test status
Simulation time 18488223118 ps
CPU time 28.47 seconds
Started Jul 12 06:31:50 PM PDT 24
Finished Jul 12 06:32:19 PM PDT 24
Peak memory 216540 kb
Host smart-97e9b92a-ff4c-4909-9618-e082fb1727ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986718622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.3986718622
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.3178337087
Short name T709
Test name
Test status
Simulation time 4127757031 ps
CPU time 4.76 seconds
Started Jul 12 06:31:54 PM PDT 24
Finished Jul 12 06:31:59 PM PDT 24
Peak memory 216256 kb
Host smart-f44326ab-8084-45f3-b58a-bee1a7b22119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178337087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.3178337087
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.1157521537
Short name T404
Test name
Test status
Simulation time 52592147 ps
CPU time 0.82 seconds
Started Jul 12 06:31:54 PM PDT 24
Finished Jul 12 06:31:55 PM PDT 24
Peak memory 205932 kb
Host smart-ff558d12-ecc0-4085-99d9-b39036eeacc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157521537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.1157521537
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.2734310525
Short name T707
Test name
Test status
Simulation time 215650889 ps
CPU time 0.81 seconds
Started Jul 12 06:31:52 PM PDT 24
Finished Jul 12 06:31:54 PM PDT 24
Peak memory 205864 kb
Host smart-a241ee99-62a3-4537-bc49-f3897216eed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734310525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.2734310525
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.3600935674
Short name T411
Test name
Test status
Simulation time 977349259 ps
CPU time 4.41 seconds
Started Jul 12 06:31:52 PM PDT 24
Finished Jul 12 06:31:58 PM PDT 24
Peak memory 232676 kb
Host smart-afb390e3-b59f-4067-95cb-879dd911781e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600935674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.3600935674
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.43387834
Short name T591
Test name
Test status
Simulation time 12827289 ps
CPU time 0.77 seconds
Started Jul 12 06:32:02 PM PDT 24
Finished Jul 12 06:32:04 PM PDT 24
Peak memory 205780 kb
Host smart-12b050a0-ff66-47ad-bfa8-40d800288ea4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43387834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.43387834
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.327412729
Short name T1009
Test name
Test status
Simulation time 295772112 ps
CPU time 6.27 seconds
Started Jul 12 06:31:59 PM PDT 24
Finished Jul 12 06:32:07 PM PDT 24
Peak memory 232620 kb
Host smart-343324ff-cf6a-4c3c-bfb0-09d69a5776bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327412729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.327412729
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.2346793468
Short name T1002
Test name
Test status
Simulation time 64988992 ps
CPU time 0.79 seconds
Started Jul 12 06:31:58 PM PDT 24
Finished Jul 12 06:31:59 PM PDT 24
Peak memory 206868 kb
Host smart-e970051d-90a3-4844-bda4-acb8396498b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346793468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.2346793468
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.1300275946
Short name T548
Test name
Test status
Simulation time 1896575940 ps
CPU time 16.12 seconds
Started Jul 12 06:32:00 PM PDT 24
Finished Jul 12 06:32:18 PM PDT 24
Peak memory 235096 kb
Host smart-a5ace381-ce17-4f46-a38d-601d2ff75867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300275946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.1300275946
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.3995390329
Short name T884
Test name
Test status
Simulation time 26217432907 ps
CPU time 38.34 seconds
Started Jul 12 06:32:05 PM PDT 24
Finished Jul 12 06:32:45 PM PDT 24
Peak memory 217696 kb
Host smart-16d129a2-68fb-4a9f-8c26-a21af3c5f3f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995390329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.3995390329
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.3065263235
Short name T710
Test name
Test status
Simulation time 39175444522 ps
CPU time 49.4 seconds
Started Jul 12 06:31:59 PM PDT 24
Finished Jul 12 06:32:50 PM PDT 24
Peak memory 250500 kb
Host smart-4302e7e4-16c2-4226-97c4-a115a45f2356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065263235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.3065263235
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.1015068598
Short name T481
Test name
Test status
Simulation time 9171910990 ps
CPU time 86.27 seconds
Started Jul 12 06:31:58 PM PDT 24
Finished Jul 12 06:33:25 PM PDT 24
Peak memory 251704 kb
Host smart-aa69d96b-129c-4ac4-9759-1f18428e01f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015068598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd
s.1015068598
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.1803841715
Short name T368
Test name
Test status
Simulation time 89317268699 ps
CPU time 153.87 seconds
Started Jul 12 06:32:01 PM PDT 24
Finished Jul 12 06:34:36 PM PDT 24
Peak memory 251544 kb
Host smart-20d034cc-e72a-42a9-b5db-08ea3bdb2e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803841715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.1803841715
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.1867962625
Short name T911
Test name
Test status
Simulation time 4675243676 ps
CPU time 11.08 seconds
Started Jul 12 06:31:58 PM PDT 24
Finished Jul 12 06:32:11 PM PDT 24
Peak memory 232576 kb
Host smart-a50a3d63-8768-437f-a496-7f1227fd4b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867962625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.1867962625
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.221906063
Short name T521
Test name
Test status
Simulation time 268544260 ps
CPU time 5.93 seconds
Started Jul 12 06:31:59 PM PDT 24
Finished Jul 12 06:32:07 PM PDT 24
Peak memory 232596 kb
Host smart-9ef54595-2bcb-472c-8d00-c3d40c4dcb64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221906063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.221906063
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.343228291
Short name T359
Test name
Test status
Simulation time 1164712402 ps
CPU time 12.45 seconds
Started Jul 12 06:31:58 PM PDT 24
Finished Jul 12 06:32:12 PM PDT 24
Peak memory 222264 kb
Host smart-e1350ce4-85d8-460b-9863-ceed65489bce
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=343228291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dire
ct.343228291
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.2574608534
Short name T11
Test name
Test status
Simulation time 213247171 ps
CPU time 1.02 seconds
Started Jul 12 06:31:58 PM PDT 24
Finished Jul 12 06:32:01 PM PDT 24
Peak memory 206824 kb
Host smart-e3bd4e6d-5213-4593-a74b-b9f680c08f20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574608534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.2574608534
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.806372862
Short name T699
Test name
Test status
Simulation time 12341523639 ps
CPU time 27.27 seconds
Started Jul 12 06:32:00 PM PDT 24
Finished Jul 12 06:32:29 PM PDT 24
Peak memory 216300 kb
Host smart-9aca8b3e-1555-424e-ad89-d109237e65f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806372862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.806372862
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.3476876415
Short name T346
Test name
Test status
Simulation time 223396361 ps
CPU time 2.34 seconds
Started Jul 12 06:31:58 PM PDT 24
Finished Jul 12 06:32:02 PM PDT 24
Peak memory 216164 kb
Host smart-870a00ca-ce9c-482b-b92f-b7e8a8aef567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476876415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.3476876415
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.358809007
Short name T639
Test name
Test status
Simulation time 32930168 ps
CPU time 1.18 seconds
Started Jul 12 06:31:57 PM PDT 24
Finished Jul 12 06:31:58 PM PDT 24
Peak memory 207868 kb
Host smart-5e42e5e6-0fcc-428f-9ba2-da5001c235a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358809007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.358809007
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.244397267
Short name T780
Test name
Test status
Simulation time 20183240 ps
CPU time 0.72 seconds
Started Jul 12 06:31:58 PM PDT 24
Finished Jul 12 06:32:01 PM PDT 24
Peak memory 205924 kb
Host smart-5eec84a6-d49f-4fbf-943c-e30b66cb389d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244397267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.244397267
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.2231407845
Short name T666
Test name
Test status
Simulation time 574044562 ps
CPU time 3.85 seconds
Started Jul 12 06:32:03 PM PDT 24
Finished Jul 12 06:32:07 PM PDT 24
Peak memory 224440 kb
Host smart-a46867ea-f817-49e2-a89e-302db9485c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231407845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.2231407845
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.872078368
Short name T954
Test name
Test status
Simulation time 43935036 ps
CPU time 0.73 seconds
Started Jul 12 06:32:06 PM PDT 24
Finished Jul 12 06:32:09 PM PDT 24
Peak memory 204880 kb
Host smart-2fb0120f-7261-488b-889f-ca401f135963
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872078368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.872078368
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.616007790
Short name T718
Test name
Test status
Simulation time 266830368 ps
CPU time 4.01 seconds
Started Jul 12 06:31:59 PM PDT 24
Finished Jul 12 06:32:05 PM PDT 24
Peak memory 232544 kb
Host smart-47339b03-d7fa-43ef-9e01-42db376d7bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616007790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.616007790
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.3760915157
Short name T893
Test name
Test status
Simulation time 47807357 ps
CPU time 0.75 seconds
Started Jul 12 06:31:57 PM PDT 24
Finished Jul 12 06:31:59 PM PDT 24
Peak memory 205808 kb
Host smart-8e9becca-21a2-461a-9606-a14f940ed007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760915157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.3760915157
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.3255322773
Short name T781
Test name
Test status
Simulation time 10023891422 ps
CPU time 18.48 seconds
Started Jul 12 06:31:58 PM PDT 24
Finished Jul 12 06:32:17 PM PDT 24
Peak memory 249892 kb
Host smart-d20d3816-287a-46f7-b711-bae884527886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255322773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.3255322773
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.950221846
Short name T756
Test name
Test status
Simulation time 10265542611 ps
CPU time 22.42 seconds
Started Jul 12 06:31:58 PM PDT 24
Finished Jul 12 06:32:23 PM PDT 24
Peak memory 234896 kb
Host smart-6dd6d9f0-f556-4247-a0d8-902119a8fa01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950221846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.950221846
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.1407588158
Short name T259
Test name
Test status
Simulation time 121100350974 ps
CPU time 583.23 seconds
Started Jul 12 06:31:58 PM PDT 24
Finished Jul 12 06:41:43 PM PDT 24
Peak memory 265168 kb
Host smart-68a0ca94-4227-4a2a-aff2-f09b6c44d9c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407588158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.1407588158
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.3860858600
Short name T538
Test name
Test status
Simulation time 1194368715 ps
CPU time 18.49 seconds
Started Jul 12 06:31:59 PM PDT 24
Finished Jul 12 06:32:19 PM PDT 24
Peak memory 249044 kb
Host smart-c2cafe7f-ba25-4ae7-aba9-a9a3bee7bee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860858600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.3860858600
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.1029613704
Short name T493
Test name
Test status
Simulation time 1156242643 ps
CPU time 17.94 seconds
Started Jul 12 06:31:58 PM PDT 24
Finished Jul 12 06:32:18 PM PDT 24
Peak memory 240832 kb
Host smart-51ed1236-04d4-4b97-92b1-9644841da93c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029613704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmd
s.1029613704
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_intercept.1335485592
Short name T641
Test name
Test status
Simulation time 749897304 ps
CPU time 8.22 seconds
Started Jul 12 06:32:03 PM PDT 24
Finished Jul 12 06:32:12 PM PDT 24
Peak memory 224428 kb
Host smart-13d12f3c-91d6-43f1-b5ec-ac6c0f982650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335485592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.1335485592
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.1551379429
Short name T416
Test name
Test status
Simulation time 10452670518 ps
CPU time 78.1 seconds
Started Jul 12 06:31:59 PM PDT 24
Finished Jul 12 06:33:20 PM PDT 24
Peak memory 232728 kb
Host smart-8a611f17-acb4-40a9-b592-83b4cc53986a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551379429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.1551379429
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.493931853
Short name T931
Test name
Test status
Simulation time 1105032611 ps
CPU time 7.83 seconds
Started Jul 12 06:31:58 PM PDT 24
Finished Jul 12 06:32:08 PM PDT 24
Peak memory 232552 kb
Host smart-650a4a43-f576-4bfb-893a-68f0c0f0913e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493931853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swap
.493931853
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.650100608
Short name T890
Test name
Test status
Simulation time 4926405395 ps
CPU time 15.88 seconds
Started Jul 12 06:32:00 PM PDT 24
Finished Jul 12 06:32:18 PM PDT 24
Peak memory 240300 kb
Host smart-356d889d-0a37-4118-90dd-a29aff294780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650100608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.650100608
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.1967138345
Short name T619
Test name
Test status
Simulation time 409559436 ps
CPU time 3.88 seconds
Started Jul 12 06:32:00 PM PDT 24
Finished Jul 12 06:32:05 PM PDT 24
Peak memory 223112 kb
Host smart-02731715-4eb7-4afe-8ac2-31b14f2819d2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1967138345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.1967138345
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.1380005200
Short name T241
Test name
Test status
Simulation time 8654673413 ps
CPU time 138.98 seconds
Started Jul 12 06:32:07 PM PDT 24
Finished Jul 12 06:34:29 PM PDT 24
Peak memory 257404 kb
Host smart-e8d22511-7202-473e-a2f8-6b348635ed45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380005200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.1380005200
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.2174640712
Short name T314
Test name
Test status
Simulation time 15632279681 ps
CPU time 19.45 seconds
Started Jul 12 06:32:00 PM PDT 24
Finished Jul 12 06:32:21 PM PDT 24
Peak memory 216224 kb
Host smart-a2bbb3f2-dee1-4042-a6f9-c790b308499e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174640712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.2174640712
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.2483091807
Short name T292
Test name
Test status
Simulation time 3917913769 ps
CPU time 9.1 seconds
Started Jul 12 06:31:59 PM PDT 24
Finished Jul 12 06:32:10 PM PDT 24
Peak memory 216180 kb
Host smart-5a706ec6-0241-4a28-aca7-cba1e8e7fc0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483091807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.2483091807
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.757271691
Short name T900
Test name
Test status
Simulation time 18431144 ps
CPU time 1.13 seconds
Started Jul 12 06:31:58 PM PDT 24
Finished Jul 12 06:32:00 PM PDT 24
Peak memory 215864 kb
Host smart-5d446d2e-73ba-41c9-b340-f3707cd88182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757271691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.757271691
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.355178483
Short name T799
Test name
Test status
Simulation time 105090265 ps
CPU time 0.99 seconds
Started Jul 12 06:31:59 PM PDT 24
Finished Jul 12 06:32:02 PM PDT 24
Peak memory 206964 kb
Host smart-b0279d80-8fb1-4cd7-889e-00b4d7a9f1d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355178483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.355178483
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.2565505501
Short name T747
Test name
Test status
Simulation time 942660513 ps
CPU time 3.63 seconds
Started Jul 12 06:32:03 PM PDT 24
Finished Jul 12 06:32:07 PM PDT 24
Peak memory 232580 kb
Host smart-5e30f1c6-00ec-46ad-964f-a6b80c00775c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565505501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.2565505501
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.2165609911
Short name T60
Test name
Test status
Simulation time 49798432 ps
CPU time 0.74 seconds
Started Jul 12 06:32:07 PM PDT 24
Finished Jul 12 06:32:10 PM PDT 24
Peak memory 204936 kb
Host smart-f93fb80f-a781-4c39-ac80-16df78bca960
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165609911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
2165609911
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.2987292432
Short name T645
Test name
Test status
Simulation time 452560743 ps
CPU time 2.85 seconds
Started Jul 12 06:32:08 PM PDT 24
Finished Jul 12 06:32:13 PM PDT 24
Peak memory 224396 kb
Host smart-d12edd3b-8275-418e-baed-ca95767c322b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987292432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.2987292432
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.1028402339
Short name T322
Test name
Test status
Simulation time 33813606 ps
CPU time 0.77 seconds
Started Jul 12 06:32:05 PM PDT 24
Finished Jul 12 06:32:08 PM PDT 24
Peak memory 205496 kb
Host smart-c4b09a29-fdbe-4895-9798-66d586dd7fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028402339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.1028402339
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.1268411063
Short name T555
Test name
Test status
Simulation time 15812160442 ps
CPU time 40.94 seconds
Started Jul 12 06:32:06 PM PDT 24
Finished Jul 12 06:32:49 PM PDT 24
Peak memory 240960 kb
Host smart-acd7fc2e-c92e-45c9-bd42-a1f0af73b377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268411063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.1268411063
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.2727403544
Short name T238
Test name
Test status
Simulation time 67842041382 ps
CPU time 208.03 seconds
Started Jul 12 06:32:10 PM PDT 24
Finished Jul 12 06:35:39 PM PDT 24
Peak memory 250800 kb
Host smart-432d0d96-976b-41af-8d27-76872b34c1e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727403544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.2727403544
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.3228902550
Short name T56
Test name
Test status
Simulation time 1868205763 ps
CPU time 6.08 seconds
Started Jul 12 06:32:07 PM PDT 24
Finished Jul 12 06:32:15 PM PDT 24
Peak memory 240584 kb
Host smart-e59e8cfa-5e3c-4917-8f60-69ac7b2d0d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228902550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.3228902550
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.898658140
Short name T167
Test name
Test status
Simulation time 244206075379 ps
CPU time 198.53 seconds
Started Jul 12 06:32:09 PM PDT 24
Finished Jul 12 06:35:29 PM PDT 24
Peak memory 273692 kb
Host smart-936f4618-4bfa-4beb-a576-e2524231663b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898658140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmds
.898658140
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.1448268777
Short name T439
Test name
Test status
Simulation time 550957064 ps
CPU time 5.78 seconds
Started Jul 12 06:32:06 PM PDT 24
Finished Jul 12 06:32:14 PM PDT 24
Peak memory 224432 kb
Host smart-391d8e3a-32ff-4aed-810f-adcfe22c5d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448268777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.1448268777
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.3449470844
Short name T539
Test name
Test status
Simulation time 27703267974 ps
CPU time 39.93 seconds
Started Jul 12 06:32:06 PM PDT 24
Finished Jul 12 06:32:48 PM PDT 24
Peak memory 232644 kb
Host smart-44cb406e-12c3-49b0-8832-fcb8280d8196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449470844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.3449470844
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.3921481556
Short name T255
Test name
Test status
Simulation time 4029583249 ps
CPU time 20.01 seconds
Started Jul 12 06:32:08 PM PDT 24
Finished Jul 12 06:32:30 PM PDT 24
Peak memory 232684 kb
Host smart-ff8846a2-34fb-4aec-96dc-7ef839b1257b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921481556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.3921481556
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.2009213356
Short name T973
Test name
Test status
Simulation time 40156906058 ps
CPU time 23.74 seconds
Started Jul 12 06:32:11 PM PDT 24
Finished Jul 12 06:32:36 PM PDT 24
Peak memory 232724 kb
Host smart-242ab3aa-0bad-4c17-bc04-4c66fb29c2fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009213356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.2009213356
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.3729295729
Short name T584
Test name
Test status
Simulation time 8035256814 ps
CPU time 21.1 seconds
Started Jul 12 06:32:05 PM PDT 24
Finished Jul 12 06:32:27 PM PDT 24
Peak memory 222136 kb
Host smart-891391bb-d1ef-48e8-9638-a700f46152f2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3729295729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.3729295729
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.2258330416
Short name T613
Test name
Test status
Simulation time 225172139307 ps
CPU time 413.14 seconds
Started Jul 12 06:32:08 PM PDT 24
Finished Jul 12 06:39:03 PM PDT 24
Peak memory 267636 kb
Host smart-fcad0cc5-5018-44db-9b04-bb8fc40b7102
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258330416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.2258330416
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.849476668
Short name T897
Test name
Test status
Simulation time 4855621199 ps
CPU time 23.65 seconds
Started Jul 12 06:32:06 PM PDT 24
Finished Jul 12 06:32:32 PM PDT 24
Peak memory 216316 kb
Host smart-f72ad04f-c10c-49a6-b090-6afbbae00c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849476668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.849476668
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.3322507104
Short name T902
Test name
Test status
Simulation time 5886556840 ps
CPU time 19.2 seconds
Started Jul 12 06:32:08 PM PDT 24
Finished Jul 12 06:32:29 PM PDT 24
Peak memory 216216 kb
Host smart-cc9086b1-c746-4ea1-b19d-d407a0b18bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322507104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.3322507104
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.3872068180
Short name T723
Test name
Test status
Simulation time 272014774 ps
CPU time 2.23 seconds
Started Jul 12 06:32:05 PM PDT 24
Finished Jul 12 06:32:08 PM PDT 24
Peak memory 216116 kb
Host smart-a5212fb1-5a2b-439e-af94-499bfc887dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872068180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.3872068180
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.3226083127
Short name T441
Test name
Test status
Simulation time 97818623 ps
CPU time 0.85 seconds
Started Jul 12 06:32:06 PM PDT 24
Finished Jul 12 06:32:09 PM PDT 24
Peak memory 205936 kb
Host smart-5113b93d-21ad-453b-9e17-ef14e7d13beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226083127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.3226083127
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.2212059188
Short name T93
Test name
Test status
Simulation time 4669346239 ps
CPU time 18.83 seconds
Started Jul 12 06:32:07 PM PDT 24
Finished Jul 12 06:32:28 PM PDT 24
Peak memory 224504 kb
Host smart-3b0d1190-6f8f-4cbf-86dc-1b4cc334f050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212059188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.2212059188
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.13978892
Short name T295
Test name
Test status
Simulation time 24000080 ps
CPU time 0.73 seconds
Started Jul 12 06:32:14 PM PDT 24
Finished Jul 12 06:32:16 PM PDT 24
Peak memory 204872 kb
Host smart-0c512321-1365-4e56-bae6-f64b5cb69363
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13978892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.13978892
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.3610098533
Short name T600
Test name
Test status
Simulation time 2234665839 ps
CPU time 11.24 seconds
Started Jul 12 06:32:06 PM PDT 24
Finished Jul 12 06:32:20 PM PDT 24
Peak memory 232604 kb
Host smart-e177b499-4380-4072-a577-8ffc6a06a7fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610098533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.3610098533
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.4048523106
Short name T500
Test name
Test status
Simulation time 29100438 ps
CPU time 0.76 seconds
Started Jul 12 06:32:07 PM PDT 24
Finished Jul 12 06:32:10 PM PDT 24
Peak memory 206516 kb
Host smart-504f353e-08f3-476b-ab87-58f59ef223f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048523106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.4048523106
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.74520149
Short name T605
Test name
Test status
Simulation time 26468237681 ps
CPU time 128.88 seconds
Started Jul 12 06:32:14 PM PDT 24
Finished Jul 12 06:34:24 PM PDT 24
Peak memory 249116 kb
Host smart-aab37bde-e906-475a-8569-ef818b815ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74520149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.74520149
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.373575667
Short name T955
Test name
Test status
Simulation time 2181387712 ps
CPU time 27.03 seconds
Started Jul 12 06:32:14 PM PDT 24
Finished Jul 12 06:32:42 PM PDT 24
Peak memory 224564 kb
Host smart-06bf345f-68e8-4dc8-977f-9979286a621c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373575667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.373575667
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.619793776
Short name T133
Test name
Test status
Simulation time 17179553612 ps
CPU time 121.3 seconds
Started Jul 12 06:32:14 PM PDT 24
Finished Jul 12 06:34:16 PM PDT 24
Peak memory 270752 kb
Host smart-5f0f90bc-3f17-4efa-9b9c-8051cd6f0256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619793776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idle
.619793776
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.1444132554
Short name T657
Test name
Test status
Simulation time 36806625701 ps
CPU time 273.99 seconds
Started Jul 12 06:32:14 PM PDT 24
Finished Jul 12 06:36:49 PM PDT 24
Peak memory 256992 kb
Host smart-6e3887ee-98cf-43c4-b9eb-412cb4629880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444132554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmd
s.1444132554
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.1485205238
Short name T518
Test name
Test status
Simulation time 4273476843 ps
CPU time 11.64 seconds
Started Jul 12 06:32:06 PM PDT 24
Finished Jul 12 06:32:20 PM PDT 24
Peak memory 224732 kb
Host smart-f3aa4700-2d47-4db0-bb87-78c40a65126e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485205238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.1485205238
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.3725944894
Short name T294
Test name
Test status
Simulation time 278195617 ps
CPU time 2.21 seconds
Started Jul 12 06:32:06 PM PDT 24
Finished Jul 12 06:32:10 PM PDT 24
Peak memory 223748 kb
Host smart-bbfeb00f-fec9-40bc-9eb0-316da5574c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725944894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.3725944894
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.2916278591
Short name T195
Test name
Test status
Simulation time 816893597 ps
CPU time 4.65 seconds
Started Jul 12 06:32:05 PM PDT 24
Finished Jul 12 06:32:11 PM PDT 24
Peak memory 224396 kb
Host smart-ba08f44e-8d7d-4eed-9f3e-d804022e8166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916278591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.2916278591
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.123290718
Short name T833
Test name
Test status
Simulation time 7324675662 ps
CPU time 22.03 seconds
Started Jul 12 06:32:05 PM PDT 24
Finished Jul 12 06:32:28 PM PDT 24
Peak memory 224548 kb
Host smart-1fe2bb3e-dbf3-4ed3-9061-a5b4963be5a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123290718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.123290718
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.3126990648
Short name T562
Test name
Test status
Simulation time 2367615546 ps
CPU time 11.17 seconds
Started Jul 12 06:32:12 PM PDT 24
Finished Jul 12 06:32:24 PM PDT 24
Peak memory 222000 kb
Host smart-99d1262a-d874-494e-a4ff-2c0dbe9754be
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3126990648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.3126990648
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.698514269
Short name T963
Test name
Test status
Simulation time 15258917491 ps
CPU time 238.12 seconds
Started Jul 12 06:32:16 PM PDT 24
Finished Jul 12 06:36:15 PM PDT 24
Peak memory 270112 kb
Host smart-bd7fd10b-e796-4a1e-bfc5-a036a6f91014
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698514269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stres
s_all.698514269
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.1447529169
Short name T326
Test name
Test status
Simulation time 3081275418 ps
CPU time 5.55 seconds
Started Jul 12 06:32:10 PM PDT 24
Finished Jul 12 06:32:17 PM PDT 24
Peak memory 216208 kb
Host smart-5673f41b-115e-4324-9242-ae6848e291c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447529169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.1447529169
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.3681880972
Short name T760
Test name
Test status
Simulation time 26016713781 ps
CPU time 7.68 seconds
Started Jul 12 06:32:07 PM PDT 24
Finished Jul 12 06:32:17 PM PDT 24
Peak memory 216284 kb
Host smart-9b3d5fa6-b912-4320-8ab7-65c8a57b18bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681880972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.3681880972
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.2772189096
Short name T557
Test name
Test status
Simulation time 24965814 ps
CPU time 0.97 seconds
Started Jul 12 06:32:06 PM PDT 24
Finished Jul 12 06:32:10 PM PDT 24
Peak memory 206704 kb
Host smart-a84583c7-bc61-438d-b4e5-328863d6f104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772189096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.2772189096
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.2407781548
Short name T498
Test name
Test status
Simulation time 34396807 ps
CPU time 0.76 seconds
Started Jul 12 06:32:06 PM PDT 24
Finished Jul 12 06:32:09 PM PDT 24
Peak memory 205864 kb
Host smart-90f56357-5138-4066-b4ae-9755ee63ac80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407781548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.2407781548
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.2247809194
Short name T943
Test name
Test status
Simulation time 1019460498 ps
CPU time 4.77 seconds
Started Jul 12 06:32:09 PM PDT 24
Finished Jul 12 06:32:15 PM PDT 24
Peak memory 224380 kb
Host smart-49f8dda5-8af0-4146-8412-380baf317d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247809194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.2247809194
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.2980435257
Short name T608
Test name
Test status
Simulation time 34133885 ps
CPU time 0.71 seconds
Started Jul 12 06:32:22 PM PDT 24
Finished Jul 12 06:32:23 PM PDT 24
Peak memory 204936 kb
Host smart-b5b29adf-2de5-4a97-94c6-c7c2ae67e465
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980435257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
2980435257
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.1600895413
Short name T652
Test name
Test status
Simulation time 1011854357 ps
CPU time 7.25 seconds
Started Jul 12 06:32:17 PM PDT 24
Finished Jul 12 06:32:25 PM PDT 24
Peak memory 224348 kb
Host smart-3e38a40b-1256-49ac-8881-1fa76edd1a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600895413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.1600895413
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.2566514060
Short name T675
Test name
Test status
Simulation time 18727944 ps
CPU time 0.79 seconds
Started Jul 12 06:32:15 PM PDT 24
Finished Jul 12 06:32:17 PM PDT 24
Peak memory 206492 kb
Host smart-88c62486-df6d-4e7a-aed8-8ffb2c059b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566514060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.2566514060
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.1896528348
Short name T507
Test name
Test status
Simulation time 4790940642 ps
CPU time 67.45 seconds
Started Jul 12 06:32:17 PM PDT 24
Finished Jul 12 06:33:24 PM PDT 24
Peak memory 249104 kb
Host smart-7edc8ac6-9750-4318-80b4-df18309eb60f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896528348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.1896528348
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.3594746410
Short name T366
Test name
Test status
Simulation time 214361092214 ps
CPU time 267.38 seconds
Started Jul 12 06:32:16 PM PDT 24
Finished Jul 12 06:36:44 PM PDT 24
Peak memory 273152 kb
Host smart-664802a5-cc4c-4303-93f6-55a58bef5f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594746410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.3594746410
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.2437424489
Short name T267
Test name
Test status
Simulation time 910924012 ps
CPU time 13.88 seconds
Started Jul 12 06:32:15 PM PDT 24
Finished Jul 12 06:32:29 PM PDT 24
Peak memory 224404 kb
Host smart-b0032514-6a42-442a-9698-c161292144e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437424489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.2437424489
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.423780522
Short name T681
Test name
Test status
Simulation time 71089011608 ps
CPU time 119.61 seconds
Started Jul 12 06:32:16 PM PDT 24
Finished Jul 12 06:34:16 PM PDT 24
Peak memory 240928 kb
Host smart-9b21d29f-409e-4e40-9588-0375b1dbf107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423780522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmds
.423780522
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_intercept.2732214627
Short name T800
Test name
Test status
Simulation time 17833632931 ps
CPU time 32.89 seconds
Started Jul 12 06:32:14 PM PDT 24
Finished Jul 12 06:32:47 PM PDT 24
Peak memory 232756 kb
Host smart-caf6dc58-d0fb-4871-8d2a-f6f53a22e91e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732214627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.2732214627
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.345671314
Short name T200
Test name
Test status
Simulation time 1739107406 ps
CPU time 16.55 seconds
Started Jul 12 06:32:14 PM PDT 24
Finished Jul 12 06:32:31 PM PDT 24
Peak memory 224676 kb
Host smart-91d8e0b8-4190-4041-9226-1d4d27555050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345671314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.345671314
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.2233890507
Short name T396
Test name
Test status
Simulation time 3209033832 ps
CPU time 6.76 seconds
Started Jul 12 06:32:16 PM PDT 24
Finished Jul 12 06:32:23 PM PDT 24
Peak memory 224464 kb
Host smart-d579775f-131e-49c5-934f-38aeb4b0ccab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233890507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.2233890507
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.880926300
Short name T504
Test name
Test status
Simulation time 495018423 ps
CPU time 10.42 seconds
Started Jul 12 06:32:19 PM PDT 24
Finished Jul 12 06:32:30 PM PDT 24
Peak memory 240536 kb
Host smart-55548237-3900-4d14-994f-560ad3064624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880926300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.880926300
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.720533308
Short name T1008
Test name
Test status
Simulation time 2613801498 ps
CPU time 12.34 seconds
Started Jul 12 06:32:15 PM PDT 24
Finished Jul 12 06:32:28 PM PDT 24
Peak memory 223092 kb
Host smart-f995d137-bc7a-4ace-810f-1c8dfa16f1ae
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=720533308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dire
ct.720533308
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.1953825429
Short name T624
Test name
Test status
Simulation time 56323624997 ps
CPU time 150.13 seconds
Started Jul 12 06:32:25 PM PDT 24
Finished Jul 12 06:34:56 PM PDT 24
Peak memory 254404 kb
Host smart-d5708e9e-c1d0-4536-88e1-d3c0a7442225
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953825429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.1953825429
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.3127184383
Short name T489
Test name
Test status
Simulation time 9883598666 ps
CPU time 52.12 seconds
Started Jul 12 06:32:14 PM PDT 24
Finished Jul 12 06:33:07 PM PDT 24
Peak memory 216464 kb
Host smart-103bd7a0-e684-49cc-9573-64c405525295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127184383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.3127184383
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.2745798959
Short name T920
Test name
Test status
Simulation time 39641933 ps
CPU time 0.73 seconds
Started Jul 12 06:32:19 PM PDT 24
Finished Jul 12 06:32:21 PM PDT 24
Peak memory 205620 kb
Host smart-b4e906ad-afba-4f59-8ba2-7ad6fae9ab89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745798959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.2745798959
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.2381937256
Short name T328
Test name
Test status
Simulation time 109835071 ps
CPU time 1.75 seconds
Started Jul 12 06:32:19 PM PDT 24
Finished Jul 12 06:32:22 PM PDT 24
Peak memory 216172 kb
Host smart-e61ce2af-9d4a-4a24-9cda-1c213d77c0f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381937256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.2381937256
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.428169827
Short name T885
Test name
Test status
Simulation time 94939290 ps
CPU time 0.98 seconds
Started Jul 12 06:32:15 PM PDT 24
Finished Jul 12 06:32:17 PM PDT 24
Peak memory 206956 kb
Host smart-1bf7fa11-95b6-4ec9-9c3c-337cd872b738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428169827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.428169827
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.2807984743
Short name T305
Test name
Test status
Simulation time 44404893 ps
CPU time 2.62 seconds
Started Jul 12 06:32:11 PM PDT 24
Finished Jul 12 06:32:15 PM PDT 24
Peak memory 232260 kb
Host smart-da6131cc-9a1d-44a8-be95-a43f93696cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807984743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.2807984743
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.226520864
Short name T649
Test name
Test status
Simulation time 12781569 ps
CPU time 0.71 seconds
Started Jul 12 06:32:26 PM PDT 24
Finished Jul 12 06:32:28 PM PDT 24
Peak memory 204776 kb
Host smart-809e32b1-4b6d-4909-817b-0392dcfc01d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226520864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.226520864
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.3308199153
Short name T813
Test name
Test status
Simulation time 950112495 ps
CPU time 2.63 seconds
Started Jul 12 06:32:23 PM PDT 24
Finished Jul 12 06:32:28 PM PDT 24
Peak memory 224344 kb
Host smart-b09e7d21-9d61-4008-b3fe-c0aed305c095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308199153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.3308199153
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.2275300688
Short name T437
Test name
Test status
Simulation time 15691165 ps
CPU time 0.75 seconds
Started Jul 12 06:32:23 PM PDT 24
Finished Jul 12 06:32:26 PM PDT 24
Peak memory 205792 kb
Host smart-d0b44896-fb4f-4429-8147-e68543a89261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275300688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.2275300688
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.2031644975
Short name T501
Test name
Test status
Simulation time 4040725546 ps
CPU time 11.7 seconds
Started Jul 12 06:32:24 PM PDT 24
Finished Jul 12 06:32:38 PM PDT 24
Peak memory 224864 kb
Host smart-4a634cd5-b95a-4a19-a2ad-c16cd0b51f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031644975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.2031644975
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.2366158893
Short name T128
Test name
Test status
Simulation time 43981163214 ps
CPU time 431.24 seconds
Started Jul 12 06:32:24 PM PDT 24
Finished Jul 12 06:39:37 PM PDT 24
Peak memory 262592 kb
Host smart-e53684a8-f174-4ba4-a5bc-d532e18d602d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366158893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.2366158893
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.2218988810
Short name T155
Test name
Test status
Simulation time 12255747697 ps
CPU time 76.67 seconds
Started Jul 12 06:32:23 PM PDT 24
Finished Jul 12 06:33:42 PM PDT 24
Peak memory 255464 kb
Host smart-fb73ba15-2891-4035-8299-2743e326d091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218988810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmd
s.2218988810
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_intercept.3712218346
Short name T577
Test name
Test status
Simulation time 5622103790 ps
CPU time 17.08 seconds
Started Jul 12 06:32:24 PM PDT 24
Finished Jul 12 06:32:42 PM PDT 24
Peak memory 218860 kb
Host smart-c95ca4f2-4603-4bfe-b5b8-d3ec18033d59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712218346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.3712218346
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.894742506
Short name T59
Test name
Test status
Simulation time 19382876069 ps
CPU time 61.16 seconds
Started Jul 12 06:32:26 PM PDT 24
Finished Jul 12 06:33:28 PM PDT 24
Peak memory 248860 kb
Host smart-13d1c936-46ae-406f-8f70-9d3901ed1df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894742506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.894742506
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.3088691264
Short name T225
Test name
Test status
Simulation time 4497186679 ps
CPU time 13.53 seconds
Started Jul 12 06:32:26 PM PDT 24
Finished Jul 12 06:32:41 PM PDT 24
Peak memory 223820 kb
Host smart-10186d24-856e-487c-8228-817cc6445e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088691264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.3088691264
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.2015519093
Short name T486
Test name
Test status
Simulation time 20923416892 ps
CPU time 14.75 seconds
Started Jul 12 06:32:24 PM PDT 24
Finished Jul 12 06:32:40 PM PDT 24
Peak memory 224552 kb
Host smart-c5025591-fb6c-471a-b9aa-316afc2243b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015519093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.2015519093
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.3338086684
Short name T412
Test name
Test status
Simulation time 762488055 ps
CPU time 4.17 seconds
Started Jul 12 06:32:24 PM PDT 24
Finished Jul 12 06:32:30 PM PDT 24
Peak memory 220496 kb
Host smart-d4d990d8-4a31-4d75-9e7a-4cb520740d90
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3338086684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.3338086684
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.6219892
Short name T129
Test name
Test status
Simulation time 179668725619 ps
CPU time 434.75 seconds
Started Jul 12 06:32:24 PM PDT 24
Finished Jul 12 06:39:41 PM PDT 24
Peak memory 273748 kb
Host smart-43097d91-7203-46e9-86f2-fb3e8115e93e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6219892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stress_
all.6219892
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.744156108
Short name T726
Test name
Test status
Simulation time 41965405707 ps
CPU time 59.25 seconds
Started Jul 12 06:32:24 PM PDT 24
Finished Jul 12 06:33:24 PM PDT 24
Peak memory 216364 kb
Host smart-fd870d24-be03-4139-8dd3-1c842e14fa25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744156108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.744156108
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.517185261
Short name T988
Test name
Test status
Simulation time 2372363773 ps
CPU time 3.69 seconds
Started Jul 12 06:32:21 PM PDT 24
Finished Jul 12 06:32:26 PM PDT 24
Peak memory 216224 kb
Host smart-f7ebb4b6-95e8-48f8-bdab-dc05a211af1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517185261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.517185261
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.643786843
Short name T846
Test name
Test status
Simulation time 43136191 ps
CPU time 2.03 seconds
Started Jul 12 06:32:22 PM PDT 24
Finished Jul 12 06:32:25 PM PDT 24
Peak memory 216100 kb
Host smart-a66897a8-df6b-4547-a125-2dfc879f6ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643786843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.643786843
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.1407197531
Short name T767
Test name
Test status
Simulation time 22424077 ps
CPU time 0.77 seconds
Started Jul 12 06:32:23 PM PDT 24
Finished Jul 12 06:32:25 PM PDT 24
Peak memory 205928 kb
Host smart-dafda3ec-1da5-45a2-86b7-d7c23bf999d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407197531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.1407197531
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.2064480921
Short name T610
Test name
Test status
Simulation time 9611153934 ps
CPU time 7.28 seconds
Started Jul 12 06:32:24 PM PDT 24
Finished Jul 12 06:32:33 PM PDT 24
Peak memory 232780 kb
Host smart-531a60fa-9b8a-442e-a2a7-92d48ae8d64c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064480921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.2064480921
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.4090543491
Short name T460
Test name
Test status
Simulation time 25984581 ps
CPU time 0.74 seconds
Started Jul 12 06:32:33 PM PDT 24
Finished Jul 12 06:32:34 PM PDT 24
Peak memory 205452 kb
Host smart-c5b9225e-f0e2-45ff-b364-51102810487e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090543491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
4090543491
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.273719473
Short name T751
Test name
Test status
Simulation time 175454055 ps
CPU time 3.12 seconds
Started Jul 12 06:32:33 PM PDT 24
Finished Jul 12 06:32:37 PM PDT 24
Peak memory 224456 kb
Host smart-8def6e3c-cb59-4843-8abc-d350f249b4b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273719473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.273719473
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.1887724869
Short name T908
Test name
Test status
Simulation time 24951528 ps
CPU time 0.75 seconds
Started Jul 12 06:32:23 PM PDT 24
Finished Jul 12 06:32:25 PM PDT 24
Peak memory 206812 kb
Host smart-baacbcfb-71ff-485e-b131-73029e6208b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887724869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.1887724869
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.772061096
Short name T250
Test name
Test status
Simulation time 80814500388 ps
CPU time 577.73 seconds
Started Jul 12 06:32:32 PM PDT 24
Finished Jul 12 06:42:10 PM PDT 24
Peak memory 265548 kb
Host smart-7408e0b3-4d90-4e52-aaa6-a0f0cbc48738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772061096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.772061096
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.1571711329
Short name T809
Test name
Test status
Simulation time 15763350211 ps
CPU time 98.02 seconds
Started Jul 12 06:32:33 PM PDT 24
Finished Jul 12 06:34:12 PM PDT 24
Peak memory 234848 kb
Host smart-f6e6e689-fd72-4236-acdd-685c0260e9cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571711329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.1571711329
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.3955709475
Short name T236
Test name
Test status
Simulation time 2694946671 ps
CPU time 53.42 seconds
Started Jul 12 06:32:32 PM PDT 24
Finished Jul 12 06:33:26 PM PDT 24
Peak memory 249672 kb
Host smart-9a120ff8-9960-4353-8fc6-9239d9a9a59c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955709475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.3955709475
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.3217842655
Short name T261
Test name
Test status
Simulation time 957680669 ps
CPU time 16.28 seconds
Started Jul 12 06:32:33 PM PDT 24
Finished Jul 12 06:32:50 PM PDT 24
Peak memory 249000 kb
Host smart-76afd991-2ca5-4949-94be-9929397bb456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217842655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.3217842655
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.172494923
Short name T852
Test name
Test status
Simulation time 381139458 ps
CPU time 4.94 seconds
Started Jul 12 06:32:32 PM PDT 24
Finished Jul 12 06:32:38 PM PDT 24
Peak memory 224360 kb
Host smart-1f0b0307-ae58-40ba-94fa-6d986e01ea45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172494923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.172494923
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.57291035
Short name T471
Test name
Test status
Simulation time 4520581767 ps
CPU time 15.29 seconds
Started Jul 12 06:32:34 PM PDT 24
Finished Jul 12 06:32:50 PM PDT 24
Peak memory 218824 kb
Host smart-7bfa0371-28d3-40df-b536-d0cc5ce76a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57291035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.57291035
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.1600107267
Short name T570
Test name
Test status
Simulation time 3892944913 ps
CPU time 5.79 seconds
Started Jul 12 06:32:34 PM PDT 24
Finished Jul 12 06:32:41 PM PDT 24
Peak memory 224480 kb
Host smart-80371d29-14d1-4917-9824-74bf14331ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600107267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.1600107267
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.1305713881
Short name T611
Test name
Test status
Simulation time 8260954160 ps
CPU time 10.3 seconds
Started Jul 12 06:32:32 PM PDT 24
Finished Jul 12 06:32:43 PM PDT 24
Peak memory 236092 kb
Host smart-7dce6af6-b159-4d3f-adff-02c8fd09f36b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305713881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.1305713881
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.589140939
Short name T386
Test name
Test status
Simulation time 2034151909 ps
CPU time 16.78 seconds
Started Jul 12 06:32:33 PM PDT 24
Finished Jul 12 06:32:51 PM PDT 24
Peak memory 219120 kb
Host smart-2b1b81ad-f9af-4983-9ef8-45238e9aa2d8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=589140939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dire
ct.589140939
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.2808897339
Short name T892
Test name
Test status
Simulation time 3801692323 ps
CPU time 65.69 seconds
Started Jul 12 06:32:35 PM PDT 24
Finished Jul 12 06:33:42 PM PDT 24
Peak memory 239224 kb
Host smart-0dcb5da6-b738-4338-b54e-d63dcb00ccb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808897339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.2808897339
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.3659864881
Short name T278
Test name
Test status
Simulation time 26900473402 ps
CPU time 37.15 seconds
Started Jul 12 06:32:23 PM PDT 24
Finished Jul 12 06:33:01 PM PDT 24
Peak memory 216224 kb
Host smart-5142831a-c08f-49ac-820a-52f2d414a2da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659864881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.3659864881
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.3156105546
Short name T590
Test name
Test status
Simulation time 47376856135 ps
CPU time 12.89 seconds
Started Jul 12 06:32:29 PM PDT 24
Finished Jul 12 06:32:43 PM PDT 24
Peak memory 216312 kb
Host smart-d4cd2b3c-373e-4bf2-a30b-de9cbb05793d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156105546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.3156105546
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.1144614746
Short name T277
Test name
Test status
Simulation time 85086641 ps
CPU time 2.52 seconds
Started Jul 12 06:32:35 PM PDT 24
Finished Jul 12 06:32:38 PM PDT 24
Peak memory 216208 kb
Host smart-382dac97-2d41-40de-882c-d5b1387e3ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144614746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.1144614746
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.3112347186
Short name T929
Test name
Test status
Simulation time 87539405 ps
CPU time 0.96 seconds
Started Jul 12 06:32:33 PM PDT 24
Finished Jul 12 06:32:35 PM PDT 24
Peak memory 206424 kb
Host smart-a52d0301-5c71-4345-b19b-bb0f4776fe72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112347186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.3112347186
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.117912241
Short name T579
Test name
Test status
Simulation time 8599844700 ps
CPU time 9.4 seconds
Started Jul 12 06:32:34 PM PDT 24
Finished Jul 12 06:32:44 PM PDT 24
Peak memory 232740 kb
Host smart-9007f736-022a-4084-857c-4cbacc94ae41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117912241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.117912241
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.3249840454
Short name T906
Test name
Test status
Simulation time 31483754 ps
CPU time 0.7 seconds
Started Jul 12 06:31:04 PM PDT 24
Finished Jul 12 06:31:06 PM PDT 24
Peak memory 204924 kb
Host smart-fc1582fb-1535-4003-a49c-c9092e8103a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249840454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.3
249840454
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.1718706422
Short name T845
Test name
Test status
Simulation time 532925583 ps
CPU time 5.16 seconds
Started Jul 12 06:31:01 PM PDT 24
Finished Jul 12 06:31:08 PM PDT 24
Peak memory 232532 kb
Host smart-252ec009-8909-4d58-9426-481e17c96028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718706422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.1718706422
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.2928344256
Short name T898
Test name
Test status
Simulation time 189626286 ps
CPU time 0.77 seconds
Started Jul 12 06:31:00 PM PDT 24
Finished Jul 12 06:31:02 PM PDT 24
Peak memory 206884 kb
Host smart-707bb72c-ea05-406f-a32b-5a6a9141843e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928344256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.2928344256
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.566877458
Short name T949
Test name
Test status
Simulation time 119197448509 ps
CPU time 169.53 seconds
Started Jul 12 06:30:59 PM PDT 24
Finished Jul 12 06:33:49 PM PDT 24
Peak memory 232820 kb
Host smart-db022d10-00f0-44ab-85b9-d9ac5bac21a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566877458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle.
566877458
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.439879694
Short name T262
Test name
Test status
Simulation time 5117162047 ps
CPU time 24.29 seconds
Started Jul 12 06:31:01 PM PDT 24
Finished Jul 12 06:31:27 PM PDT 24
Peak memory 224524 kb
Host smart-7130abb6-f9c8-4420-8f7c-075dc90ee344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439879694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.439879694
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.3649423732
Short name T617
Test name
Test status
Simulation time 75004659684 ps
CPU time 121.71 seconds
Started Jul 12 06:31:01 PM PDT 24
Finished Jul 12 06:33:04 PM PDT 24
Peak memory 255448 kb
Host smart-56add67c-2dc3-4a8f-8aab-9fd76cabc8c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649423732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds
.3649423732
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.824500376
Short name T1010
Test name
Test status
Simulation time 503614356 ps
CPU time 3.76 seconds
Started Jul 12 06:31:04 PM PDT 24
Finished Jul 12 06:31:09 PM PDT 24
Peak memory 224348 kb
Host smart-32889e60-c77b-4623-b6ed-3d84433d1bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824500376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.824500376
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.3220842859
Short name T214
Test name
Test status
Simulation time 5760813555 ps
CPU time 54.47 seconds
Started Jul 12 06:31:01 PM PDT 24
Finished Jul 12 06:31:57 PM PDT 24
Peak memory 240704 kb
Host smart-5e150a2e-1e00-47a1-bd1c-e6aea72ba317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220842859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.3220842859
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.3122859540
Short name T525
Test name
Test status
Simulation time 7867347672 ps
CPU time 21.62 seconds
Started Jul 12 06:31:04 PM PDT 24
Finished Jul 12 06:31:27 PM PDT 24
Peak memory 240456 kb
Host smart-d315eaee-a46a-415c-adc1-24b949d92bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122859540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.3122859540
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.221197359
Short name T656
Test name
Test status
Simulation time 24870382167 ps
CPU time 7.28 seconds
Started Jul 12 06:31:03 PM PDT 24
Finished Jul 12 06:31:12 PM PDT 24
Peak memory 224572 kb
Host smart-e838efee-aab8-4457-8401-bc7ff9abe931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221197359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.221197359
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.3578134089
Short name T318
Test name
Test status
Simulation time 125360361 ps
CPU time 3.96 seconds
Started Jul 12 06:31:01 PM PDT 24
Finished Jul 12 06:31:07 PM PDT 24
Peak memory 224144 kb
Host smart-b9f2d0e7-9c83-4e76-ae6e-6d419d90acf0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3578134089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.3578134089
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.3863599488
Short name T68
Test name
Test status
Simulation time 112322968 ps
CPU time 1.11 seconds
Started Jul 12 06:31:01 PM PDT 24
Finished Jul 12 06:31:04 PM PDT 24
Peak memory 236440 kb
Host smart-81df9c61-7b4d-424b-b8b4-c27f2f3bdca5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863599488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.3863599488
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.1706152971
Short name T778
Test name
Test status
Simulation time 3994837585 ps
CPU time 104.62 seconds
Started Jul 12 06:31:01 PM PDT 24
Finished Jul 12 06:32:48 PM PDT 24
Peak memory 255416 kb
Host smart-0c78a7c3-d1fb-4796-bc41-6bb57f2bdb2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706152971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.1706152971
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.1459157363
Short name T274
Test name
Test status
Simulation time 3617729981 ps
CPU time 9.31 seconds
Started Jul 12 06:31:00 PM PDT 24
Finished Jul 12 06:31:10 PM PDT 24
Peak memory 216272 kb
Host smart-9c451df8-046b-4fcd-9a9d-2b3dbe65cdff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459157363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.1459157363
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.4120234636
Short name T776
Test name
Test status
Simulation time 1038637921 ps
CPU time 5.97 seconds
Started Jul 12 06:31:02 PM PDT 24
Finished Jul 12 06:31:10 PM PDT 24
Peak memory 216144 kb
Host smart-0530f318-647e-42ca-8885-846cc2a4fc74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120234636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.4120234636
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.2287102779
Short name T524
Test name
Test status
Simulation time 18450705 ps
CPU time 0.84 seconds
Started Jul 12 06:31:00 PM PDT 24
Finished Jul 12 06:31:02 PM PDT 24
Peak memory 205920 kb
Host smart-257c4405-23e6-4bbe-b731-6ab00f3b0a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287102779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.2287102779
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.3304472959
Short name T300
Test name
Test status
Simulation time 30257114 ps
CPU time 0.69 seconds
Started Jul 12 06:31:03 PM PDT 24
Finished Jul 12 06:31:05 PM PDT 24
Peak memory 205580 kb
Host smart-9e04838a-4a44-49d4-a057-e607c97d9871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304472959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.3304472959
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.2753191906
Short name T866
Test name
Test status
Simulation time 7613171383 ps
CPU time 8.75 seconds
Started Jul 12 06:31:02 PM PDT 24
Finished Jul 12 06:31:12 PM PDT 24
Peak memory 224432 kb
Host smart-6736c8df-1b78-442d-8e62-c575d30e51fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753191906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.2753191906
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.3122773199
Short name T974
Test name
Test status
Simulation time 12715084 ps
CPU time 0.73 seconds
Started Jul 12 06:32:49 PM PDT 24
Finished Jul 12 06:32:52 PM PDT 24
Peak memory 205644 kb
Host smart-8b255965-9158-44e0-8e4b-491b99425734
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122773199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
3122773199
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.168165198
Short name T554
Test name
Test status
Simulation time 2456353271 ps
CPU time 7.64 seconds
Started Jul 12 06:55:55 PM PDT 24
Finished Jul 12 06:56:04 PM PDT 24
Peak memory 232820 kb
Host smart-dbeb01df-9fa6-495f-bcbf-987d8a2427e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168165198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.168165198
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.1943314627
Short name T353
Test name
Test status
Simulation time 25810056 ps
CPU time 0.82 seconds
Started Jul 12 06:32:33 PM PDT 24
Finished Jul 12 06:32:35 PM PDT 24
Peak memory 206556 kb
Host smart-5352f9e7-83bd-4036-88ab-e62e73844be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943314627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.1943314627
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.2303131248
Short name T226
Test name
Test status
Simulation time 28939048374 ps
CPU time 217.04 seconds
Started Jul 12 06:32:40 PM PDT 24
Finished Jul 12 06:36:18 PM PDT 24
Peak memory 253984 kb
Host smart-b4226505-e857-4bb3-95ff-7cc38982d8c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303131248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.2303131248
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.675381911
Short name T244
Test name
Test status
Simulation time 95766732979 ps
CPU time 487.69 seconds
Started Jul 12 06:32:43 PM PDT 24
Finished Jul 12 06:40:52 PM PDT 24
Peak memory 255784 kb
Host smart-f0d225c9-dba0-4eb0-a02f-99d0e438d82f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675381911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.675381911
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.3290936361
Short name T219
Test name
Test status
Simulation time 116139451862 ps
CPU time 262 seconds
Started Jul 12 06:32:44 PM PDT 24
Finished Jul 12 06:37:07 PM PDT 24
Peak memory 249208 kb
Host smart-c1137ace-28d6-45c7-8f2f-05ee730c4d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290936361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.3290936361
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.3587597469
Short name T997
Test name
Test status
Simulation time 1484945681 ps
CPU time 8.2 seconds
Started Jul 12 06:32:42 PM PDT 24
Finished Jul 12 06:32:51 PM PDT 24
Peak memory 224448 kb
Host smart-4e456f8e-a567-4f37-ab07-de25e7b42733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587597469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.3587597469
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.2706580593
Short name T953
Test name
Test status
Simulation time 3607225378 ps
CPU time 66.8 seconds
Started Jul 12 06:32:49 PM PDT 24
Finished Jul 12 06:33:58 PM PDT 24
Peak memory 253076 kb
Host smart-2132f740-dd95-4481-a268-0896cf320aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706580593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmd
s.2706580593
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_intercept.4056568658
Short name T410
Test name
Test status
Simulation time 202681600 ps
CPU time 5.04 seconds
Started Jul 12 06:32:49 PM PDT 24
Finished Jul 12 06:32:56 PM PDT 24
Peak memory 224376 kb
Host smart-b3b971f1-f4c8-4172-aca8-3e4cf655fb15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056568658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.4056568658
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.987233262
Short name T192
Test name
Test status
Simulation time 11702370066 ps
CPU time 95.1 seconds
Started Jul 12 06:32:40 PM PDT 24
Finished Jul 12 06:34:16 PM PDT 24
Peak memory 232700 kb
Host smart-0380767f-0f44-4eae-9dc3-8ad36ef13212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987233262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.987233262
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.2833069604
Short name T659
Test name
Test status
Simulation time 194628711 ps
CPU time 3.99 seconds
Started Jul 12 06:32:44 PM PDT 24
Finished Jul 12 06:32:49 PM PDT 24
Peak memory 232568 kb
Host smart-950acd22-851d-4c8d-a745-a1a1f4fb829f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833069604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.2833069604
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.3753846109
Short name T424
Test name
Test status
Simulation time 362488245 ps
CPU time 5.87 seconds
Started Jul 12 06:32:35 PM PDT 24
Finished Jul 12 06:32:41 PM PDT 24
Peak memory 232604 kb
Host smart-daa10451-cd38-410a-b4d8-d58631fd0b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753846109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.3753846109
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.2677572142
Short name T39
Test name
Test status
Simulation time 26315996941 ps
CPU time 13.23 seconds
Started Jul 12 06:32:39 PM PDT 24
Finished Jul 12 06:32:53 PM PDT 24
Peak memory 220652 kb
Host smart-a7644cd6-791e-4a2d-99a3-0bf47a4324b5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2677572142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.2677572142
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.2429816046
Short name T499
Test name
Test status
Simulation time 5091459125 ps
CPU time 109.43 seconds
Started Jul 12 06:32:43 PM PDT 24
Finished Jul 12 06:34:34 PM PDT 24
Peak memory 261212 kb
Host smart-82f01db1-8b7d-458b-a869-f3901764d975
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429816046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.2429816046
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.313297653
Short name T527
Test name
Test status
Simulation time 3960970815 ps
CPU time 16.85 seconds
Started Jul 12 06:32:35 PM PDT 24
Finished Jul 12 06:32:53 PM PDT 24
Peak memory 216420 kb
Host smart-2ee40adc-992f-4e4e-bb6e-ef4de724a056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313297653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.313297653
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.2661942402
Short name T859
Test name
Test status
Simulation time 4837726433 ps
CPU time 8.31 seconds
Started Jul 12 06:32:34 PM PDT 24
Finished Jul 12 06:32:43 PM PDT 24
Peak memory 216260 kb
Host smart-80551dd5-4ff1-4727-8356-9a27181123ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661942402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.2661942402
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.334861781
Short name T535
Test name
Test status
Simulation time 13790193 ps
CPU time 0.71 seconds
Started Jul 12 06:32:33 PM PDT 24
Finished Jul 12 06:32:35 PM PDT 24
Peak memory 205596 kb
Host smart-a1f15b52-8249-4ead-b259-7cc54b17c5de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334861781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.334861781
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.4262229560
Short name T883
Test name
Test status
Simulation time 122428966 ps
CPU time 0.98 seconds
Started Jul 12 06:32:33 PM PDT 24
Finished Jul 12 06:32:34 PM PDT 24
Peak memory 205924 kb
Host smart-16712a8f-a918-41cc-91f6-72f22008e171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262229560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.4262229560
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.1568930018
Short name T417
Test name
Test status
Simulation time 3961834371 ps
CPU time 14.43 seconds
Started Jul 12 06:32:40 PM PDT 24
Finished Jul 12 06:32:55 PM PDT 24
Peak memory 240916 kb
Host smart-8fd482c3-195d-4721-aa39-5be659d62ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568930018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.1568930018
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.1083689868
Short name T391
Test name
Test status
Simulation time 41839722 ps
CPU time 0.71 seconds
Started Jul 12 06:32:41 PM PDT 24
Finished Jul 12 06:32:42 PM PDT 24
Peak memory 205468 kb
Host smart-019977b5-e6dd-48e4-bc7d-552381a4fe12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083689868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
1083689868
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.1417634181
Short name T683
Test name
Test status
Simulation time 15609867521 ps
CPU time 11.62 seconds
Started Jul 12 06:32:45 PM PDT 24
Finished Jul 12 06:32:58 PM PDT 24
Peak memory 224500 kb
Host smart-98997480-b6d3-43fd-b2d0-cc28053f4d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417634181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.1417634181
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.3304246523
Short name T547
Test name
Test status
Simulation time 18559308 ps
CPU time 0.78 seconds
Started Jul 12 06:32:39 PM PDT 24
Finished Jul 12 06:32:40 PM PDT 24
Peak memory 206556 kb
Host smart-25f90fa1-b54e-4087-828b-db81a3e7d0c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304246523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.3304246523
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.1190679036
Short name T828
Test name
Test status
Simulation time 3428065276 ps
CPU time 39.13 seconds
Started Jul 12 06:32:39 PM PDT 24
Finished Jul 12 06:33:19 PM PDT 24
Peak memory 232784 kb
Host smart-c61915eb-ca44-454c-82c4-eabc4edadfff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190679036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.1190679036
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.2650046762
Short name T970
Test name
Test status
Simulation time 13424629388 ps
CPU time 70.04 seconds
Started Jul 12 06:32:45 PM PDT 24
Finished Jul 12 06:33:55 PM PDT 24
Peak memory 236544 kb
Host smart-22ed5f03-cd8c-4e9b-9015-953ae50195a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650046762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.2650046762
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.2982911925
Short name T385
Test name
Test status
Simulation time 1423980509 ps
CPU time 4.01 seconds
Started Jul 12 06:32:44 PM PDT 24
Finished Jul 12 06:32:49 PM PDT 24
Peak memory 224360 kb
Host smart-8082eec4-210c-4e01-b27c-90e8e48a5ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982911925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.2982911925
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.1211715051
Short name T213
Test name
Test status
Simulation time 1867686600 ps
CPU time 29.12 seconds
Started Jul 12 06:32:42 PM PDT 24
Finished Jul 12 06:33:12 PM PDT 24
Peak memory 249020 kb
Host smart-ec9e340f-a4eb-49a1-b72f-ab40204aaf78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211715051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmd
s.1211715051
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.4075367549
Short name T983
Test name
Test status
Simulation time 23928654867 ps
CPU time 16.15 seconds
Started Jul 12 06:32:44 PM PDT 24
Finished Jul 12 06:33:01 PM PDT 24
Peak memory 224588 kb
Host smart-304252f8-fa41-4e75-a7b8-fe5657965d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075367549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.4075367549
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.2024121498
Short name T918
Test name
Test status
Simulation time 12887335800 ps
CPU time 137.03 seconds
Started Jul 12 06:32:40 PM PDT 24
Finished Jul 12 06:34:58 PM PDT 24
Peak memory 240372 kb
Host smart-453c99d3-035e-4db6-a1f9-9c71597a0d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024121498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.2024121498
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.2589696217
Short name T434
Test name
Test status
Simulation time 490145185 ps
CPU time 6.5 seconds
Started Jul 12 06:32:44 PM PDT 24
Finished Jul 12 06:32:51 PM PDT 24
Peak memory 224400 kb
Host smart-88a924b7-1281-4643-a9a5-67db92f516c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589696217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.2589696217
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.1944176521
Short name T380
Test name
Test status
Simulation time 1486684825 ps
CPU time 5 seconds
Started Jul 12 06:32:42 PM PDT 24
Finished Jul 12 06:32:48 PM PDT 24
Peak memory 224472 kb
Host smart-5adcbd7b-63c2-4427-b5cd-7e49380914ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944176521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.1944176521
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.2093900379
Short name T27
Test name
Test status
Simulation time 1218315531 ps
CPU time 5.21 seconds
Started Jul 12 06:32:43 PM PDT 24
Finished Jul 12 06:32:50 PM PDT 24
Peak memory 218620 kb
Host smart-f1358cc1-dc22-42d7-990e-4e10aceee45b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2093900379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.2093900379
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.1435979331
Short name T30
Test name
Test status
Simulation time 123526484124 ps
CPU time 325.91 seconds
Started Jul 12 06:32:41 PM PDT 24
Finished Jul 12 06:38:08 PM PDT 24
Peak memory 265332 kb
Host smart-5512c9d9-d76f-48ef-b79b-977cb8145c4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435979331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.1435979331
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.3915472820
Short name T71
Test name
Test status
Simulation time 2253119329 ps
CPU time 8.84 seconds
Started Jul 12 06:32:38 PM PDT 24
Finished Jul 12 06:32:48 PM PDT 24
Peak memory 219264 kb
Host smart-90471944-7ad8-480a-88a2-801f0aa144f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915472820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.3915472820
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.1981082065
Short name T317
Test name
Test status
Simulation time 19108571214 ps
CPU time 8 seconds
Started Jul 12 06:32:40 PM PDT 24
Finished Jul 12 06:32:48 PM PDT 24
Peak memory 216428 kb
Host smart-510a66db-a342-40a2-bf05-65b8c55fbf82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981082065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.1981082065
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.438612894
Short name T761
Test name
Test status
Simulation time 42703589 ps
CPU time 1.19 seconds
Started Jul 12 06:32:44 PM PDT 24
Finished Jul 12 06:32:46 PM PDT 24
Peak memory 207780 kb
Host smart-10f76044-c8bc-4d3e-b7c6-c55b43fb9dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438612894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.438612894
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.2345908891
Short name T293
Test name
Test status
Simulation time 50935913 ps
CPU time 0.89 seconds
Started Jul 12 06:32:42 PM PDT 24
Finished Jul 12 06:32:44 PM PDT 24
Peak memory 205924 kb
Host smart-d5bdad1a-7b2d-4803-9047-2d250fe3c3e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345908891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.2345908891
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.1609724888
Short name T960
Test name
Test status
Simulation time 14308264672 ps
CPU time 10.22 seconds
Started Jul 12 06:32:40 PM PDT 24
Finished Jul 12 06:32:51 PM PDT 24
Peak memory 232584 kb
Host smart-0dda214d-6726-4fce-a0b1-4a5318457922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609724888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.1609724888
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.3710369344
Short name T848
Test name
Test status
Simulation time 92951189 ps
CPU time 0.7 seconds
Started Jul 12 06:32:53 PM PDT 24
Finished Jul 12 06:32:54 PM PDT 24
Peak memory 205468 kb
Host smart-de42c9b1-53d0-44d0-a490-ca9510806631
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710369344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
3710369344
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.2736334459
Short name T622
Test name
Test status
Simulation time 1075050463 ps
CPU time 9.39 seconds
Started Jul 12 06:32:48 PM PDT 24
Finished Jul 12 06:32:58 PM PDT 24
Peak memory 232596 kb
Host smart-58d9ef99-5ed9-4bff-b8e8-4ca8f5f6cee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736334459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.2736334459
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.1082673339
Short name T655
Test name
Test status
Simulation time 17444607 ps
CPU time 0.78 seconds
Started Jul 12 06:32:43 PM PDT 24
Finished Jul 12 06:32:45 PM PDT 24
Peak memory 205808 kb
Host smart-b08f9d89-a073-4569-a357-fd05fed05825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082673339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.1082673339
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.1319797657
Short name T693
Test name
Test status
Simulation time 13060760143 ps
CPU time 181.42 seconds
Started Jul 12 06:32:48 PM PDT 24
Finished Jul 12 06:35:51 PM PDT 24
Peak memory 260616 kb
Host smart-33b615f0-9b19-44a6-a3f3-4ff88dfb36c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319797657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.1319797657
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.1544405412
Short name T933
Test name
Test status
Simulation time 4084498941 ps
CPU time 14.39 seconds
Started Jul 12 06:32:48 PM PDT 24
Finished Jul 12 06:33:04 PM PDT 24
Peak memory 232828 kb
Host smart-e6bf6fab-68bc-496c-9f84-efbfdfb721ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544405412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.1544405412
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.3310679943
Short name T770
Test name
Test status
Simulation time 361433153 ps
CPU time 3.26 seconds
Started Jul 12 06:32:46 PM PDT 24
Finished Jul 12 06:32:50 PM PDT 24
Peak memory 232652 kb
Host smart-838d72f8-6569-460c-98ab-2a1b677ca72b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310679943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.3310679943
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.4050680805
Short name T254
Test name
Test status
Simulation time 33147234263 ps
CPU time 60.2 seconds
Started Jul 12 06:32:47 PM PDT 24
Finished Jul 12 06:33:49 PM PDT 24
Peak memory 256456 kb
Host smart-f0739686-3f12-4c91-83c7-223b7ed90c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050680805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmd
s.4050680805
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.178373375
Short name T787
Test name
Test status
Simulation time 107901816 ps
CPU time 2.35 seconds
Started Jul 12 06:32:41 PM PDT 24
Finished Jul 12 06:32:44 PM PDT 24
Peak memory 232344 kb
Host smart-412a55d0-ff2d-42de-9749-f9548049d56f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178373375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.178373375
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.2357446221
Short name T905
Test name
Test status
Simulation time 552499617 ps
CPU time 9.64 seconds
Started Jul 12 06:32:48 PM PDT 24
Finished Jul 12 06:32:59 PM PDT 24
Peak memory 240776 kb
Host smart-0bd39345-6459-48d0-8707-39c7b7fe1f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357446221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.2357446221
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.269304623
Short name T476
Test name
Test status
Simulation time 255918377 ps
CPU time 3.26 seconds
Started Jul 12 06:32:39 PM PDT 24
Finished Jul 12 06:32:43 PM PDT 24
Peak memory 232536 kb
Host smart-f6b1fac7-7b88-4e8d-8a7e-3b2ea7d4a6a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269304623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swap
.269304623
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.61067172
Short name T329
Test name
Test status
Simulation time 606864735 ps
CPU time 3.57 seconds
Started Jul 12 06:32:41 PM PDT 24
Finished Jul 12 06:32:46 PM PDT 24
Peak memory 232612 kb
Host smart-f930d04d-a268-4ad7-a607-492523bf1f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61067172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.61067172
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.3816473823
Short name T135
Test name
Test status
Simulation time 4509067764 ps
CPU time 10.3 seconds
Started Jul 12 06:32:49 PM PDT 24
Finished Jul 12 06:33:01 PM PDT 24
Peak memory 221076 kb
Host smart-de6e28f3-2a05-4eb1-919f-f91299d2877a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3816473823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.3816473823
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.474979569
Short name T152
Test name
Test status
Simulation time 21630230911 ps
CPU time 89.85 seconds
Started Jul 12 06:32:48 PM PDT 24
Finished Jul 12 06:34:20 PM PDT 24
Peak memory 256976 kb
Host smart-c790fca4-861f-4e99-8270-397a73f06f38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474979569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stres
s_all.474979569
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.1092962717
Short name T891
Test name
Test status
Simulation time 32745308884 ps
CPU time 41.79 seconds
Started Jul 12 06:32:41 PM PDT 24
Finished Jul 12 06:33:23 PM PDT 24
Peak memory 216304 kb
Host smart-61ac4e21-bdfa-4932-ae5e-32c5cb6e2ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092962717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.1092962717
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.1748440408
Short name T981
Test name
Test status
Simulation time 20479155402 ps
CPU time 16.3 seconds
Started Jul 12 06:32:41 PM PDT 24
Finished Jul 12 06:32:58 PM PDT 24
Peak memory 216228 kb
Host smart-8298bcfa-b629-4928-a02e-deccbb87d81a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748440408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.1748440408
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.3492881762
Short name T496
Test name
Test status
Simulation time 34346199 ps
CPU time 0.86 seconds
Started Jul 12 06:32:49 PM PDT 24
Finished Jul 12 06:32:52 PM PDT 24
Peak memory 206580 kb
Host smart-1e7c206f-6989-408d-a639-d1cbba20dd3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492881762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.3492881762
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.2768658074
Short name T334
Test name
Test status
Simulation time 15447822 ps
CPU time 0.71 seconds
Started Jul 12 06:32:42 PM PDT 24
Finished Jul 12 06:32:44 PM PDT 24
Peak memory 205596 kb
Host smart-f84546ff-6450-4fdb-98d1-dc6ba8ab2134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768658074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.2768658074
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.626189544
Short name T561
Test name
Test status
Simulation time 60993665 ps
CPU time 1.98 seconds
Started Jul 12 06:32:51 PM PDT 24
Finished Jul 12 06:32:54 PM PDT 24
Peak memory 224108 kb
Host smart-776ca8d3-6f87-4b10-91fb-f2be981c3a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626189544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.626189544
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.4175270332
Short name T784
Test name
Test status
Simulation time 39289940 ps
CPU time 0.73 seconds
Started Jul 12 06:32:48 PM PDT 24
Finished Jul 12 06:32:50 PM PDT 24
Peak memory 205452 kb
Host smart-5a8d4972-bbda-4a9e-88b2-13a435d5c0bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175270332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
4175270332
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.2623559081
Short name T456
Test name
Test status
Simulation time 81623774 ps
CPU time 2.83 seconds
Started Jul 12 06:32:47 PM PDT 24
Finished Jul 12 06:32:51 PM PDT 24
Peak memory 224396 kb
Host smart-c9c55d8e-b98a-47bd-af89-31ab6b64e40e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623559081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.2623559081
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.572628246
Short name T429
Test name
Test status
Simulation time 25009587 ps
CPU time 0.81 seconds
Started Jul 12 06:32:50 PM PDT 24
Finished Jul 12 06:32:52 PM PDT 24
Peak memory 206520 kb
Host smart-e67cfb53-ff8a-4cef-a89a-705c4658281a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572628246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.572628246
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.414575448
Short name T461
Test name
Test status
Simulation time 92727496308 ps
CPU time 194.55 seconds
Started Jul 12 06:32:51 PM PDT 24
Finished Jul 12 06:36:07 PM PDT 24
Peak memory 253432 kb
Host smart-456e3c05-2b54-4a93-87ce-f34c40847361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414575448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.414575448
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.1235536686
Short name T134
Test name
Test status
Simulation time 110366661799 ps
CPU time 254.28 seconds
Started Jul 12 06:32:49 PM PDT 24
Finished Jul 12 06:37:05 PM PDT 24
Peak memory 256216 kb
Host smart-f27facf1-63d4-4993-9c91-95170759002f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235536686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.1235536686
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.4011314868
Short name T1006
Test name
Test status
Simulation time 45527841844 ps
CPU time 143.34 seconds
Started Jul 12 06:32:48 PM PDT 24
Finished Jul 12 06:35:14 PM PDT 24
Peak memory 251628 kb
Host smart-17e24783-eb66-4e3a-a035-4bb79eb8643f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011314868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.4011314868
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.59197968
Short name T375
Test name
Test status
Simulation time 1607403890 ps
CPU time 25.14 seconds
Started Jul 12 06:36:31 PM PDT 24
Finished Jul 12 06:36:57 PM PDT 24
Peak memory 233572 kb
Host smart-55bd3864-6a89-45b5-8a94-10b20e0832d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59197968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.59197968
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.1431857084
Short name T85
Test name
Test status
Simulation time 4722292052 ps
CPU time 25.04 seconds
Started Jul 12 06:32:47 PM PDT 24
Finished Jul 12 06:33:13 PM PDT 24
Peak memory 250440 kb
Host smart-4e630d6d-1025-4f37-985e-851cdca890cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431857084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmd
s.1431857084
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.2910450962
Short name T849
Test name
Test status
Simulation time 3990546879 ps
CPU time 18.77 seconds
Started Jul 12 06:32:50 PM PDT 24
Finished Jul 12 06:33:10 PM PDT 24
Peak memory 224440 kb
Host smart-f3389971-d829-4b2a-8551-7d5049c39f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910450962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.2910450962
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.2877450869
Short name T788
Test name
Test status
Simulation time 454155884 ps
CPU time 10.45 seconds
Started Jul 12 06:32:50 PM PDT 24
Finished Jul 12 06:33:03 PM PDT 24
Peak memory 238492 kb
Host smart-20938274-e95d-48eb-9f27-5a97da4c5039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877450869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.2877450869
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.3062429730
Short name T201
Test name
Test status
Simulation time 7635102052 ps
CPU time 18.87 seconds
Started Jul 12 06:32:46 PM PDT 24
Finished Jul 12 06:33:05 PM PDT 24
Peak memory 248828 kb
Host smart-0e69a5a6-b266-41cf-b8f1-b9dd6c86ee61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062429730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.3062429730
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.2228596061
Short name T450
Test name
Test status
Simulation time 4309876527 ps
CPU time 18.63 seconds
Started Jul 12 06:32:49 PM PDT 24
Finished Jul 12 06:33:10 PM PDT 24
Peak memory 240948 kb
Host smart-cb8ced26-80cd-4464-9980-232123b53fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228596061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.2228596061
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.574385338
Short name T777
Test name
Test status
Simulation time 288917237 ps
CPU time 5.27 seconds
Started Jul 12 06:32:50 PM PDT 24
Finished Jul 12 06:32:57 PM PDT 24
Peak memory 223060 kb
Host smart-01ab2a3e-8f99-4f94-ad95-ec42db2d475f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=574385338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dire
ct.574385338
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.1181411959
Short name T587
Test name
Test status
Simulation time 20761486815 ps
CPU time 30.86 seconds
Started Jul 12 06:32:50 PM PDT 24
Finished Jul 12 06:33:23 PM PDT 24
Peak memory 216316 kb
Host smart-9f1ffc89-d743-4f5d-bf64-56311f215286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181411959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.1181411959
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.3582348202
Short name T1001
Test name
Test status
Simulation time 1219291681 ps
CPU time 9.11 seconds
Started Jul 12 06:32:48 PM PDT 24
Finished Jul 12 06:32:59 PM PDT 24
Peak memory 216108 kb
Host smart-d218c742-16e5-46c9-850c-4cfacfe59989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582348202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.3582348202
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.393347951
Short name T546
Test name
Test status
Simulation time 191502900 ps
CPU time 2.05 seconds
Started Jul 12 06:32:50 PM PDT 24
Finished Jul 12 06:32:54 PM PDT 24
Peak memory 216128 kb
Host smart-7f9bc226-835a-450e-b36b-1acc51edff87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393347951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.393347951
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.2293997707
Short name T297
Test name
Test status
Simulation time 593354440 ps
CPU time 0.99 seconds
Started Jul 12 06:32:47 PM PDT 24
Finished Jul 12 06:32:49 PM PDT 24
Peak memory 206960 kb
Host smart-1637908c-3bb5-40bd-a72f-2b3c9334b0af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293997707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.2293997707
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.708552823
Short name T567
Test name
Test status
Simulation time 1161551346 ps
CPU time 9.52 seconds
Started Jul 12 06:32:52 PM PDT 24
Finished Jul 12 06:33:03 PM PDT 24
Peak memory 232604 kb
Host smart-76993e73-05b9-43d1-a466-84ab002b4ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708552823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.708552823
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.3032806375
Short name T287
Test name
Test status
Simulation time 35233728 ps
CPU time 0.72 seconds
Started Jul 12 06:32:57 PM PDT 24
Finished Jul 12 06:33:00 PM PDT 24
Peak memory 205792 kb
Host smart-8eebe60a-42c6-481c-8ae8-d665d0bbc933
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032806375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
3032806375
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.3773185335
Short name T690
Test name
Test status
Simulation time 7237875941 ps
CPU time 10 seconds
Started Jul 12 06:32:56 PM PDT 24
Finished Jul 12 06:33:08 PM PDT 24
Peak memory 232644 kb
Host smart-3e271479-dff4-4581-8ce1-b9e4b8a5a439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773185335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.3773185335
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.3594736005
Short name T937
Test name
Test status
Simulation time 151294665 ps
CPU time 0.77 seconds
Started Jul 12 06:32:48 PM PDT 24
Finished Jul 12 06:32:51 PM PDT 24
Peak memory 206840 kb
Host smart-290715a3-2da1-4d7e-be5a-1a514172db0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594736005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.3594736005
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.3403781554
Short name T927
Test name
Test status
Simulation time 61364736 ps
CPU time 0.78 seconds
Started Jul 12 06:32:58 PM PDT 24
Finished Jul 12 06:33:01 PM PDT 24
Peak memory 215744 kb
Host smart-08a8a04d-54d5-4650-abb7-d83f84c90dfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403781554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.3403781554
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.653695838
Short name T363
Test name
Test status
Simulation time 1474097955 ps
CPU time 30.62 seconds
Started Jul 12 06:32:57 PM PDT 24
Finished Jul 12 06:33:30 PM PDT 24
Peak memory 249624 kb
Host smart-7581138a-1591-4e2f-be0b-a30f174a9124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653695838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.653695838
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.2947875105
Short name T381
Test name
Test status
Simulation time 66839560710 ps
CPU time 181.17 seconds
Started Jul 12 06:32:54 PM PDT 24
Finished Jul 12 06:35:56 PM PDT 24
Peak memory 254256 kb
Host smart-c97b2874-9c3a-4d03-8803-b32579c6c9c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947875105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.2947875105
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.715364256
Short name T332
Test name
Test status
Simulation time 843183895 ps
CPU time 9.74 seconds
Started Jul 12 06:32:55 PM PDT 24
Finished Jul 12 06:33:06 PM PDT 24
Peak memory 224408 kb
Host smart-7763776e-afce-49a2-ac6f-cadb46c0c54b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715364256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.715364256
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.4274967140
Short name T880
Test name
Test status
Simulation time 7190380413 ps
CPU time 52.02 seconds
Started Jul 12 06:32:54 PM PDT 24
Finished Jul 12 06:33:47 PM PDT 24
Peak memory 257344 kb
Host smart-326d8b6a-b5f8-4291-8a65-eef36506d99b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274967140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmd
s.4274967140
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.3503648237
Short name T306
Test name
Test status
Simulation time 125841299 ps
CPU time 4.29 seconds
Started Jul 12 06:32:54 PM PDT 24
Finished Jul 12 06:32:59 PM PDT 24
Peak memory 224420 kb
Host smart-2b6448f4-3a51-4dc7-91d7-4efa9a251804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503648237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.3503648237
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.1376972443
Short name T510
Test name
Test status
Simulation time 466522329 ps
CPU time 3.98 seconds
Started Jul 12 06:32:56 PM PDT 24
Finished Jul 12 06:33:02 PM PDT 24
Peak memory 232584 kb
Host smart-67d8c345-4945-428e-b934-7e4dbe1929d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376972443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.1376972443
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.262540446
Short name T873
Test name
Test status
Simulation time 557928562 ps
CPU time 2.47 seconds
Started Jul 12 06:32:59 PM PDT 24
Finished Jul 12 06:33:02 PM PDT 24
Peak memory 232260 kb
Host smart-1eeb1295-9c30-47f7-93a7-6b60a1a1b1bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262540446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swap
.262540446
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.428235813
Short name T755
Test name
Test status
Simulation time 339347975 ps
CPU time 5.43 seconds
Started Jul 12 06:33:38 PM PDT 24
Finished Jul 12 06:33:45 PM PDT 24
Peak memory 232676 kb
Host smart-32bdacca-73d5-4bcf-af7d-e602ca622f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428235813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.428235813
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.376088722
Short name T741
Test name
Test status
Simulation time 4470602229 ps
CPU time 13.71 seconds
Started Jul 12 06:32:56 PM PDT 24
Finished Jul 12 06:33:11 PM PDT 24
Peak memory 220384 kb
Host smart-dd152945-6283-4303-878f-ec3269ff1027
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=376088722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dire
ct.376088722
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.2083074901
Short name T47
Test name
Test status
Simulation time 26570613097 ps
CPU time 318.86 seconds
Started Jul 12 06:32:57 PM PDT 24
Finished Jul 12 06:38:18 PM PDT 24
Peak memory 273772 kb
Host smart-77e183f1-54a0-4f50-8f12-c71704bb2ab1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083074901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.2083074901
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.3235406823
Short name T436
Test name
Test status
Simulation time 5264210144 ps
CPU time 34.34 seconds
Started Jul 12 06:32:55 PM PDT 24
Finished Jul 12 06:33:31 PM PDT 24
Peak memory 216264 kb
Host smart-e2f3f004-88f7-49ac-9a85-d92087edb9b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235406823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.3235406823
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.4107705862
Short name T8
Test name
Test status
Simulation time 8555914433 ps
CPU time 14.17 seconds
Started Jul 12 06:32:55 PM PDT 24
Finished Jul 12 06:33:10 PM PDT 24
Peak memory 216184 kb
Host smart-0a74e91c-f1ce-48ee-b4f1-346479e5bedb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107705862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.4107705862
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.323259999
Short name T536
Test name
Test status
Simulation time 726480068 ps
CPU time 2.84 seconds
Started Jul 12 06:32:55 PM PDT 24
Finished Jul 12 06:32:59 PM PDT 24
Peak memory 216144 kb
Host smart-84a07c0c-34d8-454e-9482-63eafcf3f4dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323259999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.323259999
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.3086599510
Short name T559
Test name
Test status
Simulation time 41092452 ps
CPU time 0.71 seconds
Started Jul 12 06:32:56 PM PDT 24
Finished Jul 12 06:32:58 PM PDT 24
Peak memory 205880 kb
Host smart-744be175-5818-48af-aaf2-3b83a34b3338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086599510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.3086599510
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.3399342694
Short name T903
Test name
Test status
Simulation time 6660970662 ps
CPU time 12.67 seconds
Started Jul 12 06:32:55 PM PDT 24
Finished Jul 12 06:33:08 PM PDT 24
Peak memory 224688 kb
Host smart-bb4d61f1-6cf1-4de7-90e4-a14dade74a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399342694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.3399342694
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.1767722480
Short name T330
Test name
Test status
Simulation time 19942097 ps
CPU time 0.72 seconds
Started Jul 12 06:33:02 PM PDT 24
Finished Jul 12 06:33:04 PM PDT 24
Peak memory 205464 kb
Host smart-83bd1b68-ad1e-419e-8217-0c27cf7bf829
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767722480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
1767722480
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.864197648
Short name T173
Test name
Test status
Simulation time 122849942 ps
CPU time 2.59 seconds
Started Jul 12 06:33:04 PM PDT 24
Finished Jul 12 06:33:07 PM PDT 24
Peak memory 224304 kb
Host smart-8d769518-b03f-4227-a0d2-e3bcc4e56e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864197648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.864197648
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.3580262921
Short name T541
Test name
Test status
Simulation time 34560414 ps
CPU time 0.78 seconds
Started Jul 12 06:32:56 PM PDT 24
Finished Jul 12 06:32:59 PM PDT 24
Peak memory 206572 kb
Host smart-727903bb-138d-4a78-adb9-9390b380e845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580262921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.3580262921
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.785907439
Short name T492
Test name
Test status
Simulation time 174437563620 ps
CPU time 271.39 seconds
Started Jul 12 06:33:03 PM PDT 24
Finished Jul 12 06:37:36 PM PDT 24
Peak memory 250720 kb
Host smart-700a87be-d624-4fff-80ff-3c9b94adde3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785907439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.785907439
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.2799378603
Short name T222
Test name
Test status
Simulation time 22195481369 ps
CPU time 139.53 seconds
Started Jul 12 06:33:04 PM PDT 24
Finished Jul 12 06:35:24 PM PDT 24
Peak memory 264496 kb
Host smart-760bcb18-1b45-4119-ad74-873e4f0e978f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799378603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.2799378603
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.878897180
Short name T184
Test name
Test status
Simulation time 229399439151 ps
CPU time 439.76 seconds
Started Jul 12 06:33:02 PM PDT 24
Finished Jul 12 06:40:23 PM PDT 24
Peak memory 265532 kb
Host smart-8edf82e4-ba8e-45d7-80a0-360b5e9ceba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878897180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idle
.878897180
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.533997897
Short name T871
Test name
Test status
Simulation time 161712936 ps
CPU time 2.84 seconds
Started Jul 12 06:33:00 PM PDT 24
Finished Jul 12 06:33:04 PM PDT 24
Peak memory 224452 kb
Host smart-cf284f4d-a29e-42a6-92dc-8b372f558ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533997897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.533997897
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.1144968276
Short name T882
Test name
Test status
Simulation time 99537151725 ps
CPU time 198.6 seconds
Started Jul 12 06:33:02 PM PDT 24
Finished Jul 12 06:36:22 PM PDT 24
Peak memory 256000 kb
Host smart-fd01c912-62be-46fb-b5f8-e02306cae61d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144968276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmd
s.1144968276
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.3583260714
Short name T992
Test name
Test status
Simulation time 1048621411 ps
CPU time 10.7 seconds
Started Jul 12 06:33:01 PM PDT 24
Finished Jul 12 06:33:13 PM PDT 24
Peak memory 232648 kb
Host smart-03c769d2-761f-4201-a4de-603fa7f7473c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583260714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.3583260714
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.1760849972
Short name T177
Test name
Test status
Simulation time 1045283607 ps
CPU time 14.57 seconds
Started Jul 12 06:33:04 PM PDT 24
Finished Jul 12 06:33:20 PM PDT 24
Peak memory 218828 kb
Host smart-8bd82998-9ef8-43ee-a84f-c66363bfbb02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760849972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.1760849972
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.1969142080
Short name T663
Test name
Test status
Simulation time 584607907 ps
CPU time 7.05 seconds
Started Jul 12 06:33:00 PM PDT 24
Finished Jul 12 06:33:08 PM PDT 24
Peak memory 224436 kb
Host smart-16ee0f3b-b1d2-4aca-9f6c-81a4ffde5f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969142080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.1969142080
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.3902417831
Short name T771
Test name
Test status
Simulation time 14640481056 ps
CPU time 10.89 seconds
Started Jul 12 06:32:58 PM PDT 24
Finished Jul 12 06:33:11 PM PDT 24
Peak memory 232740 kb
Host smart-19a2c5e8-888e-4bfa-a76f-44bf869a66da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902417831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.3902417831
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.734430403
Short name T430
Test name
Test status
Simulation time 2156573422 ps
CPU time 4.62 seconds
Started Jul 12 06:33:00 PM PDT 24
Finished Jul 12 06:33:05 PM PDT 24
Peak memory 223368 kb
Host smart-3dab55bd-b334-46cf-87db-5c3a295d4859
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=734430403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dire
ct.734430403
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.3084528157
Short name T662
Test name
Test status
Simulation time 8735224237 ps
CPU time 8.47 seconds
Started Jul 12 06:32:56 PM PDT 24
Finished Jul 12 06:33:06 PM PDT 24
Peak memory 216260 kb
Host smart-24d09de8-5153-4a2a-90b1-66292d756f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084528157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.3084528157
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.3365916760
Short name T82
Test name
Test status
Simulation time 4041777537 ps
CPU time 12.22 seconds
Started Jul 12 06:32:56 PM PDT 24
Finished Jul 12 06:33:10 PM PDT 24
Peak memory 216288 kb
Host smart-95d89a05-3e86-4054-a3b3-492bfe611cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365916760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.3365916760
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.3416697263
Short name T643
Test name
Test status
Simulation time 57892985 ps
CPU time 0.87 seconds
Started Jul 12 06:32:59 PM PDT 24
Finished Jul 12 06:33:01 PM PDT 24
Peak memory 205928 kb
Host smart-d28f3604-06ab-486c-9f13-5306ffb55ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416697263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.3416697263
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.4238281853
Short name T851
Test name
Test status
Simulation time 46043142 ps
CPU time 0.71 seconds
Started Jul 12 06:32:56 PM PDT 24
Finished Jul 12 06:32:58 PM PDT 24
Peak memory 205884 kb
Host smart-e68ea6c1-c15b-48a7-9ae4-9d77c6e49fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238281853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.4238281853
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.3078544373
Short name T218
Test name
Test status
Simulation time 1893435792 ps
CPU time 9.28 seconds
Started Jul 12 06:33:03 PM PDT 24
Finished Jul 12 06:33:13 PM PDT 24
Peak memory 240076 kb
Host smart-1e63a6ae-3eb7-4856-978b-db79a4ee0caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078544373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.3078544373
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.1884383095
Short name T9
Test name
Test status
Simulation time 44324897 ps
CPU time 0.8 seconds
Started Jul 12 06:33:10 PM PDT 24
Finished Jul 12 06:33:11 PM PDT 24
Peak memory 205792 kb
Host smart-f9e32a51-db5c-4b82-aab1-7499c8a82b23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884383095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
1884383095
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.3203834962
Short name T515
Test name
Test status
Simulation time 105227205 ps
CPU time 2.44 seconds
Started Jul 12 06:33:02 PM PDT 24
Finished Jul 12 06:33:06 PM PDT 24
Peak memory 224020 kb
Host smart-96653d0a-dc1a-402b-8304-69f794606467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203834962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.3203834962
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.2513447438
Short name T407
Test name
Test status
Simulation time 65818297 ps
CPU time 0.76 seconds
Started Jul 12 06:33:02 PM PDT 24
Finished Jul 12 06:33:04 PM PDT 24
Peak memory 206516 kb
Host smart-0409ed09-0c3e-437f-9259-6951cf291d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513447438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.2513447438
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.4262135486
Short name T658
Test name
Test status
Simulation time 864982618 ps
CPU time 18.74 seconds
Started Jul 12 06:33:00 PM PDT 24
Finished Jul 12 06:33:20 PM PDT 24
Peak memory 238080 kb
Host smart-3db9cd9f-2fab-4cb9-8a54-15ea00ab5c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262135486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.4262135486
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.2828553326
Short name T132
Test name
Test status
Simulation time 18257982760 ps
CPU time 70.07 seconds
Started Jul 12 06:33:09 PM PDT 24
Finished Jul 12 06:34:19 PM PDT 24
Peak memory 252356 kb
Host smart-b2887fce-f032-41b8-9778-16314544932a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828553326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.2828553326
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.1006319212
Short name T936
Test name
Test status
Simulation time 679045927 ps
CPU time 19.42 seconds
Started Jul 12 06:33:02 PM PDT 24
Finished Jul 12 06:33:23 PM PDT 24
Peak memory 240820 kb
Host smart-4b900774-ee9e-4216-9538-de8c822f027c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006319212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.1006319212
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.1622567169
Short name T186
Test name
Test status
Simulation time 26878432795 ps
CPU time 89.36 seconds
Started Jul 12 06:33:04 PM PDT 24
Finished Jul 12 06:34:34 PM PDT 24
Peak memory 249772 kb
Host smart-d62c4fe9-10e6-45a3-be80-fc87faef845c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622567169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmd
s.1622567169
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.292356506
Short name T323
Test name
Test status
Simulation time 73974011 ps
CPU time 3.53 seconds
Started Jul 12 06:33:05 PM PDT 24
Finished Jul 12 06:33:10 PM PDT 24
Peak memory 232584 kb
Host smart-9c49d606-5a50-4f6b-9fdd-66bea9a3def7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292356506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.292356506
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.1994011235
Short name T752
Test name
Test status
Simulation time 609081706 ps
CPU time 13.16 seconds
Started Jul 12 06:33:02 PM PDT 24
Finished Jul 12 06:33:16 PM PDT 24
Peak memory 224420 kb
Host smart-88ee51c0-e105-410f-b725-94154cab608f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994011235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.1994011235
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.198765685
Short name T989
Test name
Test status
Simulation time 466217881 ps
CPU time 5.72 seconds
Started Jul 12 06:33:05 PM PDT 24
Finished Jul 12 06:33:12 PM PDT 24
Peak memory 224372 kb
Host smart-43cba8c9-a60b-4b44-8eb2-ef0e0b8499ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198765685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swap
.198765685
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.376338531
Short name T211
Test name
Test status
Simulation time 4319742735 ps
CPU time 17.04 seconds
Started Jul 12 06:33:05 PM PDT 24
Finished Jul 12 06:33:23 PM PDT 24
Peak memory 224576 kb
Host smart-5580d5c4-17f0-45d7-8f10-4cffb9878480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376338531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.376338531
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.15747407
Short name T854
Test name
Test status
Simulation time 257670689 ps
CPU time 4.11 seconds
Started Jul 12 06:33:00 PM PDT 24
Finished Jul 12 06:33:05 PM PDT 24
Peak memory 222624 kb
Host smart-73d110b9-efea-42c9-875a-ad061c77bf83
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=15747407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_direc
t.15747407
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.600177869
Short name T637
Test name
Test status
Simulation time 3399593115 ps
CPU time 10.08 seconds
Started Jul 12 06:33:04 PM PDT 24
Finished Jul 12 06:33:15 PM PDT 24
Peak memory 216292 kb
Host smart-4187456b-bc65-4ab1-9a24-998721283b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600177869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.600177869
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.1799553235
Short name T426
Test name
Test status
Simulation time 1640302692 ps
CPU time 9.94 seconds
Started Jul 12 06:33:04 PM PDT 24
Finished Jul 12 06:33:15 PM PDT 24
Peak memory 216128 kb
Host smart-80a1a360-78dc-4ecf-96e6-3c89d6db4b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799553235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.1799553235
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.2065171999
Short name T594
Test name
Test status
Simulation time 128347497 ps
CPU time 1.45 seconds
Started Jul 12 06:33:05 PM PDT 24
Finished Jul 12 06:33:08 PM PDT 24
Peak memory 216132 kb
Host smart-0f1bb64f-3955-48c3-ab57-fbdaa2096beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065171999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.2065171999
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.1918986775
Short name T864
Test name
Test status
Simulation time 47477787 ps
CPU time 0.9 seconds
Started Jul 12 06:33:00 PM PDT 24
Finished Jul 12 06:33:02 PM PDT 24
Peak memory 205928 kb
Host smart-34eadd35-26bc-4bfc-b06e-33ebb63067e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918986775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.1918986775
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.3235287851
Short name T996
Test name
Test status
Simulation time 5019239407 ps
CPU time 4.47 seconds
Started Jul 12 06:33:01 PM PDT 24
Finished Jul 12 06:33:06 PM PDT 24
Peak memory 224432 kb
Host smart-7df7855c-88d4-4571-b7b4-e494f62e7c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235287851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.3235287851
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.651416656
Short name T924
Test name
Test status
Simulation time 32181576 ps
CPU time 0.8 seconds
Started Jul 12 06:33:16 PM PDT 24
Finished Jul 12 06:33:18 PM PDT 24
Peak memory 205360 kb
Host smart-82fa6e7e-dda6-448c-a599-a896f957a851
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651416656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.651416656
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.3205625156
Short name T720
Test name
Test status
Simulation time 109903676 ps
CPU time 3.01 seconds
Started Jul 12 06:33:09 PM PDT 24
Finished Jul 12 06:33:13 PM PDT 24
Peak memory 224372 kb
Host smart-1f80dcb7-160f-45dc-9335-69dbcbd0c518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205625156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.3205625156
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.3512767087
Short name T717
Test name
Test status
Simulation time 38925893 ps
CPU time 0.86 seconds
Started Jul 12 06:33:10 PM PDT 24
Finished Jul 12 06:33:12 PM PDT 24
Peak memory 206516 kb
Host smart-8935f9d1-17a3-4d09-9482-58e361cd0e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512767087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.3512767087
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.1107782833
Short name T204
Test name
Test status
Simulation time 63961402483 ps
CPU time 128.65 seconds
Started Jul 12 06:33:09 PM PDT 24
Finished Jul 12 06:35:19 PM PDT 24
Peak memory 255124 kb
Host smart-94c11fd6-dc0f-4b8f-a18f-6025d488d931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107782833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.1107782833
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.3248705953
Short name T286
Test name
Test status
Simulation time 1695415686 ps
CPU time 17.67 seconds
Started Jul 12 06:33:09 PM PDT 24
Finished Jul 12 06:33:27 PM PDT 24
Peak memory 224388 kb
Host smart-c0a50ebb-ba01-40cd-9872-716400023801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248705953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.3248705953
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.183273071
Short name T190
Test name
Test status
Simulation time 12682156489 ps
CPU time 100.47 seconds
Started Jul 12 06:33:11 PM PDT 24
Finished Jul 12 06:34:53 PM PDT 24
Peak memory 238212 kb
Host smart-236ddb8c-3799-4072-a1d1-45e0973a3356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183273071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmds
.183273071
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.982288046
Short name T673
Test name
Test status
Simulation time 1722341875 ps
CPU time 7.87 seconds
Started Jul 12 06:33:10 PM PDT 24
Finished Jul 12 06:33:19 PM PDT 24
Peak memory 232560 kb
Host smart-404a0b8e-1f9d-4e28-9ddf-e8940a0dc334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982288046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.982288046
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.2470533174
Short name T340
Test name
Test status
Simulation time 13382949422 ps
CPU time 72.57 seconds
Started Jul 12 06:33:08 PM PDT 24
Finished Jul 12 06:34:21 PM PDT 24
Peak memory 249844 kb
Host smart-19e229ea-f453-4ff5-b66f-bb13c65581e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470533174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.2470533174
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.3359466986
Short name T446
Test name
Test status
Simulation time 4778483239 ps
CPU time 15.79 seconds
Started Jul 12 06:33:11 PM PDT 24
Finished Jul 12 06:33:28 PM PDT 24
Peak memory 238676 kb
Host smart-40267608-f0f4-475e-b000-3277677a5b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359466986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.3359466986
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.3214854759
Short name T721
Test name
Test status
Simulation time 3344489209 ps
CPU time 5.63 seconds
Started Jul 12 06:33:11 PM PDT 24
Finished Jul 12 06:33:18 PM PDT 24
Peak memory 224528 kb
Host smart-0bfce1a2-1500-4027-a006-cd4a3ea4c6e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214854759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.3214854759
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.266356364
Short name T829
Test name
Test status
Simulation time 901497330 ps
CPU time 9.8 seconds
Started Jul 12 06:33:09 PM PDT 24
Finished Jul 12 06:33:20 PM PDT 24
Peak memory 221288 kb
Host smart-3b9caadb-4187-459c-8ef2-2f30ac4a39aa
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=266356364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dire
ct.266356364
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.1921843602
Short name T150
Test name
Test status
Simulation time 235941723 ps
CPU time 1.08 seconds
Started Jul 12 06:33:08 PM PDT 24
Finished Jul 12 06:33:10 PM PDT 24
Peak memory 207680 kb
Host smart-d89eef85-8a4c-419e-9c79-041e06145044
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921843602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.1921843602
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.2217491505
Short name T395
Test name
Test status
Simulation time 2411116719 ps
CPU time 12.69 seconds
Started Jul 12 06:33:08 PM PDT 24
Finished Jul 12 06:33:21 PM PDT 24
Peak memory 218068 kb
Host smart-b7a63343-6282-4a8a-b243-1ae13d079f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217491505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.2217491505
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.224059891
Short name T302
Test name
Test status
Simulation time 2721669022 ps
CPU time 7.51 seconds
Started Jul 12 06:33:08 PM PDT 24
Finished Jul 12 06:33:16 PM PDT 24
Peak memory 216256 kb
Host smart-8cc595b0-eaab-4341-a028-dd66ac2b533d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224059891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.224059891
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.3604831144
Short name T724
Test name
Test status
Simulation time 29374391 ps
CPU time 0.73 seconds
Started Jul 12 06:33:08 PM PDT 24
Finished Jul 12 06:33:10 PM PDT 24
Peak memory 205904 kb
Host smart-bad65658-af92-4587-85f5-0c66a400fbcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604831144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.3604831144
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.4083729161
Short name T4
Test name
Test status
Simulation time 22861819 ps
CPU time 0.75 seconds
Started Jul 12 06:33:09 PM PDT 24
Finished Jul 12 06:33:10 PM PDT 24
Peak memory 205596 kb
Host smart-7c682ac8-7934-4f33-8b29-1935e739b77e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083729161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.4083729161
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.1926104699
Short name T156
Test name
Test status
Simulation time 20291511580 ps
CPU time 31.67 seconds
Started Jul 12 06:33:09 PM PDT 24
Finished Jul 12 06:33:42 PM PDT 24
Peak memory 240908 kb
Host smart-57955e06-fb02-4ad7-81da-e37ed5ae4057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926104699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.1926104699
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.2678901612
Short name T284
Test name
Test status
Simulation time 33413242 ps
CPU time 0.69 seconds
Started Jul 12 06:33:24 PM PDT 24
Finished Jul 12 06:33:27 PM PDT 24
Peak memory 205416 kb
Host smart-4bd5d943-8373-4ddb-84c8-2cec2ae6224d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678901612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
2678901612
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.3236337533
Short name T921
Test name
Test status
Simulation time 409249139 ps
CPU time 3.31 seconds
Started Jul 12 06:33:17 PM PDT 24
Finished Jul 12 06:33:21 PM PDT 24
Peak memory 224392 kb
Host smart-04b284be-6f5c-42f4-9410-2a55d996fba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236337533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.3236337533
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.2970469197
Short name T290
Test name
Test status
Simulation time 31825794 ps
CPU time 0.79 seconds
Started Jul 12 06:33:17 PM PDT 24
Finished Jul 12 06:33:19 PM PDT 24
Peak memory 206864 kb
Host smart-abda19fd-63ae-4aaf-abb9-3ac65758ffa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970469197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.2970469197
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.4132906056
Short name T870
Test name
Test status
Simulation time 93748450350 ps
CPU time 331.41 seconds
Started Jul 12 06:33:24 PM PDT 24
Finished Jul 12 06:38:57 PM PDT 24
Peak memory 257328 kb
Host smart-f222e5b7-d7ad-4d6a-9b69-94add5f45bd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132906056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.4132906056
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.1948325336
Short name T36
Test name
Test status
Simulation time 393427793840 ps
CPU time 773.16 seconds
Started Jul 12 06:33:23 PM PDT 24
Finished Jul 12 06:46:17 PM PDT 24
Peak memory 272284 kb
Host smart-6200b2a9-f4fa-4af9-8a21-79fd7c87b8e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948325336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.1948325336
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.4020676495
Short name T422
Test name
Test status
Simulation time 22806764107 ps
CPU time 225.5 seconds
Started Jul 12 06:33:26 PM PDT 24
Finished Jul 12 06:37:13 PM PDT 24
Peak memory 267528 kb
Host smart-fbc4540c-ff06-4d2e-97b5-7f4d14fbd288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020676495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.4020676495
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.2925982548
Short name T265
Test name
Test status
Simulation time 964066971 ps
CPU time 8.3 seconds
Started Jul 12 06:33:17 PM PDT 24
Finished Jul 12 06:33:27 PM PDT 24
Peak memory 240832 kb
Host smart-b1f9696c-f900-48bc-8988-29d10eb270b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925982548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.2925982548
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.1248607472
Short name T979
Test name
Test status
Simulation time 2252968914 ps
CPU time 41.13 seconds
Started Jul 12 06:33:18 PM PDT 24
Finished Jul 12 06:34:00 PM PDT 24
Peak memory 249104 kb
Host smart-cd779cfb-8c6d-44c3-ac4d-c0293d81c0b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248607472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmd
s.1248607472
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.2380690270
Short name T886
Test name
Test status
Simulation time 45308490 ps
CPU time 2.37 seconds
Started Jul 12 06:33:17 PM PDT 24
Finished Jul 12 06:33:20 PM PDT 24
Peak memory 224424 kb
Host smart-4b54cd57-d419-4710-ba04-85301a8224d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380690270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.2380690270
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.822111171
Short name T773
Test name
Test status
Simulation time 165350879 ps
CPU time 2.27 seconds
Started Jul 12 06:33:16 PM PDT 24
Finished Jul 12 06:33:19 PM PDT 24
Peak memory 223792 kb
Host smart-09cf8b47-8ced-4479-9076-9266d1a5e091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822111171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.822111171
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.1641923606
Short name T627
Test name
Test status
Simulation time 1115979139 ps
CPU time 3.69 seconds
Started Jul 12 06:33:16 PM PDT 24
Finished Jul 12 06:33:21 PM PDT 24
Peak memory 232592 kb
Host smart-b14bcf3f-068f-41e8-b797-f77e7a432039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641923606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.1641923606
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.2300834779
Short name T202
Test name
Test status
Simulation time 92911431 ps
CPU time 3.58 seconds
Started Jul 12 06:33:16 PM PDT 24
Finished Jul 12 06:33:21 PM PDT 24
Peak memory 232644 kb
Host smart-3c031798-91f1-4013-bbc4-cf039f1bc69d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300834779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.2300834779
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.213631160
Short name T74
Test name
Test status
Simulation time 3072312629 ps
CPU time 9.24 seconds
Started Jul 12 06:33:17 PM PDT 24
Finished Jul 12 06:33:27 PM PDT 24
Peak memory 223104 kb
Host smart-9bb140b4-0fa2-4c4f-b7a4-15f0d5b91861
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=213631160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dire
ct.213631160
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.2137723522
Short name T640
Test name
Test status
Simulation time 101008843418 ps
CPU time 297.43 seconds
Started Jul 12 06:33:25 PM PDT 24
Finished Jul 12 06:38:24 PM PDT 24
Peak memory 263760 kb
Host smart-bebe2f1d-542d-4623-96af-06eb89fc2ef7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137723522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.2137723522
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.2217406400
Short name T331
Test name
Test status
Simulation time 18303696 ps
CPU time 0.8 seconds
Started Jul 12 06:33:17 PM PDT 24
Finished Jul 12 06:33:19 PM PDT 24
Peak memory 205692 kb
Host smart-9adf3d3f-afb7-4167-bdc6-562bcad04def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217406400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.2217406400
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.3217784956
Short name T945
Test name
Test status
Simulation time 115065922 ps
CPU time 1.35 seconds
Started Jul 12 06:33:19 PM PDT 24
Finished Jul 12 06:33:21 PM PDT 24
Peak memory 207840 kb
Host smart-40e67b8a-eedd-42f6-aa3e-9b6fcb076656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217784956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.3217784956
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.388008242
Short name T812
Test name
Test status
Simulation time 906775994 ps
CPU time 3.17 seconds
Started Jul 12 06:33:18 PM PDT 24
Finished Jul 12 06:33:22 PM PDT 24
Peak memory 216140 kb
Host smart-d8dbda52-ca77-4f89-9d47-896adc5b21bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388008242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.388008242
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.1341159257
Short name T934
Test name
Test status
Simulation time 66280037 ps
CPU time 0.89 seconds
Started Jul 12 06:33:17 PM PDT 24
Finished Jul 12 06:33:19 PM PDT 24
Peak memory 205924 kb
Host smart-2fae9fdd-75f3-46b0-b2bb-83345521b089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341159257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.1341159257
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.2107191926
Short name T212
Test name
Test status
Simulation time 2277172323 ps
CPU time 7.61 seconds
Started Jul 12 06:33:16 PM PDT 24
Finished Jul 12 06:33:24 PM PDT 24
Peak memory 232640 kb
Host smart-5fb066a9-b7b2-4019-ba75-66382a9a3243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107191926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.2107191926
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.520895816
Short name T907
Test name
Test status
Simulation time 12295051 ps
CPU time 0.73 seconds
Started Jul 12 06:33:25 PM PDT 24
Finished Jul 12 06:33:27 PM PDT 24
Peak memory 204920 kb
Host smart-7c2f91f7-7079-4c81-ac44-9772d701e3bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520895816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.520895816
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.2114176065
Short name T939
Test name
Test status
Simulation time 237339502 ps
CPU time 4.58 seconds
Started Jul 12 06:33:25 PM PDT 24
Finished Jul 12 06:33:31 PM PDT 24
Peak memory 224400 kb
Host smart-66fa7977-f6fa-4dea-ae02-18cb2f7b140b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114176065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.2114176065
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.2018280536
Short name T418
Test name
Test status
Simulation time 21295315 ps
CPU time 0.8 seconds
Started Jul 12 06:33:25 PM PDT 24
Finished Jul 12 06:33:28 PM PDT 24
Peak memory 206864 kb
Host smart-333ace66-9cb3-4f3f-98c1-b3f948ad14b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018280536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.2018280536
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.331937953
Short name T179
Test name
Test status
Simulation time 27703515351 ps
CPU time 94.37 seconds
Started Jul 12 06:33:26 PM PDT 24
Finished Jul 12 06:35:02 PM PDT 24
Peak memory 264272 kb
Host smart-ed1073fd-8d79-4bdc-bdce-a4cf4b9c25e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331937953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.331937953
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.2841382447
Short name T961
Test name
Test status
Simulation time 25130104893 ps
CPU time 90.74 seconds
Started Jul 12 06:33:24 PM PDT 24
Finished Jul 12 06:34:56 PM PDT 24
Peak memory 249248 kb
Host smart-86706e1e-6b5b-4430-a1ce-825d4b8647dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841382447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.2841382447
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.2420533815
Short name T789
Test name
Test status
Simulation time 22985622062 ps
CPU time 191.26 seconds
Started Jul 12 06:33:25 PM PDT 24
Finished Jul 12 06:36:38 PM PDT 24
Peak memory 265000 kb
Host smart-45c4d4cf-eb7f-4480-a405-eed44df7b41e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420533815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.2420533815
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.4178451343
Short name T409
Test name
Test status
Simulation time 124004050 ps
CPU time 3.21 seconds
Started Jul 12 06:33:24 PM PDT 24
Finished Jul 12 06:33:28 PM PDT 24
Peak memory 224412 kb
Host smart-660e35cf-c01f-48b6-9063-d05fb3b7250b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178451343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.4178451343
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.2896513486
Short name T560
Test name
Test status
Simulation time 17238963 ps
CPU time 0.79 seconds
Started Jul 12 06:33:25 PM PDT 24
Finished Jul 12 06:33:27 PM PDT 24
Peak memory 215700 kb
Host smart-ea231087-f281-4441-b664-c98337e884d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896513486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmd
s.2896513486
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.3450946182
Short name T344
Test name
Test status
Simulation time 1038747714 ps
CPU time 6.73 seconds
Started Jul 12 06:33:25 PM PDT 24
Finished Jul 12 06:33:33 PM PDT 24
Peak memory 224360 kb
Host smart-e82be01f-f17f-4422-b5d4-16142f8cfd22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450946182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.3450946182
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.1899064947
Short name T550
Test name
Test status
Simulation time 5282246196 ps
CPU time 40.18 seconds
Started Jul 12 06:33:24 PM PDT 24
Finished Jul 12 06:34:06 PM PDT 24
Peak memory 219836 kb
Host smart-baa9bcfb-5ce6-4ff9-ade6-f86ffd35da29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899064947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.1899064947
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.2692577282
Short name T42
Test name
Test status
Simulation time 1157544531 ps
CPU time 7.47 seconds
Started Jul 12 06:33:23 PM PDT 24
Finished Jul 12 06:33:31 PM PDT 24
Peak memory 232644 kb
Host smart-3bbc8348-115d-47c0-8954-38541ae96921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692577282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.2692577282
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.3606660848
Short name T209
Test name
Test status
Simulation time 731025770 ps
CPU time 7.77 seconds
Started Jul 12 06:33:24 PM PDT 24
Finished Jul 12 06:33:34 PM PDT 24
Peak memory 232636 kb
Host smart-00e02dec-72cb-4abd-8bc4-3b70b5924124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606660848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.3606660848
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.1582466449
Short name T137
Test name
Test status
Simulation time 804261273 ps
CPU time 10.94 seconds
Started Jul 12 06:33:24 PM PDT 24
Finished Jul 12 06:33:36 PM PDT 24
Peak memory 220732 kb
Host smart-99ee3c26-dc56-4839-b69e-87a298dc5353
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1582466449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.1582466449
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.3067998343
Short name T235
Test name
Test status
Simulation time 29442638931 ps
CPU time 345.28 seconds
Started Jul 12 06:33:25 PM PDT 24
Finished Jul 12 06:39:12 PM PDT 24
Peak memory 270212 kb
Host smart-31d47c73-ac83-43fd-a6d0-292404b98df5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067998343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.3067998343
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.3084508265
Short name T711
Test name
Test status
Simulation time 14724865979 ps
CPU time 7.75 seconds
Started Jul 12 06:33:25 PM PDT 24
Finished Jul 12 06:33:35 PM PDT 24
Peak memory 216872 kb
Host smart-a42c68e1-0455-41f1-95dd-95d25e58e6c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084508265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.3084508265
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.617667768
Short name T1017
Test name
Test status
Simulation time 3360980642 ps
CPU time 7.19 seconds
Started Jul 12 06:33:25 PM PDT 24
Finished Jul 12 06:33:34 PM PDT 24
Peak memory 216260 kb
Host smart-ad0db0f5-d6fe-4c93-98da-b5d52ef22af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617667768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.617667768
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.3747366948
Short name T719
Test name
Test status
Simulation time 621848721 ps
CPU time 2.45 seconds
Started Jul 12 06:33:23 PM PDT 24
Finished Jul 12 06:33:26 PM PDT 24
Peak memory 216208 kb
Host smart-8afe392e-b556-488a-81b1-fec85db50128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747366948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.3747366948
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.754848596
Short name T423
Test name
Test status
Simulation time 84559566 ps
CPU time 0.81 seconds
Started Jul 12 06:33:36 PM PDT 24
Finished Jul 12 06:33:38 PM PDT 24
Peak memory 205904 kb
Host smart-85197a28-a57f-4a2e-a01d-e407cf538ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754848596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.754848596
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.2837831832
Short name T768
Test name
Test status
Simulation time 1119085798 ps
CPU time 3.98 seconds
Started Jul 12 06:33:26 PM PDT 24
Finished Jul 12 06:33:32 PM PDT 24
Peak memory 232608 kb
Host smart-1b19c8e8-ee6c-4085-bb44-63efbbbc8efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837831832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.2837831832
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.2517247658
Short name T713
Test name
Test status
Simulation time 38884854 ps
CPU time 0.72 seconds
Started Jul 12 06:31:09 PM PDT 24
Finished Jul 12 06:31:12 PM PDT 24
Peak memory 205468 kb
Host smart-9779be29-562e-4f02-96fd-10486b6a6bcb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517247658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.2
517247658
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.1766882713
Short name T534
Test name
Test status
Simulation time 337946948 ps
CPU time 6.38 seconds
Started Jul 12 06:31:01 PM PDT 24
Finished Jul 12 06:31:09 PM PDT 24
Peak memory 232548 kb
Host smart-a6111e6d-f092-4499-8376-98aaecba6647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766882713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.1766882713
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.2202761666
Short name T630
Test name
Test status
Simulation time 172953638 ps
CPU time 0.87 seconds
Started Jul 12 06:31:02 PM PDT 24
Finished Jul 12 06:31:04 PM PDT 24
Peak memory 206496 kb
Host smart-02c320ca-cd74-43f3-9f32-be528bade3bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202761666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.2202761666
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.3593041197
Short name T405
Test name
Test status
Simulation time 61185811944 ps
CPU time 101.52 seconds
Started Jul 12 06:31:00 PM PDT 24
Finished Jul 12 06:32:43 PM PDT 24
Peak memory 256772 kb
Host smart-6eced971-f551-45ce-b96e-6b81e13e70d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593041197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.3593041197
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.686470734
Short name T928
Test name
Test status
Simulation time 39881880977 ps
CPU time 41.25 seconds
Started Jul 12 06:31:03 PM PDT 24
Finished Jul 12 06:31:46 PM PDT 24
Peak memory 232784 kb
Host smart-fd8db4d8-636f-4537-abcc-298a5a1a8fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686470734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.686470734
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.2576040449
Short name T248
Test name
Test status
Simulation time 202463077867 ps
CPU time 356.16 seconds
Started Jul 12 06:31:02 PM PDT 24
Finished Jul 12 06:37:01 PM PDT 24
Peak memory 253264 kb
Host smart-e06ecd3d-97e4-4122-a284-c04ff2de79ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576040449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.2576040449
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.1201238109
Short name T10
Test name
Test status
Simulation time 327216762 ps
CPU time 6.41 seconds
Started Jul 12 06:31:02 PM PDT 24
Finished Jul 12 06:31:10 PM PDT 24
Peak memory 224412 kb
Host smart-97d00a2c-4805-4a22-a716-c6c3c318a74d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201238109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.1201238109
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.1766486048
Short name T601
Test name
Test status
Simulation time 10416015968 ps
CPU time 20.73 seconds
Started Jul 12 06:31:09 PM PDT 24
Finished Jul 12 06:31:31 PM PDT 24
Peak memory 224536 kb
Host smart-45acc8d2-ad39-4c6d-9816-e980242949b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766486048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.1766486048
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.3771294850
Short name T827
Test name
Test status
Simulation time 250587848 ps
CPU time 6.4 seconds
Started Jul 12 06:31:03 PM PDT 24
Finished Jul 12 06:31:11 PM PDT 24
Peak memory 232652 kb
Host smart-44c745de-0d8d-4db6-a293-9f2db81fe896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771294850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.3771294850
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.2533482026
Short name T228
Test name
Test status
Simulation time 12386595953 ps
CPU time 11.87 seconds
Started Jul 12 06:31:02 PM PDT 24
Finished Jul 12 06:31:16 PM PDT 24
Peak memory 238876 kb
Host smart-dd9aa75e-a09f-4c13-a8b8-8d67d6816bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533482026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.2533482026
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.4127626904
Short name T227
Test name
Test status
Simulation time 1519742281 ps
CPU time 2.86 seconds
Started Jul 12 06:31:02 PM PDT 24
Finished Jul 12 06:31:07 PM PDT 24
Peak memory 224428 kb
Host smart-1360ebeb-384c-4f95-bb75-3bff742130d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127626904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.4127626904
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.1283026525
Short name T844
Test name
Test status
Simulation time 959056474 ps
CPU time 4.32 seconds
Started Jul 12 06:31:04 PM PDT 24
Finished Jul 12 06:31:10 PM PDT 24
Peak memory 220376 kb
Host smart-5b5ac238-c5d3-44c9-8248-f8e459ac544b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1283026525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.1283026525
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.4094909319
Short name T66
Test name
Test status
Simulation time 34218498 ps
CPU time 0.95 seconds
Started Jul 12 06:31:08 PM PDT 24
Finished Jul 12 06:31:10 PM PDT 24
Peak memory 235476 kb
Host smart-ac26b0a7-3a62-485d-940f-568c5476485e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094909319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.4094909319
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.3048881418
Short name T528
Test name
Test status
Simulation time 2303567201 ps
CPU time 11.08 seconds
Started Jul 12 06:31:01 PM PDT 24
Finished Jul 12 06:31:13 PM PDT 24
Peak memory 216344 kb
Host smart-286d40e6-27b5-4330-88ab-18be2b5563f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048881418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.3048881418
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.3962478998
Short name T413
Test name
Test status
Simulation time 1847238782 ps
CPU time 10.41 seconds
Started Jul 12 06:31:01 PM PDT 24
Finished Jul 12 06:31:13 PM PDT 24
Peak memory 216172 kb
Host smart-cbcbf57a-81d3-4431-843e-d92db8e4f494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962478998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.3962478998
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.2106088165
Short name T968
Test name
Test status
Simulation time 16215531 ps
CPU time 0.75 seconds
Started Jul 12 06:31:02 PM PDT 24
Finished Jul 12 06:31:04 PM PDT 24
Peak memory 205612 kb
Host smart-6f9f4c1a-b4ec-4803-b57f-2053f763add0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106088165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.2106088165
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.1643300151
Short name T764
Test name
Test status
Simulation time 30352948 ps
CPU time 0.81 seconds
Started Jul 12 06:31:02 PM PDT 24
Finished Jul 12 06:31:05 PM PDT 24
Peak memory 205884 kb
Host smart-efffb865-c263-47f2-be61-4077f2314dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643300151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.1643300151
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.916306201
Short name T999
Test name
Test status
Simulation time 544857335 ps
CPU time 8.3 seconds
Started Jul 12 06:31:02 PM PDT 24
Finished Jul 12 06:31:12 PM PDT 24
Peak memory 224624 kb
Host smart-fa285d2d-fb81-487b-9a94-91530d44c66e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916306201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.916306201
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.1014260010
Short name T532
Test name
Test status
Simulation time 38387821 ps
CPU time 0.76 seconds
Started Jul 12 06:33:33 PM PDT 24
Finished Jul 12 06:33:35 PM PDT 24
Peak memory 204904 kb
Host smart-fa19e392-5788-4290-bfb6-155230c472db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014260010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
1014260010
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.2987754416
Short name T1003
Test name
Test status
Simulation time 142618282 ps
CPU time 2.46 seconds
Started Jul 12 06:33:33 PM PDT 24
Finished Jul 12 06:33:37 PM PDT 24
Peak memory 232572 kb
Host smart-2aa6a42f-e379-4d14-be42-f81c7be971f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987754416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.2987754416
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.1945649454
Short name T746
Test name
Test status
Simulation time 27078489 ps
CPU time 0.76 seconds
Started Jul 12 06:33:24 PM PDT 24
Finished Jul 12 06:33:27 PM PDT 24
Peak memory 206572 kb
Host smart-d0c98d31-6581-48fc-87d6-bb82b80f829a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945649454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.1945649454
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.3868202334
Short name T991
Test name
Test status
Simulation time 9059265070 ps
CPU time 48.54 seconds
Started Jul 12 06:33:30 PM PDT 24
Finished Jul 12 06:34:20 PM PDT 24
Peak memory 257020 kb
Host smart-7c5cfae5-ad0f-44bb-99fd-6e9fcade68fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868202334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.3868202334
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.483469766
Short name T35
Test name
Test status
Simulation time 39868510113 ps
CPU time 339.45 seconds
Started Jul 12 06:33:31 PM PDT 24
Finished Jul 12 06:39:12 PM PDT 24
Peak memory 257408 kb
Host smart-f5fcdd5c-9525-4914-ba99-b6ad8317d454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483469766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.483469766
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.4150389366
Short name T727
Test name
Test status
Simulation time 2654778540 ps
CPU time 43.79 seconds
Started Jul 12 06:33:32 PM PDT 24
Finished Jul 12 06:34:17 PM PDT 24
Peak memory 239496 kb
Host smart-04eb1c40-6035-49ac-8b46-c9d826c2dee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150389366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.4150389366
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.3771294227
Short name T553
Test name
Test status
Simulation time 2386483728 ps
CPU time 7.39 seconds
Started Jul 12 06:33:30 PM PDT 24
Finished Jul 12 06:33:38 PM PDT 24
Peak memory 240920 kb
Host smart-7ca64657-7e97-499b-b43d-0b5335c04327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771294227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.3771294227
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.3021242834
Short name T475
Test name
Test status
Simulation time 17159957837 ps
CPU time 67.29 seconds
Started Jul 12 06:33:34 PM PDT 24
Finished Jul 12 06:34:42 PM PDT 24
Peak memory 236672 kb
Host smart-c0549a35-86cb-4a7c-9870-4b971cd84272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021242834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmd
s.3021242834
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.995705080
Short name T742
Test name
Test status
Simulation time 986738640 ps
CPU time 4.49 seconds
Started Jul 12 06:33:32 PM PDT 24
Finished Jul 12 06:33:38 PM PDT 24
Peak memory 224344 kb
Host smart-f2bbe846-449c-425f-9a24-4c1415832280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995705080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.995705080
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.4171458198
Short name T803
Test name
Test status
Simulation time 5627036735 ps
CPU time 39.36 seconds
Started Jul 12 06:33:33 PM PDT 24
Finished Jul 12 06:34:14 PM PDT 24
Peak memory 232772 kb
Host smart-6a298184-bd3a-4105-b9d8-e6361ebcdcb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171458198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.4171458198
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.1288252749
Short name T464
Test name
Test status
Simulation time 13762058432 ps
CPU time 16.26 seconds
Started Jul 12 06:33:38 PM PDT 24
Finished Jul 12 06:33:55 PM PDT 24
Peak memory 232780 kb
Host smart-af7d87ea-71ad-41d2-91b4-11ff1216b0bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288252749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.1288252749
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.2967932277
Short name T904
Test name
Test status
Simulation time 764995884 ps
CPU time 7.66 seconds
Started Jul 12 06:33:32 PM PDT 24
Finished Jul 12 06:33:41 PM PDT 24
Peak memory 232508 kb
Host smart-55f2aae2-6a1e-4735-9faf-135d8a4cf75d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967932277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.2967932277
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.3619471307
Short name T814
Test name
Test status
Simulation time 4698064270 ps
CPU time 15.42 seconds
Started Jul 12 06:33:32 PM PDT 24
Finished Jul 12 06:33:49 PM PDT 24
Peak memory 222092 kb
Host smart-54a720e0-9097-476a-9766-8de2df8f6f83
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3619471307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.3619471307
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.2395916225
Short name T825
Test name
Test status
Simulation time 135733806 ps
CPU time 1.11 seconds
Started Jul 12 06:33:29 PM PDT 24
Finished Jul 12 06:33:30 PM PDT 24
Peak memory 207056 kb
Host smart-9b61a0b8-eed9-4b0a-b93e-13cef8f0dcb9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395916225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.2395916225
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.3789093753
Short name T1011
Test name
Test status
Simulation time 6645749712 ps
CPU time 30.02 seconds
Started Jul 12 06:33:24 PM PDT 24
Finished Jul 12 06:33:55 PM PDT 24
Peak memory 220688 kb
Host smart-076d84fe-4261-44fd-bd7b-2b6b435857cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789093753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.3789093753
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.3820640797
Short name T325
Test name
Test status
Simulation time 346039359 ps
CPU time 1.59 seconds
Started Jul 12 06:33:26 PM PDT 24
Finished Jul 12 06:33:29 PM PDT 24
Peak memory 207832 kb
Host smart-ac7ec81c-40b4-4e70-b307-7b873e71b1e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820640797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.3820640797
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.4201277316
Short name T801
Test name
Test status
Simulation time 31419060 ps
CPU time 0.9 seconds
Started Jul 12 06:33:33 PM PDT 24
Finished Jul 12 06:33:35 PM PDT 24
Peak memory 207856 kb
Host smart-f7478979-535d-4c85-9d6f-6d931636b889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201277316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.4201277316
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.2044921217
Short name T819
Test name
Test status
Simulation time 50388366 ps
CPU time 0.75 seconds
Started Jul 12 06:33:31 PM PDT 24
Finished Jul 12 06:33:33 PM PDT 24
Peak memory 205940 kb
Host smart-5a55ba87-c531-4f64-ac64-996e07d3297a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044921217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.2044921217
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.1216015234
Short name T427
Test name
Test status
Simulation time 26481042025 ps
CPU time 17.77 seconds
Started Jul 12 06:33:34 PM PDT 24
Finished Jul 12 06:33:53 PM PDT 24
Peak memory 232760 kb
Host smart-e9c3719f-cf29-461f-8755-723a2548883e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216015234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.1216015234
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.2535015954
Short name T602
Test name
Test status
Simulation time 36734060 ps
CPU time 0.71 seconds
Started Jul 12 06:33:33 PM PDT 24
Finished Jul 12 06:33:35 PM PDT 24
Peak memory 205468 kb
Host smart-bc2f5a8f-40fc-4f8e-8cf0-a29f7b05c997
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535015954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
2535015954
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.2408173542
Short name T757
Test name
Test status
Simulation time 68231187 ps
CPU time 2.84 seconds
Started Jul 12 06:33:31 PM PDT 24
Finished Jul 12 06:33:35 PM PDT 24
Peak memory 232556 kb
Host smart-ac514d78-a428-4cac-85e6-f25acd1e7625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408173542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.2408173542
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.2556472026
Short name T895
Test name
Test status
Simulation time 14253043 ps
CPU time 0.77 seconds
Started Jul 12 06:33:33 PM PDT 24
Finished Jul 12 06:33:35 PM PDT 24
Peak memory 205484 kb
Host smart-7185fe20-2030-46ff-b178-13d2610e80f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556472026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.2556472026
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.2583387098
Short name T338
Test name
Test status
Simulation time 17735114 ps
CPU time 0.79 seconds
Started Jul 12 06:33:35 PM PDT 24
Finished Jul 12 06:33:37 PM PDT 24
Peak memory 215688 kb
Host smart-21e3fe2d-d055-49a3-b52a-b02dc765259e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583387098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.2583387098
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.1248199032
Short name T957
Test name
Test status
Simulation time 27420415850 ps
CPU time 111.98 seconds
Started Jul 12 06:33:37 PM PDT 24
Finished Jul 12 06:35:30 PM PDT 24
Peak memory 249220 kb
Host smart-0c57b35e-ff91-4b2d-8a46-041e29f9a4c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248199032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.1248199032
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.1137752408
Short name T826
Test name
Test status
Simulation time 3842995885 ps
CPU time 73.2 seconds
Started Jul 12 06:33:32 PM PDT 24
Finished Jul 12 06:34:47 PM PDT 24
Peak memory 250220 kb
Host smart-84bf95dc-61f3-4e8f-aff1-dd426fffe7ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137752408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.1137752408
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.3647233264
Short name T264
Test name
Test status
Simulation time 628624850 ps
CPU time 9.22 seconds
Started Jul 12 06:33:31 PM PDT 24
Finished Jul 12 06:33:42 PM PDT 24
Peak memory 232584 kb
Host smart-415f1f81-4128-4fcd-ace4-7c310e1ee7e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647233264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.3647233264
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.3070862986
Short name T198
Test name
Test status
Simulation time 56651342517 ps
CPU time 392.1 seconds
Started Jul 12 06:33:32 PM PDT 24
Finished Jul 12 06:40:06 PM PDT 24
Peak memory 261336 kb
Host smart-25f4f4b6-d213-4b0b-b7f6-f7e8ca5fce00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070862986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmd
s.3070862986
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.2266519504
Short name T447
Test name
Test status
Simulation time 172093925 ps
CPU time 3.05 seconds
Started Jul 12 06:33:30 PM PDT 24
Finished Jul 12 06:33:34 PM PDT 24
Peak memory 224436 kb
Host smart-e8887db0-4ce6-4b51-9174-ef3f50bcd2f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266519504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.2266519504
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.3810862253
Short name T217
Test name
Test status
Simulation time 1243003216 ps
CPU time 10.39 seconds
Started Jul 12 06:33:30 PM PDT 24
Finished Jul 12 06:33:41 PM PDT 24
Peak memory 233640 kb
Host smart-a1e7cd55-a69e-495c-a88f-a91b5b7d0a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810862253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.3810862253
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.425613915
Short name T231
Test name
Test status
Simulation time 249998011 ps
CPU time 4.4 seconds
Started Jul 12 06:33:31 PM PDT 24
Finished Jul 12 06:33:36 PM PDT 24
Peak memory 224400 kb
Host smart-bb1c0c76-2fda-4986-988d-16673d3c4b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425613915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swap
.425613915
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.1259846588
Short name T737
Test name
Test status
Simulation time 7911561970 ps
CPU time 27.28 seconds
Started Jul 12 06:33:33 PM PDT 24
Finished Jul 12 06:34:02 PM PDT 24
Peak memory 240636 kb
Host smart-0617534c-9270-44c8-9d5f-a6c37affa1c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259846588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.1259846588
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.1531814953
Short name T70
Test name
Test status
Simulation time 56874934 ps
CPU time 3.2 seconds
Started Jul 12 06:33:33 PM PDT 24
Finished Jul 12 06:33:38 PM PDT 24
Peak memory 223192 kb
Host smart-9b5817be-59db-46f8-a42d-68945448c987
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1531814953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.1531814953
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.997284731
Short name T615
Test name
Test status
Simulation time 60891596 ps
CPU time 0.72 seconds
Started Jul 12 06:33:33 PM PDT 24
Finished Jul 12 06:33:35 PM PDT 24
Peak memory 205668 kb
Host smart-76e06bdc-0f5f-498a-b6d1-af84872fcbaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997284731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.997284731
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.2339980639
Short name T660
Test name
Test status
Simulation time 220365659 ps
CPU time 1.25 seconds
Started Jul 12 06:33:37 PM PDT 24
Finished Jul 12 06:33:39 PM PDT 24
Peak memory 207832 kb
Host smart-1e5ebcf6-d787-4f1e-bdba-a6fd89b444b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339980639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.2339980639
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.1994035135
Short name T313
Test name
Test status
Simulation time 61536908 ps
CPU time 1.1 seconds
Started Jul 12 06:33:33 PM PDT 24
Finished Jul 12 06:33:36 PM PDT 24
Peak memory 207844 kb
Host smart-93e4a3ac-268c-4090-b04d-53df0a8623f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994035135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.1994035135
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.341340648
Short name T288
Test name
Test status
Simulation time 55345924 ps
CPU time 0.89 seconds
Started Jul 12 06:33:33 PM PDT 24
Finished Jul 12 06:33:36 PM PDT 24
Peak memory 205932 kb
Host smart-ac210aa8-658d-4fb4-9b5d-0b145f6734a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341340648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.341340648
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.3933381755
Short name T847
Test name
Test status
Simulation time 3077072643 ps
CPU time 9.47 seconds
Started Jul 12 06:33:32 PM PDT 24
Finished Jul 12 06:33:43 PM PDT 24
Peak memory 224428 kb
Host smart-84ea8418-7878-4860-9212-c916388bee02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933381755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.3933381755
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.2686004672
Short name T519
Test name
Test status
Simulation time 52190076 ps
CPU time 0.78 seconds
Started Jul 12 06:33:39 PM PDT 24
Finished Jul 12 06:33:41 PM PDT 24
Peak memory 204916 kb
Host smart-bb08f442-a778-4b4e-be99-03a78a99cd42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686004672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
2686004672
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.2668317477
Short name T454
Test name
Test status
Simulation time 47460073 ps
CPU time 2.73 seconds
Started Jul 12 06:33:36 PM PDT 24
Finished Jul 12 06:33:40 PM PDT 24
Peak memory 232612 kb
Host smart-2f436d54-0e33-4af7-8b2e-8cf9a02a77de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668317477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.2668317477
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.3606546743
Short name T634
Test name
Test status
Simulation time 176320805 ps
CPU time 0.75 seconds
Started Jul 12 06:33:31 PM PDT 24
Finished Jul 12 06:33:32 PM PDT 24
Peak memory 206876 kb
Host smart-dcccfb4b-22b2-4443-87b9-d92d2b8b86d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606546743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.3606546743
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.191901045
Short name T356
Test name
Test status
Simulation time 38886223546 ps
CPU time 56.86 seconds
Started Jul 12 06:33:36 PM PDT 24
Finished Jul 12 06:34:34 PM PDT 24
Peak memory 238252 kb
Host smart-34abe9e8-8a68-4211-8f3e-6410eb441588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191901045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.191901045
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.1763346304
Short name T793
Test name
Test status
Simulation time 90296152628 ps
CPU time 439.14 seconds
Started Jul 12 06:33:38 PM PDT 24
Finished Jul 12 06:40:59 PM PDT 24
Peak memory 253676 kb
Host smart-1dba16c0-9bb3-4f31-8aa2-b8e6e4f5b509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763346304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.1763346304
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.303775595
Short name T270
Test name
Test status
Simulation time 518787126 ps
CPU time 3.59 seconds
Started Jul 12 06:33:38 PM PDT 24
Finished Jul 12 06:33:43 PM PDT 24
Peak memory 224428 kb
Host smart-89170a5a-939f-47a3-a240-cf73c0394ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303775595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.303775595
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.16643276
Short name T169
Test name
Test status
Simulation time 8603787487 ps
CPU time 118.24 seconds
Started Jul 12 06:33:38 PM PDT 24
Finished Jul 12 06:35:38 PM PDT 24
Peak memory 265436 kb
Host smart-a8828cfe-5b15-41e0-b0b4-08979ee56c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16643276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmds.16643276
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.748363922
Short name T2
Test name
Test status
Simulation time 2582806719 ps
CPU time 21.98 seconds
Started Jul 12 06:33:37 PM PDT 24
Finished Jul 12 06:34:00 PM PDT 24
Peak memory 228424 kb
Host smart-d103cf7f-8e6b-48d2-9401-7c1205167052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748363922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.748363922
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.2178711686
Short name T940
Test name
Test status
Simulation time 3585256810 ps
CPU time 11.53 seconds
Started Jul 12 06:33:38 PM PDT 24
Finished Jul 12 06:33:52 PM PDT 24
Peak memory 240212 kb
Host smart-09542b79-70a0-4a06-9425-928ba24a4c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178711686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.2178711686
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.3062461680
Short name T233
Test name
Test status
Simulation time 1708180099 ps
CPU time 5.08 seconds
Started Jul 12 06:33:41 PM PDT 24
Finished Jul 12 06:33:47 PM PDT 24
Peak memory 231908 kb
Host smart-4131f271-6603-4408-b886-bd4e4c74115c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062461680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.3062461680
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.1836169366
Short name T674
Test name
Test status
Simulation time 4100881439 ps
CPU time 14.23 seconds
Started Jul 12 06:33:39 PM PDT 24
Finished Jul 12 06:33:55 PM PDT 24
Peak memory 224568 kb
Host smart-e916c446-c3cb-43d6-a59b-0d306cf3bc0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836169366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.1836169366
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.2617655357
Short name T805
Test name
Test status
Simulation time 711022008 ps
CPU time 7.49 seconds
Started Jul 12 06:33:41 PM PDT 24
Finished Jul 12 06:33:50 PM PDT 24
Peak memory 222372 kb
Host smart-044f34c1-8d52-400e-989f-1a9eae80065e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2617655357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.2617655357
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.3963572356
Short name T18
Test name
Test status
Simulation time 46339280 ps
CPU time 1.01 seconds
Started Jul 12 06:33:41 PM PDT 24
Finished Jul 12 06:33:43 PM PDT 24
Peak memory 206960 kb
Host smart-621bc45d-515a-4334-b5be-6dbdbaf76546
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963572356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.3963572356
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.4011792845
Short name T850
Test name
Test status
Simulation time 139319701 ps
CPU time 0.7 seconds
Started Jul 12 06:33:31 PM PDT 24
Finished Jul 12 06:33:33 PM PDT 24
Peak memory 205612 kb
Host smart-e5626938-3320-4074-afda-dc9ea0b9f939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011792845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.4011792845
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.2132881268
Short name T458
Test name
Test status
Simulation time 1953548044 ps
CPU time 7.47 seconds
Started Jul 12 06:33:31 PM PDT 24
Finished Jul 12 06:33:40 PM PDT 24
Peak memory 216136 kb
Host smart-a214941f-6f29-4566-b50b-702c2446ef44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132881268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.2132881268
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.1085206434
Short name T517
Test name
Test status
Simulation time 146599447 ps
CPU time 2.31 seconds
Started Jul 12 06:33:40 PM PDT 24
Finished Jul 12 06:33:44 PM PDT 24
Peak memory 216208 kb
Host smart-7af056db-3901-45ff-858e-c11d9fea9e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085206434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.1085206434
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.443921571
Short name T588
Test name
Test status
Simulation time 375409445 ps
CPU time 0.99 seconds
Started Jul 12 06:33:38 PM PDT 24
Finished Jul 12 06:33:40 PM PDT 24
Peak memory 206900 kb
Host smart-e329b559-0487-4d5c-9f54-7c33fd9ea94b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443921571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.443921571
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.2971227741
Short name T616
Test name
Test status
Simulation time 12185263466 ps
CPU time 24.46 seconds
Started Jul 12 06:33:40 PM PDT 24
Finished Jul 12 06:34:06 PM PDT 24
Peak memory 232764 kb
Host smart-3885c162-f82d-4733-93c9-e55c6a0666d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971227741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.2971227741
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.1725242331
Short name T947
Test name
Test status
Simulation time 76579336 ps
CPU time 0.69 seconds
Started Jul 12 06:33:51 PM PDT 24
Finished Jul 12 06:33:53 PM PDT 24
Peak memory 204920 kb
Host smart-6fa1b90b-98eb-4430-b8ad-36a11e2bcb69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725242331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
1725242331
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.826425765
Short name T759
Test name
Test status
Simulation time 126324621 ps
CPU time 4.25 seconds
Started Jul 12 06:33:50 PM PDT 24
Finished Jul 12 06:33:56 PM PDT 24
Peak memory 232612 kb
Host smart-9fa8d831-2ad1-4752-b412-d09a32fdc4f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826425765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.826425765
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.1249105168
Short name T684
Test name
Test status
Simulation time 121758303 ps
CPU time 0.79 seconds
Started Jul 12 06:33:38 PM PDT 24
Finished Jul 12 06:33:41 PM PDT 24
Peak memory 206520 kb
Host smart-36420701-37dd-4742-8c82-8c5e40ed4efb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249105168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.1249105168
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.2620221970
Short name T207
Test name
Test status
Simulation time 525803776416 ps
CPU time 300.62 seconds
Started Jul 12 06:33:48 PM PDT 24
Finished Jul 12 06:38:49 PM PDT 24
Peak memory 250948 kb
Host smart-398a0dfe-d404-422c-bd75-e8c103f7d639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620221970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.2620221970
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.1167984329
Short name T565
Test name
Test status
Simulation time 146631054137 ps
CPU time 292.27 seconds
Started Jul 12 06:33:50 PM PDT 24
Finished Jul 12 06:38:44 PM PDT 24
Peak memory 253536 kb
Host smart-7c758f57-814f-464d-ae04-6964c3f957ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167984329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.1167984329
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.2988288141
Short name T984
Test name
Test status
Simulation time 11284674453 ps
CPU time 118.99 seconds
Started Jul 12 06:33:49 PM PDT 24
Finished Jul 12 06:35:50 PM PDT 24
Peak memory 255068 kb
Host smart-0613097b-8ef6-4647-a06f-fc67534be961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988288141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.2988288141
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.1019017731
Short name T467
Test name
Test status
Simulation time 341935326 ps
CPU time 7.29 seconds
Started Jul 12 06:33:49 PM PDT 24
Finished Jul 12 06:33:57 PM PDT 24
Peak memory 240756 kb
Host smart-f06b9bd0-49c2-4b90-9872-44dcd10ca807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019017731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.1019017731
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.3095333779
Short name T571
Test name
Test status
Simulation time 45610916321 ps
CPU time 120.12 seconds
Started Jul 12 06:33:48 PM PDT 24
Finished Jul 12 06:35:49 PM PDT 24
Peak memory 257084 kb
Host smart-9ff7a4d8-1593-478e-91a7-96a952ad911b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095333779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmd
s.3095333779
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.4124423397
Short name T234
Test name
Test status
Simulation time 350538026 ps
CPU time 5.66 seconds
Started Jul 12 06:33:46 PM PDT 24
Finished Jul 12 06:33:53 PM PDT 24
Peak memory 232664 kb
Host smart-2e1ebba0-634d-4adb-a38e-ffb17fa30188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124423397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.4124423397
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.3024131146
Short name T347
Test name
Test status
Simulation time 3199412149 ps
CPU time 15.95 seconds
Started Jul 12 06:33:49 PM PDT 24
Finished Jul 12 06:34:07 PM PDT 24
Peak memory 232700 kb
Host smart-e91be743-d6e8-420f-beb4-b07f19d9f905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024131146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.3024131146
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.2620167639
Short name T694
Test name
Test status
Simulation time 3569750189 ps
CPU time 10.56 seconds
Started Jul 12 06:33:50 PM PDT 24
Finished Jul 12 06:34:03 PM PDT 24
Peak memory 232672 kb
Host smart-343243b7-6d3d-4b19-8a20-04cb3d46446c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620167639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.2620167639
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.326974114
Short name T853
Test name
Test status
Simulation time 356300356 ps
CPU time 3.94 seconds
Started Jul 12 06:33:50 PM PDT 24
Finished Jul 12 06:33:55 PM PDT 24
Peak memory 224444 kb
Host smart-b20094ed-f983-4edc-8971-cd141dcbeef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326974114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.326974114
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.2446090906
Short name T350
Test name
Test status
Simulation time 321464352 ps
CPU time 3.59 seconds
Started Jul 12 06:33:49 PM PDT 24
Finished Jul 12 06:33:54 PM PDT 24
Peak memory 222984 kb
Host smart-81824b6b-92bc-4fb9-a9b5-c02fdaf6f3a2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2446090906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.2446090906
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.1072281786
Short name T766
Test name
Test status
Simulation time 20514963672 ps
CPU time 72.99 seconds
Started Jul 12 06:33:49 PM PDT 24
Finished Jul 12 06:35:04 PM PDT 24
Peak memory 232780 kb
Host smart-c816c943-a8e5-4dc8-9bf0-28e96b290a05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072281786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.1072281786
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.1067353894
Short name T638
Test name
Test status
Simulation time 7032220662 ps
CPU time 11.07 seconds
Started Jul 12 06:33:38 PM PDT 24
Finished Jul 12 06:33:50 PM PDT 24
Peak memory 216388 kb
Host smart-3b8e97f1-b43c-46d5-93de-da9740154425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067353894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.1067353894
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.220872451
Short name T341
Test name
Test status
Simulation time 2311985979 ps
CPU time 7.36 seconds
Started Jul 12 06:33:38 PM PDT 24
Finished Jul 12 06:33:46 PM PDT 24
Peak memory 216256 kb
Host smart-26d4827f-34ec-48c9-8255-0ef639aa6c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220872451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.220872451
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.3614288215
Short name T739
Test name
Test status
Simulation time 104193472 ps
CPU time 1.41 seconds
Started Jul 12 06:33:49 PM PDT 24
Finished Jul 12 06:33:52 PM PDT 24
Peak memory 216060 kb
Host smart-40825c87-ee52-4f29-9813-09db46fe94d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614288215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.3614288215
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.4055334241
Short name T472
Test name
Test status
Simulation time 24970635 ps
CPU time 0.73 seconds
Started Jul 12 06:33:49 PM PDT 24
Finished Jul 12 06:33:51 PM PDT 24
Peak memory 205940 kb
Host smart-0142cfc2-0548-4dac-a650-caf38d50a5da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055334241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.4055334241
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.143774222
Short name T388
Test name
Test status
Simulation time 10306890964 ps
CPU time 33.19 seconds
Started Jul 12 06:33:50 PM PDT 24
Finished Jul 12 06:34:24 PM PDT 24
Peak memory 232692 kb
Host smart-0f86d9d5-c982-481f-bc13-0245f6fdf58e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143774222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.143774222
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.2389319974
Short name T901
Test name
Test status
Simulation time 12398274 ps
CPU time 0.71 seconds
Started Jul 12 06:33:56 PM PDT 24
Finished Jul 12 06:33:58 PM PDT 24
Peak memory 205448 kb
Host smart-67666b76-002b-4511-96c2-69af5c173ca4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389319974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
2389319974
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.2526740224
Short name T513
Test name
Test status
Simulation time 822926068 ps
CPU time 6.24 seconds
Started Jul 12 06:34:03 PM PDT 24
Finished Jul 12 06:34:10 PM PDT 24
Peak memory 224400 kb
Host smart-1d3fe716-01a3-45e3-a504-069e208c1623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526740224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.2526740224
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.3482670642
Short name T919
Test name
Test status
Simulation time 16004993 ps
CPU time 0.75 seconds
Started Jul 12 06:33:50 PM PDT 24
Finished Jul 12 06:33:53 PM PDT 24
Peak memory 205820 kb
Host smart-b15c63fe-9211-49a1-9298-c8c6feffd23b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482670642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.3482670642
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.4293891451
Short name T965
Test name
Test status
Simulation time 17763267179 ps
CPU time 39.78 seconds
Started Jul 12 06:33:58 PM PDT 24
Finished Jul 12 06:34:39 PM PDT 24
Peak memory 250468 kb
Host smart-c8169e59-c653-480b-bab6-02533b4f176d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293891451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.4293891451
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.4093938915
Short name T769
Test name
Test status
Simulation time 184818400323 ps
CPU time 396.22 seconds
Started Jul 12 06:33:58 PM PDT 24
Finished Jul 12 06:40:36 PM PDT 24
Peak memory 249180 kb
Host smart-e03c2cdf-c800-42ef-9317-1fdc22c4e9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093938915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.4093938915
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.2865193830
Short name T26
Test name
Test status
Simulation time 15353641323 ps
CPU time 100.22 seconds
Started Jul 12 06:33:56 PM PDT 24
Finished Jul 12 06:35:38 PM PDT 24
Peak memory 265400 kb
Host smart-f550e2be-f4ca-46e5-8545-f2020153551c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865193830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.2865193830
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.39489533
Short name T568
Test name
Test status
Simulation time 782292140 ps
CPU time 17.46 seconds
Started Jul 12 06:33:58 PM PDT 24
Finished Jul 12 06:34:17 PM PDT 24
Peak memory 234204 kb
Host smart-8f63be5d-ca1b-4ea0-bc95-d84417c5774c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39489533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmds.39489533
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.1552933159
Short name T14
Test name
Test status
Simulation time 1209699261 ps
CPU time 12.73 seconds
Started Jul 12 06:33:47 PM PDT 24
Finished Jul 12 06:34:01 PM PDT 24
Peak memory 232552 kb
Host smart-b23319a3-892f-424b-812f-bd4ebc1a4c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552933159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.1552933159
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.2331349029
Short name T400
Test name
Test status
Simulation time 1042320889 ps
CPU time 18.39 seconds
Started Jul 12 06:33:52 PM PDT 24
Finished Jul 12 06:34:12 PM PDT 24
Peak memory 232620 kb
Host smart-c8d3ba9f-c828-4b5b-9ff8-0ac5b8d75f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331349029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.2331349029
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.1695788867
Short name T337
Test name
Test status
Simulation time 3734044576 ps
CPU time 5.51 seconds
Started Jul 12 06:33:48 PM PDT 24
Finished Jul 12 06:33:55 PM PDT 24
Peak memory 232620 kb
Host smart-0b404a15-334c-46e8-b92c-f0bcc6ca0cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695788867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.1695788867
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.3912906675
Short name T457
Test name
Test status
Simulation time 2377901513 ps
CPU time 5.71 seconds
Started Jul 12 06:33:49 PM PDT 24
Finished Jul 12 06:33:57 PM PDT 24
Peak memory 224568 kb
Host smart-aefb68f4-2ee7-484f-aa19-db66b0964ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912906675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.3912906675
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.2274256394
Short name T55
Test name
Test status
Simulation time 7255969583 ps
CPU time 19.28 seconds
Started Jul 12 06:33:54 PM PDT 24
Finished Jul 12 06:34:15 PM PDT 24
Peak memory 220140 kb
Host smart-6df571ea-87d2-4131-a434-2fb9fdd305c9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2274256394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.2274256394
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.2124130108
Short name T197
Test name
Test status
Simulation time 82810557752 ps
CPU time 191.13 seconds
Started Jul 12 06:33:55 PM PDT 24
Finished Jul 12 06:37:07 PM PDT 24
Peak memory 249356 kb
Host smart-ae80dfc4-a09f-4aca-ac15-1e19f0e7406a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124130108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.2124130108
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.1791558199
Short name T444
Test name
Test status
Simulation time 1844457601 ps
CPU time 2.97 seconds
Started Jul 12 06:33:47 PM PDT 24
Finished Jul 12 06:33:51 PM PDT 24
Peak memory 216156 kb
Host smart-d82e7990-13ce-483d-a97f-1c8fa64192dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791558199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.1791558199
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.2632963081
Short name T465
Test name
Test status
Simulation time 2519514470 ps
CPU time 4.61 seconds
Started Jul 12 06:33:48 PM PDT 24
Finished Jul 12 06:33:53 PM PDT 24
Peak memory 216252 kb
Host smart-48fd6a94-4d9d-44fc-8c05-b63815e9a5a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632963081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.2632963081
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.1768585382
Short name T276
Test name
Test status
Simulation time 103582552 ps
CPU time 0.88 seconds
Started Jul 12 06:33:50 PM PDT 24
Finished Jul 12 06:33:53 PM PDT 24
Peak memory 206692 kb
Host smart-568ac15a-8205-4841-a29b-34c3c07eaec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768585382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.1768585382
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.1713161102
Short name T830
Test name
Test status
Simulation time 137925841 ps
CPU time 1.03 seconds
Started Jul 12 06:33:48 PM PDT 24
Finished Jul 12 06:33:50 PM PDT 24
Peak memory 205908 kb
Host smart-d5f31d31-2318-4790-8e96-0b3158ae66ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713161102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.1713161102
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.1807041975
Short name T735
Test name
Test status
Simulation time 3249775183 ps
CPU time 12.56 seconds
Started Jul 12 06:33:59 PM PDT 24
Finished Jul 12 06:34:13 PM PDT 24
Peak memory 232276 kb
Host smart-15946172-966f-4e92-aace-2627e5e7ce8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807041975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.1807041975
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.1786827186
Short name T792
Test name
Test status
Simulation time 14574394 ps
CPU time 0.71 seconds
Started Jul 12 06:34:04 PM PDT 24
Finished Jul 12 06:34:05 PM PDT 24
Peak memory 205468 kb
Host smart-0089b349-5782-4cd8-a04a-7731ed1d1e22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786827186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
1786827186
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.4125267035
Short name T868
Test name
Test status
Simulation time 102038249 ps
CPU time 2.35 seconds
Started Jul 12 06:33:57 PM PDT 24
Finished Jul 12 06:34:01 PM PDT 24
Peak memory 232524 kb
Host smart-c428a72c-7c6a-4a60-ae6c-1f160530d476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125267035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.4125267035
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.4191209431
Short name T312
Test name
Test status
Simulation time 55834658 ps
CPU time 0.81 seconds
Started Jul 12 06:33:56 PM PDT 24
Finished Jul 12 06:33:58 PM PDT 24
Peak memory 206432 kb
Host smart-939b4ce9-93c4-4f68-a7bf-df252c80093b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191209431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.4191209431
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.756010479
Short name T941
Test name
Test status
Simulation time 221840943166 ps
CPU time 369.42 seconds
Started Jul 12 06:33:59 PM PDT 24
Finished Jul 12 06:40:10 PM PDT 24
Peak memory 252536 kb
Host smart-ea8b32f2-4600-416a-bb27-02d958b73352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756010479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.756010479
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.104467747
Short name T256
Test name
Test status
Simulation time 3924434663 ps
CPU time 55.49 seconds
Started Jul 12 06:33:56 PM PDT 24
Finished Jul 12 06:34:54 PM PDT 24
Peak memory 253020 kb
Host smart-a12ce0bf-7966-4979-973d-c796e3f179ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104467747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.104467747
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.267980350
Short name T474
Test name
Test status
Simulation time 1525822826 ps
CPU time 25.89 seconds
Started Jul 12 06:34:02 PM PDT 24
Finished Jul 12 06:34:29 PM PDT 24
Peak memory 222360 kb
Host smart-e027a85d-081b-4518-a75a-935eef1ed18d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267980350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idle
.267980350
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.3335167507
Short name T268
Test name
Test status
Simulation time 7253426531 ps
CPU time 29.16 seconds
Started Jul 12 06:33:56 PM PDT 24
Finished Jul 12 06:34:27 PM PDT 24
Peak memory 224508 kb
Host smart-4857e7d8-888f-4596-98e9-42d08b32c0a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335167507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.3335167507
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.2407136782
Short name T237
Test name
Test status
Simulation time 11456315689 ps
CPU time 80.49 seconds
Started Jul 12 06:33:57 PM PDT 24
Finished Jul 12 06:35:19 PM PDT 24
Peak memory 247928 kb
Host smart-65e5f3c0-98d7-4193-bdcb-ade3ac260cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407136782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmd
s.2407136782
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.3363514701
Short name T343
Test name
Test status
Simulation time 263201425 ps
CPU time 5.45 seconds
Started Jul 12 06:33:56 PM PDT 24
Finished Jul 12 06:34:02 PM PDT 24
Peak memory 232592 kb
Host smart-0efbe595-95e3-4ff5-9185-c5d41c0a36b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363514701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.3363514701
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.76804797
Short name T401
Test name
Test status
Simulation time 4821219465 ps
CPU time 18.38 seconds
Started Jul 12 06:33:59 PM PDT 24
Finished Jul 12 06:34:19 PM PDT 24
Peak memory 232688 kb
Host smart-8ed1c405-0d74-49ad-bf1d-d611499821a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76804797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.76804797
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.2859781096
Short name T399
Test name
Test status
Simulation time 1015989511 ps
CPU time 7.69 seconds
Started Jul 12 06:33:57 PM PDT 24
Finished Jul 12 06:34:06 PM PDT 24
Peak memory 232688 kb
Host smart-6c3cdaee-9728-4204-a1c6-4819a152294c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859781096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.2859781096
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.1332342032
Short name T75
Test name
Test status
Simulation time 288074361 ps
CPU time 2.26 seconds
Started Jul 12 06:33:55 PM PDT 24
Finished Jul 12 06:33:59 PM PDT 24
Peak memory 223836 kb
Host smart-e4345719-2920-4964-bbd2-05eee9b5694c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332342032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.1332342032
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.2027856267
Short name T324
Test name
Test status
Simulation time 560710610 ps
CPU time 5.07 seconds
Started Jul 12 06:33:56 PM PDT 24
Finished Jul 12 06:34:03 PM PDT 24
Peak memory 223072 kb
Host smart-af04464f-96cd-4fb2-9f40-eb750d188a25
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2027856267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.2027856267
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.1556569115
Short name T21
Test name
Test status
Simulation time 21418212860 ps
CPU time 42.8 seconds
Started Jul 12 06:34:06 PM PDT 24
Finished Jul 12 06:34:50 PM PDT 24
Peak memory 235432 kb
Host smart-ab6bc28c-8abf-43c2-b48a-6599706754a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556569115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.1556569115
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.1955382173
Short name T509
Test name
Test status
Simulation time 9444544695 ps
CPU time 24.47 seconds
Started Jul 12 06:34:01 PM PDT 24
Finished Jul 12 06:34:26 PM PDT 24
Peak memory 216220 kb
Host smart-fa793dd7-d3b9-46f4-a53c-39a3aa15e94a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955382173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.1955382173
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.1222090565
Short name T993
Test name
Test status
Simulation time 12315262 ps
CPU time 0.73 seconds
Started Jul 12 06:33:57 PM PDT 24
Finished Jul 12 06:33:59 PM PDT 24
Peak memory 205764 kb
Host smart-72da3248-e95e-4967-a185-edbedc7f3a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222090565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.1222090565
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.3519594903
Short name T926
Test name
Test status
Simulation time 94451074 ps
CPU time 1.34 seconds
Started Jul 12 06:33:55 PM PDT 24
Finished Jul 12 06:33:58 PM PDT 24
Peak memory 216188 kb
Host smart-cc33338a-e850-45c6-9196-f15ffad8a8ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519594903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.3519594903
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.1743058234
Short name T319
Test name
Test status
Simulation time 17830705 ps
CPU time 0.79 seconds
Started Jul 12 06:33:57 PM PDT 24
Finished Jul 12 06:33:59 PM PDT 24
Peak memory 205924 kb
Host smart-5a8b2b4e-49c1-4452-9ba7-a2cfc0e6e1c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743058234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.1743058234
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.642776361
Short name T544
Test name
Test status
Simulation time 556189477 ps
CPU time 6.12 seconds
Started Jul 12 06:33:58 PM PDT 24
Finished Jul 12 06:34:06 PM PDT 24
Peak memory 232616 kb
Host smart-232eeeac-e871-4569-ae79-5f813a30de78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642776361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.642776361
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.2935980784
Short name T679
Test name
Test status
Simulation time 40895890 ps
CPU time 0.71 seconds
Started Jul 12 06:34:04 PM PDT 24
Finished Jul 12 06:34:06 PM PDT 24
Peak memory 205460 kb
Host smart-50c6cead-9a67-4a4c-95d9-067150e9f5c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935980784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
2935980784
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.1456304816
Short name T644
Test name
Test status
Simulation time 4272806937 ps
CPU time 21.01 seconds
Started Jul 12 06:34:04 PM PDT 24
Finished Jul 12 06:34:25 PM PDT 24
Peak memory 232744 kb
Host smart-7aef2b9f-9ca4-4dbf-9301-375cea63c7a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456304816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.1456304816
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.3655458523
Short name T348
Test name
Test status
Simulation time 352159257 ps
CPU time 0.88 seconds
Started Jul 12 06:34:09 PM PDT 24
Finished Jul 12 06:34:11 PM PDT 24
Peak memory 206396 kb
Host smart-56ce1689-9279-45b2-99b4-a36a2d007245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655458523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.3655458523
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.1387663225
Short name T609
Test name
Test status
Simulation time 884410182 ps
CPU time 16.9 seconds
Started Jul 12 06:34:02 PM PDT 24
Finished Jul 12 06:34:19 PM PDT 24
Peak memory 239688 kb
Host smart-83e1b8de-6163-4ff6-b4c3-5194bd58720d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387663225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.1387663225
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.1686172909
Short name T251
Test name
Test status
Simulation time 20624429454 ps
CPU time 166.63 seconds
Started Jul 12 06:34:04 PM PDT 24
Finished Jul 12 06:36:51 PM PDT 24
Peak memory 249132 kb
Host smart-60ee6b7d-6e22-42a5-952d-2850c87124be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686172909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.1686172909
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.1853544131
Short name T130
Test name
Test status
Simulation time 9240959755 ps
CPU time 58.77 seconds
Started Jul 12 06:34:09 PM PDT 24
Finished Jul 12 06:35:09 PM PDT 24
Peak memory 250080 kb
Host smart-e7538167-19cc-4644-9406-f177d46a0c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853544131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.1853544131
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.2604743620
Short name T309
Test name
Test status
Simulation time 690807400 ps
CPU time 12.02 seconds
Started Jul 12 06:34:05 PM PDT 24
Finished Jul 12 06:34:18 PM PDT 24
Peak memory 233660 kb
Host smart-fb0b3f2e-e64b-4adc-a19c-1cdea4596940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604743620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.2604743620
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.4257944138
Short name T581
Test name
Test status
Simulation time 17797350296 ps
CPU time 33.16 seconds
Started Jul 12 06:34:03 PM PDT 24
Finished Jul 12 06:34:37 PM PDT 24
Peak memory 233780 kb
Host smart-ed1b500b-d796-466e-a407-2eb1828f48b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257944138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.4257944138
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.3251499935
Short name T621
Test name
Test status
Simulation time 946226116 ps
CPU time 9.58 seconds
Started Jul 12 06:34:05 PM PDT 24
Finished Jul 12 06:34:16 PM PDT 24
Peak memory 232524 kb
Host smart-027ef2ba-d936-4b93-81ae-ff0b70894960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251499935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.3251499935
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.2090994203
Short name T54
Test name
Test status
Simulation time 7656688978 ps
CPU time 29.06 seconds
Started Jul 12 06:34:03 PM PDT 24
Finished Jul 12 06:34:32 PM PDT 24
Peak memory 224556 kb
Host smart-20305d69-41f9-40b2-9ea5-ecc3bbdbd395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090994203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.2090994203
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.2214772442
Short name T620
Test name
Test status
Simulation time 145545742 ps
CPU time 2.35 seconds
Started Jul 12 06:34:02 PM PDT 24
Finished Jul 12 06:34:05 PM PDT 24
Peak memory 224396 kb
Host smart-a98318e4-fe38-44e4-a067-d19a869787c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214772442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.2214772442
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.1855517380
Short name T794
Test name
Test status
Simulation time 119901476 ps
CPU time 2.54 seconds
Started Jul 12 06:34:03 PM PDT 24
Finished Jul 12 06:34:06 PM PDT 24
Peak memory 232256 kb
Host smart-cc9aa2ae-333d-428d-9ac8-fe9b325059bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855517380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.1855517380
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.2461292280
Short name T362
Test name
Test status
Simulation time 1087478582 ps
CPU time 5.95 seconds
Started Jul 12 06:34:05 PM PDT 24
Finished Jul 12 06:34:12 PM PDT 24
Peak memory 222548 kb
Host smart-734e57a0-c93a-485b-ac66-e8fad4c1776c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2461292280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.2461292280
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.922118643
Short name T448
Test name
Test status
Simulation time 40815677263 ps
CPU time 129.82 seconds
Started Jul 12 06:34:09 PM PDT 24
Finished Jul 12 06:36:20 PM PDT 24
Peak memory 256336 kb
Host smart-e116856e-4e06-49fe-9919-77ee59680915
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922118643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stres
s_all.922118643
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.3320304421
Short name T569
Test name
Test status
Simulation time 7261914408 ps
CPU time 19.55 seconds
Started Jul 12 06:34:09 PM PDT 24
Finished Jul 12 06:34:30 PM PDT 24
Peak memory 216300 kb
Host smart-fb90f7a4-6d6b-44e3-917c-956e185f7d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320304421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.3320304421
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.2177117772
Short name T291
Test name
Test status
Simulation time 16242350 ps
CPU time 0.73 seconds
Started Jul 12 06:34:03 PM PDT 24
Finished Jul 12 06:34:05 PM PDT 24
Peak memory 205632 kb
Host smart-5119a3a3-e74a-45f4-9f37-86af94dd1df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177117772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.2177117772
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.2487144096
Short name T987
Test name
Test status
Simulation time 30015201 ps
CPU time 0.69 seconds
Started Jul 12 06:34:02 PM PDT 24
Finished Jul 12 06:34:04 PM PDT 24
Peak memory 205580 kb
Host smart-f005d745-776e-48d5-877d-78e3f3d44149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487144096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.2487144096
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.3092928244
Short name T775
Test name
Test status
Simulation time 140574491 ps
CPU time 0.97 seconds
Started Jul 12 06:34:04 PM PDT 24
Finished Jul 12 06:34:06 PM PDT 24
Peak memory 206884 kb
Host smart-316f70d4-5d11-408e-b09e-17242505b69a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092928244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.3092928244
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.3673222948
Short name T12
Test name
Test status
Simulation time 2881668567 ps
CPU time 11.36 seconds
Started Jul 12 06:34:07 PM PDT 24
Finished Jul 12 06:34:19 PM PDT 24
Peak memory 232892 kb
Host smart-cfb380ef-b0c2-4d73-a4f4-c16bf26a03a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673222948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.3673222948
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.81330847
Short name T282
Test name
Test status
Simulation time 42616113 ps
CPU time 0.71 seconds
Started Jul 12 06:34:11 PM PDT 24
Finished Jul 12 06:34:13 PM PDT 24
Peak memory 205720 kb
Host smart-b09c03af-3315-45e2-b254-e66cadf0bfca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81330847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.81330847
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.1724293131
Short name T327
Test name
Test status
Simulation time 219254547 ps
CPU time 3.46 seconds
Started Jul 12 06:34:15 PM PDT 24
Finished Jul 12 06:34:20 PM PDT 24
Peak memory 224404 kb
Host smart-f6dd3827-29b1-4e05-a9df-18648816e796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724293131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.1724293131
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.671730806
Short name T636
Test name
Test status
Simulation time 24020070 ps
CPU time 0.79 seconds
Started Jul 12 06:34:04 PM PDT 24
Finished Jul 12 06:34:06 PM PDT 24
Peak memory 206548 kb
Host smart-3e47e12e-a338-4cae-b322-5339d3cabda2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671730806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.671730806
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.724240937
Short name T716
Test name
Test status
Simulation time 4621520414 ps
CPU time 21.81 seconds
Started Jul 12 06:34:11 PM PDT 24
Finished Jul 12 06:34:35 PM PDT 24
Peak memory 224536 kb
Host smart-f311b100-2733-418b-bdb2-780dd2500665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724240937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.724240937
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.4100002532
Short name T564
Test name
Test status
Simulation time 18293300450 ps
CPU time 65.39 seconds
Started Jul 12 06:34:11 PM PDT 24
Finished Jul 12 06:35:18 PM PDT 24
Peak memory 252500 kb
Host smart-7e9bdc92-1304-4d8a-acf3-b799c096494f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100002532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.4100002532
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.1388939172
Short name T242
Test name
Test status
Simulation time 196290665712 ps
CPU time 251.57 seconds
Started Jul 12 06:34:14 PM PDT 24
Finished Jul 12 06:38:27 PM PDT 24
Peak memory 249168 kb
Host smart-af76e7b2-5625-4423-b45d-9a57ceec08f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388939172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.1388939172
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.3773700907
Short name T912
Test name
Test status
Simulation time 687737930 ps
CPU time 16.71 seconds
Started Jul 12 06:34:14 PM PDT 24
Finished Jul 12 06:34:32 PM PDT 24
Peak memory 249044 kb
Host smart-da2b210a-092d-4a58-93bd-8288f3b87927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773700907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.3773700907
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.4073061028
Short name T369
Test name
Test status
Simulation time 1997077706 ps
CPU time 29.16 seconds
Started Jul 12 06:34:15 PM PDT 24
Finished Jul 12 06:34:45 PM PDT 24
Peak memory 249916 kb
Host smart-47ca96ba-9a13-479f-90da-9de56a5bd6be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073061028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmd
s.4073061028
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.1099706971
Short name T915
Test name
Test status
Simulation time 899994948 ps
CPU time 4.77 seconds
Started Jul 12 06:34:10 PM PDT 24
Finished Jul 12 06:34:16 PM PDT 24
Peak memory 224384 kb
Host smart-2575e114-1b96-41b8-afe2-6b45ad2c140c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099706971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.1099706971
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.641704973
Short name T887
Test name
Test status
Simulation time 1018667773 ps
CPU time 21.98 seconds
Started Jul 12 06:34:13 PM PDT 24
Finished Jul 12 06:34:36 PM PDT 24
Peak memory 236904 kb
Host smart-5e836c03-b9c1-43bb-bf28-6629464a296d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641704973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.641704973
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.2526520241
Short name T320
Test name
Test status
Simulation time 112362489 ps
CPU time 2.62 seconds
Started Jul 12 06:34:17 PM PDT 24
Finished Jul 12 06:34:21 PM PDT 24
Peak memory 232588 kb
Host smart-c3089380-aed4-49ea-975c-e9086864c11a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526520241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.2526520241
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.704734826
Short name T378
Test name
Test status
Simulation time 831251726 ps
CPU time 2.64 seconds
Started Jul 12 06:34:05 PM PDT 24
Finished Jul 12 06:34:09 PM PDT 24
Peak memory 224384 kb
Host smart-b4e6f9fb-8a4e-4b4e-821f-8fcdac9c7c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704734826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.704734826
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.3292235361
Short name T490
Test name
Test status
Simulation time 1047239968 ps
CPU time 9.42 seconds
Started Jul 12 06:34:10 PM PDT 24
Finished Jul 12 06:34:21 PM PDT 24
Peak memory 222512 kb
Host smart-8a0a551b-1e37-4af5-9b90-1a2618fbc646
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3292235361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.3292235361
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.3360687280
Short name T879
Test name
Test status
Simulation time 167003079 ps
CPU time 0.97 seconds
Started Jul 12 06:34:13 PM PDT 24
Finished Jul 12 06:34:16 PM PDT 24
Peak memory 205640 kb
Host smart-453cb716-e5b8-4473-86d3-da969c21c2f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360687280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.3360687280
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.53747897
Short name T479
Test name
Test status
Simulation time 20621238917 ps
CPU time 21.86 seconds
Started Jul 12 06:34:05 PM PDT 24
Finished Jul 12 06:34:28 PM PDT 24
Peak memory 216232 kb
Host smart-f9c13f62-db7b-47a3-8cd8-54c2ff041026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53747897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.53747897
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.1411064179
Short name T790
Test name
Test status
Simulation time 8503364123 ps
CPU time 5.97 seconds
Started Jul 12 06:34:05 PM PDT 24
Finished Jul 12 06:34:13 PM PDT 24
Peak memory 217644 kb
Host smart-121b38af-bce7-44af-89df-f34803dc9e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411064179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.1411064179
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.1581573712
Short name T403
Test name
Test status
Simulation time 123882326 ps
CPU time 4.91 seconds
Started Jul 12 06:34:05 PM PDT 24
Finished Jul 12 06:34:12 PM PDT 24
Peak memory 216284 kb
Host smart-21086c60-2f60-42cc-a4e6-c4c96818a49d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581573712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.1581573712
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.791525298
Short name T732
Test name
Test status
Simulation time 99895801 ps
CPU time 0.96 seconds
Started Jul 12 06:34:04 PM PDT 24
Finished Jul 12 06:34:05 PM PDT 24
Peak memory 206908 kb
Host smart-0684cea2-14e4-447b-b322-095dbc28a128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791525298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.791525298
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.1456049072
Short name T221
Test name
Test status
Simulation time 19282519679 ps
CPU time 17.28 seconds
Started Jul 12 06:34:13 PM PDT 24
Finished Jul 12 06:34:32 PM PDT 24
Peak memory 232728 kb
Host smart-b7b1ae3b-cb68-4598-a7cc-b280a42b99f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456049072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.1456049072
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.1681055819
Short name T730
Test name
Test status
Simulation time 20928666 ps
CPU time 0.72 seconds
Started Jul 12 06:34:20 PM PDT 24
Finished Jul 12 06:34:23 PM PDT 24
Peak memory 205828 kb
Host smart-4285a4fa-3241-4f1a-a92f-97a14bc5188c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681055819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
1681055819
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.4113489077
Short name T815
Test name
Test status
Simulation time 798585965 ps
CPU time 4.44 seconds
Started Jul 12 06:34:12 PM PDT 24
Finished Jul 12 06:34:18 PM PDT 24
Peak memory 232604 kb
Host smart-b85d4dd1-1ea1-4982-9d7b-d38981a89b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113489077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.4113489077
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.3608319796
Short name T392
Test name
Test status
Simulation time 47332447 ps
CPU time 0.78 seconds
Started Jul 12 06:34:11 PM PDT 24
Finished Jul 12 06:34:14 PM PDT 24
Peak memory 206508 kb
Host smart-8382db37-f2fa-4c78-ad94-1f5a1deef431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608319796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.3608319796
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.2538426695
Short name T543
Test name
Test status
Simulation time 18248922455 ps
CPU time 35.77 seconds
Started Jul 12 06:34:20 PM PDT 24
Finished Jul 12 06:34:58 PM PDT 24
Peak memory 249132 kb
Host smart-821e9b74-0025-40f4-8e10-37fc0cd164f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538426695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.2538426695
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.2807760967
Short name T52
Test name
Test status
Simulation time 81293626 ps
CPU time 2.02 seconds
Started Jul 12 06:34:20 PM PDT 24
Finished Jul 12 06:34:25 PM PDT 24
Peak memory 217580 kb
Host smart-75cc924a-1773-4cb1-9f83-aeb18206fbbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807760967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.2807760967
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.703229254
Short name T188
Test name
Test status
Simulation time 51192095887 ps
CPU time 134.25 seconds
Started Jul 12 06:34:21 PM PDT 24
Finished Jul 12 06:36:37 PM PDT 24
Peak memory 266356 kb
Host smart-d44595d9-1dd6-42a5-ae22-dfe4b5674f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703229254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idle
.703229254
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.4081320458
Short name T725
Test name
Test status
Simulation time 419696007 ps
CPU time 8.51 seconds
Started Jul 12 06:34:14 PM PDT 24
Finished Jul 12 06:34:24 PM PDT 24
Peak memory 232656 kb
Host smart-db7879fe-4e9c-4480-a258-7a034d8d60c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081320458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.4081320458
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.1513841181
Short name T170
Test name
Test status
Simulation time 9091888270 ps
CPU time 62.6 seconds
Started Jul 12 06:34:11 PM PDT 24
Finished Jul 12 06:35:15 PM PDT 24
Peak memory 252744 kb
Host smart-28659105-0d19-41dc-a5c7-9fa873d12af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513841181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmd
s.1513841181
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.1169594806
Short name T593
Test name
Test status
Simulation time 959831396 ps
CPU time 4.63 seconds
Started Jul 12 06:34:11 PM PDT 24
Finished Jul 12 06:34:17 PM PDT 24
Peak memory 232584 kb
Host smart-55a7fb65-4133-4333-95ee-c4eae0a20a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169594806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.1169594806
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.2630178017
Short name T990
Test name
Test status
Simulation time 1076897157 ps
CPU time 5.1 seconds
Started Jul 12 06:34:16 PM PDT 24
Finished Jul 12 06:34:22 PM PDT 24
Peak memory 224364 kb
Host smart-d7c9ea8d-ffa9-471c-836d-068337fc3c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630178017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.2630178017
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.3519030791
Short name T432
Test name
Test status
Simulation time 8236288216 ps
CPU time 13.79 seconds
Started Jul 12 06:34:12 PM PDT 24
Finished Jul 12 06:34:27 PM PDT 24
Peak memory 232692 kb
Host smart-a7728dce-e5f7-45d9-8044-c87a9a728062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519030791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.3519030791
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.364492482
Short name T549
Test name
Test status
Simulation time 16151569127 ps
CPU time 7.17 seconds
Started Jul 12 06:34:13 PM PDT 24
Finished Jul 12 06:34:22 PM PDT 24
Peak memory 232748 kb
Host smart-e0ba7fa6-c909-4f4e-9442-c702fa0efae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364492482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.364492482
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.1592996934
Short name T835
Test name
Test status
Simulation time 5595365971 ps
CPU time 8.86 seconds
Started Jul 12 06:34:13 PM PDT 24
Finished Jul 12 06:34:23 PM PDT 24
Peak memory 222104 kb
Host smart-1815baee-5751-4f6f-8f58-d5d822b224a0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1592996934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.1592996934
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.333640192
Short name T664
Test name
Test status
Simulation time 19113461582 ps
CPU time 19.51 seconds
Started Jul 12 06:34:11 PM PDT 24
Finished Jul 12 06:34:32 PM PDT 24
Peak memory 216548 kb
Host smart-5ea860f1-4a14-4dc5-82ad-709640880305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333640192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.333640192
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.1249471359
Short name T950
Test name
Test status
Simulation time 10488476062 ps
CPU time 15.17 seconds
Started Jul 12 06:34:11 PM PDT 24
Finished Jul 12 06:34:28 PM PDT 24
Peak memory 216308 kb
Host smart-e1c12db0-ff20-49c8-8e07-90a98ee7c66c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249471359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.1249471359
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.937648536
Short name T958
Test name
Test status
Simulation time 67415105 ps
CPU time 1.61 seconds
Started Jul 12 06:34:12 PM PDT 24
Finished Jul 12 06:34:15 PM PDT 24
Peak memory 216176 kb
Host smart-500048e7-6d4d-4a6c-a0fe-10a30cc2b519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937648536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.937648536
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.4057867316
Short name T473
Test name
Test status
Simulation time 64907277 ps
CPU time 0.82 seconds
Started Jul 12 06:34:12 PM PDT 24
Finished Jul 12 06:34:14 PM PDT 24
Peak memory 205908 kb
Host smart-1faa5c51-e714-4cfb-904a-4760c9da74fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057867316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.4057867316
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.871396226
Short name T748
Test name
Test status
Simulation time 385546666 ps
CPU time 6.76 seconds
Started Jul 12 06:34:11 PM PDT 24
Finished Jul 12 06:34:20 PM PDT 24
Peak memory 232640 kb
Host smart-bd24164f-d3b9-445a-b8b7-28fdf7615e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871396226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.871396226
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.579798569
Short name T824
Test name
Test status
Simulation time 13303219 ps
CPU time 0.73 seconds
Started Jul 12 06:34:20 PM PDT 24
Finished Jul 12 06:34:23 PM PDT 24
Peak memory 205452 kb
Host smart-ee33bec4-220d-4268-9ca8-a967a526e039
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579798569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.579798569
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.2139222577
Short name T749
Test name
Test status
Simulation time 723602476 ps
CPU time 6.87 seconds
Started Jul 12 06:34:20 PM PDT 24
Finished Jul 12 06:34:28 PM PDT 24
Peak memory 224388 kb
Host smart-c90b219a-c8df-4e45-a3ec-edc395368e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139222577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.2139222577
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.1485627842
Short name T836
Test name
Test status
Simulation time 15870286 ps
CPU time 0.79 seconds
Started Jul 12 06:34:16 PM PDT 24
Finished Jul 12 06:34:18 PM PDT 24
Peak memory 206824 kb
Host smart-362f2e90-09fd-49ac-b4a3-babe3dd9984c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485627842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.1485627842
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.3915921034
Short name T206
Test name
Test status
Simulation time 3130321630 ps
CPU time 77.2 seconds
Started Jul 12 06:34:21 PM PDT 24
Finished Jul 12 06:35:40 PM PDT 24
Peak memory 255020 kb
Host smart-f8db3337-f96c-4db3-8828-642141b1af46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915921034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.3915921034
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.3260540081
Short name T246
Test name
Test status
Simulation time 80746307499 ps
CPU time 649.76 seconds
Started Jul 12 06:34:23 PM PDT 24
Finished Jul 12 06:45:13 PM PDT 24
Peak memory 266540 kb
Host smart-7455db7b-23c5-45bc-8892-fba420591c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260540081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.3260540081
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.2023535330
Short name T838
Test name
Test status
Simulation time 31936506803 ps
CPU time 92.15 seconds
Started Jul 12 06:34:19 PM PDT 24
Finished Jul 12 06:35:52 PM PDT 24
Peak memory 249172 kb
Host smart-5003501b-1383-4683-bfb7-83d39593b196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023535330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.2023535330
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.1646029982
Short name T888
Test name
Test status
Simulation time 1918904892 ps
CPU time 16.7 seconds
Started Jul 12 06:34:21 PM PDT 24
Finished Jul 12 06:34:39 PM PDT 24
Peak memory 232652 kb
Host smart-1918ce59-859a-4899-8abd-950f307ebe42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646029982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.1646029982
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.1560358554
Short name T869
Test name
Test status
Simulation time 26773318523 ps
CPU time 57.15 seconds
Started Jul 12 06:34:20 PM PDT 24
Finished Jul 12 06:35:19 PM PDT 24
Peak memory 251336 kb
Host smart-d6491106-be84-4dab-8de6-0dca8b8f1f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560358554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmd
s.1560358554
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.4037386405
Short name T230
Test name
Test status
Simulation time 8258729670 ps
CPU time 21.69 seconds
Started Jul 12 06:34:19 PM PDT 24
Finished Jul 12 06:34:42 PM PDT 24
Peak memory 232704 kb
Host smart-12022e23-2292-4aa1-9e74-4c7a939d7799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037386405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.4037386405
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.1782142658
Short name T503
Test name
Test status
Simulation time 13778141643 ps
CPU time 38.86 seconds
Started Jul 12 06:34:23 PM PDT 24
Finished Jul 12 06:35:03 PM PDT 24
Peak memory 249008 kb
Host smart-93cd1cd2-b0c3-4bd5-a617-0621d7bfb1c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782142658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.1782142658
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.2402030876
Short name T469
Test name
Test status
Simulation time 875264453 ps
CPU time 8.31 seconds
Started Jul 12 06:34:27 PM PDT 24
Finished Jul 12 06:34:36 PM PDT 24
Peak memory 232328 kb
Host smart-8f988644-1464-4bea-9729-fa61f56d5876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402030876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.2402030876
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.3063435810
Short name T944
Test name
Test status
Simulation time 1327663472 ps
CPU time 5.12 seconds
Started Jul 12 06:34:19 PM PDT 24
Finished Jul 12 06:34:25 PM PDT 24
Peak memory 240504 kb
Host smart-18c95dd6-fdc5-42b0-a856-169df1a0ab06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063435810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.3063435810
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.1936212946
Short name T372
Test name
Test status
Simulation time 156394564 ps
CPU time 3.78 seconds
Started Jul 12 06:34:20 PM PDT 24
Finished Jul 12 06:34:26 PM PDT 24
Peak memory 218748 kb
Host smart-f1f9a07d-d011-4b02-809e-56bdf685dfe7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1936212946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.1936212946
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.559052078
Short name T148
Test name
Test status
Simulation time 60410629949 ps
CPU time 326.45 seconds
Started Jul 12 06:34:22 PM PDT 24
Finished Jul 12 06:39:50 PM PDT 24
Peak memory 249216 kb
Host smart-9f101ee8-2f22-491c-a4c8-cb7c1af05e91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559052078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stres
s_all.559052078
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.3937329793
Short name T797
Test name
Test status
Simulation time 8522985555 ps
CPU time 24.74 seconds
Started Jul 12 06:34:27 PM PDT 24
Finished Jul 12 06:34:52 PM PDT 24
Peak memory 216308 kb
Host smart-3cf8f04f-98b9-4108-97a3-a59d79510de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937329793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.3937329793
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.2568061210
Short name T352
Test name
Test status
Simulation time 175398955 ps
CPU time 1.1 seconds
Started Jul 12 06:34:18 PM PDT 24
Finished Jul 12 06:34:20 PM PDT 24
Peak memory 206028 kb
Host smart-67aa080f-a11e-4b74-ae8d-f8aadbe90bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568061210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.2568061210
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.4195847953
Short name T623
Test name
Test status
Simulation time 51659736 ps
CPU time 1.06 seconds
Started Jul 12 06:34:20 PM PDT 24
Finished Jul 12 06:34:24 PM PDT 24
Peak memory 207836 kb
Host smart-8a95dc6d-80da-41c5-8a4c-d62f0574954a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195847953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.4195847953
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.497995112
Short name T335
Test name
Test status
Simulation time 207404888 ps
CPU time 0.97 seconds
Started Jul 12 06:34:19 PM PDT 24
Finished Jul 12 06:34:21 PM PDT 24
Peak memory 206272 kb
Host smart-bfb29e46-4829-4e6c-93ba-26c00692d1a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497995112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.497995112
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.3033128304
Short name T861
Test name
Test status
Simulation time 26766422073 ps
CPU time 21.59 seconds
Started Jul 12 06:34:20 PM PDT 24
Finished Jul 12 06:34:44 PM PDT 24
Peak memory 232768 kb
Host smart-a3c3a9e0-4efa-4354-943b-41284ed53d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033128304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.3033128304
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.2546348617
Short name T705
Test name
Test status
Simulation time 14276128 ps
CPU time 0.79 seconds
Started Jul 12 06:31:09 PM PDT 24
Finished Jul 12 06:31:11 PM PDT 24
Peak memory 204860 kb
Host smart-271f1c0d-c4c4-41aa-937b-91c78267b830
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546348617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.2
546348617
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.3294441111
Short name T834
Test name
Test status
Simulation time 67872855 ps
CPU time 2.59 seconds
Started Jul 12 06:31:10 PM PDT 24
Finished Jul 12 06:31:15 PM PDT 24
Peak memory 224384 kb
Host smart-528e393d-be31-4bdd-b05d-dd8b4c9a7881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294441111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.3294441111
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.180039349
Short name T393
Test name
Test status
Simulation time 21945710 ps
CPU time 0.82 seconds
Started Jul 12 06:31:12 PM PDT 24
Finished Jul 12 06:31:16 PM PDT 24
Peak memory 206552 kb
Host smart-3e0a7357-e70a-4d07-aed1-57c37d67c2ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180039349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.180039349
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.752098745
Short name T258
Test name
Test status
Simulation time 15458137671 ps
CPU time 151.13 seconds
Started Jul 12 06:31:13 PM PDT 24
Finished Jul 12 06:33:47 PM PDT 24
Peak memory 265324 kb
Host smart-b7edb3a9-ea80-437e-9e21-c3c7a7ad4e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752098745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.752098745
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.1327233952
Short name T367
Test name
Test status
Simulation time 107806504123 ps
CPU time 265.04 seconds
Started Jul 12 06:31:10 PM PDT 24
Finished Jul 12 06:35:37 PM PDT 24
Peak memory 250460 kb
Host smart-c39d9fde-cbf2-4395-be9e-2c84300abd6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327233952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.1327233952
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.2522430038
Short name T131
Test name
Test status
Simulation time 1505929776 ps
CPU time 39.37 seconds
Started Jul 12 06:31:11 PM PDT 24
Finished Jul 12 06:31:54 PM PDT 24
Peak memory 249136 kb
Host smart-c01c7a75-f316-4cce-bf82-5bc09dc49a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522430038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.2522430038
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.2505455386
Short name T470
Test name
Test status
Simulation time 14746336509 ps
CPU time 25.19 seconds
Started Jul 12 06:31:09 PM PDT 24
Finished Jul 12 06:31:37 PM PDT 24
Peak memory 240952 kb
Host smart-5e1e7e47-1b33-40a4-9d1e-5b12eb7992fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505455386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.2505455386
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.4100097031
Short name T647
Test name
Test status
Simulation time 50588445544 ps
CPU time 192.7 seconds
Started Jul 12 06:31:10 PM PDT 24
Finished Jul 12 06:34:26 PM PDT 24
Peak memory 253968 kb
Host smart-0b651771-5d34-4673-9d3f-927dad3c4f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100097031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds
.4100097031
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.3724988497
Short name T858
Test name
Test status
Simulation time 1894306058 ps
CPU time 16.64 seconds
Started Jul 12 06:31:09 PM PDT 24
Finished Jul 12 06:31:28 PM PDT 24
Peak memory 224320 kb
Host smart-bcd21500-385e-40a9-b056-a03e67c873b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724988497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.3724988497
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.982378947
Short name T986
Test name
Test status
Simulation time 4421981996 ps
CPU time 24.56 seconds
Started Jul 12 06:31:12 PM PDT 24
Finished Jul 12 06:31:39 PM PDT 24
Peak memory 232688 kb
Host smart-2e29ce4a-c885-4656-8e0a-6d723d9175fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982378947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.982378947
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.2774642048
Short name T420
Test name
Test status
Simulation time 15769751019 ps
CPU time 14.51 seconds
Started Jul 12 06:31:11 PM PDT 24
Finished Jul 12 06:31:28 PM PDT 24
Peak memory 224564 kb
Host smart-d502ed30-bb62-46ff-a22a-cbf0b047e72c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774642048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.2774642048
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.570619763
Short name T530
Test name
Test status
Simulation time 3491569530 ps
CPU time 5.54 seconds
Started Jul 12 06:31:13 PM PDT 24
Finished Jul 12 06:31:21 PM PDT 24
Peak memory 224524 kb
Host smart-91a2017e-c0e0-4b3b-8579-7da08156f30e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570619763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.570619763
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.2894196367
Short name T428
Test name
Test status
Simulation time 263746636 ps
CPU time 5.55 seconds
Started Jul 12 06:31:10 PM PDT 24
Finished Jul 12 06:31:19 PM PDT 24
Peak memory 223000 kb
Host smart-70f59aa3-230a-4a40-8ff5-a05e42b7e573
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2894196367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.2894196367
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.1867408448
Short name T65
Test name
Test status
Simulation time 5587985069 ps
CPU time 2.23 seconds
Started Jul 12 06:31:14 PM PDT 24
Finished Jul 12 06:31:18 PM PDT 24
Peak memory 236624 kb
Host smart-d933a220-e3fe-49d7-be37-5daf5d66d792
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867408448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.1867408448
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.3255131900
Short name T69
Test name
Test status
Simulation time 9356040797 ps
CPU time 16.96 seconds
Started Jul 12 06:31:10 PM PDT 24
Finished Jul 12 06:31:29 PM PDT 24
Peak memory 216340 kb
Host smart-5d6dcc9b-2ae5-4ce4-aa02-9f0b993160cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255131900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.3255131900
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.896421264
Short name T774
Test name
Test status
Simulation time 2622359272 ps
CPU time 2.88 seconds
Started Jul 12 06:31:14 PM PDT 24
Finished Jul 12 06:31:19 PM PDT 24
Peak memory 216256 kb
Host smart-5bfcad26-de21-46de-bdf0-b27db9821895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896421264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.896421264
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.1317755977
Short name T697
Test name
Test status
Simulation time 1918449338 ps
CPU time 3.04 seconds
Started Jul 12 06:31:10 PM PDT 24
Finished Jul 12 06:31:16 PM PDT 24
Peak memory 216184 kb
Host smart-d6203b76-e15c-4d7e-8cbf-69b97b7a5133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317755977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.1317755977
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.2792625042
Short name T916
Test name
Test status
Simulation time 1100785949 ps
CPU time 1.08 seconds
Started Jul 12 06:31:11 PM PDT 24
Finished Jul 12 06:31:16 PM PDT 24
Peak memory 207080 kb
Host smart-f767bd0d-a48a-4174-a535-cb3cc88c998b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792625042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.2792625042
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.3072308568
Short name T478
Test name
Test status
Simulation time 220055431 ps
CPU time 2.44 seconds
Started Jul 12 06:31:09 PM PDT 24
Finished Jul 12 06:31:14 PM PDT 24
Peak memory 224276 kb
Host smart-b6ccda8f-5125-4cd1-9d56-6847efa383f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072308568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.3072308568
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.1269291102
Short name T598
Test name
Test status
Simulation time 25017652 ps
CPU time 0.75 seconds
Started Jul 12 06:34:27 PM PDT 24
Finished Jul 12 06:34:28 PM PDT 24
Peak memory 204860 kb
Host smart-aeb3df70-9d8d-405f-ba81-3e218f0acf32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269291102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
1269291102
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.3479679511
Short name T686
Test name
Test status
Simulation time 3040719533 ps
CPU time 15.32 seconds
Started Jul 12 06:34:20 PM PDT 24
Finished Jul 12 06:34:37 PM PDT 24
Peak memory 232744 kb
Host smart-2fffc1bb-6f02-4015-bfbf-b7e8eb7c6d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479679511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.3479679511
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.253255730
Short name T798
Test name
Test status
Simulation time 16561892 ps
CPU time 0.77 seconds
Started Jul 12 06:34:27 PM PDT 24
Finished Jul 12 06:34:28 PM PDT 24
Peak memory 206844 kb
Host smart-845f2377-18e2-4a0e-8219-7a8c23cc932a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253255730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.253255730
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.1945306397
Short name T863
Test name
Test status
Simulation time 11356048845 ps
CPU time 99.35 seconds
Started Jul 12 06:34:29 PM PDT 24
Finished Jul 12 06:36:10 PM PDT 24
Peak memory 249316 kb
Host smart-3378ea65-ad67-405c-bfd6-558193f936a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945306397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.1945306397
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.3763995146
Short name T50
Test name
Test status
Simulation time 9928038260 ps
CPU time 74.24 seconds
Started Jul 12 06:34:30 PM PDT 24
Finished Jul 12 06:35:45 PM PDT 24
Peak memory 249196 kb
Host smart-d906de19-00bc-4e87-8846-70d04233887b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763995146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.3763995146
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.1058810408
Short name T671
Test name
Test status
Simulation time 7364438409 ps
CPU time 27.37 seconds
Started Jul 12 06:34:29 PM PDT 24
Finished Jul 12 06:34:57 PM PDT 24
Peak memory 249156 kb
Host smart-2520aac1-b4cd-4daf-bfc7-074e1aa3b17f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058810408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.1058810408
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.3355084439
Short name T174
Test name
Test status
Simulation time 19481324604 ps
CPU time 194.55 seconds
Started Jul 12 06:34:29 PM PDT 24
Finished Jul 12 06:37:44 PM PDT 24
Peak memory 255336 kb
Host smart-88dd27d5-37fd-483e-a7f4-d2f285eeba2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355084439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmd
s.3355084439
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.1073865946
Short name T975
Test name
Test status
Simulation time 594342682 ps
CPU time 5.02 seconds
Started Jul 12 06:34:17 PM PDT 24
Finished Jul 12 06:34:23 PM PDT 24
Peak memory 224396 kb
Host smart-17c1760b-85dc-4bcb-9937-58ece0477cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073865946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.1073865946
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.1488200188
Short name T537
Test name
Test status
Simulation time 34009990 ps
CPU time 2.57 seconds
Started Jul 12 06:34:20 PM PDT 24
Finished Jul 12 06:34:25 PM PDT 24
Peak memory 232248 kb
Host smart-c2a283ad-b021-4079-ac88-9dd70ff0041b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488200188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.1488200188
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.650077273
Short name T932
Test name
Test status
Simulation time 3249403328 ps
CPU time 12.48 seconds
Started Jul 12 06:34:17 PM PDT 24
Finished Jul 12 06:34:30 PM PDT 24
Peak memory 235564 kb
Host smart-72fba7e1-04ae-415e-a485-567dccadaa90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650077273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swap
.650077273
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.1165857747
Short name T872
Test name
Test status
Simulation time 2735367935 ps
CPU time 11.26 seconds
Started Jul 12 06:34:19 PM PDT 24
Finished Jul 12 06:34:31 PM PDT 24
Peak memory 240100 kb
Host smart-79911e30-4afa-4cf6-aadf-ce75b2074098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165857747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.1165857747
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.685664289
Short name T582
Test name
Test status
Simulation time 547348590 ps
CPU time 4.58 seconds
Started Jul 12 06:34:28 PM PDT 24
Finished Jul 12 06:34:34 PM PDT 24
Peak memory 219092 kb
Host smart-dc5c82b4-510b-4d7d-8c83-00929aa4bdf0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=685664289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dire
ct.685664289
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.3074150035
Short name T687
Test name
Test status
Simulation time 215679403219 ps
CPU time 224.16 seconds
Started Jul 12 06:34:27 PM PDT 24
Finished Jul 12 06:38:13 PM PDT 24
Peak memory 257216 kb
Host smart-608dbcee-4848-40f2-8c60-20795b39ab18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074150035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.3074150035
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.3496841643
Short name T980
Test name
Test status
Simulation time 36493471520 ps
CPU time 34.78 seconds
Started Jul 12 06:34:17 PM PDT 24
Finished Jul 12 06:34:53 PM PDT 24
Peak memory 216264 kb
Host smart-de310ff6-e69e-478f-9f55-704a9ad47c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496841643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.3496841643
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.1206186716
Short name T646
Test name
Test status
Simulation time 1654198463 ps
CPU time 3.09 seconds
Started Jul 12 06:34:18 PM PDT 24
Finished Jul 12 06:34:22 PM PDT 24
Peak memory 216140 kb
Host smart-b23dcc27-158c-4931-9bb3-92e7f40b7f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206186716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.1206186716
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.2926967361
Short name T816
Test name
Test status
Simulation time 317935797 ps
CPU time 0.9 seconds
Started Jul 12 06:34:20 PM PDT 24
Finished Jul 12 06:34:23 PM PDT 24
Peak memory 206936 kb
Host smart-5896bc95-07d9-419e-b919-744f7b51aa34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926967361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.2926967361
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.2786184746
Short name T304
Test name
Test status
Simulation time 92085422 ps
CPU time 0.84 seconds
Started Jul 12 06:34:20 PM PDT 24
Finished Jul 12 06:34:24 PM PDT 24
Peak memory 205884 kb
Host smart-bca2c6dc-18f5-46f1-bc41-85f7d820a335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786184746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.2786184746
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.1728767969
Short name T349
Test name
Test status
Simulation time 281764265 ps
CPU time 3.46 seconds
Started Jul 12 06:34:18 PM PDT 24
Finished Jul 12 06:34:22 PM PDT 24
Peak memory 232600 kb
Host smart-2f853dfb-6c05-43a8-94d5-04a97e295860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728767969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.1728767969
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.1628109380
Short name T1005
Test name
Test status
Simulation time 12851992 ps
CPU time 0.71 seconds
Started Jul 12 06:34:38 PM PDT 24
Finished Jul 12 06:34:40 PM PDT 24
Peak memory 204868 kb
Host smart-c6f6a439-a3df-4e86-87c1-a8a39d6331b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628109380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
1628109380
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.389822300
Short name T523
Test name
Test status
Simulation time 1341958228 ps
CPU time 6.26 seconds
Started Jul 12 06:34:38 PM PDT 24
Finished Jul 12 06:34:46 PM PDT 24
Peak memory 232520 kb
Host smart-5c25ba33-4fc9-4e43-9b26-c0abef334664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389822300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.389822300
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.1748285976
Short name T285
Test name
Test status
Simulation time 127046000 ps
CPU time 0.76 seconds
Started Jul 12 06:34:27 PM PDT 24
Finished Jul 12 06:34:29 PM PDT 24
Peak memory 206864 kb
Host smart-eab7e9c8-c47d-4097-9776-15f49690f06a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748285976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.1748285976
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.241153237
Short name T311
Test name
Test status
Simulation time 265894196 ps
CPU time 0.96 seconds
Started Jul 12 06:34:43 PM PDT 24
Finished Jul 12 06:34:45 PM PDT 24
Peak memory 215852 kb
Host smart-b6a00e90-36a4-4a94-93c3-9c053360005b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241153237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.241153237
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.1711961799
Short name T351
Test name
Test status
Simulation time 3016122772 ps
CPU time 48.49 seconds
Started Jul 12 06:34:44 PM PDT 24
Finished Jul 12 06:35:33 PM PDT 24
Peak memory 249216 kb
Host smart-97693014-bedd-4ab7-ac8e-c17f8212b2ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711961799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.1711961799
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.2456963516
Short name T804
Test name
Test status
Simulation time 400115027 ps
CPU time 4.76 seconds
Started Jul 12 06:34:43 PM PDT 24
Finished Jul 12 06:34:48 PM PDT 24
Peak memory 233720 kb
Host smart-fc1fb920-257f-405d-acea-2421fdcceb9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456963516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.2456963516
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.1006701735
Short name T520
Test name
Test status
Simulation time 1437771682 ps
CPU time 11.82 seconds
Started Jul 12 06:34:42 PM PDT 24
Finished Jul 12 06:34:54 PM PDT 24
Peak memory 238040 kb
Host smart-0d2b3ae6-b8e2-413a-bfb0-6e138f285186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006701735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmd
s.1006701735
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.392573628
Short name T595
Test name
Test status
Simulation time 2193847099 ps
CPU time 4.71 seconds
Started Jul 12 06:34:28 PM PDT 24
Finished Jul 12 06:34:34 PM PDT 24
Peak memory 224440 kb
Host smart-63a64ccc-12b6-4cbf-bce0-b2160abde06d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392573628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.392573628
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.221417477
Short name T733
Test name
Test status
Simulation time 1054454319 ps
CPU time 10.32 seconds
Started Jul 12 06:34:36 PM PDT 24
Finished Jul 12 06:34:48 PM PDT 24
Peak memory 240492 kb
Host smart-37cc471e-66e2-49c3-a455-1fc7c9d560ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221417477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.221417477
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.662914157
Short name T468
Test name
Test status
Simulation time 5142293532 ps
CPU time 16.54 seconds
Started Jul 12 06:34:29 PM PDT 24
Finished Jul 12 06:34:46 PM PDT 24
Peak memory 232784 kb
Host smart-8f4a1d6b-162c-47b3-9774-9b9b15bb4f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662914157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swap
.662914157
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.2390127856
Short name T189
Test name
Test status
Simulation time 823595424 ps
CPU time 4.49 seconds
Started Jul 12 06:34:28 PM PDT 24
Finished Jul 12 06:34:33 PM PDT 24
Peak memory 232660 kb
Host smart-308cb7bf-abba-4fba-a80c-087b0055c02a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390127856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.2390127856
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.2356277395
Short name T540
Test name
Test status
Simulation time 744532131 ps
CPU time 9.86 seconds
Started Jul 12 06:34:44 PM PDT 24
Finished Jul 12 06:34:54 PM PDT 24
Peak memory 218740 kb
Host smart-704a797b-d2e5-4ce8-a175-39bf169818b3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2356277395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.2356277395
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.2198616032
Short name T361
Test name
Test status
Simulation time 3748608676 ps
CPU time 20.87 seconds
Started Jul 12 06:34:30 PM PDT 24
Finished Jul 12 06:34:51 PM PDT 24
Peak memory 216544 kb
Host smart-02c0a78e-0e03-41e0-826c-857c1c8a04c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198616032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.2198616032
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.890196054
Short name T28
Test name
Test status
Simulation time 32743997719 ps
CPU time 23.61 seconds
Started Jul 12 06:34:28 PM PDT 24
Finished Jul 12 06:34:53 PM PDT 24
Peak memory 216260 kb
Host smart-d0e96a0a-ac61-4e95-9a14-6091b1eb9883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890196054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.890196054
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.309152928
Short name T667
Test name
Test status
Simulation time 125501503 ps
CPU time 1.54 seconds
Started Jul 12 06:34:29 PM PDT 24
Finished Jul 12 06:34:31 PM PDT 24
Peak memory 216168 kb
Host smart-20e1cbcb-eb80-460e-8f39-7d412e64050a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309152928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.309152928
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.4038842055
Short name T642
Test name
Test status
Simulation time 207210106 ps
CPU time 0.86 seconds
Started Jul 12 06:34:27 PM PDT 24
Finished Jul 12 06:34:29 PM PDT 24
Peak memory 205924 kb
Host smart-2f63436f-fef8-4023-88f4-32331f014aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038842055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.4038842055
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.340735233
Short name T342
Test name
Test status
Simulation time 1368372109 ps
CPU time 3.22 seconds
Started Jul 12 06:34:43 PM PDT 24
Finished Jul 12 06:34:46 PM PDT 24
Peak memory 224456 kb
Host smart-556717f4-d609-4ff9-b1ca-7ad027614b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340735233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.340735233
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.2782976132
Short name T878
Test name
Test status
Simulation time 18452520 ps
CPU time 0.69 seconds
Started Jul 12 06:34:37 PM PDT 24
Finished Jul 12 06:34:39 PM PDT 24
Peak memory 204900 kb
Host smart-20d78a05-dd41-4153-ac03-9444eb7556c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782976132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
2782976132
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.1659803225
Short name T796
Test name
Test status
Simulation time 1182730260 ps
CPU time 9.64 seconds
Started Jul 12 06:34:38 PM PDT 24
Finished Jul 12 06:34:49 PM PDT 24
Peak memory 224392 kb
Host smart-42f7298b-71af-450a-ae79-9f3f86c29354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659803225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.1659803225
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.218944324
Short name T740
Test name
Test status
Simulation time 20250859 ps
CPU time 0.78 seconds
Started Jul 12 06:34:45 PM PDT 24
Finished Jul 12 06:34:48 PM PDT 24
Peak memory 206860 kb
Host smart-9cb82acb-1ae6-4219-8c8b-96a519883067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218944324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.218944324
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.896911701
Short name T573
Test name
Test status
Simulation time 540258079 ps
CPU time 10.87 seconds
Started Jul 12 06:34:37 PM PDT 24
Finished Jul 12 06:34:49 PM PDT 24
Peak memory 238084 kb
Host smart-3849738d-71a2-401e-a302-39b12befc13a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896911701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.896911701
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.522220475
Short name T484
Test name
Test status
Simulation time 1245217809 ps
CPU time 31.86 seconds
Started Jul 12 06:34:37 PM PDT 24
Finished Jul 12 06:35:10 PM PDT 24
Peak memory 240956 kb
Host smart-f469144e-206f-435f-aafb-25cd7ff5b82e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522220475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.522220475
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.2547955822
Short name T196
Test name
Test status
Simulation time 57899057510 ps
CPU time 141.97 seconds
Started Jul 12 06:34:37 PM PDT 24
Finished Jul 12 06:37:00 PM PDT 24
Peak memory 253328 kb
Host smart-e84d1833-bbce-4a10-9143-ecc9ea04a1e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547955822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.2547955822
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.2159197586
Short name T922
Test name
Test status
Simulation time 380280431 ps
CPU time 10.92 seconds
Started Jul 12 06:34:40 PM PDT 24
Finished Jul 12 06:34:51 PM PDT 24
Peak memory 232764 kb
Host smart-f622eb67-ddb4-4b28-90d1-8cdad554afec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159197586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.2159197586
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.830722538
Short name T779
Test name
Test status
Simulation time 6564099024 ps
CPU time 50.96 seconds
Started Jul 12 06:34:44 PM PDT 24
Finished Jul 12 06:35:35 PM PDT 24
Peak memory 240948 kb
Host smart-9d9e67f6-424b-42ba-843a-c72ba32cc545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830722538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmds
.830722538
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.1766147786
Short name T76
Test name
Test status
Simulation time 1612319695 ps
CPU time 14.79 seconds
Started Jul 12 06:34:37 PM PDT 24
Finished Jul 12 06:34:53 PM PDT 24
Peak memory 232516 kb
Host smart-036c0170-e251-422d-a92b-4deec183d136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766147786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.1766147786
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.740411449
Short name T505
Test name
Test status
Simulation time 42270175627 ps
CPU time 75.19 seconds
Started Jul 12 06:34:43 PM PDT 24
Finished Jul 12 06:35:58 PM PDT 24
Peak memory 251680 kb
Host smart-a8966a6a-1625-4e2a-9f15-e930b31300e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740411449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.740411449
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.1621103148
Short name T808
Test name
Test status
Simulation time 3527972896 ps
CPU time 11.1 seconds
Started Jul 12 06:34:43 PM PDT 24
Finished Jul 12 06:34:55 PM PDT 24
Peak memory 224444 kb
Host smart-ed844063-82ad-465a-aadd-967abbd1bb2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621103148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.1621103148
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.727409026
Short name T575
Test name
Test status
Simulation time 6454313565 ps
CPU time 4.99 seconds
Started Jul 12 06:34:36 PM PDT 24
Finished Jul 12 06:34:42 PM PDT 24
Peak memory 232732 kb
Host smart-858182cf-c4d6-4d80-b6cd-21c4b08055cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727409026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.727409026
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.1623617221
Short name T876
Test name
Test status
Simulation time 2830206397 ps
CPU time 7.96 seconds
Started Jul 12 06:34:37 PM PDT 24
Finished Jul 12 06:34:47 PM PDT 24
Peak memory 222256 kb
Host smart-bed8ff57-7eb2-4dff-b0b4-202806f51094
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1623617221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.1623617221
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.3328410864
Short name T23
Test name
Test status
Simulation time 15873832065 ps
CPU time 136.5 seconds
Started Jul 12 06:34:37 PM PDT 24
Finished Jul 12 06:36:55 PM PDT 24
Peak memory 256172 kb
Host smart-2cd5abbb-d4ce-4cd1-b520-ed0e8f026dd9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328410864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.3328410864
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.2583983017
Short name T271
Test name
Test status
Simulation time 1196252355 ps
CPU time 11.36 seconds
Started Jul 12 06:34:36 PM PDT 24
Finished Jul 12 06:34:49 PM PDT 24
Peak memory 216476 kb
Host smart-f07bd701-77ee-464b-a8b8-ebcdaba37cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583983017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.2583983017
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.2296930196
Short name T896
Test name
Test status
Simulation time 1242978120 ps
CPU time 6.52 seconds
Started Jul 12 06:34:36 PM PDT 24
Finished Jul 12 06:34:43 PM PDT 24
Peak memory 216192 kb
Host smart-f74a251a-444b-485c-a187-9396f0351978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296930196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.2296930196
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.2614812092
Short name T635
Test name
Test status
Simulation time 26604470 ps
CPU time 1.71 seconds
Started Jul 12 06:34:43 PM PDT 24
Finished Jul 12 06:34:45 PM PDT 24
Peak memory 216136 kb
Host smart-fed31706-be0c-4b9b-ba25-2ff35f729ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614812092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.2614812092
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.4289703651
Short name T333
Test name
Test status
Simulation time 28677923 ps
CPU time 0.69 seconds
Started Jul 12 06:34:36 PM PDT 24
Finished Jul 12 06:34:38 PM PDT 24
Peak memory 205892 kb
Host smart-eda04455-65eb-4f5a-8aa3-4191958f7118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289703651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.4289703651
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.1995698864
Short name T917
Test name
Test status
Simulation time 3064542012 ps
CPU time 4.82 seconds
Started Jul 12 06:34:36 PM PDT 24
Finished Jul 12 06:34:43 PM PDT 24
Peak memory 224484 kb
Host smart-f19097d0-8342-4c99-befe-1a9075ff9267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995698864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.1995698864
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.732138762
Short name T783
Test name
Test status
Simulation time 15056545 ps
CPU time 0.73 seconds
Started Jul 12 06:34:44 PM PDT 24
Finished Jul 12 06:34:46 PM PDT 24
Peak memory 204920 kb
Host smart-d2f927f9-6593-4e5a-a784-a9bb79b8d846
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732138762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.732138762
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.269944956
Short name T73
Test name
Test status
Simulation time 562802866 ps
CPU time 6.44 seconds
Started Jul 12 06:34:48 PM PDT 24
Finished Jul 12 06:34:55 PM PDT 24
Peak memory 232640 kb
Host smart-36ea656a-e283-4a89-91b9-47976c4f0121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269944956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.269944956
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.93013027
Short name T477
Test name
Test status
Simulation time 52036820 ps
CPU time 0.79 seconds
Started Jul 12 06:34:43 PM PDT 24
Finished Jul 12 06:34:45 PM PDT 24
Peak memory 206852 kb
Host smart-8a52ab86-324c-4cd3-a2e5-be96db2d92a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93013027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.93013027
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.1745610786
Short name T820
Test name
Test status
Simulation time 404736082745 ps
CPU time 202.92 seconds
Started Jul 12 06:34:54 PM PDT 24
Finished Jul 12 06:38:19 PM PDT 24
Peak memory 249192 kb
Host smart-198ec2ee-f0ae-4eec-9f06-994f2a8d860f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745610786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.1745610786
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.1968221126
Short name T938
Test name
Test status
Simulation time 5969776716 ps
CPU time 16.72 seconds
Started Jul 12 06:34:51 PM PDT 24
Finished Jul 12 06:35:09 PM PDT 24
Peak memory 217476 kb
Host smart-0299c110-9326-4b88-80f6-686f22b4a317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968221126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.1968221126
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.2207392869
Short name T632
Test name
Test status
Simulation time 651802728 ps
CPU time 7.05 seconds
Started Jul 12 06:34:47 PM PDT 24
Finished Jul 12 06:34:55 PM PDT 24
Peak memory 232588 kb
Host smart-3c5d516f-b233-4744-9777-7a9c18bf9f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207392869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.2207392869
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.1658894002
Short name T704
Test name
Test status
Simulation time 207135738879 ps
CPU time 363.83 seconds
Started Jul 12 06:34:50 PM PDT 24
Finished Jul 12 06:40:54 PM PDT 24
Peak memory 254772 kb
Host smart-62b2fe5e-4bae-4e53-996f-cf360ec5beb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658894002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmd
s.1658894002
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.3857810680
Short name T280
Test name
Test status
Simulation time 68339879 ps
CPU time 2.63 seconds
Started Jul 12 06:34:54 PM PDT 24
Finished Jul 12 06:34:59 PM PDT 24
Peak memory 224356 kb
Host smart-1768a29b-34e1-4cb4-b2cd-fcebac8c5762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857810680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.3857810680
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.3596443116
Short name T431
Test name
Test status
Simulation time 309491789 ps
CPU time 5.66 seconds
Started Jul 12 06:34:48 PM PDT 24
Finished Jul 12 06:34:55 PM PDT 24
Peak memory 232572 kb
Host smart-19f6c150-fccd-44f8-935d-f60d422a5c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596443116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.3596443116
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.3608921433
Short name T229
Test name
Test status
Simulation time 1295505703 ps
CPU time 9 seconds
Started Jul 12 06:34:54 PM PDT 24
Finished Jul 12 06:35:04 PM PDT 24
Peak memory 224304 kb
Host smart-b4399fc9-1336-4a2a-832b-1acd6e8af0fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608921433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.3608921433
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.1416742634
Short name T354
Test name
Test status
Simulation time 1892062642 ps
CPU time 8.05 seconds
Started Jul 12 06:34:46 PM PDT 24
Finished Jul 12 06:34:55 PM PDT 24
Peak memory 234316 kb
Host smart-1fb99127-47ee-40c7-97ea-c56906a635f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416742634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.1416742634
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.2197803873
Short name T491
Test name
Test status
Simulation time 3171629026 ps
CPU time 9.89 seconds
Started Jul 12 06:34:53 PM PDT 24
Finished Jul 12 06:35:04 PM PDT 24
Peak memory 220676 kb
Host smart-20e3b383-ebda-4c5e-95c5-48ac77a57754
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2197803873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.2197803873
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.2008687427
Short name T147
Test name
Test status
Simulation time 44958540505 ps
CPU time 446.6 seconds
Started Jul 12 06:34:49 PM PDT 24
Finished Jul 12 06:42:16 PM PDT 24
Peak memory 264092 kb
Host smart-f996c89e-e898-41d4-a0dd-0f324056b3f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008687427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.2008687427
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.1110550650
Short name T480
Test name
Test status
Simulation time 10887963959 ps
CPU time 9.33 seconds
Started Jul 12 06:34:48 PM PDT 24
Finished Jul 12 06:34:58 PM PDT 24
Peak memory 216256 kb
Host smart-6cb97af7-cbfd-4e95-990f-26a2975f0d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110550650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.1110550650
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.3822993228
Short name T453
Test name
Test status
Simulation time 4201820555 ps
CPU time 6.78 seconds
Started Jul 12 06:34:37 PM PDT 24
Finished Jul 12 06:34:45 PM PDT 24
Peak memory 216204 kb
Host smart-c2e3fe36-c16d-48af-85c6-d7c962d06e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822993228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.3822993228
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.3567764118
Short name T315
Test name
Test status
Simulation time 57436175 ps
CPU time 0.72 seconds
Started Jul 12 06:34:45 PM PDT 24
Finished Jul 12 06:34:47 PM PDT 24
Peak memory 205560 kb
Host smart-9156e2eb-d770-4b1c-9b83-b30c4cf68c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567764118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.3567764118
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.3783120889
Short name T966
Test name
Test status
Simulation time 53729991 ps
CPU time 0.85 seconds
Started Jul 12 06:34:44 PM PDT 24
Finished Jul 12 06:34:46 PM PDT 24
Peak memory 205912 kb
Host smart-dc5e618c-ecc2-4821-b83f-7f97a1d72cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783120889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.3783120889
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.385176514
Short name T421
Test name
Test status
Simulation time 1534537464 ps
CPU time 3.68 seconds
Started Jul 12 06:34:45 PM PDT 24
Finished Jul 12 06:34:51 PM PDT 24
Peak memory 216980 kb
Host smart-b44d0a2c-8f0a-4e19-9ebc-dbea647889ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385176514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.385176514
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.153861708
Short name T382
Test name
Test status
Simulation time 86048256 ps
CPU time 0.76 seconds
Started Jul 12 06:34:52 PM PDT 24
Finished Jul 12 06:34:53 PM PDT 24
Peak memory 205820 kb
Host smart-84c07c79-113c-4ebd-9426-44e005d084ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153861708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.153861708
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.2131020866
Short name T435
Test name
Test status
Simulation time 208737305 ps
CPU time 3.14 seconds
Started Jul 12 06:34:49 PM PDT 24
Finished Jul 12 06:34:53 PM PDT 24
Peak memory 232596 kb
Host smart-477b034c-fdba-4439-8ecf-d70976234cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131020866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.2131020866
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.1324679127
Short name T283
Test name
Test status
Simulation time 14774144 ps
CPU time 0.77 seconds
Started Jul 12 06:34:49 PM PDT 24
Finished Jul 12 06:34:50 PM PDT 24
Peak memory 206508 kb
Host smart-ff6f1295-9321-4c0c-9f22-e5dbbda5f2a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324679127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.1324679127
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.3257504422
Short name T360
Test name
Test status
Simulation time 14204383032 ps
CPU time 28.81 seconds
Started Jul 12 06:34:48 PM PDT 24
Finished Jul 12 06:35:17 PM PDT 24
Peak memory 232744 kb
Host smart-7f243f5f-ab24-46c3-bdc4-c5392c87cd6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257504422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.3257504422
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.3635053349
Short name T682
Test name
Test status
Simulation time 18553277615 ps
CPU time 79.56 seconds
Started Jul 12 06:34:49 PM PDT 24
Finished Jul 12 06:36:10 PM PDT 24
Peak memory 253136 kb
Host smart-c42e219c-e93a-43bc-a078-463a6e86cdb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635053349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.3635053349
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.2532315981
Short name T46
Test name
Test status
Simulation time 24699676656 ps
CPU time 102.08 seconds
Started Jul 12 06:34:56 PM PDT 24
Finished Jul 12 06:36:39 PM PDT 24
Peak memory 250988 kb
Host smart-42293223-7c85-40f8-83eb-a256168e2f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532315981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.2532315981
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.2788662570
Short name T925
Test name
Test status
Simulation time 46993109 ps
CPU time 3.1 seconds
Started Jul 12 06:34:47 PM PDT 24
Finished Jul 12 06:34:51 PM PDT 24
Peak memory 232628 kb
Host smart-50d04762-1c6a-4cdd-8955-3b221620dd53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788662570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.2788662570
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.2121835598
Short name T578
Test name
Test status
Simulation time 186355095355 ps
CPU time 318.21 seconds
Started Jul 12 06:34:45 PM PDT 24
Finished Jul 12 06:40:05 PM PDT 24
Peak memory 273684 kb
Host smart-351f394d-8ee4-413a-a66a-c27b17c1c9c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121835598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmd
s.2121835598
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.994130082
Short name T977
Test name
Test status
Simulation time 529529168 ps
CPU time 6.47 seconds
Started Jul 12 06:34:54 PM PDT 24
Finished Jul 12 06:35:02 PM PDT 24
Peak memory 232648 kb
Host smart-b9628911-c45c-410e-bfab-345765ecd00f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994130082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.994130082
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.1153623247
Short name T497
Test name
Test status
Simulation time 921786548 ps
CPU time 8.62 seconds
Started Jul 12 06:34:54 PM PDT 24
Finished Jul 12 06:35:05 PM PDT 24
Peak memory 224352 kb
Host smart-c74e4f65-1551-471d-8e22-63f82399f3a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153623247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.1153623247
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.3865225891
Short name T672
Test name
Test status
Simulation time 13738315662 ps
CPU time 9.5 seconds
Started Jul 12 06:34:46 PM PDT 24
Finished Jul 12 06:34:56 PM PDT 24
Peak memory 232644 kb
Host smart-6f2bd4b6-676f-401d-911f-27d34fb2faf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865225891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.3865225891
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.1945191529
Short name T377
Test name
Test status
Simulation time 580913301 ps
CPU time 5.23 seconds
Started Jul 12 06:34:44 PM PDT 24
Finished Jul 12 06:34:50 PM PDT 24
Peak memory 224456 kb
Host smart-39297972-6cae-491f-8d78-3ac076256e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945191529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.1945191529
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.3959408583
Short name T678
Test name
Test status
Simulation time 4361388998 ps
CPU time 10.91 seconds
Started Jul 12 06:34:45 PM PDT 24
Finished Jul 12 06:34:57 PM PDT 24
Peak memory 222660 kb
Host smart-405d7ebe-23e7-42f0-80c4-8a419ccd2b77
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3959408583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.3959408583
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.1095358220
Short name T49
Test name
Test status
Simulation time 113706215146 ps
CPU time 621.8 seconds
Started Jul 12 06:34:55 PM PDT 24
Finished Jul 12 06:45:18 PM PDT 24
Peak memory 255208 kb
Host smart-a2a23359-76d7-44ee-92ba-032f656f0b4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095358220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.1095358220
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.4173671495
Short name T729
Test name
Test status
Simulation time 2680765915 ps
CPU time 13.36 seconds
Started Jul 12 06:34:49 PM PDT 24
Finished Jul 12 06:35:04 PM PDT 24
Peak memory 216268 kb
Host smart-5ee0d77f-8c6b-4fe5-bc27-49f0d558c705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173671495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.4173671495
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.2072659699
Short name T452
Test name
Test status
Simulation time 35058649 ps
CPU time 0.75 seconds
Started Jul 12 06:34:54 PM PDT 24
Finished Jul 12 06:34:56 PM PDT 24
Peak memory 205648 kb
Host smart-fdde1d8c-8d6d-4da8-ac96-99c16f521d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072659699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.2072659699
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.825777596
Short name T604
Test name
Test status
Simulation time 30795131 ps
CPU time 0.96 seconds
Started Jul 12 06:34:50 PM PDT 24
Finished Jul 12 06:34:51 PM PDT 24
Peak memory 206924 kb
Host smart-aa9a0af8-538e-4309-937f-08e548f1ba6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825777596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.825777596
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.2259249011
Short name T972
Test name
Test status
Simulation time 57441274 ps
CPU time 0.77 seconds
Started Jul 12 06:34:44 PM PDT 24
Finished Jul 12 06:34:45 PM PDT 24
Peak memory 205932 kb
Host smart-b976c2c4-1008-4596-a1fc-7fab091f4ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259249011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.2259249011
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.3807157479
Short name T433
Test name
Test status
Simulation time 2228577261 ps
CPU time 5.09 seconds
Started Jul 12 06:34:45 PM PDT 24
Finished Jul 12 06:34:52 PM PDT 24
Peak memory 224508 kb
Host smart-5a04295e-b756-40ce-8d88-cdc9ba560f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807157479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.3807157479
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.2300859471
Short name T631
Test name
Test status
Simulation time 10848982 ps
CPU time 0.7 seconds
Started Jul 12 06:35:00 PM PDT 24
Finished Jul 12 06:35:02 PM PDT 24
Peak memory 204880 kb
Host smart-2e21d8e3-bc36-4ed4-ae34-01fcb5d28735
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300859471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
2300859471
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.1622793120
Short name T125
Test name
Test status
Simulation time 1398133557 ps
CPU time 3.76 seconds
Started Jul 12 06:34:54 PM PDT 24
Finished Jul 12 06:34:59 PM PDT 24
Peak memory 224384 kb
Host smart-5cc586fb-a0f2-421e-afc2-8a72806fc793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622793120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.1622793120
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.523256500
Short name T398
Test name
Test status
Simulation time 14842261 ps
CPU time 0.84 seconds
Started Jul 12 06:34:52 PM PDT 24
Finished Jul 12 06:34:53 PM PDT 24
Peak memory 206572 kb
Host smart-6bb3f5ad-0eed-490d-820c-9c4e2ad13e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523256500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.523256500
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.459058178
Short name T5
Test name
Test status
Simulation time 20566293997 ps
CPU time 134.31 seconds
Started Jul 12 06:34:52 PM PDT 24
Finished Jul 12 06:37:08 PM PDT 24
Peak memory 250376 kb
Host smart-e7effbd6-3fcf-433e-9ff6-c11a9a7b2603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459058178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.459058178
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.3454340103
Short name T185
Test name
Test status
Simulation time 7530921038 ps
CPU time 116.56 seconds
Started Jul 12 06:34:54 PM PDT 24
Finished Jul 12 06:36:52 PM PDT 24
Peak memory 255716 kb
Host smart-2370c554-a393-46f2-8310-63699be554ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454340103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.3454340103
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.4144963762
Short name T48
Test name
Test status
Simulation time 1329461211 ps
CPU time 27.36 seconds
Started Jul 12 06:34:51 PM PDT 24
Finished Jul 12 06:35:19 PM PDT 24
Peak memory 234200 kb
Host smart-4e327a68-da59-4216-97b2-caa325833f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144963762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.4144963762
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.3268648253
Short name T625
Test name
Test status
Simulation time 37506485621 ps
CPU time 56.69 seconds
Started Jul 12 06:34:51 PM PDT 24
Finished Jul 12 06:35:48 PM PDT 24
Peak memory 240908 kb
Host smart-11eb1270-79c2-4490-866c-b052adb9e0c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268648253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmd
s.3268648253
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.2895335719
Short name T745
Test name
Test status
Simulation time 274949488 ps
CPU time 2.12 seconds
Started Jul 12 06:34:53 PM PDT 24
Finished Jul 12 06:34:56 PM PDT 24
Peak memory 224368 kb
Host smart-c86bc2d5-5d9d-479c-b0a8-158c046f0ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895335719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.2895335719
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.3249165535
Short name T661
Test name
Test status
Simulation time 826993135 ps
CPU time 13.15 seconds
Started Jul 12 06:34:55 PM PDT 24
Finished Jul 12 06:35:10 PM PDT 24
Peak memory 232608 kb
Host smart-7dc6720e-dcd5-452f-a249-984f52e0afb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249165535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.3249165535
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.543247292
Short name T374
Test name
Test status
Simulation time 5773020635 ps
CPU time 11.08 seconds
Started Jul 12 06:34:54 PM PDT 24
Finished Jul 12 06:35:07 PM PDT 24
Peak memory 224512 kb
Host smart-d03973e0-0b8d-4177-905f-7a9e904b8b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543247292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swap
.543247292
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.3397285551
Short name T840
Test name
Test status
Simulation time 76078603464 ps
CPU time 28.03 seconds
Started Jul 12 06:34:54 PM PDT 24
Finished Jul 12 06:35:24 PM PDT 24
Peak memory 232768 kb
Host smart-a093b4ee-c8f0-4bda-9ca6-455fdb39ae89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397285551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.3397285551
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.1374385622
Short name T384
Test name
Test status
Simulation time 845768405 ps
CPU time 4.18 seconds
Started Jul 12 06:34:51 PM PDT 24
Finished Jul 12 06:34:56 PM PDT 24
Peak memory 223092 kb
Host smart-8e89dcd0-3563-40f6-b36e-8bd9b8ce0ca6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1374385622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.1374385622
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.980587284
Short name T865
Test name
Test status
Simulation time 27444661875 ps
CPU time 48.34 seconds
Started Jul 12 06:35:08 PM PDT 24
Finished Jul 12 06:35:59 PM PDT 24
Peak memory 239512 kb
Host smart-1895e480-8a89-4c40-a1e8-7d6df5672f4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980587284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stres
s_all.980587284
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.3923753672
Short name T272
Test name
Test status
Simulation time 10545763818 ps
CPU time 29.13 seconds
Started Jul 12 06:34:53 PM PDT 24
Finished Jul 12 06:35:24 PM PDT 24
Peak memory 216316 kb
Host smart-9091c18b-2d46-458a-91b0-d721e81a9494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923753672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.3923753672
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.3426068463
Short name T298
Test name
Test status
Simulation time 1324714530 ps
CPU time 4.86 seconds
Started Jul 12 06:34:53 PM PDT 24
Finished Jul 12 06:34:59 PM PDT 24
Peak memory 216088 kb
Host smart-1b70feea-5564-49e9-8c32-7df5fbc96848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426068463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.3426068463
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.2862489982
Short name T1012
Test name
Test status
Simulation time 42256602 ps
CPU time 1.06 seconds
Started Jul 12 06:34:54 PM PDT 24
Finished Jul 12 06:34:56 PM PDT 24
Peak memory 207408 kb
Host smart-4f9f78ee-045e-4a01-bfbd-cbc17fce210c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862489982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.2862489982
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.636945528
Short name T365
Test name
Test status
Simulation time 94811929 ps
CPU time 0.94 seconds
Started Jul 12 06:34:51 PM PDT 24
Finished Jul 12 06:34:53 PM PDT 24
Peak memory 205948 kb
Host smart-b977259c-0913-418e-bf3d-26b3e144cdb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636945528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.636945528
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.2164418758
Short name T355
Test name
Test status
Simulation time 11325957734 ps
CPU time 10.76 seconds
Started Jul 12 06:34:53 PM PDT 24
Finished Jul 12 06:35:05 PM PDT 24
Peak memory 232732 kb
Host smart-6a2cb32b-0ce6-4613-a232-11512482579b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164418758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.2164418758
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.3172555979
Short name T706
Test name
Test status
Simulation time 44291680 ps
CPU time 0.69 seconds
Started Jul 12 06:35:08 PM PDT 24
Finished Jul 12 06:35:11 PM PDT 24
Peak memory 205484 kb
Host smart-cd73e269-2bed-4614-bca2-333b10dae39a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172555979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
3172555979
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.4132195362
Short name T978
Test name
Test status
Simulation time 257089417 ps
CPU time 2.2 seconds
Started Jul 12 06:35:01 PM PDT 24
Finished Jul 12 06:35:05 PM PDT 24
Peak memory 224064 kb
Host smart-5998cfbb-ecc2-4e05-8bce-80176104d401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132195362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.4132195362
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.2868295861
Short name T376
Test name
Test status
Simulation time 23824474 ps
CPU time 0.77 seconds
Started Jul 12 06:34:59 PM PDT 24
Finished Jul 12 06:35:01 PM PDT 24
Peak memory 205532 kb
Host smart-836376f3-de3e-4b31-afce-628eea512203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868295861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.2868295861
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.3234074410
Short name T962
Test name
Test status
Simulation time 2955407279 ps
CPU time 65.32 seconds
Started Jul 12 06:35:01 PM PDT 24
Finished Jul 12 06:36:08 PM PDT 24
Peak memory 250692 kb
Host smart-16e70abb-9fd4-4cc6-84c9-fb5e2b98d498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234074410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.3234074410
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.2770353042
Short name T603
Test name
Test status
Simulation time 88322179390 ps
CPU time 165.67 seconds
Started Jul 12 06:35:08 PM PDT 24
Finished Jul 12 06:37:56 PM PDT 24
Peak memory 250444 kb
Host smart-07268199-6814-4d6d-b276-ec70c1754079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770353042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.2770353042
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.2211305867
Short name T1015
Test name
Test status
Simulation time 4579197133 ps
CPU time 37.8 seconds
Started Jul 12 06:35:00 PM PDT 24
Finished Jul 12 06:35:39 PM PDT 24
Peak memory 241012 kb
Host smart-6e2cc6cb-0a30-4456-a1bb-22ceaabd64f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211305867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.2211305867
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.3534756819
Short name T596
Test name
Test status
Simulation time 550151042 ps
CPU time 4.16 seconds
Started Jul 12 06:35:08 PM PDT 24
Finished Jul 12 06:35:14 PM PDT 24
Peak memory 224380 kb
Host smart-815ddcbd-23c7-40da-ad27-761a1d8b36fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534756819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.3534756819
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.4067901965
Short name T171
Test name
Test status
Simulation time 1076652057 ps
CPU time 27.9 seconds
Started Jul 12 06:35:01 PM PDT 24
Finished Jul 12 06:35:30 PM PDT 24
Peak memory 240788 kb
Host smart-2c1a650d-f5bd-4984-9246-fb5da998352f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067901965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmd
s.4067901965
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.807971634
Short name T695
Test name
Test status
Simulation time 240336156 ps
CPU time 3.47 seconds
Started Jul 12 06:35:00 PM PDT 24
Finished Jul 12 06:35:05 PM PDT 24
Peak memory 224388 kb
Host smart-fc124541-0c60-4af7-9e80-ff57e9f2fb42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807971634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.807971634
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.1778329427
Short name T818
Test name
Test status
Simulation time 910146760 ps
CPU time 4.02 seconds
Started Jul 12 06:35:09 PM PDT 24
Finished Jul 12 06:35:15 PM PDT 24
Peak memory 224364 kb
Host smart-dd5eff8d-5d3c-42b7-9aa2-4539fc252587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778329427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.1778329427
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.3465209767
Short name T956
Test name
Test status
Simulation time 8731124660 ps
CPU time 28.26 seconds
Started Jul 12 06:35:08 PM PDT 24
Finished Jul 12 06:35:39 PM PDT 24
Peak memory 240408 kb
Host smart-ac35f44d-2423-421e-a255-34e3063b53fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465209767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.3465209767
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.651201849
Short name T494
Test name
Test status
Simulation time 6197667620 ps
CPU time 14.23 seconds
Started Jul 12 06:35:05 PM PDT 24
Finished Jul 12 06:35:20 PM PDT 24
Peak memory 232772 kb
Host smart-96252e16-2884-43bd-9130-1bdf23df5531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651201849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.651201849
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.2872526015
Short name T951
Test name
Test status
Simulation time 4158878149 ps
CPU time 11.25 seconds
Started Jul 12 06:35:00 PM PDT 24
Finished Jul 12 06:35:13 PM PDT 24
Peak memory 223212 kb
Host smart-69afb1d8-5fb2-440f-a863-efb972a58ad0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2872526015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.2872526015
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.1895508696
Short name T952
Test name
Test status
Simulation time 106299831904 ps
CPU time 221.84 seconds
Started Jul 12 06:35:00 PM PDT 24
Finished Jul 12 06:38:43 PM PDT 24
Peak memory 255952 kb
Host smart-01d6f0d6-6002-43b4-8e68-0d3a53682bd6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895508696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.1895508696
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.2235990742
Short name T512
Test name
Test status
Simulation time 4337171352 ps
CPU time 30.25 seconds
Started Jul 12 06:35:00 PM PDT 24
Finished Jul 12 06:35:31 PM PDT 24
Peak memory 216404 kb
Host smart-06bd778f-bdf4-41b2-8753-16f8be2a2e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235990742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.2235990742
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.818782592
Short name T316
Test name
Test status
Simulation time 97628593 ps
CPU time 0.73 seconds
Started Jul 12 06:35:02 PM PDT 24
Finished Jul 12 06:35:04 PM PDT 24
Peak memory 205656 kb
Host smart-c871ea97-ab59-458a-9f78-0eb6fd338292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818782592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.818782592
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.2021741451
Short name T585
Test name
Test status
Simulation time 505129372 ps
CPU time 5.92 seconds
Started Jul 12 06:35:06 PM PDT 24
Finished Jul 12 06:35:13 PM PDT 24
Peak memory 216196 kb
Host smart-8567c6ab-0d37-4f9f-8c24-32bd41057d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021741451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.2021741451
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.2781527543
Short name T508
Test name
Test status
Simulation time 199924174 ps
CPU time 0.9 seconds
Started Jul 12 06:35:00 PM PDT 24
Finished Jul 12 06:35:01 PM PDT 24
Peak memory 205924 kb
Host smart-0d592c67-7aa3-40a9-9cae-952846cf7d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781527543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.2781527543
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.1572124614
Short name T842
Test name
Test status
Simulation time 2329072342 ps
CPU time 9.82 seconds
Started Jul 12 06:35:00 PM PDT 24
Finished Jul 12 06:35:12 PM PDT 24
Peak memory 238764 kb
Host smart-77581071-782c-4ca2-9d35-85524a6541a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572124614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.1572124614
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.4259613176
Short name T942
Test name
Test status
Simulation time 31123875 ps
CPU time 0.71 seconds
Started Jul 12 06:35:08 PM PDT 24
Finished Jul 12 06:35:11 PM PDT 24
Peak memory 204888 kb
Host smart-59c5b8b1-6ab1-42d3-acd0-1b3019d62fe0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259613176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
4259613176
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.3667134481
Short name T86
Test name
Test status
Simulation time 199664270 ps
CPU time 3.11 seconds
Started Jul 12 06:35:03 PM PDT 24
Finished Jul 12 06:35:06 PM PDT 24
Peak memory 224576 kb
Host smart-890fc9f6-39d9-47c1-8602-c5800cf8540e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667134481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.3667134481
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.531291277
Short name T736
Test name
Test status
Simulation time 45876105 ps
CPU time 0.85 seconds
Started Jul 12 06:35:02 PM PDT 24
Finished Jul 12 06:35:04 PM PDT 24
Peak memory 206532 kb
Host smart-596bc87a-4aef-421b-88b2-790cbb411dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531291277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.531291277
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.205760313
Short name T252
Test name
Test status
Simulation time 13253378039 ps
CPU time 135.69 seconds
Started Jul 12 06:35:08 PM PDT 24
Finished Jul 12 06:37:25 PM PDT 24
Peak memory 255020 kb
Host smart-0ce5603f-56b6-4a7c-8c4e-2ca6488d84ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205760313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.205760313
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.1507637431
Short name T1004
Test name
Test status
Simulation time 25872553332 ps
CPU time 47.03 seconds
Started Jul 12 06:35:08 PM PDT 24
Finished Jul 12 06:35:57 PM PDT 24
Peak memory 252884 kb
Host smart-7d509116-14ef-4ff4-ad6d-7c126feffd69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507637431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.1507637431
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.309755132
Short name T402
Test name
Test status
Simulation time 28729806777 ps
CPU time 144.87 seconds
Started Jul 12 06:35:06 PM PDT 24
Finished Jul 12 06:37:32 PM PDT 24
Peak memory 252620 kb
Host smart-8611d3b8-5f53-44af-b699-36d66989d0df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309755132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idle
.309755132
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.2723791143
Short name T857
Test name
Test status
Simulation time 1050277355 ps
CPU time 6.11 seconds
Started Jul 12 06:35:08 PM PDT 24
Finished Jul 12 06:35:16 PM PDT 24
Peak memory 224432 kb
Host smart-1b2f9713-4e09-44a8-9da4-932789abe4c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723791143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.2723791143
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.2671622026
Short name T459
Test name
Test status
Simulation time 4497704581 ps
CPU time 53.47 seconds
Started Jul 12 06:35:07 PM PDT 24
Finished Jul 12 06:36:02 PM PDT 24
Peak memory 249120 kb
Host smart-76d7d047-65f9-4e92-8f4e-dc2c945db32f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671622026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmd
s.2671622026
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.3109015594
Short name T414
Test name
Test status
Simulation time 59066513 ps
CPU time 2.3 seconds
Started Jul 12 06:35:00 PM PDT 24
Finished Jul 12 06:35:04 PM PDT 24
Peak memory 232268 kb
Host smart-57356944-40dc-4e1a-a487-d7f7b2012cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109015594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.3109015594
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.2568378998
Short name T877
Test name
Test status
Simulation time 4302758403 ps
CPU time 48.52 seconds
Started Jul 12 06:35:08 PM PDT 24
Finished Jul 12 06:35:59 PM PDT 24
Peak memory 238884 kb
Host smart-bcbe9d98-e56f-4547-8145-c70b781fd21d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568378998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.2568378998
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.2996431438
Short name T94
Test name
Test status
Simulation time 6648637773 ps
CPU time 21.66 seconds
Started Jul 12 06:35:08 PM PDT 24
Finished Jul 12 06:35:32 PM PDT 24
Peak memory 224484 kb
Host smart-4708b846-1ad1-4a3b-a455-b2f8826de42c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996431438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.2996431438
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.4180605289
Short name T651
Test name
Test status
Simulation time 1421239097 ps
CPU time 6.91 seconds
Started Jul 12 06:35:05 PM PDT 24
Finished Jul 12 06:35:12 PM PDT 24
Peak memory 223048 kb
Host smart-ae5d6f02-c87c-4fd1-972a-61ab18212fe0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4180605289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.4180605289
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.3743815946
Short name T176
Test name
Test status
Simulation time 385797883603 ps
CPU time 291.7 seconds
Started Jul 12 06:35:08 PM PDT 24
Finished Jul 12 06:40:02 PM PDT 24
Peak memory 265596 kb
Host smart-39126eda-52aa-4930-a767-649ee4fe0e3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743815946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.3743815946
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.919637251
Short name T529
Test name
Test status
Simulation time 17931790 ps
CPU time 0.74 seconds
Started Jul 12 06:35:00 PM PDT 24
Finished Jul 12 06:35:01 PM PDT 24
Peak memory 205688 kb
Host smart-ba3540b5-ec06-4eab-8468-eb92cb8ce8f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919637251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.919637251
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.2005686391
Short name T440
Test name
Test status
Simulation time 24848966 ps
CPU time 0.72 seconds
Started Jul 12 06:35:00 PM PDT 24
Finished Jul 12 06:35:01 PM PDT 24
Peak memory 205600 kb
Host smart-286fe350-d467-466c-83a6-df5de6c046c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005686391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.2005686391
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.2076678568
Short name T574
Test name
Test status
Simulation time 35099915 ps
CPU time 1.55 seconds
Started Jul 12 06:34:59 PM PDT 24
Finished Jul 12 06:35:01 PM PDT 24
Peak memory 216208 kb
Host smart-03f473bb-ff18-4d67-abce-a9c3a96fadca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076678568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.2076678568
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.3975506210
Short name T72
Test name
Test status
Simulation time 157295236 ps
CPU time 0.77 seconds
Started Jul 12 06:35:06 PM PDT 24
Finished Jul 12 06:35:08 PM PDT 24
Peak memory 205908 kb
Host smart-9c9f5806-8a26-4fa4-b50e-292c57dd67a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975506210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.3975506210
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.2941749718
Short name T744
Test name
Test status
Simulation time 2294161078 ps
CPU time 11.32 seconds
Started Jul 12 06:35:01 PM PDT 24
Finished Jul 12 06:35:14 PM PDT 24
Peak memory 224536 kb
Host smart-65c7961c-0b4c-41af-abbc-27c5de83afb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941749718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.2941749718
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.2719909488
Short name T6
Test name
Test status
Simulation time 27940297 ps
CPU time 0.79 seconds
Started Jul 12 06:35:06 PM PDT 24
Finished Jul 12 06:35:09 PM PDT 24
Peak memory 204920 kb
Host smart-aae2feda-25b4-4d3b-9484-03206e6ec7d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719909488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
2719909488
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.1004790448
Short name T32
Test name
Test status
Simulation time 474925936 ps
CPU time 3.11 seconds
Started Jul 12 06:35:06 PM PDT 24
Finished Jul 12 06:35:10 PM PDT 24
Peak memory 224420 kb
Host smart-aebba333-1857-4432-a724-58517b5ff2a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004790448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.1004790448
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.3087180089
Short name T731
Test name
Test status
Simulation time 39406276 ps
CPU time 0.73 seconds
Started Jul 12 06:35:07 PM PDT 24
Finished Jul 12 06:35:09 PM PDT 24
Peak memory 206564 kb
Host smart-9c801544-17c4-4cff-8c45-588eec3e4f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087180089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.3087180089
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.2432976537
Short name T712
Test name
Test status
Simulation time 395277581382 ps
CPU time 193.01 seconds
Started Jul 12 06:35:09 PM PDT 24
Finished Jul 12 06:38:24 PM PDT 24
Peak memory 255372 kb
Host smart-0688c369-ec4a-409e-88ae-20e93debcf75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432976537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.2432976537
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.1859854101
Short name T364
Test name
Test status
Simulation time 283634648872 ps
CPU time 386.01 seconds
Started Jul 12 06:35:08 PM PDT 24
Finished Jul 12 06:41:36 PM PDT 24
Peak memory 255836 kb
Host smart-ca92b16c-1149-46f3-a669-417197217e11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859854101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.1859854101
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.947520158
Short name T38
Test name
Test status
Simulation time 15297414682 ps
CPU time 144.11 seconds
Started Jul 12 06:35:09 PM PDT 24
Finished Jul 12 06:37:35 PM PDT 24
Peak memory 249200 kb
Host smart-bf05a0fd-95c1-4a28-a3d5-83ebad502d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947520158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idle
.947520158
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.3948958050
Short name T762
Test name
Test status
Simulation time 12125107864 ps
CPU time 30.81 seconds
Started Jul 12 06:35:07 PM PDT 24
Finished Jul 12 06:35:39 PM PDT 24
Peak memory 249140 kb
Host smart-c70193fa-0418-45fd-a64d-74cb3a8da3c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948958050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.3948958050
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.3921568277
Short name T572
Test name
Test status
Simulation time 7490605384 ps
CPU time 42.85 seconds
Started Jul 12 06:35:07 PM PDT 24
Finished Jul 12 06:35:51 PM PDT 24
Peak memory 249096 kb
Host smart-7e31adb5-ce90-452c-8f63-337c1cf479a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921568277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmd
s.3921568277
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.3188997922
Short name T487
Test name
Test status
Simulation time 99196099 ps
CPU time 2.23 seconds
Started Jul 12 06:35:10 PM PDT 24
Finished Jul 12 06:35:14 PM PDT 24
Peak memory 232236 kb
Host smart-41950df9-9735-4aa7-b8c2-07318c1556d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188997922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.3188997922
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.4184912535
Short name T442
Test name
Test status
Simulation time 3938367954 ps
CPU time 14.71 seconds
Started Jul 12 06:35:07 PM PDT 24
Finished Jul 12 06:35:23 PM PDT 24
Peak memory 250496 kb
Host smart-256c0c92-93dc-4ebc-939d-eef01843801e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184912535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.4184912535
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.2360721175
Short name T807
Test name
Test status
Simulation time 1460715765 ps
CPU time 2.98 seconds
Started Jul 12 06:35:09 PM PDT 24
Finished Jul 12 06:35:14 PM PDT 24
Peak memory 224384 kb
Host smart-e325dd51-8878-428c-8c85-3576d0655aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360721175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.2360721175
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.1577107145
Short name T408
Test name
Test status
Simulation time 3025425565 ps
CPU time 4.23 seconds
Started Jul 12 06:35:07 PM PDT 24
Finished Jul 12 06:35:13 PM PDT 24
Peak memory 224464 kb
Host smart-75fc73a2-110c-4d0c-ba96-e485a97e4c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577107145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.1577107145
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.766148064
Short name T390
Test name
Test status
Simulation time 124286300 ps
CPU time 3.22 seconds
Started Jul 12 06:35:07 PM PDT 24
Finished Jul 12 06:35:11 PM PDT 24
Peak memory 222604 kb
Host smart-30c2a50e-69be-4f7f-9110-e5613ab0fbea
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=766148064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dire
ct.766148064
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.4230595091
Short name T394
Test name
Test status
Simulation time 76523229238 ps
CPU time 123.58 seconds
Started Jul 12 06:35:09 PM PDT 24
Finished Jul 12 06:37:14 PM PDT 24
Peak memory 257348 kb
Host smart-299709c1-4230-4273-9a78-cb1e7ce2e85d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230595091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.4230595091
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.4105575983
Short name T806
Test name
Test status
Simulation time 83175848625 ps
CPU time 31.5 seconds
Started Jul 12 06:35:09 PM PDT 24
Finished Jul 12 06:35:43 PM PDT 24
Peak memory 216272 kb
Host smart-767417cd-c540-441a-b05b-0f745b522773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105575983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.4105575983
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.56945553
Short name T357
Test name
Test status
Simulation time 1394946066 ps
CPU time 6.29 seconds
Started Jul 12 06:35:09 PM PDT 24
Finished Jul 12 06:35:17 PM PDT 24
Peak memory 216168 kb
Host smart-4b145d0d-1e1d-433c-a413-37eb2fefcd15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56945553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.56945553
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.788661154
Short name T913
Test name
Test status
Simulation time 134074412 ps
CPU time 5.68 seconds
Started Jul 12 06:35:07 PM PDT 24
Finished Jul 12 06:35:14 PM PDT 24
Peak memory 216144 kb
Host smart-f51a57d9-b097-4d46-8760-d57c375a1f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788661154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.788661154
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.927042343
Short name T994
Test name
Test status
Simulation time 29986617 ps
CPU time 0.86 seconds
Started Jul 12 06:35:09 PM PDT 24
Finished Jul 12 06:35:12 PM PDT 24
Peak memory 205920 kb
Host smart-88dd61ef-12c6-4d6e-aa92-86538e53ef1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927042343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.927042343
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.3403979753
Short name T438
Test name
Test status
Simulation time 707114751 ps
CPU time 3.58 seconds
Started Jul 12 06:35:10 PM PDT 24
Finished Jul 12 06:35:16 PM PDT 24
Peak memory 232572 kb
Host smart-50740921-a9c8-4f8f-96c7-7f5436c78e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403979753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.3403979753
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.2351725932
Short name T629
Test name
Test status
Simulation time 28426236 ps
CPU time 0.74 seconds
Started Jul 12 06:35:19 PM PDT 24
Finished Jul 12 06:35:21 PM PDT 24
Peak memory 205472 kb
Host smart-5120705a-72f9-40fa-8dd3-bfc3b9828f64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351725932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
2351725932
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.2492639132
Short name T592
Test name
Test status
Simulation time 564273376 ps
CPU time 5.6 seconds
Started Jul 12 06:35:20 PM PDT 24
Finished Jul 12 06:35:27 PM PDT 24
Peak memory 224372 kb
Host smart-0687dbd8-e188-4777-8122-553db3c95fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492639132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.2492639132
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.2614655276
Short name T321
Test name
Test status
Simulation time 18494367 ps
CPU time 0.81 seconds
Started Jul 12 06:35:06 PM PDT 24
Finished Jul 12 06:35:08 PM PDT 24
Peak memory 206500 kb
Host smart-1e340386-facf-45d1-b40a-21a6ec9ca5b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614655276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.2614655276
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.587544968
Short name T25
Test name
Test status
Simulation time 22113531678 ps
CPU time 50.98 seconds
Started Jul 12 06:35:20 PM PDT 24
Finished Jul 12 06:36:13 PM PDT 24
Peak memory 254220 kb
Host smart-94ec73e4-4a71-4251-b75c-534a47c95729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587544968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.587544968
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.2871719274
Short name T785
Test name
Test status
Simulation time 2398878738 ps
CPU time 26.21 seconds
Started Jul 12 06:35:30 PM PDT 24
Finished Jul 12 06:35:58 PM PDT 24
Peak memory 248420 kb
Host smart-cfe565eb-5ab8-4c66-b197-4294252226e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871719274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.2871719274
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.1544194666
Short name T701
Test name
Test status
Simulation time 27364228686 ps
CPU time 79.32 seconds
Started Jul 12 06:35:20 PM PDT 24
Finished Jul 12 06:36:40 PM PDT 24
Peak memory 250244 kb
Host smart-db7fd236-bdc1-48d8-ac6c-75cb7a57ac2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544194666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.1544194666
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.2632175134
Short name T653
Test name
Test status
Simulation time 5779907483 ps
CPU time 21.95 seconds
Started Jul 12 06:35:18 PM PDT 24
Finished Jul 12 06:35:41 PM PDT 24
Peak memory 248800 kb
Host smart-ff2263b4-07f2-4e3d-a994-0419dd0d6790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632175134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.2632175134
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.3688399063
Short name T43
Test name
Test status
Simulation time 46531247021 ps
CPU time 119.69 seconds
Started Jul 12 06:35:18 PM PDT 24
Finished Jul 12 06:37:18 PM PDT 24
Peak memory 264392 kb
Host smart-6d60c2e4-6e4e-4d23-8066-060d878176b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688399063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmd
s.3688399063
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.2914797662
Short name T714
Test name
Test status
Simulation time 86286704 ps
CPU time 3.43 seconds
Started Jul 12 06:35:22 PM PDT 24
Finished Jul 12 06:35:26 PM PDT 24
Peak memory 227784 kb
Host smart-9d9372e6-3204-4f99-b264-568b3e5e8484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914797662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.2914797662
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.807973741
Short name T703
Test name
Test status
Simulation time 384653132 ps
CPU time 8.06 seconds
Started Jul 12 06:35:18 PM PDT 24
Finished Jul 12 06:35:28 PM PDT 24
Peak memory 224436 kb
Host smart-602e6c3b-6015-40e5-9c62-edda8819382e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807973741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.807973741
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.293696483
Short name T811
Test name
Test status
Simulation time 25521961692 ps
CPU time 9.02 seconds
Started Jul 12 06:35:20 PM PDT 24
Finished Jul 12 06:35:30 PM PDT 24
Peak memory 232760 kb
Host smart-8e48a606-d782-4894-b030-bc75b7f9098e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293696483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swap
.293696483
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.3991747461
Short name T576
Test name
Test status
Simulation time 8008451509 ps
CPU time 31.3 seconds
Started Jul 12 06:35:06 PM PDT 24
Finished Jul 12 06:35:38 PM PDT 24
Peak memory 224592 kb
Host smart-49059bcf-3590-4638-ad68-c70747f47a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991747461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.3991747461
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.4223133638
Short name T669
Test name
Test status
Simulation time 1773937227 ps
CPU time 12.14 seconds
Started Jul 12 06:35:19 PM PDT 24
Finished Jul 12 06:35:33 PM PDT 24
Peak memory 222908 kb
Host smart-1140ca7a-8fa2-4df7-a56a-73eac8dae348
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4223133638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.4223133638
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.3240601842
Short name T758
Test name
Test status
Simulation time 499481449 ps
CPU time 3.46 seconds
Started Jul 12 06:35:06 PM PDT 24
Finished Jul 12 06:35:10 PM PDT 24
Peak memory 216112 kb
Host smart-1ad0f1a0-f677-48ad-892d-43155eb263b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240601842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.3240601842
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.1999258514
Short name T589
Test name
Test status
Simulation time 3979615186 ps
CPU time 6.41 seconds
Started Jul 12 06:35:07 PM PDT 24
Finished Jul 12 06:35:16 PM PDT 24
Peak memory 216244 kb
Host smart-bb79a912-7430-4abc-9ca9-2e34c57bc034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999258514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.1999258514
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.3758914563
Short name T580
Test name
Test status
Simulation time 37679161 ps
CPU time 1.35 seconds
Started Jul 12 06:35:08 PM PDT 24
Finished Jul 12 06:35:12 PM PDT 24
Peak memory 216132 kb
Host smart-1282471b-5fae-470b-9489-8ef7a9717c75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758914563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.3758914563
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.1502015885
Short name T583
Test name
Test status
Simulation time 102700486 ps
CPU time 0.79 seconds
Started Jul 12 06:35:07 PM PDT 24
Finished Jul 12 06:35:09 PM PDT 24
Peak memory 205920 kb
Host smart-4fb71c45-9bcd-42dd-9116-8861d132d8c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502015885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.1502015885
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.217761138
Short name T1000
Test name
Test status
Simulation time 3067860371 ps
CPU time 7.5 seconds
Started Jul 12 06:35:20 PM PDT 24
Finished Jul 12 06:35:29 PM PDT 24
Peak memory 224500 kb
Host smart-b8143efd-853a-42c3-974c-4753b4e18022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217761138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.217761138
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.3769271743
Short name T708
Test name
Test status
Simulation time 18066914 ps
CPU time 0.78 seconds
Started Jul 12 06:31:11 PM PDT 24
Finished Jul 12 06:31:15 PM PDT 24
Peak memory 204924 kb
Host smart-02645756-f643-48b6-aebb-407a20873f3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769271743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.3
769271743
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.2330478413
Short name T358
Test name
Test status
Simulation time 37459101 ps
CPU time 2.62 seconds
Started Jul 12 06:31:11 PM PDT 24
Finished Jul 12 06:31:17 PM PDT 24
Peak memory 232644 kb
Host smart-6040b4e1-7f9c-47e0-9a5a-a049a9263b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330478413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.2330478413
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.2995411254
Short name T754
Test name
Test status
Simulation time 44864173 ps
CPU time 0.78 seconds
Started Jul 12 06:31:10 PM PDT 24
Finished Jul 12 06:31:14 PM PDT 24
Peak memory 205848 kb
Host smart-22d21547-3bf0-4571-9e9a-ce0d11ccc96a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995411254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.2995411254
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.1410961436
Short name T516
Test name
Test status
Simulation time 34235864576 ps
CPU time 52.53 seconds
Started Jul 12 06:31:09 PM PDT 24
Finished Jul 12 06:32:04 PM PDT 24
Peak memory 232700 kb
Host smart-31718cfe-53a5-4ec8-8272-6a5dc373dfbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410961436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.1410961436
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.1777337196
Short name T606
Test name
Test status
Simulation time 22014298794 ps
CPU time 189.54 seconds
Started Jul 12 06:31:10 PM PDT 24
Finished Jul 12 06:34:22 PM PDT 24
Peak memory 249236 kb
Host smart-fb480ecc-e04c-4222-90ac-1ce4649a4ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777337196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.1777337196
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.1790734461
Short name T243
Test name
Test status
Simulation time 80696358317 ps
CPU time 178.74 seconds
Started Jul 12 06:31:13 PM PDT 24
Finished Jul 12 06:34:15 PM PDT 24
Peak memory 254900 kb
Host smart-877a9cbb-e76d-4bd8-8ed5-06a70d4ae074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790734461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.1790734461
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.2985632684
Short name T867
Test name
Test status
Simulation time 581234539 ps
CPU time 5.71 seconds
Started Jul 12 06:31:13 PM PDT 24
Finished Jul 12 06:31:22 PM PDT 24
Peak memory 224340 kb
Host smart-bfcb5dfc-2343-4e7f-a6ad-1b418c0c5e11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985632684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.2985632684
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.339220208
Short name T563
Test name
Test status
Simulation time 1696884942 ps
CPU time 40.32 seconds
Started Jul 12 06:31:10 PM PDT 24
Finished Jul 12 06:31:54 PM PDT 24
Peak memory 253628 kb
Host smart-31385e1f-8c29-4a4d-9883-94eed6af790e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339220208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds.
339220208
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.1230818083
Short name T689
Test name
Test status
Simulation time 2311340783 ps
CPU time 7.61 seconds
Started Jul 12 06:31:09 PM PDT 24
Finished Jul 12 06:31:20 PM PDT 24
Peak memory 232768 kb
Host smart-3c2c8b6d-0440-41c7-942c-b147d28c1e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230818083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.1230818083
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.591234590
Short name T552
Test name
Test status
Simulation time 551920293 ps
CPU time 14.54 seconds
Started Jul 12 06:31:14 PM PDT 24
Finished Jul 12 06:31:30 PM PDT 24
Peak memory 248984 kb
Host smart-aaa987db-335b-408d-a4fd-ad332203ad4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591234590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.591234590
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.301735696
Short name T126
Test name
Test status
Simulation time 31731309109 ps
CPU time 18.14 seconds
Started Jul 12 06:31:10 PM PDT 24
Finished Jul 12 06:31:32 PM PDT 24
Peak memory 232676 kb
Host smart-488c47d2-e9e9-471a-bd98-0d4ff6e59ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301735696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap.
301735696
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.1308998000
Short name T1016
Test name
Test status
Simulation time 23122443721 ps
CPU time 19.92 seconds
Started Jul 12 06:31:12 PM PDT 24
Finished Jul 12 06:31:35 PM PDT 24
Peak memory 232732 kb
Host smart-442d2e05-ca7c-479a-a2f4-aaf1f2955a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308998000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.1308998000
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.1329435311
Short name T738
Test name
Test status
Simulation time 1134337944 ps
CPU time 5.97 seconds
Started Jul 12 06:31:14 PM PDT 24
Finished Jul 12 06:31:22 PM PDT 24
Peak memory 220116 kb
Host smart-517d107d-f242-45ae-b5cb-c931cf34e2ce
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1329435311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.1329435311
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.1641528297
Short name T702
Test name
Test status
Simulation time 1209043223540 ps
CPU time 573.47 seconds
Started Jul 12 06:31:13 PM PDT 24
Finished Jul 12 06:40:49 PM PDT 24
Peak memory 255456 kb
Host smart-30561684-9145-4ef7-b19b-b25f32849513
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641528297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.1641528297
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.1856317102
Short name T44
Test name
Test status
Simulation time 42327423828 ps
CPU time 30.09 seconds
Started Jul 12 06:31:12 PM PDT 24
Finished Jul 12 06:31:45 PM PDT 24
Peak memory 216316 kb
Host smart-49906c7a-34fd-45bd-b507-0f6a20fdf472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856317102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.1856317102
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.130058530
Short name T339
Test name
Test status
Simulation time 30078606384 ps
CPU time 14.07 seconds
Started Jul 12 06:31:11 PM PDT 24
Finished Jul 12 06:31:29 PM PDT 24
Peak memory 216456 kb
Host smart-23e9d731-364a-44fc-b064-4c42ec6c9080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130058530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.130058530
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.2727477477
Short name T53
Test name
Test status
Simulation time 159991801 ps
CPU time 1.41 seconds
Started Jul 12 06:31:11 PM PDT 24
Finished Jul 12 06:31:15 PM PDT 24
Peak memory 216092 kb
Host smart-a77c6055-d5b3-4bd5-bddf-6d7f976ef736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727477477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.2727477477
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.1053300164
Short name T308
Test name
Test status
Simulation time 156470330 ps
CPU time 0.81 seconds
Started Jul 12 06:31:11 PM PDT 24
Finished Jul 12 06:31:15 PM PDT 24
Peak memory 205920 kb
Host smart-a700658a-664e-41ee-bd47-7a7ae16c8ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053300164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.1053300164
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.989203528
Short name T668
Test name
Test status
Simulation time 71182711 ps
CPU time 2.32 seconds
Started Jul 12 06:31:14 PM PDT 24
Finished Jul 12 06:31:18 PM PDT 24
Peak memory 224332 kb
Host smart-da617e21-a857-4125-92d8-7365e44c3435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989203528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.989203528
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.4112792849
Short name T533
Test name
Test status
Simulation time 13959411 ps
CPU time 0.72 seconds
Started Jul 12 06:31:17 PM PDT 24
Finished Jul 12 06:31:18 PM PDT 24
Peak memory 205440 kb
Host smart-364b8345-20c7-4861-9b10-01a1c555f179
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112792849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.4
112792849
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.3927010385
Short name T722
Test name
Test status
Simulation time 2269266861 ps
CPU time 8.63 seconds
Started Jul 12 06:31:21 PM PDT 24
Finished Jul 12 06:31:31 PM PDT 24
Peak memory 224456 kb
Host smart-c05d5618-6b49-45b2-bb58-1db6e66c4b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927010385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.3927010385
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.1930287528
Short name T558
Test name
Test status
Simulation time 56397523 ps
CPU time 0.78 seconds
Started Jul 12 06:31:18 PM PDT 24
Finished Jul 12 06:31:21 PM PDT 24
Peak memory 206536 kb
Host smart-2d8737d4-66b5-4b38-8dcc-5c077393d287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930287528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.1930287528
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.885722085
Short name T463
Test name
Test status
Simulation time 6173990462 ps
CPU time 29.73 seconds
Started Jul 12 06:31:18 PM PDT 24
Finished Jul 12 06:31:50 PM PDT 24
Peak memory 238812 kb
Host smart-9c7b2635-3754-4d74-8954-da25f1e31ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885722085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.885722085
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.1845976841
Short name T183
Test name
Test status
Simulation time 85914351156 ps
CPU time 240.85 seconds
Started Jul 12 06:31:18 PM PDT 24
Finished Jul 12 06:35:21 PM PDT 24
Peak memory 265264 kb
Host smart-168e18a3-70f2-4614-86e0-d2176ab00c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845976841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.1845976841
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.877376692
Short name T419
Test name
Test status
Simulation time 2963536170 ps
CPU time 50.87 seconds
Started Jul 12 06:31:17 PM PDT 24
Finished Jul 12 06:32:10 PM PDT 24
Peak memory 249196 kb
Host smart-8ea4c5a8-993f-4eae-9d4c-11f678971012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877376692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle.
877376692
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.2374830712
Short name T881
Test name
Test status
Simulation time 1871009661 ps
CPU time 6.01 seconds
Started Jul 12 06:31:19 PM PDT 24
Finished Jul 12 06:31:26 PM PDT 24
Peak memory 232644 kb
Host smart-2034c2fe-6047-4411-a06a-24a291628595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374830712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.2374830712
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.3587562830
Short name T831
Test name
Test status
Simulation time 19210825375 ps
CPU time 37.37 seconds
Started Jul 12 06:31:20 PM PDT 24
Finished Jul 12 06:31:59 PM PDT 24
Peak memory 232712 kb
Host smart-b197d482-a2cf-4aaa-8481-85c24b258157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587562830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds
.3587562830
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.3638024413
Short name T696
Test name
Test status
Simulation time 877448758 ps
CPU time 5.44 seconds
Started Jul 12 06:31:18 PM PDT 24
Finished Jul 12 06:31:25 PM PDT 24
Peak memory 232548 kb
Host smart-4eb6ff85-3f38-463e-a0b3-35d9fefa795b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638024413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.3638024413
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.1273764269
Short name T786
Test name
Test status
Simulation time 37363354 ps
CPU time 2.92 seconds
Started Jul 12 06:31:16 PM PDT 24
Finished Jul 12 06:31:20 PM PDT 24
Peak memory 232568 kb
Host smart-f19d7aaf-0680-4805-b436-7ff4fd6e5c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273764269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.1273764269
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.3138660115
Short name T232
Test name
Test status
Simulation time 473067966 ps
CPU time 4.48 seconds
Started Jul 12 06:31:20 PM PDT 24
Finished Jul 12 06:31:26 PM PDT 24
Peak memory 236144 kb
Host smart-f193d893-81a8-43b6-94f2-3dfdc957923f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138660115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.3138660115
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.1052215896
Short name T203
Test name
Test status
Simulation time 22886729224 ps
CPU time 14.85 seconds
Started Jul 12 06:31:20 PM PDT 24
Finished Jul 12 06:31:37 PM PDT 24
Peak memory 248680 kb
Host smart-4deaa06b-796b-4cd6-b028-8344b12001c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052215896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.1052215896
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.2541227811
Short name T626
Test name
Test status
Simulation time 2108273307 ps
CPU time 3.65 seconds
Started Jul 12 06:31:20 PM PDT 24
Finished Jul 12 06:31:25 PM PDT 24
Peak memory 220052 kb
Host smart-f8747ee7-189a-4cf0-bdd9-23ed5a11d498
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2541227811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.2541227811
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.3955777046
Short name T151
Test name
Test status
Simulation time 54697936 ps
CPU time 0.95 seconds
Started Jul 12 06:38:53 PM PDT 24
Finished Jul 12 06:38:56 PM PDT 24
Peak memory 207432 kb
Host smart-52f0a61f-aa3c-4659-8a33-e67fc3e6e905
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955777046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.3955777046
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.956747605
Short name T566
Test name
Test status
Simulation time 1238788239 ps
CPU time 9.02 seconds
Started Jul 12 06:31:19 PM PDT 24
Finished Jul 12 06:31:29 PM PDT 24
Peak memory 216524 kb
Host smart-0ecf1e62-4f49-490e-9f28-bceba0b72848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956747605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.956747605
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.312958093
Short name T923
Test name
Test status
Simulation time 9119170852 ps
CPU time 7.33 seconds
Started Jul 12 06:31:20 PM PDT 24
Finished Jul 12 06:31:30 PM PDT 24
Peak memory 217652 kb
Host smart-42b4f19f-8861-4050-b10c-c2eb9fae4d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312958093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.312958093
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.308398200
Short name T810
Test name
Test status
Simulation time 2751613596 ps
CPU time 3.16 seconds
Started Jul 12 06:31:20 PM PDT 24
Finished Jul 12 06:31:25 PM PDT 24
Peak memory 216260 kb
Host smart-26145be0-6171-4141-9947-1da415c43bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308398200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.308398200
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.1275686722
Short name T843
Test name
Test status
Simulation time 52849717 ps
CPU time 0.72 seconds
Started Jul 12 06:31:18 PM PDT 24
Finished Jul 12 06:31:20 PM PDT 24
Peak memory 205912 kb
Host smart-2b45325c-9f95-43ed-af0c-345ce0577b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275686722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.1275686722
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.767571330
Short name T677
Test name
Test status
Simulation time 87019555 ps
CPU time 2.18 seconds
Started Jul 12 06:31:22 PM PDT 24
Finished Jul 12 06:31:25 PM PDT 24
Peak memory 224056 kb
Host smart-fb2258af-5957-46f7-8ce7-29f66b8f1c2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767571330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.767571330
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.805892235
Short name T823
Test name
Test status
Simulation time 20723093 ps
CPU time 0.74 seconds
Started Jul 12 06:31:20 PM PDT 24
Finished Jul 12 06:31:23 PM PDT 24
Peak memory 205500 kb
Host smart-f294f634-fa84-4193-b3f0-b85f97a5286d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805892235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.805892235
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.1273211662
Short name T488
Test name
Test status
Simulation time 55421076 ps
CPU time 2.26 seconds
Started Jul 12 06:31:20 PM PDT 24
Finished Jul 12 06:31:24 PM PDT 24
Peak memory 224240 kb
Host smart-41413b01-616e-4c59-8615-f985c9552bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273211662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.1273211662
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.2751814450
Short name T946
Test name
Test status
Simulation time 16220492 ps
CPU time 0.75 seconds
Started Jul 12 06:31:17 PM PDT 24
Finished Jul 12 06:31:19 PM PDT 24
Peak memory 206860 kb
Host smart-f2f2ba7e-be33-4667-8293-e6f87bdf5cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751814450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.2751814450
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.1624047739
Short name T688
Test name
Test status
Simulation time 35986156240 ps
CPU time 214.44 seconds
Started Jul 12 06:31:21 PM PDT 24
Finished Jul 12 06:34:57 PM PDT 24
Peak memory 264028 kb
Host smart-76cb5f0c-6095-48c1-9084-37f49c8b2f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624047739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.1624047739
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.2272847780
Short name T841
Test name
Test status
Simulation time 7858289859 ps
CPU time 67.56 seconds
Started Jul 12 06:31:17 PM PDT 24
Finished Jul 12 06:32:26 PM PDT 24
Peak memory 240776 kb
Host smart-492553c1-d95d-42d2-9425-d03a46212e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272847780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.2272847780
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.726695032
Short name T930
Test name
Test status
Simulation time 3123020804 ps
CPU time 11.24 seconds
Started Jul 12 06:31:18 PM PDT 24
Finished Jul 12 06:31:31 PM PDT 24
Peak memory 224532 kb
Host smart-ed6d5d58-337b-4df1-a5d0-68e882f68a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726695032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.726695032
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.1472249168
Short name T899
Test name
Test status
Simulation time 121127626421 ps
CPU time 458.28 seconds
Started Jul 12 06:31:17 PM PDT 24
Finished Jul 12 06:38:57 PM PDT 24
Peak memory 255900 kb
Host smart-80fd8a00-e23a-46cc-825e-7e72b7b1aa4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472249168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds
.1472249168
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.4267945338
Short name T506
Test name
Test status
Simulation time 242495556 ps
CPU time 3.23 seconds
Started Jul 12 06:31:18 PM PDT 24
Finished Jul 12 06:31:23 PM PDT 24
Peak memory 224320 kb
Host smart-83dda914-be3f-474b-a299-38bc626a6411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267945338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.4267945338
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.806102150
Short name T715
Test name
Test status
Simulation time 9583719130 ps
CPU time 30.35 seconds
Started Jul 12 06:31:20 PM PDT 24
Finished Jul 12 06:31:52 PM PDT 24
Peak memory 232768 kb
Host smart-5df18b18-a535-4c93-ad3e-61118dc29664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806102150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.806102150
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.1907894345
Short name T628
Test name
Test status
Simulation time 67126006927 ps
CPU time 18.89 seconds
Started Jul 12 06:31:21 PM PDT 24
Finished Jul 12 06:31:41 PM PDT 24
Peak memory 232724 kb
Host smart-3cf0a69a-3184-4b9b-b4dc-a558df9784cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907894345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.1907894345
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.248720210
Short name T607
Test name
Test status
Simulation time 2609872158 ps
CPU time 7.35 seconds
Started Jul 12 06:31:22 PM PDT 24
Finished Jul 12 06:31:30 PM PDT 24
Peak memory 232608 kb
Host smart-c747ea67-f97e-4bc6-bb25-90a4dbb5e855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248720210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.248720210
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.2602123875
Short name T691
Test name
Test status
Simulation time 901480318 ps
CPU time 3.92 seconds
Started Jul 12 06:31:25 PM PDT 24
Finished Jul 12 06:31:30 PM PDT 24
Peak memory 220208 kb
Host smart-a7465c9a-5253-4fa3-8f24-e0635a271c67
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2602123875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.2602123875
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.3674850383
Short name T935
Test name
Test status
Simulation time 484818278 ps
CPU time 0.98 seconds
Started Jul 12 06:31:18 PM PDT 24
Finished Jul 12 06:31:20 PM PDT 24
Peak memory 206740 kb
Host smart-d0737a4e-b63c-4098-b8f3-0efd3f23a02a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674850383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.3674850383
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.732329430
Short name T817
Test name
Test status
Simulation time 25460923017 ps
CPU time 41.12 seconds
Started Jul 12 06:31:18 PM PDT 24
Finished Jul 12 06:32:00 PM PDT 24
Peak memory 216336 kb
Host smart-fa83186f-93ba-4be4-85e4-ddc016a881b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732329430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.732329430
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.3552583367
Short name T860
Test name
Test status
Simulation time 17787546 ps
CPU time 0.74 seconds
Started Jul 12 06:31:20 PM PDT 24
Finished Jul 12 06:31:23 PM PDT 24
Peak memory 205652 kb
Host smart-b7fa3c47-b6a7-4d16-821c-e3edc7d7ddf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552583367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.3552583367
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.1111282919
Short name T680
Test name
Test status
Simulation time 50412826 ps
CPU time 0.86 seconds
Started Jul 12 06:31:22 PM PDT 24
Finished Jul 12 06:31:24 PM PDT 24
Peak memory 206784 kb
Host smart-5a8817de-1192-484e-9448-fadc82892237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111282919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.1111282919
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.2160216148
Short name T29
Test name
Test status
Simulation time 78702626 ps
CPU time 0.89 seconds
Started Jul 12 06:31:17 PM PDT 24
Finished Jul 12 06:31:19 PM PDT 24
Peak memory 205908 kb
Host smart-4219167d-a67d-4adb-8ae8-f3106b8174e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160216148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.2160216148
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.120102725
Short name T665
Test name
Test status
Simulation time 1751468905 ps
CPU time 7.16 seconds
Started Jul 12 06:31:19 PM PDT 24
Finished Jul 12 06:31:28 PM PDT 24
Peak memory 232608 kb
Host smart-2da376a0-0d8d-4037-9b18-d0658f61946b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120102725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.120102725
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.1426844274
Short name T821
Test name
Test status
Simulation time 12233753 ps
CPU time 0.73 seconds
Started Jul 12 06:31:26 PM PDT 24
Finished Jul 12 06:31:29 PM PDT 24
Peak memory 205460 kb
Host smart-bd3dd389-97df-46b9-8906-8b1e73842703
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426844274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.1
426844274
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.2851086942
Short name T383
Test name
Test status
Simulation time 30502757 ps
CPU time 2.19 seconds
Started Jul 12 06:31:26 PM PDT 24
Finished Jul 12 06:31:30 PM PDT 24
Peak memory 224012 kb
Host smart-39078be4-865d-4d85-bc89-87a19fb45d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851086942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.2851086942
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.3210977206
Short name T445
Test name
Test status
Simulation time 18429656 ps
CPU time 0.78 seconds
Started Jul 12 06:31:21 PM PDT 24
Finished Jul 12 06:31:23 PM PDT 24
Peak memory 206888 kb
Host smart-bd4f5859-3527-4d4e-903e-fc45c84f62fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210977206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.3210977206
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.220544900
Short name T502
Test name
Test status
Simulation time 91184662733 ps
CPU time 175.87 seconds
Started Jul 12 06:31:27 PM PDT 24
Finished Jul 12 06:34:25 PM PDT 24
Peak memory 249316 kb
Host smart-718a875f-0b3c-49ce-9a14-2dd92b68e0be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220544900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.220544900
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.1179549766
Short name T172
Test name
Test status
Simulation time 14755678480 ps
CPU time 36.14 seconds
Started Jul 12 06:31:25 PM PDT 24
Finished Jul 12 06:32:02 PM PDT 24
Peak memory 240932 kb
Host smart-2beafacd-5577-49f1-95c2-76d374626161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179549766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.1179549766
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.2768921028
Short name T240
Test name
Test status
Simulation time 194356722421 ps
CPU time 465.86 seconds
Started Jul 12 06:31:29 PM PDT 24
Finished Jul 12 06:39:16 PM PDT 24
Peak memory 265244 kb
Host smart-2f7e7c43-b2fc-4db8-8c22-887dbd9c8f5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768921028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.2768921028
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.357737455
Short name T92
Test name
Test status
Simulation time 281541219 ps
CPU time 7.97 seconds
Started Jul 12 06:31:27 PM PDT 24
Finished Jul 12 06:31:37 PM PDT 24
Peak memory 232632 kb
Host smart-e881a2c5-3ff3-441e-b3f3-293d4047205f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357737455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.357737455
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.368827212
Short name T41
Test name
Test status
Simulation time 1255348492 ps
CPU time 10.31 seconds
Started Jul 12 06:31:26 PM PDT 24
Finished Jul 12 06:31:38 PM PDT 24
Peak memory 224432 kb
Host smart-3c0d934e-35b8-4c11-9fd2-1e4ec9e0d185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368827212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds.
368827212
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.987010776
Short name T982
Test name
Test status
Simulation time 8536544004 ps
CPU time 10.29 seconds
Started Jul 12 06:31:29 PM PDT 24
Finished Jul 12 06:31:41 PM PDT 24
Peak memory 224440 kb
Host smart-7029881e-78d0-4772-901b-b31cff48cdea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987010776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.987010776
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.2253350238
Short name T551
Test name
Test status
Simulation time 277758437 ps
CPU time 9.37 seconds
Started Jul 12 06:31:30 PM PDT 24
Finished Jul 12 06:31:40 PM PDT 24
Peak memory 240512 kb
Host smart-52ff1ef0-c707-4e6c-9fcf-dbfc2aba833a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253350238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.2253350238
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.2487735103
Short name T205
Test name
Test status
Simulation time 1202771262 ps
CPU time 8.71 seconds
Started Jul 12 06:31:29 PM PDT 24
Finished Jul 12 06:31:39 PM PDT 24
Peak memory 232800 kb
Host smart-ad8e6475-16d9-441f-811e-7da78f68e5ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487735103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.2487735103
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.3268686323
Short name T415
Test name
Test status
Simulation time 363520375 ps
CPU time 3.16 seconds
Started Jul 12 06:31:26 PM PDT 24
Finished Jul 12 06:31:31 PM PDT 24
Peak memory 232568 kb
Host smart-cdba48c6-df8c-4ded-a2df-d1cc892e4928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268686323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.3268686323
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.451814269
Short name T648
Test name
Test status
Simulation time 1362283036 ps
CPU time 14.06 seconds
Started Jul 12 06:31:26 PM PDT 24
Finished Jul 12 06:31:41 PM PDT 24
Peak memory 219152 kb
Host smart-2e045cad-2cbb-4a58-a441-e0f37d174c35
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=451814269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_direc
t.451814269
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.246301773
Short name T389
Test name
Test status
Simulation time 68253216068 ps
CPU time 222.44 seconds
Started Jul 12 06:31:27 PM PDT 24
Finished Jul 12 06:35:11 PM PDT 24
Peak memory 262640 kb
Host smart-25285753-1533-4a6f-9cc7-a1a6ff246e0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246301773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stress
_all.246301773
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.3663377490
Short name T614
Test name
Test status
Simulation time 1696142750 ps
CPU time 21.6 seconds
Started Jul 12 06:31:20 PM PDT 24
Finished Jul 12 06:31:44 PM PDT 24
Peak memory 216708 kb
Host smart-da29dd33-d30b-4049-b259-6100115683e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663377490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.3663377490
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.4206476661
Short name T462
Test name
Test status
Simulation time 8138809855 ps
CPU time 9.68 seconds
Started Jul 12 06:31:19 PM PDT 24
Finished Jul 12 06:31:30 PM PDT 24
Peak memory 216268 kb
Host smart-a1914f7b-d067-4beb-9481-2ad5af708809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206476661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.4206476661
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.1004986251
Short name T743
Test name
Test status
Simulation time 71591795 ps
CPU time 1.7 seconds
Started Jul 12 06:31:27 PM PDT 24
Finished Jul 12 06:31:31 PM PDT 24
Peak memory 216152 kb
Host smart-30010e68-663a-40bd-8342-c7bab63a9a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004986251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.1004986251
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.2127227082
Short name T281
Test name
Test status
Simulation time 94118503 ps
CPU time 0.74 seconds
Started Jul 12 06:31:26 PM PDT 24
Finished Jul 12 06:31:28 PM PDT 24
Peak memory 205908 kb
Host smart-de310fd5-b89b-4921-8abc-f0caddd55ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127227082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.2127227082
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.3126393170
Short name T522
Test name
Test status
Simulation time 84501125945 ps
CPU time 30.19 seconds
Started Jul 12 06:31:25 PM PDT 24
Finished Jul 12 06:31:56 PM PDT 24
Peak memory 239680 kb
Host smart-a4bb7471-715d-4ada-b858-bd444475e682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126393170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.3126393170
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.270236325
Short name T531
Test name
Test status
Simulation time 11829200 ps
CPU time 0.74 seconds
Started Jul 12 06:31:36 PM PDT 24
Finished Jul 12 06:31:38 PM PDT 24
Peak memory 205040 kb
Host smart-515839fe-7b54-4f8d-9d4b-6f1c53b68859
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270236325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.270236325
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.2511842563
Short name T485
Test name
Test status
Simulation time 74138076 ps
CPU time 3.07 seconds
Started Jul 12 06:31:24 PM PDT 24
Finished Jul 12 06:31:28 PM PDT 24
Peak memory 232520 kb
Host smart-fbf46b7c-b7f8-44e2-a54a-b3e195d0c833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511842563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.2511842563
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.3907143676
Short name T692
Test name
Test status
Simulation time 32383124 ps
CPU time 0.79 seconds
Started Jul 12 06:31:25 PM PDT 24
Finished Jul 12 06:31:27 PM PDT 24
Peak memory 205520 kb
Host smart-7ca6c6ce-8f57-48d8-87ba-51549f05ab7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907143676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.3907143676
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.474805032
Short name T795
Test name
Test status
Simulation time 2002392429 ps
CPU time 36.17 seconds
Started Jul 12 06:31:35 PM PDT 24
Finished Jul 12 06:32:12 PM PDT 24
Peak memory 254956 kb
Host smart-802cc131-316e-4517-9d9f-fc3d5e2d9efb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474805032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.474805032
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.1512918449
Short name T511
Test name
Test status
Simulation time 14053779460 ps
CPU time 29.98 seconds
Started Jul 12 06:32:08 PM PDT 24
Finished Jul 12 06:32:40 PM PDT 24
Peak memory 217428 kb
Host smart-36b7cfb9-d92f-4b85-b3f8-5ec3c7384b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512918449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.1512918449
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.1549278206
Short name T210
Test name
Test status
Simulation time 8423957845 ps
CPU time 51.97 seconds
Started Jul 12 06:31:35 PM PDT 24
Finished Jul 12 06:32:28 PM PDT 24
Peak memory 240468 kb
Host smart-bc37dbd5-1028-4531-9562-b4108e0539c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549278206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.1549278206
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.1187259086
Short name T914
Test name
Test status
Simulation time 2806906228 ps
CPU time 7.77 seconds
Started Jul 12 06:31:35 PM PDT 24
Finished Jul 12 06:31:44 PM PDT 24
Peak memory 233680 kb
Host smart-a9ea590c-5a73-4f80-b801-411fb52d6107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187259086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.1187259086
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.2694773415
Short name T482
Test name
Test status
Simulation time 46386584560 ps
CPU time 213.05 seconds
Started Jul 12 06:31:35 PM PDT 24
Finished Jul 12 06:35:09 PM PDT 24
Peak memory 261168 kb
Host smart-cc8f50d5-d6db-4e9b-9389-957c70438a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694773415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds
.2694773415
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.3231224705
Short name T969
Test name
Test status
Simulation time 794344748 ps
CPU time 5.02 seconds
Started Jul 12 06:31:27 PM PDT 24
Finished Jul 12 06:31:34 PM PDT 24
Peak memory 224352 kb
Host smart-6ac6f0f8-8762-40cc-b1ce-e015d6056725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231224705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.3231224705
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.4067393498
Short name T802
Test name
Test status
Simulation time 11011390494 ps
CPU time 18.44 seconds
Started Jul 12 06:31:25 PM PDT 24
Finished Jul 12 06:31:45 PM PDT 24
Peak memory 249120 kb
Host smart-f5949db5-2198-442d-a415-6637901c3f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067393498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.4067393498
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.2059090812
Short name T15
Test name
Test status
Simulation time 1181165047 ps
CPU time 9.14 seconds
Started Jul 12 06:31:28 PM PDT 24
Finished Jul 12 06:31:39 PM PDT 24
Peak memory 224436 kb
Host smart-eddebc09-6cda-4c9a-9f14-5e57b1953593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059090812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.2059090812
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.3704795491
Short name T455
Test name
Test status
Simulation time 9360035622 ps
CPU time 9.24 seconds
Started Jul 12 06:31:27 PM PDT 24
Finished Jul 12 06:31:38 PM PDT 24
Peak memory 232676 kb
Host smart-fe260c28-1932-44e7-ab12-7380753722d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704795491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.3704795491
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.640169433
Short name T299
Test name
Test status
Simulation time 969602090 ps
CPU time 10.25 seconds
Started Jul 12 06:31:39 PM PDT 24
Finished Jul 12 06:31:50 PM PDT 24
Peak memory 221948 kb
Host smart-d4a0b936-9020-4f8a-b0ba-be1079ebedc5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=640169433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_direc
t.640169433
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.1827305408
Short name T948
Test name
Test status
Simulation time 10805755738 ps
CPU time 93.23 seconds
Started Jul 12 06:31:36 PM PDT 24
Finished Jul 12 06:33:10 PM PDT 24
Peak memory 249228 kb
Host smart-40896a91-34a8-4591-9bd7-545431543b7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827305408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.1827305408
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.1710509634
Short name T862
Test name
Test status
Simulation time 134638176 ps
CPU time 3.27 seconds
Started Jul 12 06:31:28 PM PDT 24
Finished Jul 12 06:31:33 PM PDT 24
Peak memory 216152 kb
Host smart-c306d657-d4dd-4e48-876a-f9105d43b1e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710509634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.1710509634
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.786890199
Short name T406
Test name
Test status
Simulation time 5897556499 ps
CPU time 18.83 seconds
Started Jul 12 06:31:28 PM PDT 24
Finished Jul 12 06:31:49 PM PDT 24
Peak memory 216288 kb
Host smart-2c8779c3-23b7-4468-b04f-28b692154d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786890199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.786890199
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.2509599792
Short name T874
Test name
Test status
Simulation time 773946435 ps
CPU time 5.22 seconds
Started Jul 12 06:31:26 PM PDT 24
Finished Jul 12 06:31:33 PM PDT 24
Peak memory 216176 kb
Host smart-16bfa257-f6e0-4b7b-b65c-32d9fff4f5ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509599792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.2509599792
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.1061771187
Short name T612
Test name
Test status
Simulation time 92803485 ps
CPU time 0.88 seconds
Started Jul 12 06:31:29 PM PDT 24
Finished Jul 12 06:31:31 PM PDT 24
Peak memory 205956 kb
Host smart-9236334b-297a-4ddd-ae2b-af7d04bd15c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061771187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.1061771187
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.1935699684
Short name T542
Test name
Test status
Simulation time 8378498590 ps
CPU time 14.44 seconds
Started Jul 12 06:31:27 PM PDT 24
Finished Jul 12 06:31:43 PM PDT 24
Peak memory 232688 kb
Host smart-a91c069c-b1dd-438c-b4ff-ae109b7a1503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935699684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.1935699684
Directory /workspace/9.spi_device_upload/latest
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