Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2858037	1			T2	1		T4	1		T5	1
all_values[1]	2858037	1			T2	1		T4	1		T5	1
all_values[2]	2858037	1			T2	1		T4	1		T5	1
all_values[3]	2858037	1			T2	1		T4	1		T5	1
all_values[4]	2858037	1			T2	1		T4	1		T5	1
all_values[5]	2858037	1			T2	1		T4	1		T5	1
all_values[6]	2858037	1			T2	1		T4	1		T5	1
all_values[7]	2858037	1			T2	1		T4	1		T5	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21636609

1

T2

8

T4

8

T5

8

auto[1]

1227687

1

T14

2686

T49

304206

T15

69

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22836544

1

T2

8

T4

8

T5

8

auto[1]

27752

1

T33

38

T36

204

T14

26

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2648300	1			T2	1		T4	1		T5	1
all_values[0]	auto[0]	auto[1]	13037	1			T33	19		T36	115		T14	4
all_values[0]	auto[1]	auto[0]	195968	1			T14	1335		T49	60718		T15	6
all_values[0]	auto[1]	auto[1]	732	1			T49	118		T15	7		T17	1
all_values[1]	auto[0]	auto[0]	2669960	1			T2	1		T4	1		T5	1
all_values[1]	auto[0]	auto[1]	7911	1			T33	19		T36	67		T14	1
all_values[1]	auto[1]	auto[0]	179434	1			T14	1336		T49	2		T15	3
all_values[1]	auto[1]	auto[1]	732	1			T14	3		T49	2		T15	5
all_values[2]	auto[0]	auto[0]	2656343	1			T2	1		T4	1		T5	1
all_values[2]	auto[0]	auto[1]	3015	1			T36	22		T14	1		T39	45
all_values[2]	auto[1]	auto[0]	198295	1			T49	60763		T15	9		T17	1
all_values[2]	auto[1]	auto[1]	384	1			T14	1		T49	77		T15	1
all_values[3]	auto[0]	auto[0]	2643252	1			T2	1		T4	1		T5	1
all_values[3]	auto[0]	auto[1]	181	1			T14	2		T49	5		T15	6
all_values[3]	auto[1]	auto[0]	214380	1			T49	60832		T15	6		T17	1
all_values[3]	auto[1]	auto[1]	224	1			T14	3		T49	6		T15	3
all_values[4]	auto[0]	auto[0]	2741486	1			T2	1		T4	1		T5	1
all_values[4]	auto[0]	auto[1]	207	1			T14	2		T49	4		T15	3
all_values[4]	auto[1]	auto[0]	116156	1			T49	2		T15	2		T17	2
all_values[4]	auto[1]	auto[1]	188	1			T49	4		T15	4		T18	3
all_values[5]	auto[0]	auto[0]	2752744	1			T2	1		T4	1		T5	1
all_values[5]	auto[0]	auto[1]	173	1			T14	4		T49	4		T15	6
all_values[5]	auto[1]	auto[0]	104964	1			T49	60834		T15	7		T17	4
all_values[5]	auto[1]	auto[1]	156	1			T14	1		T49	6		T17	1
all_values[6]	auto[0]	auto[0]	2689243	1			T2	1		T4	1		T5	1
all_values[6]	auto[0]	auto[1]	187	1			T14	1		T49	1		T15	5
all_values[6]	auto[1]	auto[0]	168415	1			T14	3		T49	60834		T15	1
all_values[6]	auto[1]	auto[1]	192	1			T49	2		T15	4		T18	1
all_values[7]	auto[0]	auto[0]	2810334	1			T2	1		T4	1		T5	1
all_values[7]	auto[0]	auto[1]	236	1			T14	3		T49	7		T15	4
all_values[7]	auto[1]	auto[0]	47270	1			T14	4		T49	2		T15	5
all_values[7]	auto[1]	auto[1]	197	1			T49	4		T15	6		T18	3