Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	33855	1			T5	2		T6	12		T9	263
auto[SpiFlashAddrCfg]	7659	1			T4	4		T6	10		T9	30
auto[SpiFlashAddr3b]	9209	1			T4	2		T9	27		T10	68
auto[SpiFlashAddr4b]	7627	1			T2	2		T6	2		T9	19

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33055

1

T2

2

T4

6

T5

2

auto[1]

25295

1

T9

163

T10

154

T33

28

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30724

1

T2

2

T4

4

T5

2

auto[1]

27626

1

T4

2

T6

6

T9

199

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	38523	1			T5	2		T6	10		T9	268
values[1]	1089	1			T6	2		T9	1		T10	8
values[2]	1390	1			T6	2		T9	3		T10	12
values[3]	1422	1			T9	6		T10	9		T12	2
values[4]	1426	1			T4	4		T9	7		T10	16
values[5]	1498	1			T9	6		T10	6		T33	1
values[6]	1467	1			T9	4		T10	10		T36	4
values[7]	1434	1			T9	9		T10	9		T43	1
values[8]	10101	1			T2	2		T4	2		T6	10

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29950

1

T2

2

T4

6

T5

2

auto[1]

28400

1

T9

339

T33

57

T36

109

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

54975

1

T2

2

T4

6

T5

2

write

3375

1

T9

12

T10

24

T12

4

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

19164

1

T2

2

T4

4

T5

2

valids[0x1]

39186

1

T4

2

T6

14

T9

271

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1543	1			T6	2		T9	5		T10	11
internal_process_ops[0x5a]	1544	1			T4	2		T9	4		T10	7
internal_process_ops[0x05]	20020	1			T6	4		T9	201		T10	129
internal_process_ops[0x35]	1596	1			T2	2		T6	2		T9	8
internal_process_ops[0x15]	1611	1			T6	2		T9	5		T10	12
internal_process_ops[0x03]	1143	1			T9	3		T10	11		T13	4
internal_process_ops[0x0b]	1063	1			T9	2		T10	16		T43	2
internal_process_ops[0x3b]	1041	1			T6	2		T9	3		T10	10
internal_process_ops[0x6b]	1018	1			T9	4		T10	9		T12	2
internal_process_ops[0xbb]	1043	1			T4	4		T9	2		T10	6
internal_process_ops[0xeb]	1049	1			T6	4		T9	1		T10	10

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

56640

1

T2

2

T4

6

T5

2

auto[1]

1710

1

T9

5

T10

18

T33

6

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

56079

1

T2

2

T4

6

T5

2

auto[1]

2271

1

T9

9

T10

6

T33

4

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10350

1

T5

2

T6

12

T10

148

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

5755

1

T10

66

T47

3

T14

125

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2064

1

T4

4

T6

10

T10

33

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1767

1

T10

17

T47

1

T14

20

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2455

1

T4

2

T10

33

T12

8

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2121

1

T10

28

T47

5

T14

20

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1975

1

T2

2

T6

2

T10

20

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1880

1

T10

30

T47

4

T14

18

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

97

1

T47

1

T14

2

T23

5

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

79

1

T14

3

T23

1

T51

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

78

1

T10

1

T52

1

T53

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

107

1

T10

2

T14

3

T51

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

129

1

T10

3

T47

2

T23

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

95

1

T10

3

T51

4

T52

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

79

1

T10

1

T14

1

T52

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

124

1

T10

3

T23

1

T49

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

124

1

T10

1

T12

4

T44

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

112

1

T10

4

T49

1

T52

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

79

1

T14

2

T23

1

T49

5

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

104

1

T10

2

T14

1

T25

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

97

1

T44

2

T14

2

T23

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

84

1

T14

5

T49

1

T18

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

101

1

T47

1

T23

1

T51

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

94

1

T10

4

T14

2

T27

2

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9576

1

T9

134

T33

16

T36

37

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7391

1

T9

123

T33

13

T36

14

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1521

1

T9

11

T33

2

T36

4

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1430

1

T9

19

T36

4

T43

6

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1915

1

T9

15

T33

3

T36

8

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1853

1

T9

8

T33

7

T36

15

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1514

1

T9

9

T33

8

T36

10

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1408

1

T9

8

T36

7

T43

7

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

109

1

T39

3

T102

1

T93

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

104

1

T9

2

T26

5

T39

5

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

95

1

T9

3

T43

1

T26

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

114

1

T9

1

T43

1

T39

5

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

125

1

T93

6

T168

1

T169

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

115

1

T26

1

T39

3

T93

4

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

103

1

T43

1

T39

2

T94

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

107

1

T33

2

T43

2

T39

6

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

89

1

T9

3

T26

1

T39

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

111

1

T36

1

T39

2

T93

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

110

1

T36

4

T43

2

T26

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

136

1

T9

1

T33

2

T43

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

115

1

T9

1

T43

2

T102

4

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

100

1

T9

1

T36

1

T26

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

135

1

T33

2

T36

2

T102

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

124

1

T33

2

T36

2

T43

2

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3782	1			T5	2		T10	44		T50	6
auto[0]	values[0]	valids[0x1]	15062	1			T6	10		T10	211		T12	4
auto[0]	values[1]	valids[0x1]	545	1			T6	2		T10	8		T14	8
auto[0]	values[2]	valids[0x0]	463	1			T6	2		T10	4		T44	2
auto[0]	values[2]	valids[0x1]	329	1			T10	8		T14	3		T23	1
auto[0]	values[3]	valids[0x0]	518	1			T10	7		T12	2		T45	6
auto[0]	values[3]	valids[0x1]	316	1			T10	2		T99	2		T14	3
auto[0]	values[4]	valids[0x0]	526	1			T4	4		T10	7		T12	4
auto[0]	values[4]	valids[0x1]	274	1			T10	9		T51	1		T49	6
auto[0]	values[5]	valids[0x0]	552	1			T10	5		T14	3		T23	4
auto[0]	values[5]	valids[0x1]	281	1			T10	1		T14	3		T23	2
auto[0]	values[6]	valids[0x0]	567	1			T10	9		T45	4		T14	4
auto[0]	values[6]	valids[0x1]	263	1			T10	1		T14	7		T49	4
auto[0]	values[7]	valids[0x0]	470	1			T10	5		T14	15		T23	5
auto[0]	values[7]	valids[0x1]	290	1			T10	4		T14	2		T23	3
auto[0]	values[8]	valids[0x0]	3567	1			T2	2		T6	8		T10	47
auto[0]	values[8]	valids[0x1]	2145	1			T4	2		T6	2		T10	27
auto[1]	values[0]	valids[0x0]	3832	1			T9	29		T33	9		T36	26
auto[1]	values[0]	valids[0x1]	15847	1			T9	239		T33	32		T36	46
auto[1]	values[1]	valids[0x1]	544	1			T9	1		T36	1		T43	1
auto[1]	values[2]	valids[0x0]	365	1			T9	3		T33	1		T36	2
auto[1]	values[2]	valids[0x1]	233	1			T43	1		T26	2		T39	5
auto[1]	values[3]	valids[0x0]	347	1			T9	5		T33	2		T43	1
auto[1]	values[3]	valids[0x1]	241	1			T9	1		T26	2		T39	1
auto[1]	values[4]	valids[0x0]	379	1			T9	5		T33	5		T93	2
auto[1]	values[4]	valids[0x1]	247	1			T9	2		T43	2		T26	2
auto[1]	values[5]	valids[0x0]	406	1			T9	3		T36	4		T43	4
auto[1]	values[5]	valids[0x1]	259	1			T9	3		T33	1		T36	1
auto[1]	values[6]	valids[0x0]	357	1			T9	2		T36	1		T43	2
auto[1]	values[6]	valids[0x1]	280	1			T9	2		T36	3		T26	1
auto[1]	values[7]	valids[0x0]	390	1			T9	5		T43	1		T26	1
auto[1]	values[7]	valids[0x1]	284	1			T9	4		T26	6		T39	1
auto[1]	values[8]	valids[0x0]	2643	1			T9	16		T33	4		T36	13
auto[1]	values[8]	valids[0x1]	1746	1			T9	19		T33	3		T36	12