Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3205936

1

T2

791

T4

477

T5

1

auto[1]

32040

1

T9

199

T10

119

T33

17

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

801668

1

T2

791

T4

477

T5

1

auto[1]

2436308

1

T6

7216

T9

5143

T10

40526

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	575263	1			T2	371		T4	165		T6	7217
auto[524288:1048575]	365217	1			T2	397		T10	6892		T13	246
auto[1048576:1572863]	365581	1			T2	17		T9	559		T10	11515
auto[1572864:2097151]	375570	1			T4	2		T5	1		T9	329
auto[2097152:2621439]	420953	1			T4	154		T10	2539		T50	12
auto[2621440:3145727]	383228	1			T4	1		T9	261		T10	2193
auto[3145728:3670015]	389676	1			T2	6		T9	607		T10	262
auto[3670016:4194303]	362488	1			T4	155		T9	3039		T10	10954

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2466605

1

T2

18

T4

6

T5

1

auto[1]

771371

1

T2

773

T4

471

T9

3

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2770793

1

T2

791

T4

477

T6

7217

auto[1]

467183

1

T5

1

T9

40

T10

2751

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	154004	1			T2	371		T4	165		T6	1
auto[0]	auto[0]	auto[0:524287]	auto[1]	354378	1			T6	7216		T9	384		T10	3476
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	84175	1			T2	397		T10	6		T13	127
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	209758	1			T10	6886		T13	119		T47	5
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	110491	1			T2	17		T9	3		T10	22
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	211502	1			T9	514		T10	11436		T13	642
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	75775	1			T4	2		T9	6		T10	2
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	222981	1			T9	306		T33	267		T14	4
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	79050	1			T4	154		T10	1		T50	12
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	276981	1			T10	2538		T33	2		T36	134
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	89348	1			T4	1		T9	5		T10	3
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	228770	1			T9	256		T10	2190		T36	133
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	115632	1			T2	6		T9	7		T10	2
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	214407	1			T9	515		T10	260		T13	7
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	83602	1			T4	155		T9	4		T10	8
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	232310	1			T9	2972		T10	10897		T13	10
auto[0]	auto[1]	auto[0:524287]	auto[0]	789	1			T9	2		T10	4		T14	1
auto[0]	auto[1]	auto[0:524287]	auto[1]	62695	1			T9	4		T10	2730		T14	663
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	671	1			T23	9		T26	8		T39	1
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	66585	1			T36	512		T14	256		T23	518
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	535	1			T10	2		T55	21		T36	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	39119	1			T36	256		T23	738		T39	262
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	1637	1			T5	1		T33	1		T36	3
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	69873	1			T33	109		T36	2		T43	1939
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	588	1			T36	4		T43	2		T14	6
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	60000	1			T36	1027		T43	129		T14	2
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	654	1			T14	8		T25	4		T102	8
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	61347	1			T43	256		T14	1		T25	512
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	484	1			T9	5		T55	2		T43	7
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	55987	1			T9	1		T43	898		T26	384
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	519	1			T9	1		T43	2		T23	1
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	41289	1			T9	1		T43	128		T93	1195
auto[1]	auto[0]	auto[0:524287]	auto[0]	395	1			T43	5		T14	1		T39	2
auto[1]	auto[0]	auto[0:524287]	auto[1]	2571	1			T43	17		T14	4		T39	4
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	386	1			T26	7		T51	2		T102	18
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	3327	1			T51	10		T102	326		T52	2
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	353	1			T9	2		T10	3		T36	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2791	1			T9	40		T10	52		T14	4
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	374	1			T9	1		T33	2		T14	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	4550	1			T9	16		T33	4		T14	11
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	475	1			T33	2		T36	1		T43	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	3249	1			T33	9		T14	5		T39	3
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	363	1			T36	1		T43	3		T14	2
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2027	1			T36	1		T43	29		T14	24
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	382	1			T9	3		T36	1		T26	7
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2338	1			T9	72		T39	1		T51	3
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	344	1			T9	1		T10	2		T36	3
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	3704	1			T9	38		T10	47		T36	1
auto[1]	auto[1]	auto[0:524287]	auto[0]	71	1			T10	1		T39	1		T93	7
auto[1]	auto[1]	auto[0:524287]	auto[1]	360	1			T10	14		T212	1		T206	3
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	67	1			T23	1		T93	4		T94	8
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	248	1			T23	1		T40	2		T20	20
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	65	1			T23	1		T39	1		T93	4
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	725	1			T23	1		T39	8		T93	280
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	66	1			T49	1		T168	1		T180	6
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	314	1			T49	8		T168	5		T180	13
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	75	1			T43	1		T14	2		T25	2
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	535	1			T43	8		T14	26		T25	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	112	1			T14	1		T93	16		T168	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	607	1			T14	1		T168	1		T186	3
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	87	1			T9	1		T43	2		T93	2
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	359	1			T9	3		T43	37		T40	17
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	99	1			T9	1		T26	6		T93	34
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	621	1			T9	21		T93	256		T168	3

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1973779	1			T2	18		T4	6		T6	7217
auto[0]	auto[0]	auto[1]	769385	1			T2	773		T4	471		T9	1
auto[0]	auto[1]	auto[0]	461402	1			T5	1		T9	12		T10	2736
auto[0]	auto[1]	auto[1]	1370	1			T9	2		T55	3		T14	1
auto[1]	auto[0]	auto[0]	27120	1			T9	173		T10	104		T33	17
auto[1]	auto[0]	auto[1]	509	1			T43	5		T14	5		T26	4
auto[1]	auto[1]	auto[0]	4304	1			T9	26		T10	15		T43	47
auto[1]	auto[1]	auto[1]	107	1			T43	1		T14	3		T23	1