Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2858037	1			T2	1		T4	1		T5	1
all_pins[1]	2858037	1			T2	1		T4	1		T5	1
all_pins[2]	2858037	1			T2	1		T4	1		T5	1
all_pins[3]	2858037	1			T2	1		T4	1		T5	1
all_pins[4]	2858037	1			T2	1		T4	1		T5	1
all_pins[5]	2858037	1			T2	1		T4	1		T5	1
all_pins[6]	2858037	1			T2	1		T4	1		T5	1
all_pins[7]	2858037	1			T2	1		T4	1		T5	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	22692119	1			T2	8		T4	8		T5	8
values[0x1]	172177	1			T14	8		T49	61229		T15	30
transitions[0x0=>0x1]	170588	1			T14	7		T49	61002		T15	19
transitions[0x1=>0x0]	170608	1			T14	7		T49	61002		T15	19

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2857252	1			T2	1		T4	1		T5	1
all_pins[0]	values[0x1]	785	1			T49	130		T15	7		T17	1
all_pins[0]	transitions[0x0=>0x1]	487	1			T49	130		T15	4		T17	1
all_pins[0]	transitions[0x1=>0x0]	494	1			T14	3		T49	2		T15	2
all_pins[1]	values[0x0]	2857245	1			T2	1		T4	1		T5	1
all_pins[1]	values[0x1]	792	1			T14	3		T49	2		T15	5
all_pins[1]	transitions[0x0=>0x1]	641	1			T14	3		T49	2		T15	4
all_pins[1]	transitions[0x1=>0x0]	252	1			T14	1		T49	82		T18	46
all_pins[2]	values[0x0]	2857634	1			T2	1		T4	1		T5	1
all_pins[2]	values[0x1]	403	1			T14	1		T49	82		T15	1
all_pins[2]	transitions[0x0=>0x1]	345	1			T49	82		T18	44		T19	2
all_pins[2]	transitions[0x1=>0x0]	166	1			T14	2		T49	6		T15	2
all_pins[3]	values[0x0]	2857813	1			T2	1		T4	1		T5	1
all_pins[3]	values[0x1]	224	1			T14	3		T49	6		T15	3
all_pins[3]	transitions[0x0=>0x1]	160	1			T14	3		T49	5		T15	2
all_pins[3]	transitions[0x1=>0x0]	124	1			T49	3		T15	3		T19	4
all_pins[4]	values[0x0]	2857849	1			T2	1		T4	1		T5	1
all_pins[4]	values[0x1]	188	1			T49	4		T15	4		T18	3
all_pins[4]	transitions[0x0=>0x1]	158	1			T49	3		T15	4		T18	3
all_pins[4]	transitions[0x1=>0x0]	1495	1			T14	1		T49	233		T17	1
all_pins[5]	values[0x0]	2856512	1			T2	1		T4	1		T5	1
all_pins[5]	values[0x1]	1525	1			T14	1		T49	234		T17	1
all_pins[5]	transitions[0x0=>0x1]	655	1			T14	1		T49	9		T17	1
all_pins[5]	transitions[0x1=>0x0]	167193	1			T49	60542		T15	4		T18	1
all_pins[6]	values[0x0]	2689974	1			T2	1		T4	1		T5	1
all_pins[6]	values[0x1]	168063	1			T49	60767		T15	4		T18	1
all_pins[6]	transitions[0x0=>0x1]	168002	1			T49	60767		T15	1		T18	1
all_pins[6]	transitions[0x1=>0x0]	136	1			T49	4		T15	3		T18	3
all_pins[7]	values[0x0]	2857840	1			T2	1		T4	1		T5	1
all_pins[7]	values[0x1]	197	1			T49	4		T15	6		T18	3
all_pins[7]	transitions[0x0=>0x1]	140	1			T49	4		T15	4		T18	2
all_pins[7]	transitions[0x1=>0x0]	748	1			T49	130		T15	5		T17	1