Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17661

1

T2

2

T4

6

T5

2

auto[1]

12289

1

T10

154

T47

14

T14

192

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4596	1			T6	24		T12	16		T50	6
values[1]	3527	1			T5	2		T13	16		T14	22
values[2]	3934	1			T10	93		T14	20		T23	62
values[3]	3592	1			T2	2		T10	80		T99	2
values[4]	3841	1			T10	77		T47	20		T51	24
values[5]	3684	1			T4	6		T44	14		T55	16
values[6]	3373	1			T10	60		T45	20		T14	49
values[7]	3403	1			T10	89		T14	20		T25	20

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3344	1			T10	60		T55	16		T14	20
values[1]	3811	1			T2	2		T5	2		T10	107
values[2]	4139	1			T10	80		T13	16		T14	26
values[3]	2970	1			T12	16		T45	20		T29	14
values[4]	3253	1			T4	6		T10	57		T44	14
values[5]	3782	1			T6	24		T10	40		T50	6
values[6]	4840	1			T10	20		T14	69		T23	22
values[7]	3811	1			T10	35		T99	2		T47	20

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	251	1			T23	12		T54	8		T18	8
auto[0]	values[0]	values[1]	420	1			T18	11		T196	14		T225	13
auto[0]	values[0]	values[2]	486	1			T226	4		T227	2		T212	13
auto[0]	values[0]	values[3]	243	1			T12	16		T101	14		T40	27
auto[0]	values[0]	values[4]	258	1			T14	13		T23	9		T40	13
auto[0]	values[0]	values[5]	252	1			T6	24		T50	6		T14	13
auto[0]	values[0]	values[6]	764	1			T49	9		T52	8		T54	12
auto[0]	values[0]	values[7]	225	1			T104	4		T52	9		T228	10
auto[0]	values[1]	values[0]	308	1			T23	9		T25	13		T54	9
auto[0]	values[1]	values[1]	189	1			T5	2		T14	13		T49	12
auto[0]	values[1]	values[2]	274	1			T13	16		T18	8		T95	13
auto[0]	values[1]	values[3]	214	1			T214	12		T186	24		T21	9
auto[0]	values[1]	values[4]	197	1			T52	12		T204	10		T212	13
auto[0]	values[1]	values[5]	370	1			T51	13		T229	6		T21	33
auto[0]	values[1]	values[6]	146	1			T230	6		T182	8		T187	49
auto[0]	values[1]	values[7]	234	1			T95	15		T88	8		T196	15
auto[0]	values[2]	values[0]	234	1			T217	5		T37	14		T225	37
auto[0]	values[2]	values[1]	267	1			T10	66		T52	12		T191	8
auto[0]	values[2]	values[2]	330	1			T52	9		T231	145		T218	12
auto[0]	values[2]	values[3]	281	1			T29	14		T232	6		T37	16
auto[0]	values[2]	values[4]	137	1			T14	14		T23	39		T233	12
auto[0]	values[2]	values[5]	333	1			T10	16		T21	12		T183	8
auto[0]	values[2]	values[6]	350	1			T234	2		T21	118		T187	16
auto[0]	values[2]	values[7]	400	1			T51	12		T186	18		T192	12
auto[0]	values[3]	values[0]	238	1			T14	12		T235	2		T236	11
auto[0]	values[3]	values[1]	188	1			T2	2		T52	14		T37	8
auto[0]	values[3]	values[2]	346	1			T10	26		T193	8		T54	7
auto[0]	values[3]	values[3]	191	1			T237	6		T238	8		T53	13
auto[0]	values[3]	values[4]	113	1			T239	2		T240	6		T18	11
auto[0]	values[3]	values[5]	377	1			T10	8		T51	28		T54	15
auto[0]	values[3]	values[6]	281	1			T10	10		T100	12		T53	13
auto[0]	values[3]	values[7]	335	1			T99	2		T49	25		T95	18
auto[0]	values[4]	values[0]	252	1			T10	15		T49	10		T218	13
auto[0]	values[4]	values[1]	263	1			T49	14		T241	14		T53	10
auto[0]	values[4]	values[2]	296	1			T51	12		T212	13		T40	12
auto[0]	values[4]	values[3]	233	1			T21	18		T183	14		T242	102
auto[0]	values[4]	values[4]	354	1			T10	11		T243	26		T40	8
auto[0]	values[4]	values[5]	210	1			T216	4		T52	12		T18	13
auto[0]	values[4]	values[6]	271	1			T95	6		T21	12		T37	10
auto[0]	values[4]	values[7]	348	1			T47	6		T18	12		T218	77
auto[0]	values[5]	values[0]	303	1			T55	16		T51	11		T191	16
auto[0]	values[5]	values[1]	234	1			T14	14		T24	14		T186	12
auto[0]	values[5]	values[2]	180	1			T14	10		T49	11		T187	22
auto[0]	values[5]	values[3]	199	1			T21	22		T200	17		T242	12
auto[0]	values[5]	values[4]	460	1			T4	6		T44	14		T14	11
auto[0]	values[5]	values[5]	87	1			T205	10		T244	4		T245	9
auto[0]	values[5]	values[6]	317	1			T23	12		T40	12		T21	13
auto[0]	values[5]	values[7]	284	1			T23	12		T187	37		T188	10
auto[0]	values[6]	values[0]	187	1			T10	14		T48	24		T197	20
auto[0]	values[6]	values[1]	240	1			T214	38		T18	17		T95	17
auto[0]	values[6]	values[2]	187	1			T10	23		T49	7		T188	5
auto[0]	values[6]	values[3]	333	1			T45	20		T192	83		T187	28
auto[0]	values[6]	values[4]	232	1			T203	16		T49	32		T21	5
auto[0]	values[6]	values[5]	325	1			T25	12		T103	10		T40	36
auto[0]	values[6]	values[6]	331	1			T14	42		T52	10		T53	7
auto[0]	values[6]	values[7]	174	1			T212	11		T219	12		T246	16
auto[0]	values[7]	values[0]	190	1			T10	9		T49	12		T199	5
auto[0]	values[7]	values[1]	295	1			T10	26		T25	8		T49	14
auto[0]	values[7]	values[2]	337	1			T211	14		T95	15		T247	27
auto[0]	values[7]	values[3]	66	1			T53	12		T248	4		T196	6
auto[0]	values[7]	values[4]	201	1			T217	13		T196	13		T194	7
auto[0]	values[7]	values[5]	298	1			T218	14		T21	10		T37	7
auto[0]	values[7]	values[6]	489	1			T14	9		T249	8		T53	8
auto[0]	values[7]	values[7]	253	1			T10	21		T191	11		T95	14
auto[1]	values[0]	values[0]	178	1			T23	8		T54	12		T18	12
auto[1]	values[0]	values[1]	133	1			T18	9		T196	6		T225	7
auto[1]	values[0]	values[2]	230	1			T212	9		T18	8		T40	4
auto[1]	values[0]	values[3]	174	1			T40	23		T218	8		T250	18
auto[1]	values[0]	values[4]	224	1			T14	66		T23	12		T40	7
auto[1]	values[0]	values[5]	116	1			T14	7		T186	8		T21	12
auto[1]	values[0]	values[6]	365	1			T49	11		T52	12		T54	8
auto[1]	values[0]	values[7]	277	1			T52	11		T212	13		T242	7
auto[1]	values[1]	values[0]	180	1			T23	11		T25	10		T54	11
auto[1]	values[1]	values[1]	306	1			T14	9		T49	8		T218	6
auto[1]	values[1]	values[2]	178	1			T18	15		T95	28		T192	9
auto[1]	values[1]	values[3]	301	1			T214	8		T186	6		T21	57
auto[1]	values[1]	values[4]	96	1			T52	8		T212	9		T89	9
auto[1]	values[1]	values[5]	288	1			T51	7		T21	7		T183	11
auto[1]	values[1]	values[6]	141	1			T187	10		T138	10		T251	85
auto[1]	values[1]	values[7]	105	1			T95	5		T196	25		T198	12
auto[1]	values[2]	values[0]	154	1			T217	15		T37	6		T225	9
auto[1]	values[2]	values[1]	188	1			T10	7		T52	8		T191	12
auto[1]	values[2]	values[2]	216	1			T52	11		T218	11		T215	18
auto[1]	values[2]	values[3]	232	1			T37	7		T198	9		T252	10
auto[1]	values[2]	values[4]	76	1			T14	6		T23	23		T253	7
auto[1]	values[2]	values[5]	278	1			T10	4		T27	8		T21	16
auto[1]	values[2]	values[6]	206	1			T21	11		T187	8		T252	8
auto[1]	values[2]	values[7]	252	1			T51	8		T186	3		T192	9
auto[1]	values[3]	values[0]	259	1			T14	8		T236	47		T254	11
auto[1]	values[3]	values[1]	145	1			T52	6		T37	12		T187	8
auto[1]	values[3]	values[2]	266	1			T10	14		T54	13		T217	8
auto[1]	values[3]	values[3]	124	1			T53	7		T95	5		T186	8
auto[1]	values[3]	values[4]	97	1			T18	9		T183	22		T255	10
auto[1]	values[3]	values[5]	182	1			T10	12		T51	10		T54	5
auto[1]	values[3]	values[6]	212	1			T10	10		T53	7		T199	9
auto[1]	values[3]	values[7]	238	1			T49	17		T95	7		T21	23
auto[1]	values[4]	values[0]	171	1			T10	5		T49	33		T218	7
auto[1]	values[4]	values[1]	303	1			T49	16		T53	28		T192	6
auto[1]	values[4]	values[2]	240	1			T51	12		T212	7		T40	11
auto[1]	values[4]	values[3]	125	1			T21	10		T183	6		T256	22
auto[1]	values[4]	values[4]	205	1			T10	46		T40	12		T192	16
auto[1]	values[4]	values[5]	197	1			T52	8		T18	14		T95	21
auto[1]	values[4]	values[6]	204	1			T95	18		T21	8		T37	10
auto[1]	values[4]	values[7]	169	1			T47	14		T18	8		T218	12
auto[1]	values[5]	values[0]	205	1			T51	10		T66	20		T191	4
auto[1]	values[5]	values[1]	266	1			T14	48		T186	9		T192	13
auto[1]	values[5]	values[2]	163	1			T14	16		T49	9		T187	18
auto[1]	values[5]	values[3]	143	1			T21	5		T200	5		T242	34
auto[1]	values[5]	values[4]	262	1			T14	14		T49	8		T52	4
auto[1]	values[5]	values[5]	105	1			T245	11		T189	9		T257	8
auto[1]	values[5]	values[6]	285	1			T23	10		T69	2		T40	18
auto[1]	values[5]	values[7]	191	1			T23	8		T187	12		T188	10
auto[1]	values[6]	values[0]	117	1			T10	6		T40	18		T186	9
auto[1]	values[6]	values[1]	207	1			T214	9		T18	8		T95	19
auto[1]	values[6]	values[2]	189	1			T10	17		T49	13		T188	20
auto[1]	values[6]	values[3]	71	1			T187	9		T252	9		T165	6
auto[1]	values[6]	values[4]	181	1			T49	10		T21	60		T89	7
auto[1]	values[6]	values[5]	198	1			T25	8		T258	4		T40	11
auto[1]	values[6]	values[6]	223	1			T14	7		T52	10		T53	28
auto[1]	values[6]	values[7]	178	1			T212	16		T195	5		T259	64
auto[1]	values[7]	values[0]	117	1			T10	11		T49	11		T199	15
auto[1]	values[7]	values[1]	167	1			T10	8		T25	12		T49	9
auto[1]	values[7]	values[2]	221	1			T95	11		T183	8		T188	7
auto[1]	values[7]	values[3]	40	1			T53	8		T196	14		T198	13
auto[1]	values[7]	values[4]	160	1			T217	7		T196	39		T194	13
auto[1]	values[7]	values[5]	166	1			T218	6		T21	34		T37	17
auto[1]	values[7]	values[6]	255	1			T14	11		T53	12		T40	4
auto[1]	values[7]	values[7]	148	1			T10	14		T191	9		T95	8