Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	410	1			T10	3		T45	4		T14	3
auto[ReadAddrCrossIntoMailbox]	248	1			T10	4		T14	1		T23	3
auto[ReadAddrCrossOutOfMailbox]	295	1			T10	7		T14	7		T23	2
auto[ReadAddrCrossAllMailbox]	232	1			T10	7		T45	4		T14	3
auto[ReadAddrOutsideMailbox]	3607	1			T4	4		T6	6		T10	41

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2410

1

T4

2

T6

3

T10

32

auto[1]

2382

1

T4

2

T6

3

T10

30

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	867	1			T10	11		T13	4		T45	6
read_ops[0x0b]	816	1			T10	16		T47	2		T45	4
read_ops[0x3b]	784	1			T6	2		T10	10		T12	4
read_ops[0x6b]	758	1			T10	9		T12	2		T44	2
read_ops[0xbb]	792	1			T4	4		T10	6		T12	2
read_ops[0xeb]	775	1			T6	4		T10	10		T14	9

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	33	1			T10	1		T100	1		T52	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	38	1			T10	1		T23	1		T100	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	38	1			T249	2		T18	1		T213	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	22	1			T23	1		T49	1		T52	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	34	1			T10	1		T14	1		T100	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	26	1			T14	1		T23	1		T25	2
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T45	2		T100	2		T52	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	21	1			T10	1		T45	2		T25	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	310	1			T10	4		T13	2		T45	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	327	1			T10	3		T13	2		T45	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	38	1			T45	2		T23	1		T100	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	33	1			T45	2		T23	1		T100	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	21	1			T52	2		T37	1		T183	2
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	16	1			T52	1		T217	1		T186	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T49	1		T212	1		T183	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T14	1		T40	1		T187	2
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	23	1			T10	2		T53	1		T187	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	25	1			T23	1		T217	1		T40	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	300	1			T10	7		T14	3		T23	3
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	314	1			T10	7		T47	2		T14	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	28	1			T25	1		T18	1		T192	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	42	1			T14	1		T49	2		T53	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	16	1			T10	3		T23	1		T192	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	17	1			T10	1		T52	1		T212	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T14	1		T40	1		T192	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	31	1			T10	1		T49	1		T54	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	14	1			T18	1		T218	1		T186	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	25	1			T53	1		T187	1		T200	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	308	1			T6	1		T10	1		T12	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	281	1			T6	1		T10	4		T12	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	30	1			T14	1		T23	2		T49	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	29	1			T18	1		T21	1		T192	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	19	1			T212	1		T188	1		T89	2
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	23	1			T14	1		T49	2		T95	2
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	18	1			T10	1		T14	1		T23	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	17	1			T10	2		T49	1		T18	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T21	1		T199	2		T225	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	26	1			T10	2		T14	1		T25	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	287	1			T10	2		T12	1		T44	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	293	1			T10	2		T12	1		T44	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	29	1			T23	1		T52	1		T204	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	37	1			T10	1		T25	1		T52	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	21	1			T23	1		T25	1		T21	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	18	1			T183	1		T196	1		T198	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T10	1		T14	1		T52	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	37	1			T10	1		T14	1		T217	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T14	1		T18	2		T217	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T10	1		T14	1		T53	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	300	1			T4	2		T10	1		T12	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	294	1			T4	2		T10	1		T12	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	38	1			T21	1		T37	1		T183	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	35	1			T14	1		T49	1		T21	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	21	1			T18	1		T40	3		T21	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	16	1			T53	1		T54	1		T212	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	26	1			T53	1		T40	1		T95	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	16	1			T49	1		T18	1		T196	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T10	1		T23	1		T52	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	12	1			T23	1		T49	1		T53	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	323	1			T6	2		T10	7		T14	3
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	270	1			T6	2		T10	2		T14	5