Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3664	1			T10	20		T14	20		T24	14
values[1]	3459	1			T10	40		T50	6		T47	20
values[2]	4181	1			T4	6		T5	2		T14	62
values[3]	3899	1			T10	107		T14	51		T23	42
values[4]	4325	1			T2	2		T10	57		T44	14
values[5]	3349	1			T10	95		T99	2		T45	20
values[6]	3100	1			T6	24		T10	60		T13	16
values[7]	3973	1			T10	20		T12	16		T104	4

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3571	1			T10	54		T14	20		T23	21
values[1]	3843	1			T2	2		T5	2		T10	20
values[2]	3567	1			T4	6		T10	20		T14	25
values[3]	3376	1			T6	24		T99	2		T14	62
values[4]	3821	1			T10	60		T55	16		T14	22
values[5]	3281	1			T12	16		T14	20		T23	20
values[6]	4318	1			T10	205		T44	14		T45	20
values[7]	4173	1			T10	40		T13	16		T47	20

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29151

1

T2

2

T4

6

T5

2

auto[1]

799

1

T10

18

T14

14

T23

2

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	374	1			T49	18		T217	20		T218	20
auto[0]	values[0]	values[1]	607	1			T53	34		T187	59		T199	31
auto[0]	values[0]	values[2]	392	1			T192	20		T188	20		T198	19
auto[0]	values[0]	values[3]	341	1			T52	20		T197	20		T228	10
auto[0]	values[0]	values[4]	555	1			T10	17		T51	19		T203	16
auto[0]	values[0]	values[5]	318	1			T24	14		T52	18		T186	25
auto[0]	values[0]	values[6]	660	1			T191	20		T239	2		T217	19
auto[0]	values[0]	values[7]	327	1			T14	20		T199	40		T260	18
auto[0]	values[1]	values[0]	513	1			T205	10		T95	35		T200	16
auto[0]	values[1]	values[1]	566	1			T50	6		T192	80		T183	19
auto[0]	values[1]	values[2]	334	1			T51	18		T191	20		T21	39
auto[0]	values[1]	values[3]	615	1			T29	14		T54	18		T18	22
auto[0]	values[1]	values[4]	299	1			T49	43		T53	20		T54	19
auto[0]	values[1]	values[5]	285	1			T52	19		T218	29		T183	20
auto[0]	values[1]	values[6]	306	1			T10	20		T241	14		T54	19
auto[0]	values[1]	values[7]	457	1			T10	20		T47	20		T53	20
auto[0]	values[2]	values[0]	689	1			T100	12		T212	24		T40	19
auto[0]	values[2]	values[1]	586	1			T5	2		T216	4		T95	26
auto[0]	values[2]	values[2]	432	1			T4	6		T40	47		T199	20
auto[0]	values[2]	values[3]	558	1			T14	62		T49	18		T232	6
auto[0]	values[2]	values[4]	523	1			T51	37		T212	27		T40	92
auto[0]	values[2]	values[5]	448	1			T235	2		T18	19		T182	8
auto[0]	values[2]	values[6]	494	1			T261	14		T210	6		T188	22
auto[0]	values[2]	values[7]	364	1			T18	20		T183	20		T187	43
auto[0]	values[3]	values[0]	270	1			T10	29		T192	20		T188	20
auto[0]	values[3]	values[1]	230	1			T14	22		T21	88		T262	20
auto[0]	values[3]	values[2]	531	1			T14	24		T23	22		T52	19
auto[0]	values[3]	values[3]	785	1			T23	19		T18	25		T40	40
auto[0]	values[3]	values[4]	368	1			T95	24		T21	27		T89	20
auto[0]	values[3]	values[5]	561	1			T49	20		T218	42		T199	20
auto[0]	values[3]	values[6]	580	1			T10	73		T53	36		T40	23
auto[0]	values[3]	values[7]	444	1			T21	47		T263	4		T37	22
auto[0]	values[4]	values[0]	488	1			T23	21		T51	17		T89	45
auto[0]	values[4]	values[1]	580	1			T2	2		T49	41		T52	18
auto[0]	values[4]	values[2]	494	1			T52	17		T21	42		T37	21
auto[0]	values[4]	values[3]	107	1			T52	20		T198	20		T264	17
auto[0]	values[4]	values[4]	565	1			T14	21		T49	23		T192	69
auto[0]	values[4]	values[5]	447	1			T25	41		T18	20		T192	20
auto[0]	values[4]	values[6]	755	1			T10	54		T44	14		T49	30
auto[0]	values[4]	values[7]	772	1			T14	18		T27	4		T226	4
auto[0]	values[5]	values[0]	300	1			T14	20		T49	21		T54	17
auto[0]	values[5]	values[1]	226	1			T103	10		T218	20		T187	31
auto[0]	values[5]	values[2]	531	1			T10	20		T51	24		T211	14
auto[0]	values[5]	values[3]	284	1			T99	2		T223	18		T217	19
auto[0]	values[5]	values[4]	350	1			T10	20		T40	20		T186	22
auto[0]	values[5]	values[5]	433	1			T14	18		T253	20		T165	26
auto[0]	values[5]	values[6]	549	1			T10	53		T45	20		T212	19
auto[0]	values[5]	values[7]	573	1			T95	72		T21	18		T265	6
auto[0]	values[6]	values[0]	299	1			T10	18		T49	21		T18	19
auto[0]	values[6]	values[1]	377	1			T10	20		T23	40		T40	48
auto[0]	values[6]	values[2]	245	1			T48	24		T238	8		T49	20
auto[0]	values[6]	values[3]	311	1			T6	24		T186	24		T248	4
auto[0]	values[6]	values[4]	422	1			T10	20		T55	16		T101	14
auto[0]	values[6]	values[5]	378	1			T49	18		T21	59		T266	4
auto[0]	values[6]	values[6]	399	1			T14	46		T186	20		T21	59
auto[0]	values[6]	values[7]	590	1			T13	16		T230	6		T234	2
auto[0]	values[7]	values[0]	529	1			T18	20		T224	24		T196	16
auto[0]	values[7]	values[1]	563	1			T104	4		T14	78		T258	4
auto[0]	values[7]	values[2]	491	1			T23	21		T49	20		T229	6
auto[0]	values[7]	values[3]	267	1			T54	20		T207	16		T194	20
auto[0]	values[7]	values[4]	660	1			T25	19		T227	2		T95	76
auto[0]	values[7]	values[5]	326	1			T12	16		T23	20		T237	6
auto[0]	values[7]	values[6]	486	1			T23	20		T52	20		T249	8
auto[0]	values[7]	values[7]	542	1			T10	17		T193	8		T53	37
auto[1]	values[0]	values[0]	10	1			T49	2		T195	2		T189	2
auto[1]	values[0]	values[1]	12	1			T53	1		T188	1		T198	2
auto[1]	values[0]	values[2]	20	1			T198	1		T253	2		T259	1
auto[1]	values[0]	values[3]	10	1			T242	2		T194	1		T267	2
auto[1]	values[0]	values[4]	15	1			T10	3		T51	2		T245	1
auto[1]	values[0]	values[5]	11	1			T52	2		T186	3		T192	2
auto[1]	values[0]	values[6]	5	1			T217	1		T189	1		T268	1
auto[1]	values[0]	values[7]	7	1			T199	3		T58	1		T269	1
auto[1]	values[1]	values[0]	15	1			T95	1		T200	4		T189	3
auto[1]	values[1]	values[1]	16	1			T192	3		T183	1		T270	2
auto[1]	values[1]	values[2]	13	1			T51	2		T187	1		T198	1
auto[1]	values[1]	values[3]	20	1			T54	2		T18	1		T21	2
auto[1]	values[1]	values[4]	7	1			T54	1		T245	1		T271	1
auto[1]	values[1]	values[5]	8	1			T52	1		T218	1		T188	3
auto[1]	values[1]	values[6]	2	1			T54	1		T272	1		-	-
auto[1]	values[1]	values[7]	3	1			T95	1		T89	1		T252	1
auto[1]	values[2]	values[0]	10	1			T40	1		T194	2		T184	1
auto[1]	values[2]	values[1]	10	1			T259	2		T257	1		T273	1
auto[1]	values[2]	values[2]	15	1			T245	1		T274	3		T138	2
auto[1]	values[2]	values[3]	17	1			T49	2		T40	2		T242	1
auto[1]	values[2]	values[4]	6	1			T51	1		T218	1		T141	1
auto[1]	values[2]	values[5]	11	1			T18	1		T242	3		T245	2
auto[1]	values[2]	values[6]	5	1			T275	1		T274	1		T276	1
auto[1]	values[2]	values[7]	13	1			T183	2		T187	6		T277	3
auto[1]	values[3]	values[0]	15	1			T10	5		T196	2		T257	1
auto[1]	values[3]	values[1]	12	1			T14	4		T21	2		T278	2
auto[1]	values[3]	values[2]	17	1			T14	1		T52	1		T275	3
auto[1]	values[3]	values[3]	35	1			T23	1		T40	1		T21	4
auto[1]	values[3]	values[4]	6	1			T21	1		T257	2		T279	1
auto[1]	values[3]	values[5]	10	1			T190	1		T280	1		T281	2
auto[1]	values[3]	values[6]	24	1			T53	4		T187	3		T252	2
auto[1]	values[3]	values[7]	11	1			T37	2		T213	1		T195	1
auto[1]	values[4]	values[0]	19	1			T51	3		T89	1		T242	1
auto[1]	values[4]	values[1]	25	1			T49	1		T52	2		T37	1
auto[1]	values[4]	values[2]	12	1			T52	3		T37	3		T245	2
auto[1]	values[4]	values[3]	3	1			T264	3		-	-		-	-
auto[1]	values[4]	values[4]	13	1			T14	1		T196	1		T236	1
auto[1]	values[4]	values[5]	13	1			T25	2		T192	1		T187	3
auto[1]	values[4]	values[6]	18	1			T10	3		T95	2		T196	2
auto[1]	values[4]	values[7]	14	1			T14	2		T27	4		T52	1
auto[1]	values[5]	values[0]	17	1			T49	2		T54	3		T95	2
auto[1]	values[5]	values[1]	5	1			T187	1		T189	2		T282	2
auto[1]	values[5]	values[2]	20	1			T95	2		T183	4		T283	2
auto[1]	values[5]	values[3]	8	1			T217	1		T95	3		T256	4
auto[1]	values[5]	values[4]	10	1			T21	1		T199	2		T200	1
auto[1]	values[5]	values[5]	9	1			T14	2		T284	1		T276	1
auto[1]	values[5]	values[6]	16	1			T10	2		T212	1		T285	2
auto[1]	values[5]	values[7]	18	1			T95	2		T21	2		T254	2
auto[1]	values[6]	values[0]	13	1			T10	2		T49	2		T18	1
auto[1]	values[6]	values[1]	9	1			T40	1		T199	2		T286	2
auto[1]	values[6]	values[2]	6	1			T37	1		T166	1		T287	1
auto[1]	values[6]	values[3]	8	1			T194	3		T165	1		T288	1
auto[1]	values[6]	values[4]	4	1			T212	1		T21	2		T289	1
auto[1]	values[6]	values[5]	16	1			T49	3		T21	5		T266	4
auto[1]	values[6]	values[6]	10	1			T14	3		T21	2		T200	1
auto[1]	values[6]	values[7]	13	1			T186	1		T21	1		T187	2
auto[1]	values[7]	values[0]	10	1			T196	4		T290	2		T272	2
auto[1]	values[7]	values[1]	19	1			T14	1		T187	1		T252	2
auto[1]	values[7]	values[2]	14	1			T23	1		T49	1		T40	2
auto[1]	values[7]	values[3]	7	1			T284	1		T291	1		T292	2
auto[1]	values[7]	values[4]	18	1			T25	1		T293	1		T294	2
auto[1]	values[7]	values[5]	7	1			T186	2		T58	2		T281	1
auto[1]	values[7]	values[6]	9	1			T196	1		T165	1		T275	2
auto[1]	values[7]	values[7]	25	1			T10	3		T53	1		T95	2