Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	813	1			T14	7		T49	17		T15	14
all_values[1]	813	1			T14	7		T49	17		T15	14
all_values[2]	813	1			T14	7		T49	17		T15	14
all_values[3]	813	1			T14	7		T49	17		T15	14
all_values[4]	813	1			T14	7		T49	17		T15	14
all_values[5]	813	1			T14	7		T49	17		T15	14
all_values[6]	813	1			T14	7		T49	17		T15	14
all_values[7]	813	1			T14	7		T49	17		T15	14

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3511

1

T14

38

T49

72

T15

67

auto[1]

2993

1

T14

18

T49

64

T15

45

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2612

1

T14

20

T49

60

T15

36

auto[1]

3892

1

T14

36

T49

76

T15

76

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3701

1

T14

29

T49

81

T15

54

auto[1]

2803

1

T14

27

T49

55

T15

58

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	165	1			T14	1		T49	1		T15	1
all_values[0]	auto[0]	auto[0]	auto[1]	81	1			T14	2		T49	3		T18	1
all_values[0]	auto[0]	auto[1]	auto[0]	164	1			T14	1		T49	6		T15	1
all_values[0]	auto[0]	auto[1]	auto[1]	73	1			T15	2		T22	3		T37	1
all_values[0]	auto[1]	auto[0]	auto[1]	183	1			T14	2		T49	4		T15	4
all_values[0]	auto[1]	auto[1]	auto[1]	147	1			T14	1		T49	3		T15	6
all_values[1]	auto[0]	auto[0]	auto[0]	168	1			T14	1		T49	7		T15	2
all_values[1]	auto[0]	auto[0]	auto[1]	86	1			T14	1		T49	2		T18	2
all_values[1]	auto[0]	auto[1]	auto[0]	128	1			T14	1		T49	2		T15	1
all_values[1]	auto[0]	auto[1]	auto[1]	88	1			T14	1		T49	2		T15	3
all_values[1]	auto[1]	auto[0]	auto[1]	177	1			T49	2		T15	4		T18	3
all_values[1]	auto[1]	auto[1]	auto[1]	166	1			T14	3		T49	2		T15	4
all_values[2]	auto[0]	auto[0]	auto[0]	169	1			T14	2		T49	4		T15	1
all_values[2]	auto[0]	auto[0]	auto[1]	70	1			T15	1		T17	1		T18	1
all_values[2]	auto[0]	auto[1]	auto[0]	144	1			T49	8		T15	5		T17	1
all_values[2]	auto[0]	auto[1]	auto[1]	73	1			T14	1		T49	2		T15	1
all_values[2]	auto[1]	auto[0]	auto[1]	207	1			T14	4		T49	1		T15	6
all_values[2]	auto[1]	auto[1]	auto[1]	150	1			T49	2		T18	2		T19	3
all_values[3]	auto[0]	auto[0]	auto[0]	154	1			T14	1		T49	2		T15	1
all_values[3]	auto[0]	auto[0]	auto[1]	69	1			T49	1		T15	2		T17	1
all_values[3]	auto[0]	auto[1]	auto[0]	136	1			T49	2		T15	1		T17	1
all_values[3]	auto[0]	auto[1]	auto[1]	77	1			T49	3		T15	1		T18	3
all_values[3]	auto[1]	auto[0]	auto[1]	185	1			T14	3		T49	6		T15	7
all_values[3]	auto[1]	auto[1]	auto[1]	192	1			T14	3		T49	3		T15	2
all_values[4]	auto[0]	auto[0]	auto[0]	201	1			T14	3		T49	6		T15	6
all_values[4]	auto[0]	auto[0]	auto[1]	90	1			T14	2		T49	1		T15	1
all_values[4]	auto[0]	auto[1]	auto[0]	109	1			T15	1		T17	2		T18	1
all_values[4]	auto[0]	auto[1]	auto[1]	69	1			T49	2		T15	1		T18	1
all_values[4]	auto[1]	auto[0]	auto[1]	179	1			T14	2		T49	4		T15	2
all_values[4]	auto[1]	auto[1]	auto[1]	165	1			T49	4		T15	3		T18	3
all_values[5]	auto[0]	auto[0]	auto[0]	245	1			T14	1		T49	3		T15	6
all_values[5]	auto[0]	auto[1]	auto[0]	239	1			T14	1		T49	4		T15	2
all_values[5]	auto[1]	auto[0]	auto[1]	184	1			T14	5		T49	5		T15	6
all_values[5]	auto[1]	auto[1]	auto[1]	145	1			T49	5		T17	1		T19	6
all_values[6]	auto[0]	auto[0]	auto[0]	180	1			T14	3		T49	3		T15	5
all_values[6]	auto[0]	auto[0]	auto[1]	70	1			T49	1		T15	2		T20	2
all_values[6]	auto[0]	auto[1]	auto[0]	137	1			T14	2		T49	8		T17	1
all_values[6]	auto[0]	auto[1]	auto[1]	81	1			T15	1		T19	2		T22	2
all_values[6]	auto[1]	auto[0]	auto[1]	188	1			T14	1		T49	3		T15	4
all_values[6]	auto[1]	auto[1]	auto[1]	157	1			T14	1		T49	2		T15	2
all_values[7]	auto[0]	auto[0]	auto[0]	156	1			T49	3		T15	2		T17	1
all_values[7]	auto[0]	auto[0]	auto[1]	83	1			T14	2		T49	3		T15	1
all_values[7]	auto[0]	auto[1]	auto[0]	117	1			T14	3		T49	1		T15	1
all_values[7]	auto[0]	auto[1]	auto[1]	79	1			T49	1		T15	2		T18	1
all_values[7]	auto[1]	auto[0]	auto[1]	221	1			T14	2		T49	7		T15	3
all_values[7]	auto[1]	auto[1]	auto[1]	157	1			T49	2		T15	5		T17	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal