Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1840

1

T11

9

T30

1

T33

5

auto[1]

1790

1

T11

5

T30

5

T33

7

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2043

1

T33

9

T36

15

T14

16

auto[1]

1587

1

T11

14

T30

6

T33

3

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2846

1

T11

14

T30

6

T33

7

auto[1]

784

1

T33

5

T36

5

T14

6

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	712	1			T11	4		T33	3		T36	4
valid[1]	759	1			T11	3		T30	1		T33	1
valid[2]	706	1			T11	2		T30	2		T33	2
valid[3]	708	1			T11	2		T30	1		T33	2
valid[4]	745	1			T11	3		T30	2		T33	4

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	120	1			T36	1		T39	1		T51	1
auto[0]	auto[0]	valid[0]	auto[1]	154	1			T11	2		T33	2		T309	1
auto[0]	auto[0]	valid[1]	auto[0]	133	1			T36	1		T39	1		T51	1
auto[0]	auto[0]	valid[1]	auto[1]	166	1			T11	2		T34	2		T23	1
auto[0]	auto[0]	valid[2]	auto[0]	113	1			T36	1		T67	3		T316	1
auto[0]	auto[0]	valid[2]	auto[1]	152	1			T11	1		T33	1		T34	1
auto[0]	auto[0]	valid[3]	auto[0]	129	1			T23	1		T39	2		T51	1
auto[0]	auto[0]	valid[3]	auto[1]	156	1			T11	2		T34	1		T36	1
auto[0]	auto[0]	valid[4]	auto[0]	129	1			T33	1		T36	1		T14	1
auto[0]	auto[0]	valid[4]	auto[1]	177	1			T11	2		T30	1		T34	2
auto[0]	auto[1]	valid[0]	auto[0]	134	1			T33	1		T36	1		T14	1
auto[0]	auto[1]	valid[0]	auto[1]	145	1			T11	2		T36	1		T14	1
auto[0]	auto[1]	valid[1]	auto[0]	124	1			T36	2		T14	2		T23	1
auto[0]	auto[1]	valid[1]	auto[1]	167	1			T11	1		T30	1		T36	2
auto[0]	auto[1]	valid[2]	auto[0]	115	1			T14	2		T51	1		T67	3
auto[0]	auto[1]	valid[2]	auto[1]	165	1			T11	1		T30	2		T34	2
auto[0]	auto[1]	valid[3]	auto[0]	128	1			T33	2		T14	3		T51	1
auto[0]	auto[1]	valid[3]	auto[1]	147	1			T30	1		T36	1		T39	1
auto[0]	auto[1]	valid[4]	auto[0]	134	1			T36	3		T14	1		T56	1
auto[0]	auto[1]	valid[4]	auto[1]	158	1			T11	1		T30	1		T34	1
auto[1]	auto[0]	valid[0]	auto[0]	77	1			T36	1		T23	1		T51	1
auto[1]	auto[0]	valid[1]	auto[0]	85	1			T33	1		T36	1		T39	1
auto[1]	auto[0]	valid[2]	auto[0]	92	1			T23	1		T51	2		T67	1
auto[1]	auto[0]	valid[3]	auto[0]	80	1			T14	1		T23	1		T15	1
auto[1]	auto[0]	valid[4]	auto[0]	77	1			T36	2		T23	1		T39	1
auto[1]	auto[1]	valid[0]	auto[0]	82	1			T14	1		T51	1		T56	2
auto[1]	auto[1]	valid[1]	auto[0]	84	1			T36	1		T23	1		T39	1
auto[1]	auto[1]	valid[2]	auto[0]	69	1			T33	1		T14	1		T39	1
auto[1]	auto[1]	valid[3]	auto[0]	68	1			T14	2		T23	1		T39	1
auto[1]	auto[1]	valid[4]	auto[0]	70	1			T33	3		T14	1		T23	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal