Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

50529

1

T8

8

T33

167

T35

2

auto[1]

17671

1

T11

177

T30

6

T33

55

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49802

1

T8

3

T11

177

T30

6

auto[1]

18398

1

T8

5

T33

67

T35

1

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	35077	1			T8	5		T11	93		T30	6
others[1]	5711	1			T11	8		T33	19		T36	48
others[2]	5734	1			T11	18		T33	19		T36	47
others[3]	6492	1			T8	1		T11	17		T33	19
interest[1]	3785	1			T11	12		T33	7		T35	1
interest[4]	22966	1			T8	5		T11	68		T30	6
interest[64]	11401	1			T8	2		T11	29		T33	48

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	16412	1			T8	2		T33	49		T35	1
auto[0]	auto[0]	others[1]	2740	1			T33	5		T36	22		T14	24
auto[0]	auto[0]	others[2]	2695	1			T33	6		T36	27		T14	23
auto[0]	auto[0]	others[3]	3128	1			T33	10		T36	25		T14	15
auto[0]	auto[0]	interest[1]	1741	1			T33	4		T36	16		T14	10
auto[0]	auto[0]	interest[4]	10733	1			T8	2		T33	29		T35	1
auto[0]	auto[0]	interest[64]	5415	1			T8	1		T33	26		T36	34
auto[0]	auto[1]	others[0]	9257	1			T11	93		T30	6		T33	29
auto[0]	auto[1]	others[1]	1399	1			T11	8		T33	10		T36	10
auto[0]	auto[1]	others[2]	1495	1			T11	18		T33	5		T36	10
auto[0]	auto[1]	others[3]	1623	1			T11	17		T33	1		T36	10
auto[0]	auto[1]	interest[1]	1001	1			T11	12		T33	1		T36	6
auto[0]	auto[1]	interest[4]	6130	1			T11	68		T30	6		T33	20
auto[0]	auto[1]	interest[64]	2896	1			T11	29		T33	9		T36	16
auto[1]	auto[0]	others[0]	9408	1			T8	3		T33	32		T36	85
auto[1]	auto[0]	others[1]	1572	1			T33	4		T36	16		T14	6
auto[1]	auto[0]	others[2]	1544	1			T33	8		T36	10		T14	7
auto[1]	auto[0]	others[3]	1741	1			T8	1		T33	8		T36	11
auto[1]	auto[0]	interest[1]	1043	1			T33	2		T35	1		T36	10
auto[1]	auto[0]	interest[4]	6103	1			T8	3		T33	18		T36	51
auto[1]	auto[0]	interest[64]	3090	1			T8	1		T33	13		T36	36

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal