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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.04 98.38 93.99 98.62 89.36 97.19 95.45 99.26


Total test records in report: 1129
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html
T1026 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2511203329 Jul 13 06:30:04 PM PDT 24 Jul 13 06:30:08 PM PDT 24 178256569 ps
T1027 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.982611173 Jul 13 06:29:58 PM PDT 24 Jul 13 06:30:02 PM PDT 24 44245590 ps
T1028 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.3102203900 Jul 13 06:30:11 PM PDT 24 Jul 13 06:30:13 PM PDT 24 14640880 ps
T1029 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.2349296211 Jul 13 06:30:13 PM PDT 24 Jul 13 06:30:32 PM PDT 24 1336686750 ps
T158 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2793289901 Jul 13 06:30:19 PM PDT 24 Jul 13 06:30:28 PM PDT 24 3704617834 ps
T1030 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2955827913 Jul 13 06:29:57 PM PDT 24 Jul 13 06:30:02 PM PDT 24 98172038 ps
T96 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.143476211 Jul 13 06:30:03 PM PDT 24 Jul 13 06:30:05 PM PDT 24 19699410 ps
T1031 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3031232753 Jul 13 06:30:26 PM PDT 24 Jul 13 06:30:27 PM PDT 24 10837527 ps
T159 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.2874886287 Jul 13 06:30:21 PM PDT 24 Jul 13 06:30:25 PM PDT 24 528325585 ps
T1032 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.1258838111 Jul 13 06:30:12 PM PDT 24 Jul 13 06:30:14 PM PDT 24 13887609 ps
T1033 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1420706779 Jul 13 06:30:28 PM PDT 24 Jul 13 06:30:29 PM PDT 24 36932285 ps
T125 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.4262664981 Jul 13 06:30:07 PM PDT 24 Jul 13 06:30:12 PM PDT 24 36295676 ps
T1034 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3229581701 Jul 13 06:30:12 PM PDT 24 Jul 13 06:30:15 PM PDT 24 230199432 ps
T167 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3094988457 Jul 13 06:30:17 PM PDT 24 Jul 13 06:30:20 PM PDT 24 99230855 ps
T116 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2238981908 Jul 13 06:30:13 PM PDT 24 Jul 13 06:30:16 PM PDT 24 302470710 ps
T126 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.257316648 Jul 13 06:29:57 PM PDT 24 Jul 13 06:29:59 PM PDT 24 204489915 ps
T1035 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1819093557 Jul 13 06:30:29 PM PDT 24 Jul 13 06:30:30 PM PDT 24 12737863 ps
T1036 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2486246909 Jul 13 06:30:20 PM PDT 24 Jul 13 06:30:22 PM PDT 24 48307615 ps
T127 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2844320673 Jul 13 06:30:07 PM PDT 24 Jul 13 06:30:25 PM PDT 24 427326016 ps
T1037 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.2619345606 Jul 13 06:30:20 PM PDT 24 Jul 13 06:30:22 PM PDT 24 38938372 ps
T1038 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2262699960 Jul 13 06:30:30 PM PDT 24 Jul 13 06:30:33 PM PDT 24 16951970 ps
T1039 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.427699737 Jul 13 06:30:11 PM PDT 24 Jul 13 06:30:15 PM PDT 24 45909668 ps
T128 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1214672599 Jul 13 06:30:19 PM PDT 24 Jul 13 06:30:23 PM PDT 24 93022818 ps
T172 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2841423255 Jul 13 06:30:06 PM PDT 24 Jul 13 06:30:22 PM PDT 24 221288803 ps
T1040 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2811154354 Jul 13 06:30:30 PM PDT 24 Jul 13 06:30:32 PM PDT 24 52962700 ps
T160 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1407319983 Jul 13 06:30:20 PM PDT 24 Jul 13 06:30:23 PM PDT 24 300529469 ps
T1041 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2834219989 Jul 13 06:30:07 PM PDT 24 Jul 13 06:30:12 PM PDT 24 167523879 ps
T130 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3903063024 Jul 13 06:30:09 PM PDT 24 Jul 13 06:30:33 PM PDT 24 2182189028 ps
T1042 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2918595240 Jul 13 06:30:30 PM PDT 24 Jul 13 06:30:34 PM PDT 24 230686286 ps
T1043 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.2702694599 Jul 13 06:30:05 PM PDT 24 Jul 13 06:30:08 PM PDT 24 30640818 ps
T1044 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1257413021 Jul 13 06:30:31 PM PDT 24 Jul 13 06:30:34 PM PDT 24 88872984 ps
T97 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2789015028 Jul 13 06:29:58 PM PDT 24 Jul 13 06:30:00 PM PDT 24 147622652 ps
T1045 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.3547042993 Jul 13 06:30:06 PM PDT 24 Jul 13 06:30:09 PM PDT 24 16288393 ps
T117 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2150411483 Jul 13 06:30:07 PM PDT 24 Jul 13 06:30:13 PM PDT 24 126487590 ps
T98 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2008700210 Jul 13 06:30:02 PM PDT 24 Jul 13 06:30:04 PM PDT 24 31936992 ps
T161 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3549923120 Jul 13 06:30:18 PM PDT 24 Jul 13 06:30:21 PM PDT 24 324125112 ps
T1046 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.4174433611 Jul 13 06:30:30 PM PDT 24 Jul 13 06:30:33 PM PDT 24 43318155 ps
T1047 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.1930794728 Jul 13 06:30:06 PM PDT 24 Jul 13 06:30:10 PM PDT 24 151029274 ps
T1048 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3101278492 Jul 13 06:30:13 PM PDT 24 Jul 13 06:30:16 PM PDT 24 47241407 ps
T1049 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3926062388 Jul 13 06:30:11 PM PDT 24 Jul 13 06:30:13 PM PDT 24 44422566 ps
T1050 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.403130896 Jul 13 06:30:06 PM PDT 24 Jul 13 06:30:10 PM PDT 24 57041376 ps
T162 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2769942261 Jul 13 06:30:15 PM PDT 24 Jul 13 06:30:19 PM PDT 24 219419037 ps
T1051 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1720611436 Jul 13 06:30:06 PM PDT 24 Jul 13 06:30:12 PM PDT 24 45193391 ps
T1052 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2958337895 Jul 13 06:30:33 PM PDT 24 Jul 13 06:30:35 PM PDT 24 16197513 ps
T176 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.1285552052 Jul 13 06:30:22 PM PDT 24 Jul 13 06:30:36 PM PDT 24 417326175 ps
T1053 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1448311019 Jul 13 06:30:20 PM PDT 24 Jul 13 06:30:23 PM PDT 24 190911197 ps
T1054 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3233792680 Jul 13 06:30:21 PM PDT 24 Jul 13 06:30:24 PM PDT 24 28659122 ps
T1055 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1574601417 Jul 13 06:30:07 PM PDT 24 Jul 13 06:30:10 PM PDT 24 20620000 ps
T1056 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2560963758 Jul 13 06:30:15 PM PDT 24 Jul 13 06:30:19 PM PDT 24 388968226 ps
T1057 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.3266465836 Jul 13 06:30:16 PM PDT 24 Jul 13 06:30:19 PM PDT 24 178654165 ps
T1058 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.640293377 Jul 13 06:30:19 PM PDT 24 Jul 13 06:30:33 PM PDT 24 788010732 ps
T179 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.2837749858 Jul 13 06:30:12 PM PDT 24 Jul 13 06:30:26 PM PDT 24 198069069 ps
T1059 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3558920321 Jul 13 06:30:12 PM PDT 24 Jul 13 06:30:14 PM PDT 24 18180402 ps
T1060 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.3329407658 Jul 13 06:30:29 PM PDT 24 Jul 13 06:30:31 PM PDT 24 47244034 ps
T1061 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.3215563454 Jul 13 06:30:06 PM PDT 24 Jul 13 06:30:12 PM PDT 24 104879362 ps
T1062 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.1336147767 Jul 13 06:30:12 PM PDT 24 Jul 13 06:30:16 PM PDT 24 58946416 ps
T1063 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2786091135 Jul 13 06:30:04 PM PDT 24 Jul 13 06:30:08 PM PDT 24 235295990 ps
T1064 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1640512218 Jul 13 06:30:19 PM PDT 24 Jul 13 06:30:22 PM PDT 24 29903365 ps
T1065 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1715675943 Jul 13 06:30:30 PM PDT 24 Jul 13 06:30:33 PM PDT 24 21415820 ps
T1066 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.1634909440 Jul 13 06:30:11 PM PDT 24 Jul 13 06:30:13 PM PDT 24 39642631 ps
T1067 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.130135870 Jul 13 06:30:14 PM PDT 24 Jul 13 06:30:20 PM PDT 24 163614010 ps
T1068 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.507716531 Jul 13 06:30:13 PM PDT 24 Jul 13 06:30:17 PM PDT 24 138319189 ps
T1069 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3218225138 Jul 13 06:30:30 PM PDT 24 Jul 13 06:30:32 PM PDT 24 29743378 ps
T1070 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1272082515 Jul 13 06:30:03 PM PDT 24 Jul 13 06:30:20 PM PDT 24 833894218 ps
T1071 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.1835302720 Jul 13 06:30:19 PM PDT 24 Jul 13 06:30:22 PM PDT 24 22688402 ps
T1072 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.1595002498 Jul 13 06:30:29 PM PDT 24 Jul 13 06:30:31 PM PDT 24 25471320 ps
T1073 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.430076033 Jul 13 06:30:06 PM PDT 24 Jul 13 06:30:47 PM PDT 24 1839094762 ps
T1074 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.510887762 Jul 13 06:30:05 PM PDT 24 Jul 13 06:30:08 PM PDT 24 48469532 ps
T1075 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1510533721 Jul 13 06:30:04 PM PDT 24 Jul 13 06:30:10 PM PDT 24 53463756 ps
T115 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2679678871 Jul 13 06:30:29 PM PDT 24 Jul 13 06:30:31 PM PDT 24 65121059 ps
T1076 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.194447158 Jul 13 06:30:11 PM PDT 24 Jul 13 06:30:17 PM PDT 24 56271478 ps
T1077 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.4288000217 Jul 13 06:30:30 PM PDT 24 Jul 13 06:30:33 PM PDT 24 16942726 ps
T1078 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1190235665 Jul 13 06:30:17 PM PDT 24 Jul 13 06:30:21 PM PDT 24 95051861 ps
T1079 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.3098561300 Jul 13 06:30:15 PM PDT 24 Jul 13 06:30:18 PM PDT 24 15388249 ps
T1080 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2099589959 Jul 13 06:30:18 PM PDT 24 Jul 13 06:30:21 PM PDT 24 85183670 ps
T1081 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.4196653556 Jul 13 06:30:31 PM PDT 24 Jul 13 06:30:57 PM PDT 24 3864882562 ps
T170 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.3723199554 Jul 13 06:30:16 PM PDT 24 Jul 13 06:30:20 PM PDT 24 188769969 ps
T1082 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.976912077 Jul 13 06:30:15 PM PDT 24 Jul 13 06:30:18 PM PDT 24 48790414 ps
T1083 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2767667674 Jul 13 06:30:28 PM PDT 24 Jul 13 06:30:30 PM PDT 24 45324016 ps
T173 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1446855148 Jul 13 06:30:15 PM PDT 24 Jul 13 06:30:37 PM PDT 24 1893826198 ps
T1084 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3571186853 Jul 13 06:30:11 PM PDT 24 Jul 13 06:30:13 PM PDT 24 50370610 ps
T1085 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.667035210 Jul 13 06:30:22 PM PDT 24 Jul 13 06:30:27 PM PDT 24 156474073 ps
T1086 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2567371383 Jul 13 06:30:05 PM PDT 24 Jul 13 06:30:08 PM PDT 24 36853829 ps
T1087 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1909810758 Jul 13 06:30:03 PM PDT 24 Jul 13 06:30:29 PM PDT 24 1857722179 ps
T1088 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1436370128 Jul 13 06:30:19 PM PDT 24 Jul 13 06:30:22 PM PDT 24 539830001 ps
T1089 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.2744792826 Jul 13 06:30:14 PM PDT 24 Jul 13 06:30:17 PM PDT 24 238723634 ps
T1090 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.863968484 Jul 13 06:30:15 PM PDT 24 Jul 13 06:30:17 PM PDT 24 13314196 ps
T1091 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1567904913 Jul 13 06:30:12 PM PDT 24 Jul 13 06:30:15 PM PDT 24 29483972 ps
T1092 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.258870502 Jul 13 06:30:20 PM PDT 24 Jul 13 06:30:22 PM PDT 24 86820824 ps
T1093 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.362176932 Jul 13 06:30:16 PM PDT 24 Jul 13 06:30:19 PM PDT 24 90496959 ps
T1094 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.3946836471 Jul 13 06:30:12 PM PDT 24 Jul 13 06:30:14 PM PDT 24 11816789 ps
T1095 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.2918393173 Jul 13 06:30:31 PM PDT 24 Jul 13 06:30:34 PM PDT 24 14742878 ps
T1096 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.579759587 Jul 13 06:30:31 PM PDT 24 Jul 13 06:30:34 PM PDT 24 40626818 ps
T1097 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.3196340559 Jul 13 06:30:05 PM PDT 24 Jul 13 06:30:09 PM PDT 24 43271467 ps
T1098 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.2466396341 Jul 13 06:30:31 PM PDT 24 Jul 13 06:30:34 PM PDT 24 13719653 ps
T1099 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.4152294627 Jul 13 06:30:08 PM PDT 24 Jul 13 06:30:11 PM PDT 24 12030078 ps
T1100 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.551439988 Jul 13 06:30:11 PM PDT 24 Jul 13 06:30:18 PM PDT 24 207456000 ps
T1101 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2660547664 Jul 13 06:30:29 PM PDT 24 Jul 13 06:30:32 PM PDT 24 132801695 ps
T1102 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1179436823 Jul 13 06:30:05 PM PDT 24 Jul 13 06:30:21 PM PDT 24 561442367 ps
T171 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2062843477 Jul 13 06:30:06 PM PDT 24 Jul 13 06:30:12 PM PDT 24 399414946 ps
T1103 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.2170846515 Jul 13 06:30:31 PM PDT 24 Jul 13 06:30:33 PM PDT 24 23874127 ps
T1104 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.4128921291 Jul 13 06:30:05 PM PDT 24 Jul 13 06:30:28 PM PDT 24 598805941 ps
T177 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.362226709 Jul 13 06:30:20 PM PDT 24 Jul 13 06:30:36 PM PDT 24 206379597 ps
T1105 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.221913365 Jul 13 06:30:30 PM PDT 24 Jul 13 06:30:32 PM PDT 24 75107631 ps
T1106 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.1756599329 Jul 13 06:30:13 PM PDT 24 Jul 13 06:30:15 PM PDT 24 69701387 ps
T1107 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.4093738446 Jul 13 06:30:20 PM PDT 24 Jul 13 06:30:23 PM PDT 24 43400120 ps
T1108 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.271430305 Jul 13 06:29:58 PM PDT 24 Jul 13 06:30:00 PM PDT 24 27154047 ps
T1109 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.812892775 Jul 13 06:30:15 PM PDT 24 Jul 13 06:30:20 PM PDT 24 167914294 ps
T1110 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.549558402 Jul 13 06:30:19 PM PDT 24 Jul 13 06:30:22 PM PDT 24 14337497 ps
T1111 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.4041857685 Jul 13 06:30:05 PM PDT 24 Jul 13 06:30:10 PM PDT 24 45330297 ps
T1112 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3094993158 Jul 13 06:30:29 PM PDT 24 Jul 13 06:30:31 PM PDT 24 155801609 ps
T1113 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.911927568 Jul 13 06:30:20 PM PDT 24 Jul 13 06:30:26 PM PDT 24 55818729 ps
T1114 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2095640598 Jul 13 06:30:17 PM PDT 24 Jul 13 06:30:21 PM PDT 24 500390881 ps
T1115 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1138496828 Jul 13 06:30:06 PM PDT 24 Jul 13 06:30:10 PM PDT 24 12363014 ps
T1116 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2832839812 Jul 13 06:30:12 PM PDT 24 Jul 13 06:30:17 PM PDT 24 548979890 ps
T1117 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.2914923933 Jul 13 06:30:31 PM PDT 24 Jul 13 06:30:34 PM PDT 24 10835823 ps
T1118 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.1418086648 Jul 13 06:30:04 PM PDT 24 Jul 13 06:30:06 PM PDT 24 23371355 ps
T1119 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2199477641 Jul 13 06:30:18 PM PDT 24 Jul 13 06:30:21 PM PDT 24 277586908 ps
T1120 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2494958989 Jul 13 06:30:15 PM PDT 24 Jul 13 06:30:21 PM PDT 24 362407286 ps
T1121 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2255088158 Jul 13 06:30:31 PM PDT 24 Jul 13 06:30:34 PM PDT 24 17991833 ps
T1122 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3045500861 Jul 13 06:30:22 PM PDT 24 Jul 13 06:30:35 PM PDT 24 541034065 ps
T1123 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.492064134 Jul 13 06:30:31 PM PDT 24 Jul 13 06:30:34 PM PDT 24 42891665 ps
T1124 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.276534463 Jul 13 06:30:06 PM PDT 24 Jul 13 06:30:10 PM PDT 24 60436050 ps
T1125 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2922189560 Jul 13 06:30:04 PM PDT 24 Jul 13 06:30:29 PM PDT 24 3391911528 ps
T178 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1529021769 Jul 13 06:30:13 PM PDT 24 Jul 13 06:30:28 PM PDT 24 202435905 ps
T1126 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3561877760 Jul 13 06:30:31 PM PDT 24 Jul 13 06:30:36 PM PDT 24 376060602 ps
T1127 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3122614605 Jul 13 06:30:14 PM PDT 24 Jul 13 06:30:17 PM PDT 24 72316483 ps
T1128 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.1295102847 Jul 13 06:30:20 PM PDT 24 Jul 13 06:30:23 PM PDT 24 11971829 ps
T1129 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2902922019 Jul 13 06:30:20 PM PDT 24 Jul 13 06:30:24 PM PDT 24 283820301 ps

Test location /workspace/coverage/default/21.spi_device_flash_all.1045511353
Short name T10
Test name
Test status
Simulation time 4591037576 ps
CPU time 109.95 seconds
Started Jul 13 07:00:06 PM PDT 24
Finished Jul 13 07:01:57 PM PDT 24
Peak memory 271292 kb
Host smart-5f1cf4af-d09a-4ab0-9d85-38ab309b9c7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045511353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.1045511353
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.1048078495
Short name T14
Test name
Test status
Simulation time 184471320532 ps
CPU time 325.95 seconds
Started Jul 13 07:00:20 PM PDT 24
Finished Jul 13 07:05:47 PM PDT 24
Peak memory 268820 kb
Host smart-cd55a738-b19c-424a-bc5f-b1a4a39fda44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048078495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.1048078495
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.2377607467
Short name T39
Test name
Test status
Simulation time 83509746575 ps
CPU time 269.07 seconds
Started Jul 13 07:00:15 PM PDT 24
Finished Jul 13 07:04:45 PM PDT 24
Peak memory 264232 kb
Host smart-691e29b9-921d-4832-8e5e-49425b81620a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377607467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.2377607467
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.1614877906
Short name T20
Test name
Test status
Simulation time 33156312990 ps
CPU time 333.97 seconds
Started Jul 13 07:00:00 PM PDT 24
Finished Jul 13 07:05:37 PM PDT 24
Peak memory 270632 kb
Host smart-774bd962-5163-496c-a564-cfb067792eef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614877906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.1614877906
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.4222360053
Short name T156
Test name
Test status
Simulation time 1396677437 ps
CPU time 8.41 seconds
Started Jul 13 06:30:19 PM PDT 24
Finished Jul 13 06:30:29 PM PDT 24
Peak memory 216080 kb
Host smart-cae36da7-c203-4160-b0dc-49f896f4a0d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222360053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.4222360053
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.3477919677
Short name T21
Test name
Test status
Simulation time 385660491765 ps
CPU time 781.34 seconds
Started Jul 13 07:01:31 PM PDT 24
Finished Jul 13 07:14:33 PM PDT 24
Peak memory 306140 kb
Host smart-2eb8c9a3-04a5-423a-8ee5-3fa3e93d488c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477919677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.3477919677
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.1050156883
Short name T7
Test name
Test status
Simulation time 34200713 ps
CPU time 0.73 seconds
Started Jul 13 06:58:59 PM PDT 24
Finished Jul 13 06:59:00 PM PDT 24
Peak memory 216084 kb
Host smart-1b5605f5-b474-44ab-aefd-2f031c004ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050156883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.1050156883
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1730370408
Short name T110
Test name
Test status
Simulation time 246073608 ps
CPU time 5.7 seconds
Started Jul 13 06:30:07 PM PDT 24
Finished Jul 13 06:30:16 PM PDT 24
Peak memory 215892 kb
Host smart-dd56c237-96c9-413f-83c7-3add21a09eed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730370408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.1
730370408
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.1998976249
Short name T95
Test name
Test status
Simulation time 14610903440 ps
CPU time 170.17 seconds
Started Jul 13 06:59:48 PM PDT 24
Finished Jul 13 07:02:41 PM PDT 24
Peak memory 271652 kb
Host smart-b48e24ad-7eef-428a-bebc-3b364eccb208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998976249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.1998976249
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.2249433231
Short name T245
Test name
Test status
Simulation time 45389653613 ps
CPU time 225.42 seconds
Started Jul 13 06:59:14 PM PDT 24
Finished Jul 13 07:03:01 PM PDT 24
Peak memory 281940 kb
Host smart-45a1685c-62d2-4a2c-b830-3e0cd3454e26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249433231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.2249433231
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.3297172791
Short name T49
Test name
Test status
Simulation time 61685632120 ps
CPU time 578.05 seconds
Started Jul 13 07:01:01 PM PDT 24
Finished Jul 13 07:10:43 PM PDT 24
Peak memory 265688 kb
Host smart-d9e35156-d96f-4fd8-88bd-32f8c3735a2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297172791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.3297172791
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.800804960
Short name T3
Test name
Test status
Simulation time 395864388 ps
CPU time 4 seconds
Started Jul 13 07:00:50 PM PDT 24
Finished Jul 13 07:00:57 PM PDT 24
Peak memory 219928 kb
Host smart-ba2e87a0-5711-4c90-97b7-1c6202b0caa4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=800804960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dire
ct.800804960
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.1120087491
Short name T51
Test name
Test status
Simulation time 10130803867 ps
CPU time 72.59 seconds
Started Jul 13 07:01:25 PM PDT 24
Finished Jul 13 07:02:39 PM PDT 24
Peak memory 250176 kb
Host smart-eb630040-daf9-48c1-8724-98085fd470b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120087491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.1120087491
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.3211365453
Short name T72
Test name
Test status
Simulation time 25681101 ps
CPU time 0.81 seconds
Started Jul 13 06:59:55 PM PDT 24
Finished Jul 13 07:00:00 PM PDT 24
Peak memory 205564 kb
Host smart-a67d438c-479f-4c60-aeea-7e996173a8ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211365453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
3211365453
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.1318611588
Short name T187
Test name
Test status
Simulation time 4337288882 ps
CPU time 105.64 seconds
Started Jul 13 07:00:52 PM PDT 24
Finished Jul 13 07:02:43 PM PDT 24
Peak memory 256284 kb
Host smart-25680fce-5e0c-4b63-9318-6fd6092a6b47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318611588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.1318611588
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.3864730193
Short name T198
Test name
Test status
Simulation time 185453014860 ps
CPU time 291.24 seconds
Started Jul 13 06:59:53 PM PDT 24
Finished Jul 13 07:04:49 PM PDT 24
Peak memory 254328 kb
Host smart-af63e3a3-25c6-4f3b-acdd-629d282563c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864730193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmd
s.3864730193
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.143476211
Short name T96
Test name
Test status
Simulation time 19699410 ps
CPU time 1.2 seconds
Started Jul 13 06:30:03 PM PDT 24
Finished Jul 13 06:30:05 PM PDT 24
Peak memory 207544 kb
Host smart-04b61333-cbc4-4bf1-be81-c955b1a395f8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143476211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_hw_reset.143476211
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.2768610617
Short name T183
Test name
Test status
Simulation time 77547901638 ps
CPU time 706.66 seconds
Started Jul 13 07:00:06 PM PDT 24
Finished Jul 13 07:11:55 PM PDT 24
Peak memory 266780 kb
Host smart-f1f4dca0-b807-49ea-bdb1-9b7987156f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768610617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.2768610617
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.1978083558
Short name T52
Test name
Test status
Simulation time 21574120883 ps
CPU time 58.22 seconds
Started Jul 13 07:00:05 PM PDT 24
Finished Jul 13 07:01:05 PM PDT 24
Peak memory 257388 kb
Host smart-d297cd79-d728-491a-ba32-9c84aa8e16f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978083558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmd
s.1978083558
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.3721586526
Short name T286
Test name
Test status
Simulation time 79491413926 ps
CPU time 208.01 seconds
Started Jul 13 07:00:51 PM PDT 24
Finished Jul 13 07:04:23 PM PDT 24
Peak memory 267084 kb
Host smart-fe9d8f78-c690-40fc-adb0-25009c902d42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721586526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.3721586526
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.615993250
Short name T80
Test name
Test status
Simulation time 38727335 ps
CPU time 1 seconds
Started Jul 13 06:59:01 PM PDT 24
Finished Jul 13 06:59:04 PM PDT 24
Peak memory 235912 kb
Host smart-a53031d1-5e52-4344-ab47-86f037c8a531
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615993250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.615993250
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.3237809490
Short name T36
Test name
Test status
Simulation time 81589264943 ps
CPU time 189.73 seconds
Started Jul 13 06:59:10 PM PDT 24
Finished Jul 13 07:02:22 PM PDT 24
Peak memory 249288 kb
Host smart-265cd8a9-0473-4aba-9b37-a51584b0d8b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237809490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.3237809490
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.2131619760
Short name T194
Test name
Test status
Simulation time 29118326785 ps
CPU time 267.46 seconds
Started Jul 13 06:59:11 PM PDT 24
Finished Jul 13 07:03:41 PM PDT 24
Peak memory 265136 kb
Host smart-3333d47f-f64e-4086-b442-a592cffa1e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131619760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.2131619760
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2841423255
Short name T172
Test name
Test status
Simulation time 221288803 ps
CPU time 13.21 seconds
Started Jul 13 06:30:06 PM PDT 24
Finished Jul 13 06:30:22 PM PDT 24
Peak memory 215680 kb
Host smart-3eaf28d4-64d9-4761-9871-04d07e34055e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841423255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.2841423255
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.1350624201
Short name T295
Test name
Test status
Simulation time 12615601031 ps
CPU time 34.34 seconds
Started Jul 13 07:00:31 PM PDT 24
Finished Jul 13 07:01:06 PM PDT 24
Peak memory 249404 kb
Host smart-85c050ee-5e12-4f5c-ac60-f30cd8485b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350624201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.1350624201
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.1052626392
Short name T188
Test name
Test status
Simulation time 5057862167 ps
CPU time 129.68 seconds
Started Jul 13 07:01:02 PM PDT 24
Finished Jul 13 07:03:14 PM PDT 24
Peak memory 266044 kb
Host smart-1f808bf8-615c-4b2d-8834-c341fef86ec8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052626392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.1052626392
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.3912575306
Short name T195
Test name
Test status
Simulation time 5396131985 ps
CPU time 63.81 seconds
Started Jul 13 07:01:42 PM PDT 24
Finished Jul 13 07:02:49 PM PDT 24
Peak memory 239748 kb
Host smart-42e98dd0-1051-4520-909e-c5eeecfa3357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912575306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmd
s.3912575306
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.774721446
Short name T40
Test name
Test status
Simulation time 58455142422 ps
CPU time 496.98 seconds
Started Jul 13 06:59:13 PM PDT 24
Finished Jul 13 07:07:32 PM PDT 24
Peak memory 270060 kb
Host smart-40d4ac60-6926-48ec-857d-01dd068d53d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774721446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.774721446
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.4235455290
Short name T272
Test name
Test status
Simulation time 15424912231 ps
CPU time 71.36 seconds
Started Jul 13 06:59:43 PM PDT 24
Finished Jul 13 07:00:55 PM PDT 24
Peak memory 265484 kb
Host smart-7995214f-0a06-4c0f-aa62-4ebcea529548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235455290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.4235455290
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.1454515274
Short name T58
Test name
Test status
Simulation time 11765234850 ps
CPU time 192.71 seconds
Started Jul 13 06:59:36 PM PDT 24
Finished Jul 13 07:02:49 PM PDT 24
Peak memory 251004 kb
Host smart-d039b250-527f-432d-bbd7-f534425af876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454515274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.1454515274
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.712500004
Short name T141
Test name
Test status
Simulation time 123976423969 ps
CPU time 300.05 seconds
Started Jul 13 06:59:51 PM PDT 24
Finished Jul 13 07:04:54 PM PDT 24
Peak memory 270460 kb
Host smart-619e7e40-9b86-465c-bfbd-11ad8dc0ad8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712500004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stres
s_all.712500004
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.2223372650
Short name T18
Test name
Test status
Simulation time 107094735257 ps
CPU time 293.48 seconds
Started Jul 13 07:00:49 PM PDT 24
Finished Jul 13 07:05:43 PM PDT 24
Peak memory 251488 kb
Host smart-34ec983b-a9be-4ffe-bada-93006526293b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223372650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.2223372650
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.2863740938
Short name T168
Test name
Test status
Simulation time 26410999426 ps
CPU time 72.69 seconds
Started Jul 13 07:01:08 PM PDT 24
Finished Jul 13 07:02:21 PM PDT 24
Peak memory 250500 kb
Host smart-ab7d8003-db21-4a8a-a976-2f2764780b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863740938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.2863740938
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.1507240057
Short name T839
Test name
Test status
Simulation time 329185216257 ps
CPU time 720.53 seconds
Started Jul 13 07:01:38 PM PDT 24
Finished Jul 13 07:13:39 PM PDT 24
Peak memory 265448 kb
Host smart-e3041517-5237-4906-b19f-9ca105522532
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507240057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.1507240057
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.514164550
Short name T44
Test name
Test status
Simulation time 68804799439 ps
CPU time 18.57 seconds
Started Jul 13 06:59:10 PM PDT 24
Finished Jul 13 06:59:31 PM PDT 24
Peak memory 232748 kb
Host smart-0729d8bd-d1e9-4899-b132-4d32fe2f242a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514164550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.514164550
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.4284608036
Short name T302
Test name
Test status
Simulation time 994077502 ps
CPU time 20.89 seconds
Started Jul 13 06:59:13 PM PDT 24
Finished Jul 13 06:59:36 PM PDT 24
Peak memory 224492 kb
Host smart-55291360-9508-4212-bc49-21a55f3159f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284608036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.4284608036
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.3178158369
Short name T629
Test name
Test status
Simulation time 213725754 ps
CPU time 2.78 seconds
Started Jul 13 06:59:33 PM PDT 24
Finished Jul 13 06:59:36 PM PDT 24
Peak memory 232632 kb
Host smart-361d5f63-4091-4b60-adf7-fb25002251fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178158369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.3178158369
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.3215563454
Short name T1061
Test name
Test status
Simulation time 104879362 ps
CPU time 3.99 seconds
Started Jul 13 06:30:06 PM PDT 24
Finished Jul 13 06:30:12 PM PDT 24
Peak memory 216872 kb
Host smart-96306d96-5783-4bce-a5c9-943b8e46481d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215563454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.3
215563454
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2323856999
Short name T175
Test name
Test status
Simulation time 293659062 ps
CPU time 19.21 seconds
Started Jul 13 06:30:03 PM PDT 24
Finished Jul 13 06:30:23 PM PDT 24
Peak memory 215752 kb
Host smart-7c4afe1f-b5fd-4795-bdaa-cdde1e2164c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323856999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.2323856999
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.3421063173
Short name T77
Test name
Test status
Simulation time 798244370 ps
CPU time 13.15 seconds
Started Jul 13 06:30:19 PM PDT 24
Finished Jul 13 06:30:32 PM PDT 24
Peak memory 215768 kb
Host smart-72904717-b0ff-4717-a0e4-1248604f9ace
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421063173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.3421063173
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1446855148
Short name T173
Test name
Test status
Simulation time 1893826198 ps
CPU time 20.22 seconds
Started Jul 13 06:30:15 PM PDT 24
Finished Jul 13 06:30:37 PM PDT 24
Peak memory 216108 kb
Host smart-124973b7-dcaf-4421-bccc-c0834e2a8f30
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446855148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.1446855148
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2062843477
Short name T171
Test name
Test status
Simulation time 399414946 ps
CPU time 2.85 seconds
Started Jul 13 06:30:06 PM PDT 24
Finished Jul 13 06:30:12 PM PDT 24
Peak memory 217396 kb
Host smart-32c601de-ce97-4d96-8e73-83566dab4604
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062843477 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.2062843477
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.472963148
Short name T929
Test name
Test status
Simulation time 737707607 ps
CPU time 16.29 seconds
Started Jul 13 06:59:04 PM PDT 24
Finished Jul 13 06:59:22 PM PDT 24
Peak memory 240828 kb
Host smart-c7361f3f-0f3a-4f4d-8c15-eefb575b17a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472963148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.472963148
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.3223971188
Short name T37
Test name
Test status
Simulation time 76141355419 ps
CPU time 336.42 seconds
Started Jul 13 06:59:06 PM PDT 24
Finished Jul 13 07:04:44 PM PDT 24
Peak memory 255324 kb
Host smart-a0f4f89d-0f33-4b8c-8938-5d18b94fe812
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223971188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.3223971188
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.224310776
Short name T465
Test name
Test status
Simulation time 8802432848 ps
CPU time 14.98 seconds
Started Jul 13 06:59:43 PM PDT 24
Finished Jul 13 06:59:58 PM PDT 24
Peak memory 224644 kb
Host smart-9a9e4794-727f-43c6-b6a4-1c22d1ee0b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224310776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.224310776
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.483897993
Short name T264
Test name
Test status
Simulation time 57891354370 ps
CPU time 270.96 seconds
Started Jul 13 06:59:52 PM PDT 24
Finished Jul 13 07:04:27 PM PDT 24
Peak memory 257328 kb
Host smart-d943c562-2403-4bc5-9bf1-eab3145080e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483897993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stress
_all.483897993
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.2419212267
Short name T241
Test name
Test status
Simulation time 429977646 ps
CPU time 4.36 seconds
Started Jul 13 06:59:53 PM PDT 24
Finished Jul 13 07:00:01 PM PDT 24
Peak memory 224460 kb
Host smart-4959b593-6138-45bf-8dcf-c3d01494cd7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419212267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.2419212267
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1272082515
Short name T1070
Test name
Test status
Simulation time 833894218 ps
CPU time 17.04 seconds
Started Jul 13 06:30:03 PM PDT 24
Finished Jul 13 06:30:20 PM PDT 24
Peak memory 215688 kb
Host smart-8a749180-edd8-4cd2-ba33-e60ed769c9a5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272082515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.1272082515
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.430076033
Short name T1073
Test name
Test status
Simulation time 1839094762 ps
CPU time 39.08 seconds
Started Jul 13 06:30:06 PM PDT 24
Finished Jul 13 06:30:47 PM PDT 24
Peak memory 207600 kb
Host smart-a47778b1-37a9-49ce-ab0a-79f8f3acba56
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430076033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_bit_bash.430076033
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2789015028
Short name T97
Test name
Test status
Simulation time 147622652 ps
CPU time 1.36 seconds
Started Jul 13 06:29:58 PM PDT 24
Finished Jul 13 06:30:00 PM PDT 24
Peak memory 215652 kb
Host smart-e4aa4b87-602e-4271-9f42-8c5deb0c9111
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789015028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.2789015028
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2955827913
Short name T1030
Test name
Test status
Simulation time 98172038 ps
CPU time 3.34 seconds
Started Jul 13 06:29:57 PM PDT 24
Finished Jul 13 06:30:02 PM PDT 24
Peak memory 217596 kb
Host smart-369884da-4d5a-4e47-94d2-b30680165cc4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955827913 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.2955827913
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.4262664981
Short name T125
Test name
Test status
Simulation time 36295676 ps
CPU time 2.34 seconds
Started Jul 13 06:30:07 PM PDT 24
Finished Jul 13 06:30:12 PM PDT 24
Peak memory 215540 kb
Host smart-8741ed3f-be0f-4ac7-a6e1-f62d9d63b69d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262664981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.4
262664981
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.271430305
Short name T1108
Test name
Test status
Simulation time 27154047 ps
CPU time 0.78 seconds
Started Jul 13 06:29:58 PM PDT 24
Finished Jul 13 06:30:00 PM PDT 24
Peak memory 204608 kb
Host smart-e1ab65ff-136a-4b87-a87a-c6e5229435bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271430305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.271430305
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.257316648
Short name T126
Test name
Test status
Simulation time 204489915 ps
CPU time 1.95 seconds
Started Jul 13 06:29:57 PM PDT 24
Finished Jul 13 06:29:59 PM PDT 24
Peak memory 215728 kb
Host smart-2e79b24a-6e49-4817-8d48-c9cad9d333a1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257316648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_
device_mem_partial_access.257316648
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1138496828
Short name T1115
Test name
Test status
Simulation time 12363014 ps
CPU time 0.68 seconds
Started Jul 13 06:30:06 PM PDT 24
Finished Jul 13 06:30:10 PM PDT 24
Peak memory 203988 kb
Host smart-358bfdc7-edd1-4724-bd30-22ed52898544
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138496828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.1138496828
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.982611173
Short name T1027
Test name
Test status
Simulation time 44245590 ps
CPU time 2.87 seconds
Started Jul 13 06:29:58 PM PDT 24
Finished Jul 13 06:30:02 PM PDT 24
Peak memory 215732 kb
Host smart-43e273fe-f1f9-4fcb-b561-0bb03f5d1be4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982611173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sp
i_device_same_csr_outstanding.982611173
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.4085940182
Short name T114
Test name
Test status
Simulation time 25803045 ps
CPU time 1.7 seconds
Started Jul 13 06:29:57 PM PDT 24
Finished Jul 13 06:30:00 PM PDT 24
Peak memory 216980 kb
Host smart-63597121-412b-45d5-a5f5-4a189156e98b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085940182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.4
085940182
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2935448897
Short name T174
Test name
Test status
Simulation time 1011877892 ps
CPU time 8.35 seconds
Started Jul 13 06:29:58 PM PDT 24
Finished Jul 13 06:30:07 PM PDT 24
Peak memory 215972 kb
Host smart-debb6b3d-57b7-4382-92c9-6f1311c9ab2e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935448897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.2935448897
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1909810758
Short name T1087
Test name
Test status
Simulation time 1857722179 ps
CPU time 24.87 seconds
Started Jul 13 06:30:03 PM PDT 24
Finished Jul 13 06:30:29 PM PDT 24
Peak memory 215616 kb
Host smart-9e086583-e787-46e0-8526-d281b46a3188
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909810758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.1909810758
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3903063024
Short name T130
Test name
Test status
Simulation time 2182189028 ps
CPU time 22.21 seconds
Started Jul 13 06:30:09 PM PDT 24
Finished Jul 13 06:30:33 PM PDT 24
Peak memory 207420 kb
Host smart-079c81f6-5e7a-4f06-a641-bd06468ac57a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903063024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.3903063024
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1510533721
Short name T1075
Test name
Test status
Simulation time 53463756 ps
CPU time 3.63 seconds
Started Jul 13 06:30:04 PM PDT 24
Finished Jul 13 06:30:10 PM PDT 24
Peak memory 218512 kb
Host smart-8d7193fd-8f77-4b96-bf49-685a75e6ef6f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510533721 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.1510533721
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.4082065388
Short name T148
Test name
Test status
Simulation time 519792155 ps
CPU time 2.75 seconds
Started Jul 13 06:30:05 PM PDT 24
Finished Jul 13 06:30:10 PM PDT 24
Peak memory 215700 kb
Host smart-97b53d4a-8de9-4c67-be33-c1b7b3be2958
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082065388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.4
082065388
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.2702694599
Short name T1043
Test name
Test status
Simulation time 30640818 ps
CPU time 0.72 seconds
Started Jul 13 06:30:05 PM PDT 24
Finished Jul 13 06:30:08 PM PDT 24
Peak memory 204536 kb
Host smart-e8e17591-67cd-4d1f-8757-f2147f263325
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702694599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.2
702694599
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.1930794728
Short name T1047
Test name
Test status
Simulation time 151029274 ps
CPU time 1.42 seconds
Started Jul 13 06:30:06 PM PDT 24
Finished Jul 13 06:30:10 PM PDT 24
Peak memory 215744 kb
Host smart-c303a8d0-4e09-445f-a19f-258967c54af9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930794728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.1930794728
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2567371383
Short name T1086
Test name
Test status
Simulation time 36853829 ps
CPU time 0.68 seconds
Started Jul 13 06:30:05 PM PDT 24
Finished Jul 13 06:30:08 PM PDT 24
Peak memory 204424 kb
Host smart-c71d2979-d25f-4389-91f2-416c1f6848de
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567371383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.2567371383
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2786091135
Short name T1063
Test name
Test status
Simulation time 235295990 ps
CPU time 3.31 seconds
Started Jul 13 06:30:04 PM PDT 24
Finished Jul 13 06:30:08 PM PDT 24
Peak memory 215648 kb
Host smart-b5538ac8-5584-4eaa-b180-6fb4e0eb2850
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786091135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.2786091135
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.194447158
Short name T1076
Test name
Test status
Simulation time 56271478 ps
CPU time 4.36 seconds
Started Jul 13 06:30:11 PM PDT 24
Finished Jul 13 06:30:17 PM PDT 24
Peak memory 217332 kb
Host smart-a9065540-588e-4773-841d-89efd7b30157
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194447158 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.194447158
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.1336147767
Short name T1062
Test name
Test status
Simulation time 58946416 ps
CPU time 2.14 seconds
Started Jul 13 06:30:12 PM PDT 24
Finished Jul 13 06:30:16 PM PDT 24
Peak memory 207472 kb
Host smart-ddb2ed31-cd99-47d5-a39f-2bda031c7057
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336147767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
1336147767
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.3946836471
Short name T1094
Test name
Test status
Simulation time 11816789 ps
CPU time 0.71 seconds
Started Jul 13 06:30:12 PM PDT 24
Finished Jul 13 06:30:14 PM PDT 24
Peak memory 204248 kb
Host smart-c5f0705f-a211-4ede-b995-eafeccf552f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946836471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
3946836471
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.507716531
Short name T1068
Test name
Test status
Simulation time 138319189 ps
CPU time 3.15 seconds
Started Jul 13 06:30:13 PM PDT 24
Finished Jul 13 06:30:17 PM PDT 24
Peak memory 215720 kb
Host smart-deef263b-2f80-4f6c-be00-4f0a8eb1ba15
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507716531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.s
pi_device_same_csr_outstanding.507716531
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.551439988
Short name T1100
Test name
Test status
Simulation time 207456000 ps
CPU time 5.29 seconds
Started Jul 13 06:30:11 PM PDT 24
Finished Jul 13 06:30:18 PM PDT 24
Peak memory 216056 kb
Host smart-bdbe88ea-d35e-4515-a710-f9c72cbabf33
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551439988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.551439988
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.812892775
Short name T1109
Test name
Test status
Simulation time 167914294 ps
CPU time 3.99 seconds
Started Jul 13 06:30:15 PM PDT 24
Finished Jul 13 06:30:20 PM PDT 24
Peak memory 217548 kb
Host smart-896d2a68-4945-43c5-a62d-035336b10f40
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812892775 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.812892775
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.2744792826
Short name T1089
Test name
Test status
Simulation time 238723634 ps
CPU time 2.2 seconds
Started Jul 13 06:30:14 PM PDT 24
Finished Jul 13 06:30:17 PM PDT 24
Peak memory 215752 kb
Host smart-dfb96e5a-f9a1-4ccb-9123-cdaa177deb9d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744792826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
2744792826
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.3102203900
Short name T1028
Test name
Test status
Simulation time 14640880 ps
CPU time 0.8 seconds
Started Jul 13 06:30:11 PM PDT 24
Finished Jul 13 06:30:13 PM PDT 24
Peak memory 204560 kb
Host smart-41f4f107-b6b1-4654-a40a-966aa153604e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102203900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
3102203900
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3122614605
Short name T1127
Test name
Test status
Simulation time 72316483 ps
CPU time 1.99 seconds
Started Jul 13 06:30:14 PM PDT 24
Finished Jul 13 06:30:17 PM PDT 24
Peak memory 207528 kb
Host smart-9da5f2a5-dab0-41fe-868f-ecfe41e98b04
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122614605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.3122614605
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.976912077
Short name T1082
Test name
Test status
Simulation time 48790414 ps
CPU time 1.83 seconds
Started Jul 13 06:30:15 PM PDT 24
Finished Jul 13 06:30:18 PM PDT 24
Peak memory 215876 kb
Host smart-ed04006e-9cdc-4220-a2cc-fcdbe498c595
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976912077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.976912077
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1640512218
Short name T1064
Test name
Test status
Simulation time 29903365 ps
CPU time 2.02 seconds
Started Jul 13 06:30:19 PM PDT 24
Finished Jul 13 06:30:22 PM PDT 24
Peak memory 216708 kb
Host smart-fddcca8c-9000-4283-bec6-8306389b1d4b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640512218 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.1640512218
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.4267385511
Short name T145
Test name
Test status
Simulation time 499740025 ps
CPU time 2.16 seconds
Started Jul 13 06:30:16 PM PDT 24
Finished Jul 13 06:30:19 PM PDT 24
Peak memory 207272 kb
Host smart-1014fc3f-6f89-4252-8ee8-5b93b0722f63
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267385511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
4267385511
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.1756599329
Short name T1106
Test name
Test status
Simulation time 69701387 ps
CPU time 0.78 seconds
Started Jul 13 06:30:13 PM PDT 24
Finished Jul 13 06:30:15 PM PDT 24
Peak memory 204516 kb
Host smart-c568748a-4f71-4c96-b757-d09e20501479
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756599329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
1756599329
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1566142309
Short name T146
Test name
Test status
Simulation time 157516500 ps
CPU time 4.09 seconds
Started Jul 13 06:30:19 PM PDT 24
Finished Jul 13 06:30:24 PM PDT 24
Peak memory 215716 kb
Host smart-ae91f7a8-a064-4385-9cf5-9da611ad01f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566142309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.1566142309
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1222163949
Short name T113
Test name
Test status
Simulation time 650608975 ps
CPU time 3.99 seconds
Started Jul 13 06:30:15 PM PDT 24
Finished Jul 13 06:30:20 PM PDT 24
Peak memory 215968 kb
Host smart-dc67d8cd-2fa1-43b6-80da-6985c8ea53ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222163949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
1222163949
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2769942261
Short name T162
Test name
Test status
Simulation time 219419037 ps
CPU time 2.89 seconds
Started Jul 13 06:30:15 PM PDT 24
Finished Jul 13 06:30:19 PM PDT 24
Peak memory 215948 kb
Host smart-61504cfa-f698-4a8b-9b1e-3c0d1aad1f06
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769942261 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.2769942261
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1567904913
Short name T1091
Test name
Test status
Simulation time 29483972 ps
CPU time 1.96 seconds
Started Jul 13 06:30:12 PM PDT 24
Finished Jul 13 06:30:15 PM PDT 24
Peak memory 215700 kb
Host smart-8d56a099-f743-4b5a-acf7-4e93b884fb49
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567904913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
1567904913
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.863968484
Short name T1090
Test name
Test status
Simulation time 13314196 ps
CPU time 0.74 seconds
Started Jul 13 06:30:15 PM PDT 24
Finished Jul 13 06:30:17 PM PDT 24
Peak memory 204180 kb
Host smart-21e6c673-3e43-485f-b272-a24b2bd60bd5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863968484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.863968484
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.362176932
Short name T1093
Test name
Test status
Simulation time 90496959 ps
CPU time 1.66 seconds
Started Jul 13 06:30:16 PM PDT 24
Finished Jul 13 06:30:19 PM PDT 24
Peak memory 207484 kb
Host smart-fa6f94fd-6c66-4f24-9d08-35dbf37f038f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362176932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.s
pi_device_same_csr_outstanding.362176932
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.601432407
Short name T112
Test name
Test status
Simulation time 69702179 ps
CPU time 2.03 seconds
Started Jul 13 06:30:16 PM PDT 24
Finished Jul 13 06:30:19 PM PDT 24
Peak memory 215988 kb
Host smart-c5c85c87-d183-4853-9b3d-716b45baf267
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601432407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.601432407
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.2837749858
Short name T179
Test name
Test status
Simulation time 198069069 ps
CPU time 13.12 seconds
Started Jul 13 06:30:12 PM PDT 24
Finished Jul 13 06:30:26 PM PDT 24
Peak memory 215684 kb
Host smart-cf0f487e-7dc1-4496-9d80-baddc67869cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837749858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.2837749858
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2099589959
Short name T1080
Test name
Test status
Simulation time 85183670 ps
CPU time 2.52 seconds
Started Jul 13 06:30:18 PM PDT 24
Finished Jul 13 06:30:21 PM PDT 24
Peak memory 216804 kb
Host smart-583e392b-0da8-4b40-adf6-2c68fff8f2e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099589959 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.2099589959
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1214672599
Short name T128
Test name
Test status
Simulation time 93022818 ps
CPU time 2.69 seconds
Started Jul 13 06:30:19 PM PDT 24
Finished Jul 13 06:30:23 PM PDT 24
Peak memory 215788 kb
Host smart-3d075d0f-4f43-4d06-8daa-998225eb7ad3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214672599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
1214672599
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2486246909
Short name T1036
Test name
Test status
Simulation time 48307615 ps
CPU time 0.76 seconds
Started Jul 13 06:30:20 PM PDT 24
Finished Jul 13 06:30:22 PM PDT 24
Peak memory 204268 kb
Host smart-d2e92fc2-ce0a-4e45-a11a-51ceb377a1c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486246909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
2486246909
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2902922019
Short name T1129
Test name
Test status
Simulation time 283820301 ps
CPU time 2.63 seconds
Started Jul 13 06:30:20 PM PDT 24
Finished Jul 13 06:30:24 PM PDT 24
Peak memory 215728 kb
Host smart-77a9f0ca-ddc3-436a-963f-807ac479e7f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902922019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.2902922019
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.911927568
Short name T1113
Test name
Test status
Simulation time 55818729 ps
CPU time 4.04 seconds
Started Jul 13 06:30:20 PM PDT 24
Finished Jul 13 06:30:26 PM PDT 24
Peak memory 216260 kb
Host smart-6a64bb91-2196-452a-ba74-4b2d582e61f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911927568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.911927568
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.1285552052
Short name T176
Test name
Test status
Simulation time 417326175 ps
CPU time 13.62 seconds
Started Jul 13 06:30:22 PM PDT 24
Finished Jul 13 06:30:36 PM PDT 24
Peak memory 216008 kb
Host smart-8304c352-517b-41ef-841d-7722424b080f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285552052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.1285552052
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1448311019
Short name T1053
Test name
Test status
Simulation time 190911197 ps
CPU time 1.95 seconds
Started Jul 13 06:30:20 PM PDT 24
Finished Jul 13 06:30:23 PM PDT 24
Peak memory 215828 kb
Host smart-b8d6ec34-b4e6-4c1c-b9ba-c2fcee643a27
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448311019 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.1448311019
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1436370128
Short name T1088
Test name
Test status
Simulation time 539830001 ps
CPU time 1.54 seconds
Started Jul 13 06:30:19 PM PDT 24
Finished Jul 13 06:30:22 PM PDT 24
Peak memory 215680 kb
Host smart-59483607-bc0d-4c11-b456-dd41d124e6c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436370128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
1436370128
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3746641986
Short name T1022
Test name
Test status
Simulation time 103244421 ps
CPU time 0.76 seconds
Started Jul 13 06:30:20 PM PDT 24
Finished Jul 13 06:30:22 PM PDT 24
Peak memory 204568 kb
Host smart-849150d3-31b0-44a1-8789-eb2067c9c705
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746641986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
3746641986
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.4093738446
Short name T1107
Test name
Test status
Simulation time 43400120 ps
CPU time 1.73 seconds
Started Jul 13 06:30:20 PM PDT 24
Finished Jul 13 06:30:23 PM PDT 24
Peak memory 215688 kb
Host smart-3e21a086-0670-46a4-88a8-ddd965940fe7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093738446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.4093738446
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.884830971
Short name T105
Test name
Test status
Simulation time 174672440 ps
CPU time 4.98 seconds
Started Jul 13 06:30:20 PM PDT 24
Finished Jul 13 06:30:27 PM PDT 24
Peak memory 217004 kb
Host smart-2e74c982-b683-43b4-a4a6-7f2b28c0e617
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884830971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.884830971
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3045500861
Short name T1122
Test name
Test status
Simulation time 541034065 ps
CPU time 13.06 seconds
Started Jul 13 06:30:22 PM PDT 24
Finished Jul 13 06:30:35 PM PDT 24
Peak memory 215956 kb
Host smart-41ce7eae-b468-420f-a5af-810505eeac39
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045500861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.3045500861
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.667035210
Short name T1085
Test name
Test status
Simulation time 156474073 ps
CPU time 3.86 seconds
Started Jul 13 06:30:22 PM PDT 24
Finished Jul 13 06:30:27 PM PDT 24
Peak memory 218688 kb
Host smart-2274514e-e9db-458f-a0fc-d1dba29c83e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667035210 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.667035210
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.258870502
Short name T1092
Test name
Test status
Simulation time 86820824 ps
CPU time 1.5 seconds
Started Jul 13 06:30:20 PM PDT 24
Finished Jul 13 06:30:22 PM PDT 24
Peak memory 215732 kb
Host smart-3ed3a843-9275-4191-b79f-f66fe3bb62e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258870502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.258870502
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.549558402
Short name T1110
Test name
Test status
Simulation time 14337497 ps
CPU time 0.74 seconds
Started Jul 13 06:30:19 PM PDT 24
Finished Jul 13 06:30:22 PM PDT 24
Peak memory 204236 kb
Host smart-4e09d2fb-c09d-4b53-9213-dabde099f080
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549558402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.549558402
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3549923120
Short name T161
Test name
Test status
Simulation time 324125112 ps
CPU time 2.12 seconds
Started Jul 13 06:30:18 PM PDT 24
Finished Jul 13 06:30:21 PM PDT 24
Peak memory 215736 kb
Host smart-b1532da8-da8b-40ee-942d-e6473d3e3123
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549923120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.3549923120
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2199477641
Short name T1119
Test name
Test status
Simulation time 277586908 ps
CPU time 3.21 seconds
Started Jul 13 06:30:18 PM PDT 24
Finished Jul 13 06:30:21 PM PDT 24
Peak memory 216968 kb
Host smart-63267a35-5d4b-4597-8c43-f0625b5ba01a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199477641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
2199477641
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2793289901
Short name T158
Test name
Test status
Simulation time 3704617834 ps
CPU time 8.29 seconds
Started Jul 13 06:30:19 PM PDT 24
Finished Jul 13 06:30:28 PM PDT 24
Peak memory 215928 kb
Host smart-8afe736c-dab3-43ab-9878-f34c1065dbd9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793289901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.2793289901
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3233792680
Short name T1054
Test name
Test status
Simulation time 28659122 ps
CPU time 1.72 seconds
Started Jul 13 06:30:21 PM PDT 24
Finished Jul 13 06:30:24 PM PDT 24
Peak memory 216876 kb
Host smart-7267ce7f-435d-431a-9600-b52f164751ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233792680 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.3233792680
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.2874886287
Short name T159
Test name
Test status
Simulation time 528325585 ps
CPU time 2.92 seconds
Started Jul 13 06:30:21 PM PDT 24
Finished Jul 13 06:30:25 PM PDT 24
Peak memory 215660 kb
Host smart-4ce59943-1105-4c6f-812e-2b552987f1c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874886287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
2874886287
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.1295102847
Short name T1128
Test name
Test status
Simulation time 11971829 ps
CPU time 0.72 seconds
Started Jul 13 06:30:20 PM PDT 24
Finished Jul 13 06:30:23 PM PDT 24
Peak memory 204256 kb
Host smart-84ad5833-e9ad-4348-ad7b-34e15d622df5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295102847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
1295102847
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1407319983
Short name T160
Test name
Test status
Simulation time 300529469 ps
CPU time 2.19 seconds
Started Jul 13 06:30:20 PM PDT 24
Finished Jul 13 06:30:23 PM PDT 24
Peak memory 215656 kb
Host smart-1af5ad50-478c-4f1a-ae15-98fca60d4e11
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407319983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.1407319983
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.2953008763
Short name T108
Test name
Test status
Simulation time 255356906 ps
CPU time 4.57 seconds
Started Jul 13 06:30:20 PM PDT 24
Finished Jul 13 06:30:26 PM PDT 24
Peak memory 216116 kb
Host smart-4df275d0-24e1-404a-8042-b69802328f5d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953008763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
2953008763
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.640293377
Short name T1058
Test name
Test status
Simulation time 788010732 ps
CPU time 13.06 seconds
Started Jul 13 06:30:19 PM PDT 24
Finished Jul 13 06:30:33 PM PDT 24
Peak memory 216100 kb
Host smart-5fab5264-7e29-4f20-9816-c2df45cfae68
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640293377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device
_tl_intg_err.640293377
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3561877760
Short name T1126
Test name
Test status
Simulation time 376060602 ps
CPU time 3.13 seconds
Started Jul 13 06:30:31 PM PDT 24
Finished Jul 13 06:30:36 PM PDT 24
Peak memory 217124 kb
Host smart-2d545785-66e3-42fa-9853-bc1daaaa15e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561877760 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.3561877760
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3450070781
Short name T121
Test name
Test status
Simulation time 371682864 ps
CPU time 2.87 seconds
Started Jul 13 06:30:22 PM PDT 24
Finished Jul 13 06:30:26 PM PDT 24
Peak memory 215892 kb
Host smart-bf4180d4-b211-44d1-9522-ed864eff8d53
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450070781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
3450070781
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.2619345606
Short name T1037
Test name
Test status
Simulation time 38938372 ps
CPU time 0.72 seconds
Started Jul 13 06:30:20 PM PDT 24
Finished Jul 13 06:30:22 PM PDT 24
Peak memory 204244 kb
Host smart-3694bcc4-76d3-41d2-bc5b-7ce67915b833
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619345606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
2619345606
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.820382840
Short name T143
Test name
Test status
Simulation time 280627224 ps
CPU time 2.08 seconds
Started Jul 13 06:30:30 PM PDT 24
Finished Jul 13 06:30:34 PM PDT 24
Peak memory 215712 kb
Host smart-b1813938-c03f-47e9-87fe-b82de184b54b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820382840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.s
pi_device_same_csr_outstanding.820382840
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3094988457
Short name T167
Test name
Test status
Simulation time 99230855 ps
CPU time 2.48 seconds
Started Jul 13 06:30:17 PM PDT 24
Finished Jul 13 06:30:20 PM PDT 24
Peak memory 215896 kb
Host smart-86df4486-ebc1-4a70-aa18-5330cb2df127
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094988457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
3094988457
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.362226709
Short name T177
Test name
Test status
Simulation time 206379597 ps
CPU time 14.6 seconds
Started Jul 13 06:30:20 PM PDT 24
Finished Jul 13 06:30:36 PM PDT 24
Peak memory 216988 kb
Host smart-995a10f4-3eae-4f2b-82cd-a35cb78fc169
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362226709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device
_tl_intg_err.362226709
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.200417851
Short name T1021
Test name
Test status
Simulation time 83844939 ps
CPU time 1.73 seconds
Started Jul 13 06:30:31 PM PDT 24
Finished Jul 13 06:30:35 PM PDT 24
Peak memory 215600 kb
Host smart-59e7ed8c-5fec-4a6a-b224-2ace3a86de02
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200417851 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.200417851
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2660547664
Short name T1101
Test name
Test status
Simulation time 132801695 ps
CPU time 2.37 seconds
Started Jul 13 06:30:29 PM PDT 24
Finished Jul 13 06:30:32 PM PDT 24
Peak memory 207552 kb
Host smart-7064c4ef-6a99-4fcc-9d06-6e0c256d364c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660547664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
2660547664
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2958337895
Short name T1052
Test name
Test status
Simulation time 16197513 ps
CPU time 0.77 seconds
Started Jul 13 06:30:33 PM PDT 24
Finished Jul 13 06:30:35 PM PDT 24
Peak memory 204444 kb
Host smart-9200aa07-fe04-4c14-8f56-b1e59f314477
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958337895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
2958337895
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2918595240
Short name T1042
Test name
Test status
Simulation time 230686286 ps
CPU time 3.49 seconds
Started Jul 13 06:30:30 PM PDT 24
Finished Jul 13 06:30:34 PM PDT 24
Peak memory 215764 kb
Host smart-cdd56185-ef6d-4e75-ab9e-55f8381b8154
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918595240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.2918595240
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2679678871
Short name T115
Test name
Test status
Simulation time 65121059 ps
CPU time 1.83 seconds
Started Jul 13 06:30:29 PM PDT 24
Finished Jul 13 06:30:31 PM PDT 24
Peak memory 215956 kb
Host smart-1a7e1f89-5ec9-4d02-a078-711024dd719d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679678871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
2679678871
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.4196653556
Short name T1081
Test name
Test status
Simulation time 3864882562 ps
CPU time 23.9 seconds
Started Jul 13 06:30:31 PM PDT 24
Finished Jul 13 06:30:57 PM PDT 24
Peak memory 215968 kb
Host smart-d20501fa-5e83-4979-8869-3b679b06c43c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196653556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.4196653556
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.340060484
Short name T1012
Test name
Test status
Simulation time 364613528 ps
CPU time 7.36 seconds
Started Jul 13 06:30:04 PM PDT 24
Finished Jul 13 06:30:13 PM PDT 24
Peak memory 215712 kb
Host smart-b60f7906-b3e4-4546-aca5-8bdae8ccb5f4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340060484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_aliasing.340060484
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2091737874
Short name T1014
Test name
Test status
Simulation time 1234876079 ps
CPU time 13.51 seconds
Started Jul 13 06:30:09 PM PDT 24
Finished Jul 13 06:30:24 PM PDT 24
Peak memory 207420 kb
Host smart-94f435e0-6bfa-4d1f-9dd7-57883f6c2f71
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091737874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.2091737874
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2008700210
Short name T98
Test name
Test status
Simulation time 31936992 ps
CPU time 1.26 seconds
Started Jul 13 06:30:02 PM PDT 24
Finished Jul 13 06:30:04 PM PDT 24
Peak memory 207496 kb
Host smart-f27bf48a-b9a2-4a42-a951-7109bf4a0826
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008700210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.2008700210
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2289529841
Short name T123
Test name
Test status
Simulation time 358285463 ps
CPU time 2.31 seconds
Started Jul 13 06:30:07 PM PDT 24
Finished Jul 13 06:30:12 PM PDT 24
Peak memory 215700 kb
Host smart-c31a216a-bcce-487f-aa1c-b2aeebc7e213
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289529841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.2
289529841
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.276534463
Short name T1124
Test name
Test status
Simulation time 60436050 ps
CPU time 0.76 seconds
Started Jul 13 06:30:06 PM PDT 24
Finished Jul 13 06:30:10 PM PDT 24
Peak memory 204556 kb
Host smart-d998f6d1-b7b5-42d5-beeb-da9382f71edc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276534463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.276534463
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.597940536
Short name T120
Test name
Test status
Simulation time 185556488 ps
CPU time 2.11 seconds
Started Jul 13 06:30:04 PM PDT 24
Finished Jul 13 06:30:08 PM PDT 24
Peak memory 215772 kb
Host smart-32d87a37-6190-4c02-874c-6021b56ac1fb
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597940536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_
device_mem_partial_access.597940536
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2294812129
Short name T1025
Test name
Test status
Simulation time 13648351 ps
CPU time 0.68 seconds
Started Jul 13 06:30:06 PM PDT 24
Finished Jul 13 06:30:10 PM PDT 24
Peak memory 204036 kb
Host smart-7b6b3b7e-69ce-43b2-b1c5-658841d85c65
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294812129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.2294812129
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2511203329
Short name T1026
Test name
Test status
Simulation time 178256569 ps
CPU time 2.92 seconds
Started Jul 13 06:30:04 PM PDT 24
Finished Jul 13 06:30:08 PM PDT 24
Peak memory 215808 kb
Host smart-c328c8e5-5675-4e59-b4eb-dcaba94be060
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511203329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.2511203329
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1179436823
Short name T1102
Test name
Test status
Simulation time 561442367 ps
CPU time 13.08 seconds
Started Jul 13 06:30:05 PM PDT 24
Finished Jul 13 06:30:21 PM PDT 24
Peak memory 215716 kb
Host smart-f887b362-fc6f-4d28-8e23-a3401d134a66
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179436823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.1179436823
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.3418386604
Short name T1019
Test name
Test status
Simulation time 17545458 ps
CPU time 0.72 seconds
Started Jul 13 06:30:30 PM PDT 24
Finished Jul 13 06:30:33 PM PDT 24
Peak memory 204612 kb
Host smart-85716432-95d8-441e-9de5-5fbc1512473b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418386604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
3418386604
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.1595002498
Short name T1072
Test name
Test status
Simulation time 25471320 ps
CPU time 0.73 seconds
Started Jul 13 06:30:29 PM PDT 24
Finished Jul 13 06:30:31 PM PDT 24
Peak memory 204584 kb
Host smart-9ae7c6c8-d150-4fe5-aad6-9d225ef0f30f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595002498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
1595002498
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.579759587
Short name T1096
Test name
Test status
Simulation time 40626818 ps
CPU time 0.74 seconds
Started Jul 13 06:30:31 PM PDT 24
Finished Jul 13 06:30:34 PM PDT 24
Peak memory 204600 kb
Host smart-c2130ebd-7f0c-41c1-9437-51c0dd918219
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579759587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.579759587
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.3207855406
Short name T1013
Test name
Test status
Simulation time 14954050 ps
CPU time 0.76 seconds
Started Jul 13 06:30:30 PM PDT 24
Finished Jul 13 06:30:32 PM PDT 24
Peak memory 204196 kb
Host smart-e825c5ff-6f84-4cea-9d8f-36ca6d37f9a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207855406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
3207855406
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.3329407658
Short name T1060
Test name
Test status
Simulation time 47244034 ps
CPU time 0.84 seconds
Started Jul 13 06:30:29 PM PDT 24
Finished Jul 13 06:30:31 PM PDT 24
Peak memory 204296 kb
Host smart-c92d2706-8d2a-482d-8d97-dc0f097c73cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329407658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
3329407658
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.2918393173
Short name T1095
Test name
Test status
Simulation time 14742878 ps
CPU time 0.84 seconds
Started Jul 13 06:30:31 PM PDT 24
Finished Jul 13 06:30:34 PM PDT 24
Peak memory 204268 kb
Host smart-b58d3d25-2f71-460b-a764-7dc0d4625347
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918393173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
2918393173
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2262699960
Short name T1038
Test name
Test status
Simulation time 16951970 ps
CPU time 0.77 seconds
Started Jul 13 06:30:30 PM PDT 24
Finished Jul 13 06:30:33 PM PDT 24
Peak memory 204576 kb
Host smart-6b282786-0e1f-40c9-b7c8-40ec57b24301
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262699960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
2262699960
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.2927706582
Short name T1023
Test name
Test status
Simulation time 48027151 ps
CPU time 0.8 seconds
Started Jul 13 06:30:30 PM PDT 24
Finished Jul 13 06:30:33 PM PDT 24
Peak memory 204296 kb
Host smart-d1b8fce2-d337-491f-ba9e-867d096c0571
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927706582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
2927706582
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1257413021
Short name T1044
Test name
Test status
Simulation time 88872984 ps
CPU time 0.75 seconds
Started Jul 13 06:30:31 PM PDT 24
Finished Jul 13 06:30:34 PM PDT 24
Peak memory 204380 kb
Host smart-0b1833da-81e0-4260-a986-e69f5c0832c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257413021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
1257413021
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2255088158
Short name T1121
Test name
Test status
Simulation time 17991833 ps
CPU time 0.72 seconds
Started Jul 13 06:30:31 PM PDT 24
Finished Jul 13 06:30:34 PM PDT 24
Peak memory 204516 kb
Host smart-a5265461-0484-412a-b3c2-ea118a25729a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255088158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
2255088158
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2844320673
Short name T127
Test name
Test status
Simulation time 427326016 ps
CPU time 16.12 seconds
Started Jul 13 06:30:07 PM PDT 24
Finished Jul 13 06:30:25 PM PDT 24
Peak memory 207504 kb
Host smart-1862bd2f-4b84-41fb-84e5-ba090d5cc50a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844320673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.2844320673
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.959373208
Short name T157
Test name
Test status
Simulation time 12353492159 ps
CPU time 42.14 seconds
Started Jul 13 06:30:04 PM PDT 24
Finished Jul 13 06:30:48 PM PDT 24
Peak memory 207544 kb
Host smart-f4a8e40a-81d8-43e9-b529-523809cbf7ac
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959373208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_bit_bash.959373208
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1574601417
Short name T1055
Test name
Test status
Simulation time 20620000 ps
CPU time 0.95 seconds
Started Jul 13 06:30:07 PM PDT 24
Finished Jul 13 06:30:10 PM PDT 24
Peak memory 207076 kb
Host smart-bc56c29f-5e40-4a4d-b7a3-2d68b9dc6fe7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574601417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.1574601417
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3114291734
Short name T119
Test name
Test status
Simulation time 53681466 ps
CPU time 1.84 seconds
Started Jul 13 06:30:05 PM PDT 24
Finished Jul 13 06:30:09 PM PDT 24
Peak memory 215852 kb
Host smart-dd7dbdeb-6fa7-42f2-9e67-88d45ce3022e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114291734 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.3114291734
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.3196340559
Short name T1097
Test name
Test status
Simulation time 43271467 ps
CPU time 1.22 seconds
Started Jul 13 06:30:05 PM PDT 24
Finished Jul 13 06:30:09 PM PDT 24
Peak memory 215736 kb
Host smart-9a98ee6b-f4bc-4256-917e-0cc3b030cadf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196340559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.3
196340559
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.1418086648
Short name T1118
Test name
Test status
Simulation time 23371355 ps
CPU time 0.76 seconds
Started Jul 13 06:30:04 PM PDT 24
Finished Jul 13 06:30:06 PM PDT 24
Peak memory 204260 kb
Host smart-b3213a24-cf4f-43bb-8cc1-24b00bf499ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418086648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.1
418086648
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.882633363
Short name T122
Test name
Test status
Simulation time 43699223 ps
CPU time 1.44 seconds
Started Jul 13 06:30:04 PM PDT 24
Finished Jul 13 06:30:07 PM PDT 24
Peak memory 215716 kb
Host smart-30e6a4b9-9d16-4a35-8faf-2b10d45cc4ef
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882633363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_
device_mem_partial_access.882633363
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.4152294627
Short name T1099
Test name
Test status
Simulation time 12030078 ps
CPU time 0.7 seconds
Started Jul 13 06:30:08 PM PDT 24
Finished Jul 13 06:30:11 PM PDT 24
Peak memory 203988 kb
Host smart-fa63459b-0e2b-4446-b2e9-35c43a429d4d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152294627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.4152294627
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1720611436
Short name T1051
Test name
Test status
Simulation time 45193391 ps
CPU time 2.81 seconds
Started Jul 13 06:30:06 PM PDT 24
Finished Jul 13 06:30:12 PM PDT 24
Peak memory 215700 kb
Host smart-6dd7324a-a4b9-4030-89e5-689e0f349e4c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720611436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.1720611436
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2150411483
Short name T117
Test name
Test status
Simulation time 126487590 ps
CPU time 3.54 seconds
Started Jul 13 06:30:07 PM PDT 24
Finished Jul 13 06:30:13 PM PDT 24
Peak memory 216128 kb
Host smart-7f0498be-e69a-404d-b646-e3bce90616dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150411483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.2
150411483
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2922189560
Short name T1125
Test name
Test status
Simulation time 3391911528 ps
CPU time 22.81 seconds
Started Jul 13 06:30:04 PM PDT 24
Finished Jul 13 06:30:29 PM PDT 24
Peak memory 215836 kb
Host smart-8b58ac57-9fbe-47ac-af67-a07e418fd289
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922189560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.2922189560
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.221913365
Short name T1105
Test name
Test status
Simulation time 75107631 ps
CPU time 0.77 seconds
Started Jul 13 06:30:30 PM PDT 24
Finished Jul 13 06:30:32 PM PDT 24
Peak memory 204260 kb
Host smart-9ae32aa1-636d-498b-b3e5-2eea7c364244
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221913365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.221913365
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3031232753
Short name T1031
Test name
Test status
Simulation time 10837527 ps
CPU time 0.71 seconds
Started Jul 13 06:30:26 PM PDT 24
Finished Jul 13 06:30:27 PM PDT 24
Peak memory 204220 kb
Host smart-3452fdbb-3b25-4dda-b497-db7b55941f8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031232753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
3031232753
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.985251898
Short name T1017
Test name
Test status
Simulation time 24877393 ps
CPU time 0.78 seconds
Started Jul 13 06:30:30 PM PDT 24
Finished Jul 13 06:30:32 PM PDT 24
Peak memory 204268 kb
Host smart-3b687eb2-e9c6-4992-9075-d71cf434bafe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985251898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.985251898
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.2170846515
Short name T1103
Test name
Test status
Simulation time 23874127 ps
CPU time 0.77 seconds
Started Jul 13 06:30:31 PM PDT 24
Finished Jul 13 06:30:33 PM PDT 24
Peak memory 204580 kb
Host smart-1b9579a9-8adc-4d60-8a46-5a7153e7dc1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170846515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
2170846515
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1013777035
Short name T1018
Test name
Test status
Simulation time 14259181 ps
CPU time 0.72 seconds
Started Jul 13 06:30:31 PM PDT 24
Finished Jul 13 06:30:34 PM PDT 24
Peak memory 204496 kb
Host smart-e2bf2f7c-7254-41bb-8c30-4c9ecebe28df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013777035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
1013777035
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1420706779
Short name T1033
Test name
Test status
Simulation time 36932285 ps
CPU time 0.75 seconds
Started Jul 13 06:30:28 PM PDT 24
Finished Jul 13 06:30:29 PM PDT 24
Peak memory 204648 kb
Host smart-6a2030b8-2262-48ec-960e-ebc364c25c2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420706779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
1420706779
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1715675943
Short name T1065
Test name
Test status
Simulation time 21415820 ps
CPU time 0.73 seconds
Started Jul 13 06:30:30 PM PDT 24
Finished Jul 13 06:30:33 PM PDT 24
Peak memory 204324 kb
Host smart-ac0ce942-3e07-4d83-9c1b-d30167738860
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715675943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
1715675943
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.1118395988
Short name T1016
Test name
Test status
Simulation time 37148118 ps
CPU time 0.71 seconds
Started Jul 13 06:30:31 PM PDT 24
Finished Jul 13 06:30:33 PM PDT 24
Peak memory 204516 kb
Host smart-a8339df8-aa2a-4e88-a411-ba12081bcf5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118395988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
1118395988
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3218225138
Short name T1069
Test name
Test status
Simulation time 29743378 ps
CPU time 0.81 seconds
Started Jul 13 06:30:30 PM PDT 24
Finished Jul 13 06:30:32 PM PDT 24
Peak memory 204580 kb
Host smart-1358269f-e944-4976-bdcf-a060c917fa78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218225138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
3218225138
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1094904075
Short name T1024
Test name
Test status
Simulation time 29470024 ps
CPU time 0.69 seconds
Started Jul 13 06:30:29 PM PDT 24
Finished Jul 13 06:30:31 PM PDT 24
Peak memory 204244 kb
Host smart-58bad130-b5f8-4a34-8fb6-21e378dce448
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094904075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
1094904075
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.4128921291
Short name T1104
Test name
Test status
Simulation time 598805941 ps
CPU time 20.92 seconds
Started Jul 13 06:30:05 PM PDT 24
Finished Jul 13 06:30:28 PM PDT 24
Peak memory 215672 kb
Host smart-9d581868-08f5-4cd6-9210-9101550b1673
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128921291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.4128921291
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2390652084
Short name T129
Test name
Test status
Simulation time 818532795 ps
CPU time 13.14 seconds
Started Jul 13 06:30:06 PM PDT 24
Finished Jul 13 06:30:22 PM PDT 24
Peak memory 207260 kb
Host smart-8cdd3bc3-305b-40c5-bed6-7360fe6674dc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390652084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.2390652084
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.816852548
Short name T155
Test name
Test status
Simulation time 25003831 ps
CPU time 0.99 seconds
Started Jul 13 06:30:04 PM PDT 24
Finished Jul 13 06:30:07 PM PDT 24
Peak memory 207220 kb
Host smart-338d4a55-e283-43a7-9b27-8d397cd0f9fd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816852548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_hw_reset.816852548
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3028454077
Short name T76
Test name
Test status
Simulation time 146420604 ps
CPU time 2.67 seconds
Started Jul 13 06:30:06 PM PDT 24
Finished Jul 13 06:30:12 PM PDT 24
Peak memory 218172 kb
Host smart-6623e0c9-be51-404f-bdfd-953894b31b1b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028454077 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.3028454077
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.4041857685
Short name T1111
Test name
Test status
Simulation time 45330297 ps
CPU time 2.01 seconds
Started Jul 13 06:30:05 PM PDT 24
Finished Jul 13 06:30:10 PM PDT 24
Peak memory 215732 kb
Host smart-83f77e78-2469-4f87-b9be-70f878a5c0b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041857685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.4
041857685
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.510887762
Short name T1074
Test name
Test status
Simulation time 48469532 ps
CPU time 0.78 seconds
Started Jul 13 06:30:05 PM PDT 24
Finished Jul 13 06:30:08 PM PDT 24
Peak memory 204268 kb
Host smart-0af254bd-3338-4b9b-b492-d18927dff53f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510887762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.510887762
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.403130896
Short name T1050
Test name
Test status
Simulation time 57041376 ps
CPU time 1.36 seconds
Started Jul 13 06:30:06 PM PDT 24
Finished Jul 13 06:30:10 PM PDT 24
Peak memory 215712 kb
Host smart-bff15be1-c2d1-4115-b613-500fe0b3517f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403130896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_
device_mem_partial_access.403130896
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.3547042993
Short name T1045
Test name
Test status
Simulation time 16288393 ps
CPU time 0.71 seconds
Started Jul 13 06:30:06 PM PDT 24
Finished Jul 13 06:30:09 PM PDT 24
Peak memory 204392 kb
Host smart-b7bc4d3f-c60b-4dd7-a520-3d364d55bb3f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547042993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.3547042993
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1959734433
Short name T1020
Test name
Test status
Simulation time 315881803 ps
CPU time 3.6 seconds
Started Jul 13 06:30:09 PM PDT 24
Finished Jul 13 06:30:14 PM PDT 24
Peak memory 215608 kb
Host smart-4734ecd8-dfce-414f-8dc8-3659875c6421
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959734433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.1959734433
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2834219989
Short name T1041
Test name
Test status
Simulation time 167523879 ps
CPU time 2.11 seconds
Started Jul 13 06:30:07 PM PDT 24
Finished Jul 13 06:30:12 PM PDT 24
Peak memory 216040 kb
Host smart-251e1c28-7c77-48b4-ad82-e9e10da54fb8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834219989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.2
834219989
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.4288000217
Short name T1077
Test name
Test status
Simulation time 16942726 ps
CPU time 0.77 seconds
Started Jul 13 06:30:30 PM PDT 24
Finished Jul 13 06:30:33 PM PDT 24
Peak memory 204604 kb
Host smart-9d0d029e-bcba-4c16-a657-74623fbdf3c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288000217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
4288000217
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.2914923933
Short name T1117
Test name
Test status
Simulation time 10835823 ps
CPU time 0.72 seconds
Started Jul 13 06:30:31 PM PDT 24
Finished Jul 13 06:30:34 PM PDT 24
Peak memory 204260 kb
Host smart-089123c6-2957-48f3-a3b9-cf917fa9efe2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914923933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
2914923933
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.2466396341
Short name T1098
Test name
Test status
Simulation time 13719653 ps
CPU time 0.73 seconds
Started Jul 13 06:30:31 PM PDT 24
Finished Jul 13 06:30:34 PM PDT 24
Peak memory 204200 kb
Host smart-f8fff787-7b9d-4f13-8b5a-6ca6ff575ad7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466396341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
2466396341
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2767667674
Short name T1083
Test name
Test status
Simulation time 45324016 ps
CPU time 0.73 seconds
Started Jul 13 06:30:28 PM PDT 24
Finished Jul 13 06:30:30 PM PDT 24
Peak memory 204256 kb
Host smart-48579ca3-d107-4638-a8b6-d51478d43f32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767667674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
2767667674
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1819093557
Short name T1035
Test name
Test status
Simulation time 12737863 ps
CPU time 0.74 seconds
Started Jul 13 06:30:29 PM PDT 24
Finished Jul 13 06:30:30 PM PDT 24
Peak memory 204236 kb
Host smart-cf116183-e7d0-4d2b-b65f-360e63818e3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819093557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
1819093557
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3094993158
Short name T1112
Test name
Test status
Simulation time 155801609 ps
CPU time 0.73 seconds
Started Jul 13 06:30:29 PM PDT 24
Finished Jul 13 06:30:31 PM PDT 24
Peak memory 204252 kb
Host smart-2d216827-98db-444c-a80d-0ca2de88842b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094993158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
3094993158
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2811154354
Short name T1040
Test name
Test status
Simulation time 52962700 ps
CPU time 0.78 seconds
Started Jul 13 06:30:30 PM PDT 24
Finished Jul 13 06:30:32 PM PDT 24
Peak memory 204276 kb
Host smart-87772dc4-f76a-4bdd-84f4-64cede54ab97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811154354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
2811154354
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.4174433611
Short name T1046
Test name
Test status
Simulation time 43318155 ps
CPU time 0.74 seconds
Started Jul 13 06:30:30 PM PDT 24
Finished Jul 13 06:30:33 PM PDT 24
Peak memory 204192 kb
Host smart-896925c7-3e6f-40c2-8a06-5d468f228374
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174433611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
4174433611
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.492064134
Short name T1123
Test name
Test status
Simulation time 42891665 ps
CPU time 0.79 seconds
Started Jul 13 06:30:31 PM PDT 24
Finished Jul 13 06:30:34 PM PDT 24
Peak memory 204284 kb
Host smart-77e47eff-60cd-481d-89d6-b7288eb9f5f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492064134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.492064134
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.4068486061
Short name T1015
Test name
Test status
Simulation time 35843523 ps
CPU time 0.8 seconds
Started Jul 13 06:30:31 PM PDT 24
Finished Jul 13 06:30:34 PM PDT 24
Peak memory 204552 kb
Host smart-90f68f09-ac7f-4ba6-90cf-1880b73880af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068486061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
4068486061
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.3177115198
Short name T75
Test name
Test status
Simulation time 82807489 ps
CPU time 1.73 seconds
Started Jul 13 06:30:13 PM PDT 24
Finished Jul 13 06:30:16 PM PDT 24
Peak memory 215892 kb
Host smart-1b4d04c1-9293-4e54-a82a-8443c9d0ab8c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177115198 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.3177115198
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3558920321
Short name T1059
Test name
Test status
Simulation time 18180402 ps
CPU time 1.25 seconds
Started Jul 13 06:30:12 PM PDT 24
Finished Jul 13 06:30:14 PM PDT 24
Peak memory 207468 kb
Host smart-5696ee95-b64c-440f-93ad-d5d8371b2a99
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558920321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.3
558920321
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3926062388
Short name T1049
Test name
Test status
Simulation time 44422566 ps
CPU time 0.73 seconds
Started Jul 13 06:30:11 PM PDT 24
Finished Jul 13 06:30:13 PM PDT 24
Peak memory 204600 kb
Host smart-bf1f426f-6cca-45ec-9eb4-50d1b0617f6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926062388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.3
926062388
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3101278492
Short name T1048
Test name
Test status
Simulation time 47241407 ps
CPU time 1.73 seconds
Started Jul 13 06:30:13 PM PDT 24
Finished Jul 13 06:30:16 PM PDT 24
Peak memory 215756 kb
Host smart-31e0fb5a-8b85-4118-a091-0532d802ff33
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101278492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.3101278492
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.811385348
Short name T111
Test name
Test status
Simulation time 55863326 ps
CPU time 3.79 seconds
Started Jul 13 06:30:05 PM PDT 24
Finished Jul 13 06:30:12 PM PDT 24
Peak memory 217252 kb
Host smart-8eae4fea-2fb7-4f98-92fc-e07f2910883f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811385348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.811385348
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.617790937
Short name T107
Test name
Test status
Simulation time 2065950545 ps
CPU time 12.97 seconds
Started Jul 13 06:30:05 PM PDT 24
Finished Jul 13 06:30:20 PM PDT 24
Peak memory 215716 kb
Host smart-b3ad3870-955b-4522-bbeb-7a83db2105b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617790937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_
tl_intg_err.617790937
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2832839812
Short name T1116
Test name
Test status
Simulation time 548979890 ps
CPU time 3.49 seconds
Started Jul 13 06:30:12 PM PDT 24
Finished Jul 13 06:30:17 PM PDT 24
Peak memory 217648 kb
Host smart-bffab2d6-ca34-4042-99e6-664ffa432b3e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832839812 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.2832839812
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.3266465836
Short name T1057
Test name
Test status
Simulation time 178654165 ps
CPU time 1.39 seconds
Started Jul 13 06:30:16 PM PDT 24
Finished Jul 13 06:30:19 PM PDT 24
Peak memory 215656 kb
Host smart-7b756cc7-c19f-4fb0-9637-78bea5c32632
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266465836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.3
266465836
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.3098561300
Short name T1079
Test name
Test status
Simulation time 15388249 ps
CPU time 0.74 seconds
Started Jul 13 06:30:15 PM PDT 24
Finished Jul 13 06:30:18 PM PDT 24
Peak memory 204608 kb
Host smart-5e986763-0736-4617-80f2-39ec554858c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098561300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.3
098561300
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.427699737
Short name T1039
Test name
Test status
Simulation time 45909668 ps
CPU time 3.28 seconds
Started Jul 13 06:30:11 PM PDT 24
Finished Jul 13 06:30:15 PM PDT 24
Peak memory 215696 kb
Host smart-7f5b7782-fb6b-4297-8e2c-38b3341f9f7e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427699737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sp
i_device_same_csr_outstanding.427699737
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.3723199554
Short name T170
Test name
Test status
Simulation time 188769969 ps
CPU time 2.87 seconds
Started Jul 13 06:30:16 PM PDT 24
Finished Jul 13 06:30:20 PM PDT 24
Peak memory 215684 kb
Host smart-ad2edc72-a1f5-4da0-a090-a729e9a9791f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723199554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.3
723199554
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.5376511
Short name T106
Test name
Test status
Simulation time 397993715 ps
CPU time 6.93 seconds
Started Jul 13 06:30:14 PM PDT 24
Finished Jul 13 06:30:23 PM PDT 24
Peak memory 215664 kb
Host smart-1f0e633b-8968-4c76-a610-c529035899cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5376511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl
_intg_err.5376511
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1190235665
Short name T1078
Test name
Test status
Simulation time 95051861 ps
CPU time 2.99 seconds
Started Jul 13 06:30:17 PM PDT 24
Finished Jul 13 06:30:21 PM PDT 24
Peak memory 216832 kb
Host smart-b520522f-1ebb-4634-8c90-da35ce8a3afe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190235665 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.1190235665
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1962311554
Short name T144
Test name
Test status
Simulation time 59842842 ps
CPU time 1.33 seconds
Started Jul 13 06:30:15 PM PDT 24
Finished Jul 13 06:30:17 PM PDT 24
Peak memory 215728 kb
Host smart-72026797-3c88-4165-bf6f-ce2d898047b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962311554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.1
962311554
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.1258838111
Short name T1032
Test name
Test status
Simulation time 13887609 ps
CPU time 0.73 seconds
Started Jul 13 06:30:12 PM PDT 24
Finished Jul 13 06:30:14 PM PDT 24
Peak memory 204260 kb
Host smart-33e739f3-01b2-43eb-9925-1747a181679e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258838111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.1
258838111
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.414563533
Short name T147
Test name
Test status
Simulation time 98526807 ps
CPU time 1.9 seconds
Started Jul 13 06:30:15 PM PDT 24
Finished Jul 13 06:30:18 PM PDT 24
Peak memory 215660 kb
Host smart-170693d9-2262-4af5-9dc5-c919ca852691
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414563533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sp
i_device_same_csr_outstanding.414563533
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2238981908
Short name T116
Test name
Test status
Simulation time 302470710 ps
CPU time 2.59 seconds
Started Jul 13 06:30:13 PM PDT 24
Finished Jul 13 06:30:16 PM PDT 24
Peak memory 216028 kb
Host smart-2c6711bc-5827-4cde-82dc-f9ca7780d3d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238981908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.2
238981908
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.2349296211
Short name T1029
Test name
Test status
Simulation time 1336686750 ps
CPU time 18.22 seconds
Started Jul 13 06:30:13 PM PDT 24
Finished Jul 13 06:30:32 PM PDT 24
Peak memory 215724 kb
Host smart-72c7f0e8-00e0-4056-a4ae-91ffd2bcd111
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349296211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.2349296211
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2560963758
Short name T1056
Test name
Test status
Simulation time 388968226 ps
CPU time 2.78 seconds
Started Jul 13 06:30:15 PM PDT 24
Finished Jul 13 06:30:19 PM PDT 24
Peak memory 218048 kb
Host smart-f7169c2d-7359-4c42-b7a7-0a2e2d88717a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560963758 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.2560963758
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.4138795297
Short name T124
Test name
Test status
Simulation time 116299322 ps
CPU time 2.03 seconds
Started Jul 13 06:30:14 PM PDT 24
Finished Jul 13 06:30:17 PM PDT 24
Peak memory 207480 kb
Host smart-d1fa153c-caf1-40de-a30c-c82d8e678c41
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138795297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.4
138795297
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3571186853
Short name T1084
Test name
Test status
Simulation time 50370610 ps
CPU time 0.81 seconds
Started Jul 13 06:30:11 PM PDT 24
Finished Jul 13 06:30:13 PM PDT 24
Peak memory 204260 kb
Host smart-ccf090d5-f97f-4201-950b-7888ef353afa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571186853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.3
571186853
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2095640598
Short name T1114
Test name
Test status
Simulation time 500390881 ps
CPU time 2.98 seconds
Started Jul 13 06:30:17 PM PDT 24
Finished Jul 13 06:30:21 PM PDT 24
Peak memory 215660 kb
Host smart-c49f6824-4057-4330-bbc4-514e15858492
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095640598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.2095640598
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.3477012362
Short name T109
Test name
Test status
Simulation time 224260406 ps
CPU time 2.91 seconds
Started Jul 13 06:30:13 PM PDT 24
Finished Jul 13 06:30:17 PM PDT 24
Peak memory 215972 kb
Host smart-1e44c3f9-7e96-4dab-9086-b35c0ded7ff5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477012362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.3
477012362
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1529021769
Short name T178
Test name
Test status
Simulation time 202435905 ps
CPU time 13.32 seconds
Started Jul 13 06:30:13 PM PDT 24
Finished Jul 13 06:30:28 PM PDT 24
Peak memory 216176 kb
Host smart-ae500297-5c0c-4059-8a28-bb65cd1233b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529021769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.1529021769
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.130135870
Short name T1067
Test name
Test status
Simulation time 163614010 ps
CPU time 3.98 seconds
Started Jul 13 06:30:14 PM PDT 24
Finished Jul 13 06:30:20 PM PDT 24
Peak memory 218980 kb
Host smart-cdcee19e-7dda-4d21-a744-8ea7ecacc216
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130135870 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.130135870
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.1835302720
Short name T1071
Test name
Test status
Simulation time 22688402 ps
CPU time 1.41 seconds
Started Jul 13 06:30:19 PM PDT 24
Finished Jul 13 06:30:22 PM PDT 24
Peak memory 207328 kb
Host smart-347f661a-4b67-4f22-98ba-c6e00a45b15a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835302720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.1
835302720
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.1634909440
Short name T1066
Test name
Test status
Simulation time 39642631 ps
CPU time 0.71 seconds
Started Jul 13 06:30:11 PM PDT 24
Finished Jul 13 06:30:13 PM PDT 24
Peak memory 204208 kb
Host smart-d6b6fbd1-d134-4429-8246-005199b7c1a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634909440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.1
634909440
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3229581701
Short name T1034
Test name
Test status
Simulation time 230199432 ps
CPU time 2.16 seconds
Started Jul 13 06:30:12 PM PDT 24
Finished Jul 13 06:30:15 PM PDT 24
Peak memory 215640 kb
Host smart-eba2150f-e721-4c19-b585-1c96d1483134
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229581701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.3229581701
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2494958989
Short name T1120
Test name
Test status
Simulation time 362407286 ps
CPU time 5.06 seconds
Started Jul 13 06:30:15 PM PDT 24
Finished Jul 13 06:30:21 PM PDT 24
Peak memory 215984 kb
Host smart-849eff09-07e8-4544-88a6-234ba84c79ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494958989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.2
494958989
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2334661291
Short name T118
Test name
Test status
Simulation time 1249828779 ps
CPU time 19.37 seconds
Started Jul 13 06:30:13 PM PDT 24
Finished Jul 13 06:30:34 PM PDT 24
Peak memory 215624 kb
Host smart-d4c396c2-e280-44ef-adf8-fe036b55e477
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334661291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.2334661291
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.1678598868
Short name T585
Test name
Test status
Simulation time 14303364 ps
CPU time 0.71 seconds
Started Jul 13 06:59:03 PM PDT 24
Finished Jul 13 06:59:06 PM PDT 24
Peak memory 205864 kb
Host smart-9160db47-a13c-4445-9cd6-7c7a0246a1aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678598868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.1
678598868
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.3258202878
Short name T821
Test name
Test status
Simulation time 617862624 ps
CPU time 8.85 seconds
Started Jul 13 06:59:04 PM PDT 24
Finished Jul 13 06:59:15 PM PDT 24
Peak memory 224460 kb
Host smart-fb975057-263a-4747-84ef-963fe3042cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258202878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.3258202878
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.75354128
Short name T31
Test name
Test status
Simulation time 38775814 ps
CPU time 0.78 seconds
Started Jul 13 06:59:03 PM PDT 24
Finished Jul 13 06:59:06 PM PDT 24
Peak memory 206936 kb
Host smart-084bbfc5-4870-4f07-a045-735a7a598708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75354128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.75354128
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.1928449179
Short name T520
Test name
Test status
Simulation time 37206548747 ps
CPU time 75.85 seconds
Started Jul 13 06:59:04 PM PDT 24
Finished Jul 13 07:00:22 PM PDT 24
Peak memory 239544 kb
Host smart-e6fbafd3-2d6a-4f4b-a293-5e61186966a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928449179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.1928449179
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.3278051511
Short name T890
Test name
Test status
Simulation time 114855095399 ps
CPU time 548.94 seconds
Started Jul 13 06:59:11 PM PDT 24
Finished Jul 13 07:08:22 PM PDT 24
Peak memory 266672 kb
Host smart-00fa7bc0-13fa-4fde-80d0-f1fe25143eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278051511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.3278051511
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.828726050
Short name T84
Test name
Test status
Simulation time 5046991423 ps
CPU time 42.6 seconds
Started Jul 13 06:58:58 PM PDT 24
Finished Jul 13 06:59:42 PM PDT 24
Peak memory 224664 kb
Host smart-0ec10bb2-f044-4d8f-9e64-3305704460a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828726050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle.
828726050
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.1209137025
Short name T551
Test name
Test status
Simulation time 23018861 ps
CPU time 0.83 seconds
Started Jul 13 06:59:01 PM PDT 24
Finished Jul 13 06:59:04 PM PDT 24
Peak memory 215944 kb
Host smart-5d4efd12-3e87-4c8c-907a-f30eb746c271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209137025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds
.1209137025
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_intercept.1870040042
Short name T880
Test name
Test status
Simulation time 223781179 ps
CPU time 4.35 seconds
Started Jul 13 06:59:01 PM PDT 24
Finished Jul 13 06:59:07 PM PDT 24
Peak memory 232544 kb
Host smart-7d23f85f-929a-4a6f-b38c-3eb056f9ef55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870040042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.1870040042
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.509394028
Short name T859
Test name
Test status
Simulation time 57808593 ps
CPU time 2.85 seconds
Started Jul 13 06:59:02 PM PDT 24
Finished Jul 13 06:59:07 PM PDT 24
Peak memory 232640 kb
Host smart-44f38446-b77a-4a57-bbae-8d47f5ff6235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509394028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.509394028
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.3106516860
Short name T210
Test name
Test status
Simulation time 72907161 ps
CPU time 2.84 seconds
Started Jul 13 06:59:01 PM PDT 24
Finished Jul 13 06:59:05 PM PDT 24
Peak memory 232700 kb
Host smart-a0ccbd40-db4c-4de7-b235-4d520b93948a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106516860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.3106516860
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.4035630738
Short name T265
Test name
Test status
Simulation time 30787027133 ps
CPU time 24.7 seconds
Started Jul 13 06:59:01 PM PDT 24
Finished Jul 13 06:59:28 PM PDT 24
Peak memory 239652 kb
Host smart-b995874c-5a46-4094-8bde-1e468e67fe0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035630738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.4035630738
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.2452972440
Short name T132
Test name
Test status
Simulation time 1183731725 ps
CPU time 12.2 seconds
Started Jul 13 06:59:03 PM PDT 24
Finished Jul 13 06:59:17 PM PDT 24
Peak memory 222088 kb
Host smart-ede5c31b-6408-44d1-a626-4b3a1e4a0774
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2452972440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.2452972440
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.1973669748
Short name T904
Test name
Test status
Simulation time 253834235 ps
CPU time 2.74 seconds
Started Jul 13 06:59:04 PM PDT 24
Finished Jul 13 06:59:09 PM PDT 24
Peak memory 218192 kb
Host smart-ba8667f4-3bc1-4a59-a77e-2480720ef780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973669748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.1973669748
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.3391620098
Short name T690
Test name
Test status
Simulation time 2804330819 ps
CPU time 8.16 seconds
Started Jul 13 06:59:04 PM PDT 24
Finished Jul 13 06:59:15 PM PDT 24
Peak memory 216348 kb
Host smart-710ec61f-1a46-4fb8-bb40-a2e75c8ed585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391620098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.3391620098
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.692703019
Short name T738
Test name
Test status
Simulation time 143967894 ps
CPU time 1.08 seconds
Started Jul 13 06:59:02 PM PDT 24
Finished Jul 13 06:59:05 PM PDT 24
Peak memory 207268 kb
Host smart-4bc47126-e80f-409e-abac-8c5efc79a180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692703019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.692703019
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.3455191811
Short name T320
Test name
Test status
Simulation time 19401776 ps
CPU time 0.73 seconds
Started Jul 13 06:59:05 PM PDT 24
Finished Jul 13 06:59:07 PM PDT 24
Peak memory 205660 kb
Host smart-1f219e4f-6ec0-40c5-8803-bd4f689cdaaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455191811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.3455191811
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.3519781631
Short name T193
Test name
Test status
Simulation time 4602611621 ps
CPU time 8.84 seconds
Started Jul 13 06:59:01 PM PDT 24
Finished Jul 13 06:59:12 PM PDT 24
Peak memory 224860 kb
Host smart-4a93f392-6e6e-45f5-afbc-f0c22c3ebb5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519781631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.3519781631
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.804137643
Short name T835
Test name
Test status
Simulation time 11796777 ps
CPU time 0.72 seconds
Started Jul 13 06:59:12 PM PDT 24
Finished Jul 13 06:59:15 PM PDT 24
Peak memory 204988 kb
Host smart-631298a7-5ab7-4963-9b07-50e7c71f0161
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804137643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.804137643
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.4059146003
Short name T396
Test name
Test status
Simulation time 432309107 ps
CPU time 2.31 seconds
Started Jul 13 06:59:04 PM PDT 24
Finished Jul 13 06:59:09 PM PDT 24
Peak memory 224072 kb
Host smart-3ab42db4-4e0e-4ca2-ab7c-0cca4b7f2c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059146003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.4059146003
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.36055447
Short name T831
Test name
Test status
Simulation time 47675864 ps
CPU time 0.77 seconds
Started Jul 13 06:59:02 PM PDT 24
Finished Jul 13 06:59:05 PM PDT 24
Peak memory 206624 kb
Host smart-66562f43-c05c-4843-9f17-43d29b20730a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36055447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.36055447
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.2618097016
Short name T43
Test name
Test status
Simulation time 17969615264 ps
CPU time 69.15 seconds
Started Jul 13 06:59:08 PM PDT 24
Finished Jul 13 07:00:18 PM PDT 24
Peak memory 249212 kb
Host smart-e20863b2-1a25-4aea-aadc-69f34512becf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618097016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.2618097016
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.1487765257
Short name T828
Test name
Test status
Simulation time 25396065881 ps
CPU time 89.02 seconds
Started Jul 13 06:59:06 PM PDT 24
Finished Jul 13 07:00:36 PM PDT 24
Peak memory 249564 kb
Host smart-9d6e58cb-c4c7-4c4e-82c4-27eb9aec628f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487765257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.1487765257
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.128996049
Short name T25
Test name
Test status
Simulation time 14566146205 ps
CPU time 119.69 seconds
Started Jul 13 06:59:12 PM PDT 24
Finished Jul 13 07:01:14 PM PDT 24
Peak memory 239660 kb
Host smart-680c2644-e245-4fe8-8d34-dcf4220f1306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128996049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle.
128996049
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.1708941938
Short name T355
Test name
Test status
Simulation time 6477027038 ps
CPU time 10.77 seconds
Started Jul 13 06:59:05 PM PDT 24
Finished Jul 13 06:59:18 PM PDT 24
Peak memory 224536 kb
Host smart-3f454e02-8db8-4d14-864e-c5724f6e944d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708941938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.1708941938
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.79788580
Short name T208
Test name
Test status
Simulation time 42856484672 ps
CPU time 157.81 seconds
Started Jul 13 06:59:03 PM PDT 24
Finished Jul 13 07:01:43 PM PDT 24
Peak memory 249392 kb
Host smart-6846b88f-3615-407f-aeb5-cb2dd634e1f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79788580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds.79788580
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_intercept.1170963339
Short name T233
Test name
Test status
Simulation time 378581107 ps
CPU time 6.2 seconds
Started Jul 13 06:59:03 PM PDT 24
Finished Jul 13 06:59:12 PM PDT 24
Peak memory 224564 kb
Host smart-27e930a5-cb80-40c1-abbc-f9f10c07d074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170963339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.1170963339
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.3813541836
Short name T319
Test name
Test status
Simulation time 3518327083 ps
CPU time 38.92 seconds
Started Jul 13 06:59:06 PM PDT 24
Finished Jul 13 06:59:46 PM PDT 24
Peak memory 236484 kb
Host smart-1c978fc9-e781-47e5-abf5-a78a0856be19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813541836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.3813541836
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.812921994
Short name T69
Test name
Test status
Simulation time 502265043 ps
CPU time 2.66 seconds
Started Jul 13 06:59:03 PM PDT 24
Finished Jul 13 06:59:08 PM PDT 24
Peak memory 232408 kb
Host smart-e428458b-838b-4d1f-a284-08dc0ff0aaff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812921994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap.
812921994
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.3513178447
Short name T950
Test name
Test status
Simulation time 437373916 ps
CPU time 2.81 seconds
Started Jul 13 06:59:07 PM PDT 24
Finished Jul 13 06:59:10 PM PDT 24
Peak memory 224448 kb
Host smart-fe6bac7f-d807-4d12-b2ec-17fb143cf1e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513178447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.3513178447
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.1986242381
Short name T829
Test name
Test status
Simulation time 2839366228 ps
CPU time 5.05 seconds
Started Jul 13 06:59:05 PM PDT 24
Finished Jul 13 06:59:12 PM PDT 24
Peak memory 219392 kb
Host smart-e2981497-520b-4f26-9edf-40cd11860594
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1986242381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.1986242381
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.775102631
Short name T78
Test name
Test status
Simulation time 127972688 ps
CPU time 1.02 seconds
Started Jul 13 06:59:12 PM PDT 24
Finished Jul 13 06:59:15 PM PDT 24
Peak memory 236580 kb
Host smart-1de55395-95ae-48be-941d-8836cce875a9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775102631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.775102631
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.92856535
Short name T19
Test name
Test status
Simulation time 47811460 ps
CPU time 0.97 seconds
Started Jul 13 06:59:10 PM PDT 24
Finished Jul 13 06:59:13 PM PDT 24
Peak memory 206744 kb
Host smart-417f4a7d-e83e-49f9-9142-189dc339559a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92856535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stress_
all.92856535
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.822771205
Short name T471
Test name
Test status
Simulation time 795912810 ps
CPU time 11.8 seconds
Started Jul 13 06:59:01 PM PDT 24
Finished Jul 13 06:59:14 PM PDT 24
Peak memory 218800 kb
Host smart-4bf4433c-d058-47d6-bab0-526b338ab9b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822771205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.822771205
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.3395933706
Short name T928
Test name
Test status
Simulation time 17021223494 ps
CPU time 8.49 seconds
Started Jul 13 06:59:02 PM PDT 24
Finished Jul 13 06:59:12 PM PDT 24
Peak memory 217316 kb
Host smart-d5926ca4-6242-47d5-9229-bb9b645729e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395933706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.3395933706
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.1748979306
Short name T899
Test name
Test status
Simulation time 127086480 ps
CPU time 1.21 seconds
Started Jul 13 06:59:07 PM PDT 24
Finished Jul 13 06:59:09 PM PDT 24
Peak memory 207980 kb
Host smart-7a7290ea-784b-44e3-9018-2c2eb5e2ebea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748979306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.1748979306
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.1651741586
Short name T347
Test name
Test status
Simulation time 715751777 ps
CPU time 0.91 seconds
Started Jul 13 06:59:11 PM PDT 24
Finished Jul 13 06:59:14 PM PDT 24
Peak memory 206468 kb
Host smart-0fcd4827-82b5-4743-804d-e8cb2a5d34f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651741586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.1651741586
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.1270495705
Short name T234
Test name
Test status
Simulation time 380441487 ps
CPU time 4.07 seconds
Started Jul 13 06:59:10 PM PDT 24
Finished Jul 13 06:59:16 PM PDT 24
Peak memory 232644 kb
Host smart-6e5cfae0-0264-455e-b62e-f56eebed97cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270495705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.1270495705
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.2003260706
Short name T491
Test name
Test status
Simulation time 31291545 ps
CPU time 0.75 seconds
Started Jul 13 06:59:36 PM PDT 24
Finished Jul 13 06:59:37 PM PDT 24
Peak memory 205516 kb
Host smart-bdb97d7b-f821-481b-82a2-111f1941c11c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003260706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
2003260706
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.3405187905
Short name T528
Test name
Test status
Simulation time 182933386 ps
CPU time 0.76 seconds
Started Jul 13 06:59:47 PM PDT 24
Finished Jul 13 06:59:49 PM PDT 24
Peak memory 205068 kb
Host smart-d12e4158-7e3d-48d4-a154-fcc46b02c5bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405187905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.3405187905
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.1072108036
Short name T9
Test name
Test status
Simulation time 3909982989 ps
CPU time 47.03 seconds
Started Jul 13 06:59:49 PM PDT 24
Finished Jul 13 07:00:39 PM PDT 24
Peak memory 249184 kb
Host smart-72318aa3-92aa-4e06-a17d-cc657660cfa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072108036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.1072108036
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.2538885078
Short name T773
Test name
Test status
Simulation time 3558489194 ps
CPU time 24.04 seconds
Started Jul 13 06:59:37 PM PDT 24
Finished Jul 13 07:00:02 PM PDT 24
Peak memory 255216 kb
Host smart-52bfa09d-b5d7-410b-bb1f-9a1a46bd6bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538885078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.2538885078
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.2581995259
Short name T607
Test name
Test status
Simulation time 91633421801 ps
CPU time 156.9 seconds
Started Jul 13 06:59:48 PM PDT 24
Finished Jul 13 07:02:27 PM PDT 24
Peak memory 238748 kb
Host smart-19ee99b2-61ab-4cb2-ac28-ca5a41b4c805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581995259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.2581995259
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.3728313142
Short name T982
Test name
Test status
Simulation time 2243712770 ps
CPU time 14.19 seconds
Started Jul 13 06:59:36 PM PDT 24
Finished Jul 13 06:59:51 PM PDT 24
Peak memory 240988 kb
Host smart-08b9c514-47a3-4f2a-ba15-be489015084f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728313142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.3728313142
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.2484860568
Short name T255
Test name
Test status
Simulation time 31864821016 ps
CPU time 115.55 seconds
Started Jul 13 06:59:48 PM PDT 24
Finished Jul 13 07:01:47 PM PDT 24
Peak memory 237884 kb
Host smart-081d0015-b784-4ce6-9fce-5581e625aa04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484860568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmd
s.2484860568
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.726981567
Short name T85
Test name
Test status
Simulation time 1068187716 ps
CPU time 11.33 seconds
Started Jul 13 06:59:33 PM PDT 24
Finished Jul 13 06:59:45 PM PDT 24
Peak memory 232712 kb
Host smart-c57119a8-19f6-44e7-9d2a-322e5866b569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726981567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.726981567
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.3967490932
Short name T219
Test name
Test status
Simulation time 2903314226 ps
CPU time 33.84 seconds
Started Jul 13 06:59:41 PM PDT 24
Finished Jul 13 07:00:16 PM PDT 24
Peak memory 237372 kb
Host smart-8ac62186-1469-484e-b2ee-0c0eb5f7f21b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967490932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.3967490932
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.1367763027
Short name T887
Test name
Test status
Simulation time 277556794 ps
CPU time 4.71 seconds
Started Jul 13 06:59:47 PM PDT 24
Finished Jul 13 06:59:55 PM PDT 24
Peak memory 224408 kb
Host smart-8af4edaf-6b66-4f72-8233-95c88a3e6224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367763027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.1367763027
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.3018110661
Short name T517
Test name
Test status
Simulation time 6598635798 ps
CPU time 16.56 seconds
Started Jul 13 06:59:41 PM PDT 24
Finished Jul 13 06:59:59 PM PDT 24
Peak memory 220648 kb
Host smart-ca273d9e-4c72-4b75-8d98-c4691787518d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3018110661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.3018110661
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.1605907811
Short name T17
Test name
Test status
Simulation time 2466045695 ps
CPU time 33.89 seconds
Started Jul 13 06:59:45 PM PDT 24
Finished Jul 13 07:00:21 PM PDT 24
Peak memory 240996 kb
Host smart-ffcb0a8e-5aab-4491-a16f-2b2b21edbbc7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605907811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.1605907811
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.3525482401
Short name T869
Test name
Test status
Simulation time 12955042630 ps
CPU time 4.83 seconds
Started Jul 13 06:59:34 PM PDT 24
Finished Jul 13 06:59:39 PM PDT 24
Peak memory 216376 kb
Host smart-c660638f-d6b1-4e30-84a7-31da3695c00e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525482401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.3525482401
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.895339046
Short name T456
Test name
Test status
Simulation time 8260583394 ps
CPU time 7.57 seconds
Started Jul 13 06:59:31 PM PDT 24
Finished Jul 13 06:59:39 PM PDT 24
Peak memory 216376 kb
Host smart-dabfa7ec-e051-49fb-adbc-0841bbebf5e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895339046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.895339046
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.3884552237
Short name T412
Test name
Test status
Simulation time 40089068 ps
CPU time 0.74 seconds
Started Jul 13 06:59:47 PM PDT 24
Finished Jul 13 06:59:51 PM PDT 24
Peak memory 206000 kb
Host smart-6993900a-035a-46e1-8833-e8417f6c99b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884552237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.3884552237
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.1396808029
Short name T794
Test name
Test status
Simulation time 107167042 ps
CPU time 1 seconds
Started Jul 13 06:59:48 PM PDT 24
Finished Jul 13 06:59:52 PM PDT 24
Peak memory 207020 kb
Host smart-e3333ec6-3cd5-4068-9703-44283917db0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396808029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.1396808029
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.596692039
Short name T99
Test name
Test status
Simulation time 1108386787 ps
CPU time 2.71 seconds
Started Jul 13 06:59:49 PM PDT 24
Finished Jul 13 06:59:55 PM PDT 24
Peak memory 217096 kb
Host smart-5eb0d0e6-a3f0-4f00-a359-62c366296d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596692039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.596692039
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.274542680
Short name T760
Test name
Test status
Simulation time 16361688 ps
CPU time 0.74 seconds
Started Jul 13 06:59:46 PM PDT 24
Finished Jul 13 06:59:49 PM PDT 24
Peak memory 205872 kb
Host smart-ad2916a7-1b11-49d0-b980-6d655a1d164c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274542680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.274542680
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.3240216110
Short name T243
Test name
Test status
Simulation time 94514710 ps
CPU time 2.76 seconds
Started Jul 13 06:59:43 PM PDT 24
Finished Jul 13 06:59:47 PM PDT 24
Peak memory 232684 kb
Host smart-d22977f3-c0c8-4fe5-a343-99d517b67092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240216110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.3240216110
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.420528735
Short name T32
Test name
Test status
Simulation time 63076065 ps
CPU time 0.81 seconds
Started Jul 13 06:59:33 PM PDT 24
Finished Jul 13 06:59:34 PM PDT 24
Peak memory 206620 kb
Host smart-f164e6e2-9d70-40c7-9373-d74cd986d66d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420528735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.420528735
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.1793050904
Short name T213
Test name
Test status
Simulation time 27880677480 ps
CPU time 104.24 seconds
Started Jul 13 06:59:34 PM PDT 24
Finished Jul 13 07:01:19 PM PDT 24
Peak memory 240292 kb
Host smart-f724f7e0-23f2-4645-b5e0-92fe33f72a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793050904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.1793050904
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.2434234304
Short name T652
Test name
Test status
Simulation time 4438248445 ps
CPU time 32.03 seconds
Started Jul 13 06:59:32 PM PDT 24
Finished Jul 13 07:00:04 PM PDT 24
Peak memory 252588 kb
Host smart-be81db49-bab8-430f-bfeb-84fb66f66947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434234304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.2434234304
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.2013353275
Short name T779
Test name
Test status
Simulation time 310464626 ps
CPU time 5.49 seconds
Started Jul 13 06:59:35 PM PDT 24
Finished Jul 13 06:59:41 PM PDT 24
Peak memory 232652 kb
Host smart-48fcb324-54d8-4dcb-93e9-ede8cb87ca08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013353275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.2013353275
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.4258889928
Short name T83
Test name
Test status
Simulation time 19295346 ps
CPU time 0.76 seconds
Started Jul 13 06:59:43 PM PDT 24
Finished Jul 13 06:59:44 PM PDT 24
Peak memory 215804 kb
Host smart-f10e0447-7f64-4100-9c92-eba9876030b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258889928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd
s.4258889928
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.3760776314
Short name T13
Test name
Test status
Simulation time 963108263 ps
CPU time 9.01 seconds
Started Jul 13 06:59:43 PM PDT 24
Finished Jul 13 06:59:53 PM PDT 24
Peak memory 232632 kb
Host smart-1af0efe7-ca8f-4812-b46d-d04e3eb73973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760776314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.3760776314
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.1332811147
Short name T927
Test name
Test status
Simulation time 741855716 ps
CPU time 11.96 seconds
Started Jul 13 06:59:34 PM PDT 24
Finished Jul 13 06:59:47 PM PDT 24
Peak memory 240888 kb
Host smart-135ff66e-d0ff-426d-87c5-bf616bf27c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332811147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.1332811147
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.1315518948
Short name T626
Test name
Test status
Simulation time 183644316 ps
CPU time 5.15 seconds
Started Jul 13 06:59:35 PM PDT 24
Finished Jul 13 06:59:40 PM PDT 24
Peak memory 240684 kb
Host smart-16ae9d03-1d21-43e9-902d-4cba7ffc46b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315518948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.1315518948
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.3839339013
Short name T995
Test name
Test status
Simulation time 4070208378 ps
CPU time 15.96 seconds
Started Jul 13 06:59:42 PM PDT 24
Finished Jul 13 06:59:59 PM PDT 24
Peak memory 232800 kb
Host smart-8961a4f1-8859-41ac-82e5-8304557594e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839339013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.3839339013
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.41902234
Short name T358
Test name
Test status
Simulation time 2599457358 ps
CPU time 4.53 seconds
Started Jul 13 06:59:40 PM PDT 24
Finished Jul 13 06:59:45 PM PDT 24
Peak memory 222740 kb
Host smart-44194e79-7814-4ec8-8d23-8e09cc62be24
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=41902234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_direc
t.41902234
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.1698226088
Short name T267
Test name
Test status
Simulation time 76272538847 ps
CPU time 366.64 seconds
Started Jul 13 06:59:32 PM PDT 24
Finished Jul 13 07:05:39 PM PDT 24
Peak memory 281928 kb
Host smart-fcde174d-55ab-4033-8188-4f430fc5979d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698226088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.1698226088
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.2428209420
Short name T362
Test name
Test status
Simulation time 61791855658 ps
CPU time 34.88 seconds
Started Jul 13 06:59:36 PM PDT 24
Finished Jul 13 07:00:11 PM PDT 24
Peak memory 216324 kb
Host smart-38cfe1fc-4c70-4603-a427-399dbe7e4740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428209420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.2428209420
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.2027309588
Short name T445
Test name
Test status
Simulation time 33162613104 ps
CPU time 17.09 seconds
Started Jul 13 06:59:32 PM PDT 24
Finished Jul 13 06:59:50 PM PDT 24
Peak memory 216296 kb
Host smart-d650ce91-5e52-4d6c-94ee-3cebc7e12421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027309588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.2027309588
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.3919005744
Short name T533
Test name
Test status
Simulation time 1044856474 ps
CPU time 3.85 seconds
Started Jul 13 06:59:38 PM PDT 24
Finished Jul 13 06:59:42 PM PDT 24
Peak memory 216216 kb
Host smart-c297b26d-be7d-4b51-b78f-4df126fd3008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919005744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.3919005744
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.1045771071
Short name T419
Test name
Test status
Simulation time 43280875 ps
CPU time 0.89 seconds
Started Jul 13 06:59:30 PM PDT 24
Finished Jul 13 06:59:31 PM PDT 24
Peak memory 207036 kb
Host smart-1a4c6f9e-ce4e-4fa8-97b9-ff3711a796f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045771071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.1045771071
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.4076966941
Short name T486
Test name
Test status
Simulation time 198679175 ps
CPU time 4.12 seconds
Started Jul 13 06:59:40 PM PDT 24
Finished Jul 13 06:59:44 PM PDT 24
Peak memory 224420 kb
Host smart-187dc324-ee58-46a4-aa1f-7dec6454ca0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076966941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.4076966941
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.3959616487
Short name T815
Test name
Test status
Simulation time 11164619 ps
CPU time 0.69 seconds
Started Jul 13 06:59:45 PM PDT 24
Finished Jul 13 06:59:48 PM PDT 24
Peak memory 205836 kb
Host smart-a7387784-78a8-4960-a57f-19d73109dea3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959616487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
3959616487
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.3768220259
Short name T820
Test name
Test status
Simulation time 502878733 ps
CPU time 3.41 seconds
Started Jul 13 06:59:44 PM PDT 24
Finished Jul 13 06:59:50 PM PDT 24
Peak memory 224456 kb
Host smart-66c8851d-0526-447e-9233-dd7fe5b5bd62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768220259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.3768220259
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.614808873
Short name T485
Test name
Test status
Simulation time 52733183 ps
CPU time 0.8 seconds
Started Jul 13 06:59:33 PM PDT 24
Finished Jul 13 06:59:34 PM PDT 24
Peak memory 206920 kb
Host smart-355ec212-2374-494a-aebb-316a9558409e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614808873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.614808873
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.89281455
Short name T957
Test name
Test status
Simulation time 54955425136 ps
CPU time 190.91 seconds
Started Jul 13 06:59:49 PM PDT 24
Finished Jul 13 07:03:03 PM PDT 24
Peak memory 255712 kb
Host smart-8bb83737-394d-4c40-8e78-6eb5d1faedba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89281455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.89281455
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.663433311
Short name T862
Test name
Test status
Simulation time 34243997230 ps
CPU time 290.1 seconds
Started Jul 13 06:59:36 PM PDT 24
Finished Jul 13 07:04:27 PM PDT 24
Peak memory 241040 kb
Host smart-76350383-4804-410e-9069-ddad9e5f5ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663433311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.663433311
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.1236480709
Short name T389
Test name
Test status
Simulation time 14355632475 ps
CPU time 97.71 seconds
Started Jul 13 06:59:35 PM PDT 24
Finished Jul 13 07:01:13 PM PDT 24
Peak memory 265664 kb
Host smart-93b5caa1-fb3e-40af-8ee8-21c9a4efc869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236480709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.1236480709
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.1972933935
Short name T139
Test name
Test status
Simulation time 218655390 ps
CPU time 4.74 seconds
Started Jul 13 06:59:43 PM PDT 24
Finished Jul 13 06:59:48 PM PDT 24
Peak memory 224512 kb
Host smart-353f3ee5-37f6-4a72-a240-04c3214de4db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972933935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.1972933935
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.4046956824
Short name T924
Test name
Test status
Simulation time 2156772715 ps
CPU time 17.42 seconds
Started Jul 13 06:59:44 PM PDT 24
Finished Jul 13 07:00:04 PM PDT 24
Peak memory 249172 kb
Host smart-5bfa2dcc-eeff-43e1-a939-f20f44c568da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046956824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmd
s.4046956824
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_intercept.3753593332
Short name T207
Test name
Test status
Simulation time 243126081 ps
CPU time 4.96 seconds
Started Jul 13 06:59:50 PM PDT 24
Finished Jul 13 06:59:58 PM PDT 24
Peak memory 224456 kb
Host smart-ce62ca46-1617-472b-b658-66b3481a0520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753593332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.3753593332
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.3824637755
Short name T503
Test name
Test status
Simulation time 3505352125 ps
CPU time 34.47 seconds
Started Jul 13 06:59:44 PM PDT 24
Finished Jul 13 07:00:21 PM PDT 24
Peak memory 232780 kb
Host smart-56cb0ae2-a15b-4cbf-b799-67c937626e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824637755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.3824637755
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.4257173850
Short name T224
Test name
Test status
Simulation time 12079912504 ps
CPU time 18.82 seconds
Started Jul 13 06:59:43 PM PDT 24
Finished Jul 13 07:00:02 PM PDT 24
Peak memory 224592 kb
Host smart-63101f25-25f1-4d47-a98c-29747b3f89af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257173850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.4257173850
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.500004652
Short name T244
Test name
Test status
Simulation time 13566422834 ps
CPU time 10.73 seconds
Started Jul 13 06:59:45 PM PDT 24
Finished Jul 13 06:59:58 PM PDT 24
Peak memory 232776 kb
Host smart-96324c58-3a5d-4240-a4b6-16b3da7da36c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500004652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.500004652
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.2194637486
Short name T959
Test name
Test status
Simulation time 2412438793 ps
CPU time 12.67 seconds
Started Jul 13 06:59:44 PM PDT 24
Finished Jul 13 06:59:59 PM PDT 24
Peak memory 219204 kb
Host smart-6992761b-73b1-4d23-8ca2-e2d2568ff744
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2194637486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.2194637486
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.1836919837
Short name T166
Test name
Test status
Simulation time 3292892411 ps
CPU time 77.3 seconds
Started Jul 13 06:59:36 PM PDT 24
Finished Jul 13 07:00:54 PM PDT 24
Peak memory 273352 kb
Host smart-b910d131-a276-4f96-b16f-609b0979d768
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836919837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.1836919837
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.2181377685
Short name T953
Test name
Test status
Simulation time 1712505579 ps
CPU time 10.22 seconds
Started Jul 13 06:59:30 PM PDT 24
Finished Jul 13 06:59:41 PM PDT 24
Peak memory 216284 kb
Host smart-9490c02e-1827-4a22-af01-1ec819ebf27b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181377685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.2181377685
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.57795338
Short name T553
Test name
Test status
Simulation time 608333164 ps
CPU time 3.62 seconds
Started Jul 13 06:59:29 PM PDT 24
Finished Jul 13 06:59:33 PM PDT 24
Peak memory 216236 kb
Host smart-f26edaca-ff5f-42ad-85f9-3b8ceae4620f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57795338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.57795338
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.1150202940
Short name T334
Test name
Test status
Simulation time 105455034 ps
CPU time 1.16 seconds
Started Jul 13 06:59:33 PM PDT 24
Finished Jul 13 06:59:35 PM PDT 24
Peak memory 208012 kb
Host smart-b8edf5c1-6f4f-4431-8b1b-9da3c6b08e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150202940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.1150202940
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.1635558253
Short name T838
Test name
Test status
Simulation time 174096945 ps
CPU time 0.83 seconds
Started Jul 13 06:59:42 PM PDT 24
Finished Jul 13 06:59:43 PM PDT 24
Peak memory 206000 kb
Host smart-8e959a55-8ebf-4dd9-b5ce-47c9453ec55a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635558253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.1635558253
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.3698990542
Short name T509
Test name
Test status
Simulation time 2848121116 ps
CPU time 4.82 seconds
Started Jul 13 06:59:49 PM PDT 24
Finished Jul 13 06:59:56 PM PDT 24
Peak memory 224592 kb
Host smart-262b7279-764b-43c9-9652-52a49ec0237c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698990542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.3698990542
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.1216974906
Short name T570
Test name
Test status
Simulation time 27434593 ps
CPU time 0.7 seconds
Started Jul 13 06:59:54 PM PDT 24
Finished Jul 13 06:59:59 PM PDT 24
Peak memory 205552 kb
Host smart-5d14bb8f-894b-4868-aad6-3f82ef34cb14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216974906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
1216974906
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.607021555
Short name T377
Test name
Test status
Simulation time 63479954 ps
CPU time 2.41 seconds
Started Jul 13 06:59:54 PM PDT 24
Finished Jul 13 07:00:01 PM PDT 24
Peak memory 232676 kb
Host smart-3246df96-f4bd-457f-9d71-73e4b913c630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607021555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.607021555
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.481524424
Short name T565
Test name
Test status
Simulation time 13620979 ps
CPU time 0.77 seconds
Started Jul 13 06:59:55 PM PDT 24
Finished Jul 13 07:00:00 PM PDT 24
Peak memory 205544 kb
Host smart-5b486baf-6cd5-4fd1-b002-4219808d96ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481524424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.481524424
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.979947755
Short name T89
Test name
Test status
Simulation time 191458542170 ps
CPU time 348.95 seconds
Started Jul 13 06:59:39 PM PDT 24
Finished Jul 13 07:05:28 PM PDT 24
Peak memory 257340 kb
Host smart-8a6aadde-b34b-4402-85eb-5852563375b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979947755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.979947755
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.506172939
Short name T259
Test name
Test status
Simulation time 6504760648 ps
CPU time 57.31 seconds
Started Jul 13 06:59:54 PM PDT 24
Finished Jul 13 07:00:56 PM PDT 24
Peak memory 255776 kb
Host smart-70e0c149-4436-4089-9702-203b1a81a3f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506172939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.506172939
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.3823655024
Short name T782
Test name
Test status
Simulation time 5161544824 ps
CPU time 14.31 seconds
Started Jul 13 06:59:47 PM PDT 24
Finished Jul 13 07:00:04 PM PDT 24
Peak memory 217720 kb
Host smart-651b0e36-4201-41a9-a0e3-5437059c6564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823655024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.3823655024
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.3703856260
Short name T532
Test name
Test status
Simulation time 8016438209 ps
CPU time 60.37 seconds
Started Jul 13 06:59:51 PM PDT 24
Finished Jul 13 07:00:54 PM PDT 24
Peak memory 241048 kb
Host smart-59a7da05-657d-449b-a096-2d4ece4cb3e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703856260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.3703856260
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.885967796
Short name T770
Test name
Test status
Simulation time 14882977 ps
CPU time 0.78 seconds
Started Jul 13 06:59:58 PM PDT 24
Finished Jul 13 07:00:03 PM PDT 24
Peak memory 215812 kb
Host smart-fa56f7b8-8810-422c-ae3c-62c390898d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885967796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmds
.885967796
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_intercept.2754086664
Short name T495
Test name
Test status
Simulation time 924160282 ps
CPU time 6.45 seconds
Started Jul 13 06:59:50 PM PDT 24
Finished Jul 13 07:00:00 PM PDT 24
Peak memory 224436 kb
Host smart-b6734989-9058-4a9c-a7ae-19fdc3cec662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754086664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.2754086664
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.2742364416
Short name T455
Test name
Test status
Simulation time 1170915433 ps
CPU time 13.95 seconds
Started Jul 13 07:00:02 PM PDT 24
Finished Jul 13 07:00:18 PM PDT 24
Peak memory 232720 kb
Host smart-d70f29af-a56f-456f-b14c-e1f4487b6cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742364416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.2742364416
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.3470715350
Short name T1010
Test name
Test status
Simulation time 722381897 ps
CPU time 6.78 seconds
Started Jul 13 06:59:54 PM PDT 24
Finished Jul 13 07:00:05 PM PDT 24
Peak memory 240776 kb
Host smart-bac1810c-89e9-4e1a-9737-e0bf1f9da4f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470715350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.3470715350
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.132490246
Short name T919
Test name
Test status
Simulation time 2792550915 ps
CPU time 5.81 seconds
Started Jul 13 06:59:51 PM PDT 24
Finished Jul 13 07:00:01 PM PDT 24
Peak memory 224588 kb
Host smart-a98fa57c-8073-4df9-b499-e7ac44431404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132490246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.132490246
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.2922658797
Short name T851
Test name
Test status
Simulation time 1333337281 ps
CPU time 7.79 seconds
Started Jul 13 06:59:49 PM PDT 24
Finished Jul 13 07:00:00 PM PDT 24
Peak memory 223108 kb
Host smart-c3f892e3-0552-4504-9bd6-a38fd23329d2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2922658797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.2922658797
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.2516150363
Short name T280
Test name
Test status
Simulation time 35143270070 ps
CPU time 279.2 seconds
Started Jul 13 06:59:38 PM PDT 24
Finished Jul 13 07:04:18 PM PDT 24
Peak memory 264656 kb
Host smart-dee9730d-a09e-4cf9-9bab-f7eaab6fc206
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516150363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.2516150363
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.480311364
Short name T394
Test name
Test status
Simulation time 1658233008 ps
CPU time 6.57 seconds
Started Jul 13 06:59:43 PM PDT 24
Finished Jul 13 06:59:50 PM PDT 24
Peak memory 216228 kb
Host smart-1e74a789-32a2-4931-8758-5adc0f30be1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480311364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.480311364
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.3959445118
Short name T474
Test name
Test status
Simulation time 3274186262 ps
CPU time 12.87 seconds
Started Jul 13 06:59:52 PM PDT 24
Finished Jul 13 07:00:10 PM PDT 24
Peak memory 216360 kb
Host smart-e3c08b26-924c-4d01-ad4f-0183e3cab582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959445118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.3959445118
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.958341121
Short name T475
Test name
Test status
Simulation time 57351882 ps
CPU time 1.02 seconds
Started Jul 13 06:59:47 PM PDT 24
Finished Jul 13 06:59:50 PM PDT 24
Peak memory 207100 kb
Host smart-a7745b58-e7f5-4450-b6dc-af4d90a63bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958341121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.958341121
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.3212472168
Short name T750
Test name
Test status
Simulation time 43676143 ps
CPU time 0.81 seconds
Started Jul 13 06:59:50 PM PDT 24
Finished Jul 13 06:59:54 PM PDT 24
Peak memory 205980 kb
Host smart-8bd836f5-b39c-4332-ad4d-09916e8a32d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212472168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.3212472168
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.582864141
Short name T181
Test name
Test status
Simulation time 22603459878 ps
CPU time 24.81 seconds
Started Jul 13 06:59:52 PM PDT 24
Finished Jul 13 07:00:21 PM PDT 24
Peak memory 240764 kb
Host smart-2c5258fd-aa7e-4183-9d48-5d9b5ce322ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582864141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.582864141
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.3033051766
Short name T482
Test name
Test status
Simulation time 66698826 ps
CPU time 0.72 seconds
Started Jul 13 06:59:51 PM PDT 24
Finished Jul 13 06:59:55 PM PDT 24
Peak memory 205568 kb
Host smart-9f96419a-c782-4e63-8c06-fd3b6ce38dff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033051766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
3033051766
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.1332402406
Short name T321
Test name
Test status
Simulation time 287242421 ps
CPU time 4.49 seconds
Started Jul 13 06:59:37 PM PDT 24
Finished Jul 13 06:59:43 PM PDT 24
Peak memory 232616 kb
Host smart-9d0228e1-2c2f-45a7-a91d-7c24595dda4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332402406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.1332402406
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.2214817734
Short name T348
Test name
Test status
Simulation time 14229902 ps
CPU time 0.81 seconds
Started Jul 13 06:59:44 PM PDT 24
Finished Jul 13 06:59:45 PM PDT 24
Peak memory 206608 kb
Host smart-fbeaa1f8-ad48-4c37-a1bc-0f2ae35dc44f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214817734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.2214817734
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.1945624941
Short name T225
Test name
Test status
Simulation time 54991650451 ps
CPU time 94.14 seconds
Started Jul 13 06:59:53 PM PDT 24
Finished Jul 13 07:01:31 PM PDT 24
Peak memory 249236 kb
Host smart-3bcf1b5a-c8ba-4ce1-a807-4ed4ad0af30e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945624941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.1945624941
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.663317587
Short name T710
Test name
Test status
Simulation time 37475526961 ps
CPU time 182.12 seconds
Started Jul 13 06:59:45 PM PDT 24
Finished Jul 13 07:02:49 PM PDT 24
Peak memory 249404 kb
Host smart-c17450af-a194-4cdc-ab5b-a3ecee036c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663317587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.663317587
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.3575265420
Short name T315
Test name
Test status
Simulation time 9963748002 ps
CPU time 29.78 seconds
Started Jul 13 06:59:54 PM PDT 24
Finished Jul 13 07:00:28 PM PDT 24
Peak memory 224320 kb
Host smart-56868f39-60d7-43f5-8b1a-2e1b647c2ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575265420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.3575265420
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.1122386894
Short name T981
Test name
Test status
Simulation time 10512935224 ps
CPU time 27.76 seconds
Started Jul 13 06:59:44 PM PDT 24
Finished Jul 13 07:00:13 PM PDT 24
Peak memory 249244 kb
Host smart-0e35c4c8-38dd-4667-b88c-522414d3aa87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122386894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.1122386894
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.3746236929
Short name T136
Test name
Test status
Simulation time 1750128006 ps
CPU time 24.74 seconds
Started Jul 13 06:59:49 PM PDT 24
Finished Jul 13 07:00:16 PM PDT 24
Peak memory 249084 kb
Host smart-ae34db59-6a2a-4beb-a766-5a45fdbbab58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746236929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmd
s.3746236929
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_intercept.3356104368
Short name T543
Test name
Test status
Simulation time 4295829024 ps
CPU time 22.42 seconds
Started Jul 13 06:59:54 PM PDT 24
Finished Jul 13 07:00:21 PM PDT 24
Peak memory 224608 kb
Host smart-bee4e171-1db0-47a0-a88c-4ea392ce911b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356104368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.3356104368
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.2439929731
Short name T502
Test name
Test status
Simulation time 698251742 ps
CPU time 5.37 seconds
Started Jul 13 06:59:45 PM PDT 24
Finished Jul 13 06:59:53 PM PDT 24
Peak memory 224368 kb
Host smart-166f0f74-d140-4378-b176-71b5e90ac2b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439929731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.2439929731
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.715445044
Short name T256
Test name
Test status
Simulation time 20278720004 ps
CPU time 13.55 seconds
Started Jul 13 06:59:46 PM PDT 24
Finished Jul 13 07:00:02 PM PDT 24
Peak memory 232800 kb
Host smart-b9970409-f8c3-44d7-9aaf-bb615bdfcfa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715445044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swap
.715445044
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.1360618017
Short name T834
Test name
Test status
Simulation time 456430563 ps
CPU time 7.02 seconds
Started Jul 13 06:59:54 PM PDT 24
Finished Jul 13 07:00:06 PM PDT 24
Peak memory 224472 kb
Host smart-d442315f-14d1-4d4f-9bb8-e4b913e150b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360618017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.1360618017
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.2131043706
Short name T901
Test name
Test status
Simulation time 187735080 ps
CPU time 3.95 seconds
Started Jul 13 06:59:44 PM PDT 24
Finished Jul 13 06:59:51 PM PDT 24
Peak memory 223160 kb
Host smart-14f7c8c8-ed6b-406d-80b0-eec2d672f31a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2131043706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.2131043706
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.576407594
Short name T15
Test name
Test status
Simulation time 3638696036 ps
CPU time 42.49 seconds
Started Jul 13 06:59:46 PM PDT 24
Finished Jul 13 07:00:30 PM PDT 24
Peak memory 241092 kb
Host smart-b509de48-d17f-43f1-9d28-13645a68564b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576407594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stres
s_all.576407594
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.3129320167
Short name T314
Test name
Test status
Simulation time 2232742497 ps
CPU time 34.89 seconds
Started Jul 13 06:59:51 PM PDT 24
Finished Jul 13 07:00:29 PM PDT 24
Peak memory 216508 kb
Host smart-f893037c-2ba3-4259-97f2-53c466a9568a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129320167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.3129320167
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.4155391314
Short name T978
Test name
Test status
Simulation time 32313538551 ps
CPU time 8.6 seconds
Started Jul 13 06:59:46 PM PDT 24
Finished Jul 13 06:59:57 PM PDT 24
Peak memory 216312 kb
Host smart-0d429fb6-5355-4940-8c51-2df56c851252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155391314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.4155391314
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.3347736296
Short name T401
Test name
Test status
Simulation time 62831186 ps
CPU time 1.25 seconds
Started Jul 13 06:59:52 PM PDT 24
Finished Jul 13 06:59:57 PM PDT 24
Peak memory 207920 kb
Host smart-a54ea3f1-1c91-447e-b082-d4fb8947208f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347736296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.3347736296
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.688807680
Short name T837
Test name
Test status
Simulation time 136236579 ps
CPU time 0.99 seconds
Started Jul 13 06:59:45 PM PDT 24
Finished Jul 13 06:59:49 PM PDT 24
Peak memory 207024 kb
Host smart-24242cc5-a387-45c8-9a93-0d6e61c25f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688807680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.688807680
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.4252935639
Short name T247
Test name
Test status
Simulation time 4801106845 ps
CPU time 15.8 seconds
Started Jul 13 06:59:52 PM PDT 24
Finished Jul 13 07:00:12 PM PDT 24
Peak memory 232644 kb
Host smart-e4a96958-24ba-4ea3-a743-ae716b738aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252935639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.4252935639
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.3599193859
Short name T537
Test name
Test status
Simulation time 11041894 ps
CPU time 0.72 seconds
Started Jul 13 06:59:47 PM PDT 24
Finished Jul 13 06:59:51 PM PDT 24
Peak memory 204996 kb
Host smart-12f15776-aebe-4395-a9b5-a6754ad42bbb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599193859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
3599193859
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.3662263713
Short name T516
Test name
Test status
Simulation time 3572732905 ps
CPU time 9.46 seconds
Started Jul 13 06:59:52 PM PDT 24
Finished Jul 13 07:00:06 PM PDT 24
Peak memory 224576 kb
Host smart-b422b784-e821-4cd0-a55c-b6ecda6ba38a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662263713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.3662263713
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.3092677638
Short name T133
Test name
Test status
Simulation time 18003946 ps
CPU time 0.79 seconds
Started Jul 13 06:59:47 PM PDT 24
Finished Jul 13 06:59:49 PM PDT 24
Peak memory 206944 kb
Host smart-3e88d487-bfe6-4c2b-84c9-f8e612bb3d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092677638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.3092677638
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.3543560023
Short name T284
Test name
Test status
Simulation time 35118244153 ps
CPU time 260.72 seconds
Started Jul 13 06:59:51 PM PDT 24
Finished Jul 13 07:04:15 PM PDT 24
Peak memory 260160 kb
Host smart-d7053ccd-4f04-4e41-ade2-b272ac36b189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543560023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.3543560023
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.2738900414
Short name T619
Test name
Test status
Simulation time 70256613022 ps
CPU time 215.86 seconds
Started Jul 13 06:59:47 PM PDT 24
Finished Jul 13 07:03:25 PM PDT 24
Peak memory 248904 kb
Host smart-c044fff4-b135-4bb7-8217-2cb969636495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738900414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.2738900414
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.2262758794
Short name T915
Test name
Test status
Simulation time 9278890676 ps
CPU time 53.69 seconds
Started Jul 13 06:59:50 PM PDT 24
Finished Jul 13 07:00:46 PM PDT 24
Peak memory 252604 kb
Host smart-2f1b6c34-9451-46dd-b20f-d0f258bc575c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262758794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.2262758794
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.2265829332
Short name T912
Test name
Test status
Simulation time 2172670065 ps
CPU time 18.3 seconds
Started Jul 13 06:59:52 PM PDT 24
Finished Jul 13 07:00:14 PM PDT 24
Peak memory 224532 kb
Host smart-046190f0-5583-4bbe-9c9b-e975127e99c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265829332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.2265829332
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.342489745
Short name T268
Test name
Test status
Simulation time 33896374592 ps
CPU time 245.63 seconds
Started Jul 13 06:59:51 PM PDT 24
Finished Jul 13 07:04:01 PM PDT 24
Peak memory 257104 kb
Host smart-98ef29c5-b1b3-43eb-986d-7bbf9e56a9ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342489745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmds
.342489745
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.2259117368
Short name T235
Test name
Test status
Simulation time 33421672500 ps
CPU time 16.14 seconds
Started Jul 13 06:59:46 PM PDT 24
Finished Jul 13 07:00:04 PM PDT 24
Peak memory 224564 kb
Host smart-31a4adcc-8c26-4cec-b8a7-8880c437e0e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259117368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.2259117368
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.1558673196
Short name T539
Test name
Test status
Simulation time 12382024070 ps
CPU time 30.72 seconds
Started Jul 13 06:59:48 PM PDT 24
Finished Jul 13 07:00:21 PM PDT 24
Peak memory 232768 kb
Host smart-f68b34d0-c8bb-47f0-8892-6d039ebab93f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558673196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.1558673196
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.3539383417
Short name T138
Test name
Test status
Simulation time 1997181434 ps
CPU time 4.69 seconds
Started Jul 13 06:59:42 PM PDT 24
Finished Jul 13 06:59:48 PM PDT 24
Peak memory 224500 kb
Host smart-d1d5fcd6-c5e4-421a-8e15-672e5bd2082b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539383417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.3539383417
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.869879912
Short name T947
Test name
Test status
Simulation time 431433414 ps
CPU time 6.45 seconds
Started Jul 13 06:59:48 PM PDT 24
Finished Jul 13 06:59:58 PM PDT 24
Peak memory 232704 kb
Host smart-c912f0a7-8761-4e32-b0eb-62e22f2c758a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869879912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.869879912
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.2452241165
Short name T617
Test name
Test status
Simulation time 1899484320 ps
CPU time 11.45 seconds
Started Jul 13 06:59:52 PM PDT 24
Finished Jul 13 07:00:07 PM PDT 24
Peak memory 222720 kb
Host smart-bf5e9f6b-a2bc-46c5-8d9a-34dedae6e1c3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2452241165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.2452241165
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.4162154377
Short name T902
Test name
Test status
Simulation time 92815423489 ps
CPU time 749.1 seconds
Started Jul 13 06:59:42 PM PDT 24
Finished Jul 13 07:12:12 PM PDT 24
Peak memory 273772 kb
Host smart-cb6897ff-c958-495f-b006-5bf580d96c09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162154377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.4162154377
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.1565469227
Short name T673
Test name
Test status
Simulation time 4832526755 ps
CPU time 24.27 seconds
Started Jul 13 06:59:46 PM PDT 24
Finished Jul 13 07:00:12 PM PDT 24
Peak memory 216564 kb
Host smart-699188d9-a861-4ba0-bba7-b3d2ae5e873a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565469227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.1565469227
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.1612948701
Short name T877
Test name
Test status
Simulation time 278792436 ps
CPU time 2.65 seconds
Started Jul 13 06:59:55 PM PDT 24
Finished Jul 13 07:00:02 PM PDT 24
Peak memory 216200 kb
Host smart-bf8713c3-aff8-4add-8e93-c831c04c150b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612948701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.1612948701
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.4265032535
Short name T339
Test name
Test status
Simulation time 210036827 ps
CPU time 1.22 seconds
Started Jul 13 06:59:49 PM PDT 24
Finished Jul 13 06:59:53 PM PDT 24
Peak memory 216124 kb
Host smart-bf0f28aa-7c74-4761-aa38-f02ff0e7cd22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265032535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.4265032535
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.1825125933
Short name T375
Test name
Test status
Simulation time 136638611 ps
CPU time 1.04 seconds
Started Jul 13 06:59:47 PM PDT 24
Finished Jul 13 06:59:50 PM PDT 24
Peak memory 207004 kb
Host smart-2ba0ade1-8e64-4b38-9545-2ce7310de7f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825125933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.1825125933
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.2378076603
Short name T476
Test name
Test status
Simulation time 38223476 ps
CPU time 2.16 seconds
Started Jul 13 06:59:46 PM PDT 24
Finished Jul 13 06:59:50 PM PDT 24
Peak memory 224016 kb
Host smart-d2082e64-909a-4a5e-a7fb-d1620e18f9ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378076603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.2378076603
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.267789913
Short name T861
Test name
Test status
Simulation time 32576427 ps
CPU time 0.73 seconds
Started Jul 13 06:59:50 PM PDT 24
Finished Jul 13 06:59:54 PM PDT 24
Peak memory 204940 kb
Host smart-130f96e0-556c-4424-9701-e9b80bbef844
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267789913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.267789913
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.3025327625
Short name T494
Test name
Test status
Simulation time 610139445 ps
CPU time 5 seconds
Started Jul 13 06:59:55 PM PDT 24
Finished Jul 13 07:00:05 PM PDT 24
Peak memory 232616 kb
Host smart-8e0351a3-7865-489a-935f-aa192ea966e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025327625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.3025327625
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.3164627747
Short name T545
Test name
Test status
Simulation time 103232318 ps
CPU time 0.75 seconds
Started Jul 13 06:59:48 PM PDT 24
Finished Jul 13 06:59:51 PM PDT 24
Peak memory 205604 kb
Host smart-67eadc75-7e2e-40df-aa57-051e1465aa72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164627747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.3164627747
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.2914655629
Short name T742
Test name
Test status
Simulation time 2948847902 ps
CPU time 51.79 seconds
Started Jul 13 07:00:04 PM PDT 24
Finished Jul 13 07:00:57 PM PDT 24
Peak memory 254692 kb
Host smart-347d3bca-6dbd-4c5a-b5a9-4c4e4c27174b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914655629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.2914655629
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.1116907728
Short name T251
Test name
Test status
Simulation time 4722738525 ps
CPU time 41.42 seconds
Started Jul 13 07:00:00 PM PDT 24
Finished Jul 13 07:00:44 PM PDT 24
Peak memory 256356 kb
Host smart-70be837c-9545-483b-8d95-9eafef11f9c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116907728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.1116907728
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.22376630
Short name T504
Test name
Test status
Simulation time 7926286370 ps
CPU time 18.19 seconds
Started Jul 13 06:59:53 PM PDT 24
Finished Jul 13 07:00:16 PM PDT 24
Peak memory 217664 kb
Host smart-ecdc7942-9d57-4a3d-acf1-3996f35a76d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22376630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idle.22376630
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.4203236399
Short name T413
Test name
Test status
Simulation time 2738156235 ps
CPU time 42.51 seconds
Started Jul 13 06:59:55 PM PDT 24
Finished Jul 13 07:00:41 PM PDT 24
Peak memory 224556 kb
Host smart-37c66aad-93ca-4025-8555-b5cc01c3af83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203236399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.4203236399
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.3151214350
Short name T26
Test name
Test status
Simulation time 7265647138 ps
CPU time 50.09 seconds
Started Jul 13 06:59:55 PM PDT 24
Finished Jul 13 07:00:49 PM PDT 24
Peak memory 253708 kb
Host smart-5048a267-545d-4d50-8394-47e721ed2af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151214350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmd
s.3151214350
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.3048644649
Short name T941
Test name
Test status
Simulation time 2778909432 ps
CPU time 4.49 seconds
Started Jul 13 06:59:49 PM PDT 24
Finished Jul 13 06:59:56 PM PDT 24
Peak memory 232700 kb
Host smart-b2e53848-85a0-4662-94f0-0c760d27b8d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048644649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.3048644649
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.349001554
Short name T600
Test name
Test status
Simulation time 1910029045 ps
CPU time 9.6 seconds
Started Jul 13 06:59:54 PM PDT 24
Finished Jul 13 07:00:08 PM PDT 24
Peak memory 224424 kb
Host smart-50315316-f51f-402c-9f9f-358465a7e150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349001554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.349001554
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.1445587265
Short name T250
Test name
Test status
Simulation time 849191007 ps
CPU time 10.04 seconds
Started Jul 13 07:00:00 PM PDT 24
Finished Jul 13 07:00:13 PM PDT 24
Peak memory 235696 kb
Host smart-d1303b5c-143a-4f0a-b63d-bceb9ee210d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445587265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.1445587265
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.3102475779
Short name T248
Test name
Test status
Simulation time 10762738708 ps
CPU time 7.02 seconds
Started Jul 13 06:59:55 PM PDT 24
Finished Jul 13 07:00:07 PM PDT 24
Peak memory 224672 kb
Host smart-b0611068-c349-4e4d-b3ca-7a1755c164de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102475779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.3102475779
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.3019232468
Short name T152
Test name
Test status
Simulation time 3833023506 ps
CPU time 8.98 seconds
Started Jul 13 06:59:55 PM PDT 24
Finished Jul 13 07:00:09 PM PDT 24
Peak memory 219092 kb
Host smart-a48d26ad-08ca-4c3b-ba34-0a9e30ae528e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3019232468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.3019232468
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.2209947771
Short name T623
Test name
Test status
Simulation time 35720129759 ps
CPU time 19.34 seconds
Started Jul 13 06:59:49 PM PDT 24
Finished Jul 13 07:00:11 PM PDT 24
Peak memory 216560 kb
Host smart-7c6e92e7-112c-4ef0-a63d-0c2fa2c3ec04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209947771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.2209947771
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.2047890490
Short name T740
Test name
Test status
Simulation time 13046294610 ps
CPU time 15.96 seconds
Started Jul 13 06:59:59 PM PDT 24
Finished Jul 13 07:00:18 PM PDT 24
Peak memory 216380 kb
Host smart-6fd620f9-589b-40ad-8a15-d96e81b62ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047890490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.2047890490
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.427749629
Short name T449
Test name
Test status
Simulation time 16138345 ps
CPU time 0.84 seconds
Started Jul 13 06:59:52 PM PDT 24
Finished Jul 13 06:59:57 PM PDT 24
Peak memory 205988 kb
Host smart-a60f5189-1f6a-4529-ae00-b6059df49f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427749629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.427749629
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.2125764775
Short name T845
Test name
Test status
Simulation time 60252812 ps
CPU time 0.87 seconds
Started Jul 13 06:59:52 PM PDT 24
Finished Jul 13 06:59:57 PM PDT 24
Peak memory 205952 kb
Host smart-7e0bedfc-e8f7-4de9-ad44-7bb4abaef732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125764775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.2125764775
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.3314880550
Short name T769
Test name
Test status
Simulation time 16655276348 ps
CPU time 17.01 seconds
Started Jul 13 06:59:53 PM PDT 24
Finished Jul 13 07:00:14 PM PDT 24
Peak memory 224584 kb
Host smart-6b7467bf-803c-4fe9-929b-b24f6e5c3de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314880550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.3314880550
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.122795738
Short name T772
Test name
Test status
Simulation time 111569449 ps
CPU time 0.74 seconds
Started Jul 13 06:59:52 PM PDT 24
Finished Jul 13 06:59:58 PM PDT 24
Peak memory 205868 kb
Host smart-fa59a350-8c5b-48ab-b6fa-3750d9d570a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122795738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.122795738
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.319908601
Short name T803
Test name
Test status
Simulation time 31878891 ps
CPU time 0.77 seconds
Started Jul 13 06:59:54 PM PDT 24
Finished Jul 13 06:59:59 PM PDT 24
Peak memory 205580 kb
Host smart-e3168361-08d8-4d70-a205-eba3f19049fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319908601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.319908601
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.1286047733
Short name T974
Test name
Test status
Simulation time 4865182253 ps
CPU time 19.78 seconds
Started Jul 13 06:59:54 PM PDT 24
Finished Jul 13 07:00:19 PM PDT 24
Peak memory 224604 kb
Host smart-845b0874-349c-46e7-a882-3d3ce97e3481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286047733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.1286047733
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.1891698603
Short name T257
Test name
Test status
Simulation time 21552429251 ps
CPU time 149.07 seconds
Started Jul 13 06:59:55 PM PDT 24
Finished Jul 13 07:02:29 PM PDT 24
Peak memory 268188 kb
Host smart-33c11b2d-7d64-4afd-b6ac-3ca1904f2719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891698603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.1891698603
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.444921248
Short name T998
Test name
Test status
Simulation time 10600929168 ps
CPU time 36.04 seconds
Started Jul 13 06:59:53 PM PDT 24
Finished Jul 13 07:00:34 PM PDT 24
Peak memory 239128 kb
Host smart-14c6dc91-bbc8-4fbb-b78a-5f12ea588aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444921248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.444921248
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.93975522
Short name T216
Test name
Test status
Simulation time 365602540 ps
CPU time 2.45 seconds
Started Jul 13 06:59:50 PM PDT 24
Finished Jul 13 06:59:56 PM PDT 24
Peak memory 224404 kb
Host smart-fc46f6c4-e74f-48cd-88e3-df859b51f7d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93975522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.93975522
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.2123339462
Short name T239
Test name
Test status
Simulation time 156302612 ps
CPU time 4.67 seconds
Started Jul 13 06:59:55 PM PDT 24
Finished Jul 13 07:00:05 PM PDT 24
Peak memory 232652 kb
Host smart-cf58201e-973e-4c17-93df-32042036f162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123339462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.2123339462
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.3188794743
Short name T870
Test name
Test status
Simulation time 699698659 ps
CPU time 6.26 seconds
Started Jul 13 06:59:53 PM PDT 24
Finished Jul 13 07:00:04 PM PDT 24
Peak memory 232652 kb
Host smart-538aa98a-037b-464a-bb0c-b8a482c9689e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188794743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.3188794743
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.2987705185
Short name T647
Test name
Test status
Simulation time 59062583 ps
CPU time 2.21 seconds
Started Jul 13 06:59:52 PM PDT 24
Finished Jul 13 06:59:58 PM PDT 24
Peak memory 232400 kb
Host smart-ba76b0a9-19ec-4196-8bcd-af3507ed0f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987705185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.2987705185
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.2529934006
Short name T341
Test name
Test status
Simulation time 1001350574 ps
CPU time 13.91 seconds
Started Jul 13 06:59:57 PM PDT 24
Finished Jul 13 07:00:15 PM PDT 24
Peak memory 218728 kb
Host smart-c20e1c10-53de-42b3-8b6e-36e2fe1a2dd9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2529934006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.2529934006
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.3716723444
Short name T131
Test name
Test status
Simulation time 19955672664 ps
CPU time 235.73 seconds
Started Jul 13 06:59:55 PM PDT 24
Finished Jul 13 07:03:55 PM PDT 24
Peak memory 256320 kb
Host smart-1293c279-37bb-4fac-a945-2c392376a9b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716723444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.3716723444
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.3596492326
Short name T404
Test name
Test status
Simulation time 4536104649 ps
CPU time 23.33 seconds
Started Jul 13 06:59:54 PM PDT 24
Finished Jul 13 07:00:22 PM PDT 24
Peak memory 216380 kb
Host smart-cd9642dc-42f1-4239-b1dd-35cb60d87c7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596492326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.3596492326
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.673223599
Short name T407
Test name
Test status
Simulation time 862593134 ps
CPU time 2.59 seconds
Started Jul 13 06:59:49 PM PDT 24
Finished Jul 13 06:59:54 PM PDT 24
Peak memory 216480 kb
Host smart-1bef2e12-0896-46bb-b11e-e893d72b1a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673223599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.673223599
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.2833261745
Short name T399
Test name
Test status
Simulation time 11120721 ps
CPU time 0.71 seconds
Started Jul 13 06:59:55 PM PDT 24
Finished Jul 13 07:00:00 PM PDT 24
Peak memory 205652 kb
Host smart-1dbbe424-503e-4827-a767-465fd23be005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833261745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.2833261745
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.2950576085
Short name T30
Test name
Test status
Simulation time 21561764 ps
CPU time 0.76 seconds
Started Jul 13 06:59:58 PM PDT 24
Finished Jul 13 07:00:02 PM PDT 24
Peak memory 205992 kb
Host smart-375eb190-c15f-4fd1-b187-06974707fa1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950576085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.2950576085
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.3074997200
Short name T542
Test name
Test status
Simulation time 650658704 ps
CPU time 6.55 seconds
Started Jul 13 06:59:54 PM PDT 24
Finished Jul 13 07:00:05 PM PDT 24
Peak memory 224496 kb
Host smart-d28f9529-50f1-4dc9-8186-6ba2844e2854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074997200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.3074997200
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.2042673725
Short name T238
Test name
Test status
Simulation time 389398916 ps
CPU time 4.44 seconds
Started Jul 13 06:59:49 PM PDT 24
Finished Jul 13 06:59:57 PM PDT 24
Peak memory 232840 kb
Host smart-7714e26b-0a04-42fa-b586-9f0e08fe1297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042673725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.2042673725
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.997590966
Short name T371
Test name
Test status
Simulation time 80242625 ps
CPU time 0.85 seconds
Started Jul 13 06:59:49 PM PDT 24
Finished Jul 13 06:59:53 PM PDT 24
Peak memory 207084 kb
Host smart-b980c585-cfde-4989-aabe-64d9e037415c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997590966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.997590966
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.4046117296
Short name T856
Test name
Test status
Simulation time 1027732332 ps
CPU time 11.27 seconds
Started Jul 13 06:59:55 PM PDT 24
Finished Jul 13 07:00:11 PM PDT 24
Peak memory 240840 kb
Host smart-cdb62e27-9942-4446-8467-fd0f0b7030fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046117296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.4046117296
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.1395659484
Short name T33
Test name
Test status
Simulation time 1058088701 ps
CPU time 23.13 seconds
Started Jul 13 06:59:52 PM PDT 24
Finished Jul 13 07:00:19 PM PDT 24
Peak memory 240968 kb
Host smart-0e2d006f-5b52-49b1-9e3d-03f06df76812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395659484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.1395659484
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.634796546
Short name T775
Test name
Test status
Simulation time 16669916338 ps
CPU time 89.09 seconds
Started Jul 13 06:59:51 PM PDT 24
Finished Jul 13 07:01:25 PM PDT 24
Peak memory 251320 kb
Host smart-df042c98-9d82-4b07-ae03-2aeec60c2ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634796546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idle
.634796546
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.2369428751
Short name T842
Test name
Test status
Simulation time 24562141796 ps
CPU time 19.62 seconds
Started Jul 13 06:59:50 PM PDT 24
Finished Jul 13 07:00:12 PM PDT 24
Peak memory 236096 kb
Host smart-5c9b8dd3-bf92-44b1-b95b-9f1eac27d977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369428751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.2369428751
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.2924250062
Short name T4
Test name
Test status
Simulation time 919727806 ps
CPU time 3.69 seconds
Started Jul 13 06:59:52 PM PDT 24
Finished Jul 13 07:00:00 PM PDT 24
Peak memory 224448 kb
Host smart-fb108d1d-3137-47b3-9132-ff9464d0491d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924250062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.2924250062
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.1667188701
Short name T906
Test name
Test status
Simulation time 1328996386 ps
CPU time 12.21 seconds
Started Jul 13 06:59:54 PM PDT 24
Finished Jul 13 07:00:11 PM PDT 24
Peak memory 240660 kb
Host smart-4ee0c344-6960-4297-a36b-57d2419f793a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667188701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.1667188701
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.3966031512
Short name T630
Test name
Test status
Simulation time 35102157 ps
CPU time 2.35 seconds
Started Jul 13 06:59:51 PM PDT 24
Finished Jul 13 06:59:57 PM PDT 24
Peak memory 232704 kb
Host smart-95b924f7-a032-40ea-8fae-54f789a39478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966031512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.3966031512
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.2920728360
Short name T137
Test name
Test status
Simulation time 4388878730 ps
CPU time 6.24 seconds
Started Jul 13 06:59:54 PM PDT 24
Finished Jul 13 07:00:05 PM PDT 24
Peak memory 232820 kb
Host smart-20e2867c-e080-4259-861b-53e787d2c6fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920728360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.2920728360
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.1235995119
Short name T436
Test name
Test status
Simulation time 5280611413 ps
CPU time 12.87 seconds
Started Jul 13 06:59:49 PM PDT 24
Finished Jul 13 07:00:05 PM PDT 24
Peak memory 222120 kb
Host smart-0c743988-f52d-43d3-97c5-5fbc340da538
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1235995119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.1235995119
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.3920060518
Short name T876
Test name
Test status
Simulation time 62499490 ps
CPU time 1.11 seconds
Started Jul 13 06:59:54 PM PDT 24
Finished Jul 13 06:59:59 PM PDT 24
Peak memory 206924 kb
Host smart-7efefac0-5caa-4a8c-8f19-47037f833e56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920060518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.3920060518
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.1439474069
Short name T311
Test name
Test status
Simulation time 1007393867 ps
CPU time 15.9 seconds
Started Jul 13 06:59:55 PM PDT 24
Finished Jul 13 07:00:16 PM PDT 24
Peak memory 216308 kb
Host smart-08bff2fa-dcf1-4d15-9af4-8723a41f7c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439474069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.1439474069
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.3124255448
Short name T584
Test name
Test status
Simulation time 5543588975 ps
CPU time 15.16 seconds
Started Jul 13 06:59:47 PM PDT 24
Finished Jul 13 07:00:04 PM PDT 24
Peak memory 216344 kb
Host smart-7554a4ff-4b2c-4d06-8f2b-022037e13081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124255448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.3124255448
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.1199797914
Short name T627
Test name
Test status
Simulation time 47470909 ps
CPU time 1.27 seconds
Started Jul 13 06:59:51 PM PDT 24
Finished Jul 13 06:59:56 PM PDT 24
Peak memory 207928 kb
Host smart-e7acf0a8-62e0-4a84-82ff-ab3a1ea774f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199797914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.1199797914
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.3378726951
Short name T717
Test name
Test status
Simulation time 117816148 ps
CPU time 0.79 seconds
Started Jul 13 06:59:53 PM PDT 24
Finished Jul 13 06:59:58 PM PDT 24
Peak memory 205988 kb
Host smart-3fa85fef-8457-46ff-bfad-62b2292fc445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378726951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.3378726951
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.2652956783
Short name T48
Test name
Test status
Simulation time 583796603 ps
CPU time 5.99 seconds
Started Jul 13 06:59:50 PM PDT 24
Finished Jul 13 06:59:59 PM PDT 24
Peak memory 232652 kb
Host smart-aca8f603-5437-4167-99a2-291832516f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652956783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.2652956783
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.492284952
Short name T323
Test name
Test status
Simulation time 14077198 ps
CPU time 0.71 seconds
Started Jul 13 07:00:00 PM PDT 24
Finished Jul 13 07:00:04 PM PDT 24
Peak memory 205380 kb
Host smart-8d9e2a08-e0da-45a4-b732-ee4bb101091f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492284952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.492284952
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.1386109800
Short name T874
Test name
Test status
Simulation time 108230184 ps
CPU time 2.51 seconds
Started Jul 13 07:00:03 PM PDT 24
Finished Jul 13 07:00:07 PM PDT 24
Peak memory 224504 kb
Host smart-0eeacb12-1f0f-4e09-96f7-6d70023858e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386109800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.1386109800
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.2703745308
Short name T70
Test name
Test status
Simulation time 13168460 ps
CPU time 0.8 seconds
Started Jul 13 06:59:55 PM PDT 24
Finished Jul 13 07:00:01 PM PDT 24
Peak memory 206628 kb
Host smart-def9ac4f-1725-4621-b656-eb172a919a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703745308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.2703745308
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.2205382317
Short name T222
Test name
Test status
Simulation time 46376258452 ps
CPU time 110.99 seconds
Started Jul 13 07:00:12 PM PDT 24
Finished Jul 13 07:02:03 PM PDT 24
Peak memory 254588 kb
Host smart-ac1360fa-88ae-481b-abb2-d21e76f4239a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205382317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.2205382317
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.199090660
Short name T283
Test name
Test status
Simulation time 29244527563 ps
CPU time 68.09 seconds
Started Jul 13 07:00:02 PM PDT 24
Finished Jul 13 07:01:12 PM PDT 24
Peak memory 235768 kb
Host smart-a79ef60d-fb5f-4f15-a626-77727da465c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199090660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.199090660
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.2526075071
Short name T282
Test name
Test status
Simulation time 89512709176 ps
CPU time 455.85 seconds
Started Jul 13 06:59:57 PM PDT 24
Finished Jul 13 07:07:37 PM PDT 24
Peak memory 253968 kb
Host smart-35c2ae5c-9ae5-4dd7-8b51-5780e1c6c083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526075071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.2526075071
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.3885087812
Short name T930
Test name
Test status
Simulation time 189451387 ps
CPU time 5.64 seconds
Started Jul 13 06:59:57 PM PDT 24
Finished Jul 13 07:00:07 PM PDT 24
Peak memory 234732 kb
Host smart-87e75a68-896e-4c96-91d7-b67b479855f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885087812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.3885087812
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.399578834
Short name T291
Test name
Test status
Simulation time 2405948726 ps
CPU time 17.8 seconds
Started Jul 13 06:59:58 PM PDT 24
Finished Jul 13 07:00:20 PM PDT 24
Peak memory 241016 kb
Host smart-043f233e-0a62-4021-99d7-57ed28d40019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399578834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmds
.399578834
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_intercept.3099363225
Short name T201
Test name
Test status
Simulation time 890935972 ps
CPU time 5.56 seconds
Started Jul 13 07:00:12 PM PDT 24
Finished Jul 13 07:00:18 PM PDT 24
Peak memory 224476 kb
Host smart-1cd68045-ffc2-4fe4-a809-aecba3287f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099363225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.3099363225
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.2290185940
Short name T954
Test name
Test status
Simulation time 75878017 ps
CPU time 2.08 seconds
Started Jul 13 07:00:01 PM PDT 24
Finished Jul 13 07:00:06 PM PDT 24
Peak memory 223844 kb
Host smart-8529f9fe-148c-47b0-88a8-6cb49cd7bdb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290185940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.2290185940
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.1957155436
Short name T926
Test name
Test status
Simulation time 4909608650 ps
CPU time 9.46 seconds
Started Jul 13 06:59:55 PM PDT 24
Finished Jul 13 07:00:09 PM PDT 24
Peak memory 232820 kb
Host smart-4aed08f9-955b-43d1-8303-88ae89ea268e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957155436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.1957155436
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.533131594
Short name T687
Test name
Test status
Simulation time 26778822926 ps
CPU time 20.21 seconds
Started Jul 13 06:59:59 PM PDT 24
Finished Jul 13 07:00:23 PM PDT 24
Peak memory 232628 kb
Host smart-2e40bf41-5e22-4c76-8273-e1354e398cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533131594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.533131594
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.2850733761
Short name T466
Test name
Test status
Simulation time 2447754526 ps
CPU time 13.56 seconds
Started Jul 13 06:59:57 PM PDT 24
Finished Jul 13 07:00:15 PM PDT 24
Peak memory 218920 kb
Host smart-b1e78555-996a-48d8-ad60-f89bbfac4825
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2850733761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.2850733761
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.3361849376
Short name T418
Test name
Test status
Simulation time 38233265936 ps
CPU time 48.39 seconds
Started Jul 13 06:59:57 PM PDT 24
Finished Jul 13 07:00:50 PM PDT 24
Peak memory 217612 kb
Host smart-69484568-fd3a-406c-a1a0-a42c25f7f68c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361849376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.3361849376
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.2971066983
Short name T621
Test name
Test status
Simulation time 2031852769 ps
CPU time 5.37 seconds
Started Jul 13 06:59:56 PM PDT 24
Finished Jul 13 07:00:06 PM PDT 24
Peak memory 216224 kb
Host smart-e2e15c13-57f0-4b6a-a826-a602a567566b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971066983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.2971066983
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.380276451
Short name T548
Test name
Test status
Simulation time 77172432 ps
CPU time 1.21 seconds
Started Jul 13 07:00:02 PM PDT 24
Finished Jul 13 07:00:05 PM PDT 24
Peak memory 216216 kb
Host smart-fd84c483-c571-4b9d-8874-f03ae608e043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380276451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.380276451
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.1481837643
Short name T409
Test name
Test status
Simulation time 183205378 ps
CPU time 0.72 seconds
Started Jul 13 06:59:55 PM PDT 24
Finished Jul 13 07:00:00 PM PDT 24
Peak memory 205620 kb
Host smart-3ed4d354-221a-451c-ad0e-8b45d89bce80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481837643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.1481837643
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.3542440952
Short name T766
Test name
Test status
Simulation time 2235830841 ps
CPU time 6.9 seconds
Started Jul 13 06:59:57 PM PDT 24
Finished Jul 13 07:00:08 PM PDT 24
Peak memory 232728 kb
Host smart-bb385ea6-ec47-464d-8013-4bd242791ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542440952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.3542440952
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.1087010498
Short name T946
Test name
Test status
Simulation time 15181362 ps
CPU time 0.8 seconds
Started Jul 13 06:59:07 PM PDT 24
Finished Jul 13 06:59:09 PM PDT 24
Peak memory 204940 kb
Host smart-716001b4-35fc-4b2a-b822-cdaafbc9295c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087010498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.1
087010498
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.3128241149
Short name T558
Test name
Test status
Simulation time 36971574 ps
CPU time 2.08 seconds
Started Jul 13 06:59:14 PM PDT 24
Finished Jul 13 06:59:18 PM PDT 24
Peak memory 223596 kb
Host smart-2238a40e-23ee-4e0c-a1d2-9d1cdb13b052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128241149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.3128241149
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.1758415553
Short name T913
Test name
Test status
Simulation time 15017944 ps
CPU time 0.75 seconds
Started Jul 13 06:59:10 PM PDT 24
Finished Jul 13 06:59:12 PM PDT 24
Peak memory 205900 kb
Host smart-c61667f2-0214-4be5-aa4c-eca65f5d1b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758415553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.1758415553
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.3405331467
Short name T505
Test name
Test status
Simulation time 2979151745 ps
CPU time 37.59 seconds
Started Jul 13 06:59:09 PM PDT 24
Finished Jul 13 06:59:47 PM PDT 24
Peak memory 249232 kb
Host smart-b9d19c56-5f69-4616-a184-f0c7bcb17d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405331467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.3405331467
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.2602663261
Short name T1000
Test name
Test status
Simulation time 15148756648 ps
CPU time 148.68 seconds
Started Jul 13 06:59:12 PM PDT 24
Finished Jul 13 07:01:43 PM PDT 24
Peak memory 265656 kb
Host smart-a901696d-a829-4af3-aea0-bbe73f2492ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602663261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.2602663261
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.1529369045
Short name T757
Test name
Test status
Simulation time 3253934835 ps
CPU time 33.7 seconds
Started Jul 13 06:59:10 PM PDT 24
Finished Jul 13 06:59:46 PM PDT 24
Peak memory 232764 kb
Host smart-c281ddb5-0203-419d-b3aa-2ee4cfae5f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529369045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.1529369045
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.349824500
Short name T414
Test name
Test status
Simulation time 23867477260 ps
CPU time 169.41 seconds
Started Jul 13 06:59:10 PM PDT 24
Finished Jul 13 07:02:00 PM PDT 24
Peak memory 249504 kb
Host smart-ff8e45d0-6e05-4570-acb5-ada63e23f713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349824500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds.
349824500
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.2895371913
Short name T508
Test name
Test status
Simulation time 2200374110 ps
CPU time 8.56 seconds
Started Jul 13 06:59:12 PM PDT 24
Finished Jul 13 06:59:23 PM PDT 24
Peak memory 232704 kb
Host smart-50810238-3aa9-4108-a694-6e4eadcc5366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895371913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.2895371913
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.792565582
Short name T625
Test name
Test status
Simulation time 4049983363 ps
CPU time 30.78 seconds
Started Jul 13 06:59:10 PM PDT 24
Finished Jul 13 06:59:42 PM PDT 24
Peak memory 232832 kb
Host smart-cb113c44-74bb-427c-b8f3-e03aa1922b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792565582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.792565582
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.536042097
Short name T594
Test name
Test status
Simulation time 326476038 ps
CPU time 3.32 seconds
Started Jul 13 06:59:11 PM PDT 24
Finished Jul 13 06:59:17 PM PDT 24
Peak memory 232668 kb
Host smart-b149969e-403a-424d-a67f-953d42c77375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536042097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap.
536042097
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.699588782
Short name T150
Test name
Test status
Simulation time 242216142 ps
CPU time 4.56 seconds
Started Jul 13 06:59:10 PM PDT 24
Finished Jul 13 06:59:17 PM PDT 24
Peak memory 218800 kb
Host smart-baf08db6-3256-4030-8a67-057d32820e41
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=699588782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_direc
t.699588782
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.2221421037
Short name T79
Test name
Test status
Simulation time 177048572 ps
CPU time 0.97 seconds
Started Jul 13 06:59:11 PM PDT 24
Finished Jul 13 06:59:14 PM PDT 24
Peak memory 235928 kb
Host smart-1bf68753-7d43-4944-b554-1e0fcd1549df
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221421037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.2221421037
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.2430028601
Short name T289
Test name
Test status
Simulation time 12543637979 ps
CPU time 159.09 seconds
Started Jul 13 06:59:09 PM PDT 24
Finished Jul 13 07:01:49 PM PDT 24
Peak memory 273852 kb
Host smart-ba4d0ec0-d45d-4bd0-b5ef-b8423101f38d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430028601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.2430028601
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.3567265088
Short name T595
Test name
Test status
Simulation time 7724315545 ps
CPU time 36.62 seconds
Started Jul 13 06:59:10 PM PDT 24
Finished Jul 13 06:59:48 PM PDT 24
Peak memory 216568 kb
Host smart-32f349a3-d9d5-48c1-aac8-61ffe2d082ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567265088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.3567265088
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.147097467
Short name T997
Test name
Test status
Simulation time 11610031971 ps
CPU time 8.49 seconds
Started Jul 13 06:59:14 PM PDT 24
Finished Jul 13 06:59:25 PM PDT 24
Peak memory 216360 kb
Host smart-e513afab-3505-497a-83a8-a4d7a3998c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147097467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.147097467
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.547826238
Short name T427
Test name
Test status
Simulation time 345038083 ps
CPU time 1.03 seconds
Started Jul 13 06:59:13 PM PDT 24
Finished Jul 13 06:59:17 PM PDT 24
Peak memory 207880 kb
Host smart-078807e1-f934-4c1e-a036-b3f896818bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547826238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.547826238
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.375720167
Short name T424
Test name
Test status
Simulation time 58612195 ps
CPU time 0.94 seconds
Started Jul 13 06:59:08 PM PDT 24
Finished Jul 13 06:59:09 PM PDT 24
Peak memory 207028 kb
Host smart-12bda27c-3b0e-4a43-864d-c794532e18eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375720167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.375720167
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.673507569
Short name T797
Test name
Test status
Simulation time 7544080931 ps
CPU time 25.19 seconds
Started Jul 13 06:59:09 PM PDT 24
Finished Jul 13 06:59:35 PM PDT 24
Peak memory 232840 kb
Host smart-ec269c76-0509-46d8-9451-4fd37e2c2d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673507569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.673507569
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.3958616342
Short name T74
Test name
Test status
Simulation time 59580129 ps
CPU time 0.7 seconds
Started Jul 13 06:59:55 PM PDT 24
Finished Jul 13 07:00:00 PM PDT 24
Peak memory 205520 kb
Host smart-65fc394f-a2ad-4c4a-921b-c3c8a14759c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958616342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
3958616342
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.3925237172
Short name T513
Test name
Test status
Simulation time 1908923095 ps
CPU time 3.02 seconds
Started Jul 13 07:00:01 PM PDT 24
Finished Jul 13 07:00:06 PM PDT 24
Peak memory 224368 kb
Host smart-1cd06bee-dd10-48ea-bc99-7c782b007e2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925237172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.3925237172
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.1336836277
Short name T596
Test name
Test status
Simulation time 21708050 ps
CPU time 0.79 seconds
Started Jul 13 07:00:02 PM PDT 24
Finished Jul 13 07:00:05 PM PDT 24
Peak memory 206920 kb
Host smart-40b009d3-7f09-4ad4-b57b-69d4f34c337f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336836277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.1336836277
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.1117415740
Short name T610
Test name
Test status
Simulation time 9928454189 ps
CPU time 56.81 seconds
Started Jul 13 06:59:59 PM PDT 24
Finished Jul 13 07:00:59 PM PDT 24
Peak memory 249160 kb
Host smart-5ac143aa-fba4-4e38-8c8d-238629d9f0f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117415740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.1117415740
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.2647610181
Short name T189
Test name
Test status
Simulation time 22554601306 ps
CPU time 145.51 seconds
Started Jul 13 06:59:59 PM PDT 24
Finished Jul 13 07:02:28 PM PDT 24
Peak memory 273804 kb
Host smart-9541d56f-abb0-486a-9d76-f5c238928ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647610181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.2647610181
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.2995979771
Short name T611
Test name
Test status
Simulation time 27200501792 ps
CPU time 108.28 seconds
Started Jul 13 06:59:58 PM PDT 24
Finished Jul 13 07:01:50 PM PDT 24
Peak memory 257436 kb
Host smart-0a932c4d-bb74-4d7c-8630-3bc30c8889bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995979771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.2995979771
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.812352443
Short name T751
Test name
Test status
Simulation time 823763405 ps
CPU time 7.2 seconds
Started Jul 13 07:00:08 PM PDT 24
Finished Jul 13 07:00:17 PM PDT 24
Peak memory 224484 kb
Host smart-5b6dcded-0a7d-4021-b311-72b1bb157876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812352443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.812352443
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.1144452210
Short name T93
Test name
Test status
Simulation time 5117080862 ps
CPU time 60.47 seconds
Started Jul 13 06:59:57 PM PDT 24
Finished Jul 13 07:01:02 PM PDT 24
Peak memory 253676 kb
Host smart-524452d9-1c5f-4583-8263-6d4a52cb1bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144452210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmd
s.1144452210
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_intercept.2715551636
Short name T511
Test name
Test status
Simulation time 247912294 ps
CPU time 2.47 seconds
Started Jul 13 06:59:57 PM PDT 24
Finished Jul 13 07:00:03 PM PDT 24
Peak memory 224468 kb
Host smart-91fc3866-d939-4731-aa90-a3b98a92d30e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715551636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.2715551636
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.3297855058
Short name T569
Test name
Test status
Simulation time 862267098 ps
CPU time 5.81 seconds
Started Jul 13 06:59:58 PM PDT 24
Finished Jul 13 07:00:08 PM PDT 24
Peak memory 235100 kb
Host smart-1e6b2d37-b93c-4bfd-93f2-e9f76e563bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297855058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.3297855058
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.304884168
Short name T758
Test name
Test status
Simulation time 1993496163 ps
CPU time 8.81 seconds
Started Jul 13 06:59:58 PM PDT 24
Finished Jul 13 07:00:11 PM PDT 24
Peak memory 232632 kb
Host smart-692b7d01-d397-4409-a95e-410a746bbb00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304884168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swap
.304884168
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.2099981680
Short name T951
Test name
Test status
Simulation time 3171906669 ps
CPU time 5.19 seconds
Started Jul 13 07:00:01 PM PDT 24
Finished Jul 13 07:00:09 PM PDT 24
Peak memory 233828 kb
Host smart-f217a9bb-386f-46b7-92a7-de1c7a015465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099981680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.2099981680
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.939142811
Short name T151
Test name
Test status
Simulation time 2362953221 ps
CPU time 7.51 seconds
Started Jul 13 06:59:59 PM PDT 24
Finished Jul 13 07:00:10 PM PDT 24
Peak memory 220540 kb
Host smart-6560c0a4-0c40-4cb0-ba6e-82cece5e3d19
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=939142811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dire
ct.939142811
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.3482138438
Short name T538
Test name
Test status
Simulation time 17574708250 ps
CPU time 176.95 seconds
Started Jul 13 06:59:55 PM PDT 24
Finished Jul 13 07:02:57 PM PDT 24
Peak memory 249212 kb
Host smart-201dc849-6736-4503-b37a-c89f45537cc1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482138438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.3482138438
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.4075908336
Short name T893
Test name
Test status
Simulation time 79688565 ps
CPU time 0.79 seconds
Started Jul 13 07:00:03 PM PDT 24
Finished Jul 13 07:00:05 PM PDT 24
Peak memory 205728 kb
Host smart-c8f3e473-d8e6-4981-9a5e-7fba84b75fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075908336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.4075908336
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.2047672025
Short name T395
Test name
Test status
Simulation time 294580423 ps
CPU time 2 seconds
Started Jul 13 07:00:10 PM PDT 24
Finished Jul 13 07:00:13 PM PDT 24
Peak memory 207880 kb
Host smart-6429db6c-0659-4596-b32a-4f4c722a73e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047672025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.2047672025
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.1216840670
Short name T878
Test name
Test status
Simulation time 11073721 ps
CPU time 0.69 seconds
Started Jul 13 07:00:10 PM PDT 24
Finished Jul 13 07:00:12 PM PDT 24
Peak memory 205644 kb
Host smart-dd756f0f-f4d9-43f9-8b8f-0aa7cf86333c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216840670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.1216840670
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.2159286230
Short name T681
Test name
Test status
Simulation time 398650908 ps
CPU time 0.94 seconds
Started Jul 13 07:00:10 PM PDT 24
Finished Jul 13 07:00:12 PM PDT 24
Peak memory 205980 kb
Host smart-c1eb08be-9e98-42b4-bbea-cf19ae409469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159286230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.2159286230
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.3577614253
Short name T651
Test name
Test status
Simulation time 1241901642 ps
CPU time 8.46 seconds
Started Jul 13 07:00:11 PM PDT 24
Finished Jul 13 07:00:20 PM PDT 24
Peak memory 240688 kb
Host smart-1e337c9f-946f-48ce-b931-c990e39c1e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577614253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.3577614253
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.1124335508
Short name T387
Test name
Test status
Simulation time 18787054 ps
CPU time 0.73 seconds
Started Jul 13 07:00:04 PM PDT 24
Finished Jul 13 07:00:06 PM PDT 24
Peak memory 205512 kb
Host smart-872cfbac-5fab-4daf-9416-e46412079b34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124335508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
1124335508
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.2711705353
Short name T535
Test name
Test status
Simulation time 871816677 ps
CPU time 6.21 seconds
Started Jul 13 06:59:57 PM PDT 24
Finished Jul 13 07:00:07 PM PDT 24
Peak memory 232672 kb
Host smart-7c6c20d1-896c-4b6b-8f43-de7e43e1de84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711705353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.2711705353
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.2621605747
Short name T801
Test name
Test status
Simulation time 21046414 ps
CPU time 0.8 seconds
Started Jul 13 07:00:10 PM PDT 24
Finished Jul 13 07:00:12 PM PDT 24
Peak memory 206580 kb
Host smart-092a1fd3-034a-45b1-8fcc-30f20cf82f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621605747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.2621605747
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.210138133
Short name T622
Test name
Test status
Simulation time 18213985530 ps
CPU time 184.43 seconds
Started Jul 13 06:59:56 PM PDT 24
Finished Jul 13 07:03:05 PM PDT 24
Peak memory 251728 kb
Host smart-dcda6c87-b9f4-4769-8ffe-cfc03cebe032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210138133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.210138133
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.304809470
Short name T305
Test name
Test status
Simulation time 3586577805 ps
CPU time 48.64 seconds
Started Jul 13 07:00:06 PM PDT 24
Finished Jul 13 07:00:56 PM PDT 24
Peak memory 249156 kb
Host smart-d7ed4152-a91a-47da-916d-8ad58a9330c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304809470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.304809470
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.653004980
Short name T397
Test name
Test status
Simulation time 5561254002 ps
CPU time 17.46 seconds
Started Jul 13 06:59:57 PM PDT 24
Finished Jul 13 07:00:19 PM PDT 24
Peak memory 237676 kb
Host smart-d2fdccf3-3677-4790-a393-96773fbf4869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653004980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmds
.653004980
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.203702926
Short name T562
Test name
Test status
Simulation time 1924550019 ps
CPU time 20.79 seconds
Started Jul 13 07:00:10 PM PDT 24
Finished Jul 13 07:00:32 PM PDT 24
Peak memory 224480 kb
Host smart-cc779940-9125-46f9-8a06-80d168de2282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203702926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.203702926
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.2779928430
Short name T827
Test name
Test status
Simulation time 638186991 ps
CPU time 10.78 seconds
Started Jul 13 07:00:02 PM PDT 24
Finished Jul 13 07:00:15 PM PDT 24
Peak memory 224400 kb
Host smart-26074ce2-574e-4f75-9b2d-6657e82709ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779928430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.2779928430
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.1886045722
Short name T756
Test name
Test status
Simulation time 915249895 ps
CPU time 4.85 seconds
Started Jul 13 07:00:02 PM PDT 24
Finished Jul 13 07:00:09 PM PDT 24
Peak memory 224428 kb
Host smart-66edc4e5-88d1-475e-80e0-b43e9972704d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886045722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.1886045722
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.3372979890
Short name T905
Test name
Test status
Simulation time 14076208806 ps
CPU time 7.24 seconds
Started Jul 13 06:59:57 PM PDT 24
Finished Jul 13 07:00:08 PM PDT 24
Peak memory 224620 kb
Host smart-a54f19d2-39a1-4e19-97a7-95a3cd660987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372979890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.3372979890
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.3898827594
Short name T512
Test name
Test status
Simulation time 284030264 ps
CPU time 4.6 seconds
Started Jul 13 06:59:59 PM PDT 24
Finished Jul 13 07:00:07 PM PDT 24
Peak memory 223172 kb
Host smart-52ca311d-27fe-49d5-a38b-0653c0ab5714
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3898827594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.3898827594
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.2395771278
Short name T288
Test name
Test status
Simulation time 164823338836 ps
CPU time 672.01 seconds
Started Jul 13 07:00:05 PM PDT 24
Finished Jul 13 07:11:19 PM PDT 24
Peak memory 266972 kb
Host smart-fc866580-edfa-43ab-821d-f8c62ae57b75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395771278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.2395771278
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.3268491489
Short name T661
Test name
Test status
Simulation time 1367510183 ps
CPU time 19.02 seconds
Started Jul 13 07:00:01 PM PDT 24
Finished Jul 13 07:00:22 PM PDT 24
Peak memory 219408 kb
Host smart-73c6cb51-80d3-42d1-8880-b3497e96c879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268491489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.3268491489
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.139902627
Short name T499
Test name
Test status
Simulation time 960208083 ps
CPU time 4.95 seconds
Started Jul 13 07:00:01 PM PDT 24
Finished Jul 13 07:00:08 PM PDT 24
Peak memory 216220 kb
Host smart-ee24472b-40dd-44f7-8e81-c725b64e6115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139902627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.139902627
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.1251964747
Short name T555
Test name
Test status
Simulation time 67072463 ps
CPU time 1.3 seconds
Started Jul 13 07:00:02 PM PDT 24
Finished Jul 13 07:00:05 PM PDT 24
Peak memory 216200 kb
Host smart-b4897f25-b49e-4801-b844-3df032da6b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251964747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.1251964747
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.321017459
Short name T771
Test name
Test status
Simulation time 55523639 ps
CPU time 0.74 seconds
Started Jul 13 06:59:59 PM PDT 24
Finished Jul 13 07:00:03 PM PDT 24
Peak memory 205952 kb
Host smart-328d6382-6114-46fc-a89f-5ca1c41e80f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321017459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.321017459
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.731763520
Short name T556
Test name
Test status
Simulation time 4134675030 ps
CPU time 5.89 seconds
Started Jul 13 06:59:57 PM PDT 24
Finished Jul 13 07:00:07 PM PDT 24
Peak memory 224632 kb
Host smart-c5cb1d89-99e3-42f2-ab80-0c21c825dac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731763520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.731763520
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.1048690432
Short name T723
Test name
Test status
Simulation time 51831483 ps
CPU time 0.71 seconds
Started Jul 13 07:00:07 PM PDT 24
Finished Jul 13 07:00:10 PM PDT 24
Peak memory 205508 kb
Host smart-5fa6c6dc-13b7-4312-99dd-80390e93394d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048690432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
1048690432
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.260944881
Short name T437
Test name
Test status
Simulation time 206532266 ps
CPU time 3.22 seconds
Started Jul 13 07:00:06 PM PDT 24
Finished Jul 13 07:00:10 PM PDT 24
Peak memory 232704 kb
Host smart-6758f443-06bf-4ff6-9225-98f8fb3eefe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260944881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.260944881
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.1699062413
Short name T609
Test name
Test status
Simulation time 21094289 ps
CPU time 0.79 seconds
Started Jul 13 07:00:08 PM PDT 24
Finished Jul 13 07:00:11 PM PDT 24
Peak memory 206636 kb
Host smart-e5667a39-84fe-401f-9873-e677702012f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699062413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.1699062413
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.1018093110
Short name T796
Test name
Test status
Simulation time 1258999396 ps
CPU time 24.07 seconds
Started Jul 13 07:00:06 PM PDT 24
Finished Jul 13 07:00:32 PM PDT 24
Peak memory 232704 kb
Host smart-0aa2ee6a-3b6f-41ac-81cc-41801a3c3611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018093110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.1018093110
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.435667167
Short name T192
Test name
Test status
Simulation time 41460826587 ps
CPU time 414.41 seconds
Started Jul 13 07:00:04 PM PDT 24
Finished Jul 13 07:06:59 PM PDT 24
Peak memory 257452 kb
Host smart-8f0e63e1-3ab0-4ae2-9b82-3150eb7afcd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435667167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.435667167
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.1853786332
Short name T416
Test name
Test status
Simulation time 4403290087 ps
CPU time 63.98 seconds
Started Jul 13 07:00:07 PM PDT 24
Finished Jul 13 07:01:13 PM PDT 24
Peak memory 255356 kb
Host smart-85a2c5f8-cbf3-45e4-8707-8eb01c8de4f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853786332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.1853786332
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.1845819718
Short name T329
Test name
Test status
Simulation time 215531454 ps
CPU time 6.32 seconds
Started Jul 13 07:00:20 PM PDT 24
Finished Jul 13 07:00:26 PM PDT 24
Peak memory 232656 kb
Host smart-13601380-f5fe-461c-bf27-eea4892f0c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845819718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.1845819718
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.409951888
Short name T379
Test name
Test status
Simulation time 29942869450 ps
CPU time 123.64 seconds
Started Jul 13 07:00:06 PM PDT 24
Finished Jul 13 07:02:12 PM PDT 24
Peak memory 249212 kb
Host smart-42ef6303-6f28-49f3-a0d5-f2f1ebb16492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409951888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmds
.409951888
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.2348854735
Short name T220
Test name
Test status
Simulation time 615891832 ps
CPU time 6.12 seconds
Started Jul 13 07:00:06 PM PDT 24
Finished Jul 13 07:00:13 PM PDT 24
Peak memory 232644 kb
Host smart-e8248afa-b816-4a66-b7e8-2e189489317d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348854735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.2348854735
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.3625594526
Short name T763
Test name
Test status
Simulation time 15773541612 ps
CPU time 59.63 seconds
Started Jul 13 07:00:07 PM PDT 24
Finished Jul 13 07:01:09 PM PDT 24
Peak memory 232772 kb
Host smart-711a0a5e-c5dd-48bf-a01b-0fb2a7d36894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625594526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.3625594526
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.337678232
Short name T1003
Test name
Test status
Simulation time 1116528228 ps
CPU time 5.42 seconds
Started Jul 13 07:00:07 PM PDT 24
Finished Jul 13 07:00:15 PM PDT 24
Peak memory 232820 kb
Host smart-dffe01bc-7ddb-46cc-bea9-fdd47038b7cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337678232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swap
.337678232
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.3453978508
Short name T604
Test name
Test status
Simulation time 14690628044 ps
CPU time 13.59 seconds
Started Jul 13 07:00:09 PM PDT 24
Finished Jul 13 07:00:24 PM PDT 24
Peak memory 240964 kb
Host smart-25b57e11-6831-4701-86d7-f569122c7c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453978508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.3453978508
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.2589035447
Short name T922
Test name
Test status
Simulation time 1830965653 ps
CPU time 14.28 seconds
Started Jul 13 07:00:06 PM PDT 24
Finished Jul 13 07:00:22 PM PDT 24
Peak memory 219132 kb
Host smart-e8f4178c-b55b-4999-a614-035f9c231e21
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2589035447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.2589035447
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.2763754587
Short name T378
Test name
Test status
Simulation time 67669847 ps
CPU time 0.97 seconds
Started Jul 13 07:00:06 PM PDT 24
Finished Jul 13 07:00:09 PM PDT 24
Peak memory 207000 kb
Host smart-7f3623f0-22dd-4ffa-8d1b-f30577a54693
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763754587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.2763754587
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.119139307
Short name T307
Test name
Test status
Simulation time 1669217638 ps
CPU time 22.8 seconds
Started Jul 13 07:00:04 PM PDT 24
Finished Jul 13 07:00:28 PM PDT 24
Peak memory 216220 kb
Host smart-e0c3d715-7fb4-4708-9152-5ac71848228f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119139307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.119139307
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.2020864689
Short name T955
Test name
Test status
Simulation time 6417093879 ps
CPU time 10.78 seconds
Started Jul 13 07:00:19 PM PDT 24
Finished Jul 13 07:00:31 PM PDT 24
Peak memory 216264 kb
Host smart-0c46fd4b-9cbd-4920-9594-9d93986af412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020864689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.2020864689
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.943783545
Short name T383
Test name
Test status
Simulation time 580856999 ps
CPU time 2.85 seconds
Started Jul 13 07:00:08 PM PDT 24
Finished Jul 13 07:00:13 PM PDT 24
Peak memory 216248 kb
Host smart-e46a6225-1d7c-49fb-ba32-b9863c1f4c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943783545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.943783545
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.692182307
Short name T497
Test name
Test status
Simulation time 44598929 ps
CPU time 0.91 seconds
Started Jul 13 07:00:07 PM PDT 24
Finished Jul 13 07:00:10 PM PDT 24
Peak memory 205988 kb
Host smart-fe76f283-6909-4adb-b669-e7066a9d1dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692182307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.692182307
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.3313012507
Short name T1011
Test name
Test status
Simulation time 11152453035 ps
CPU time 14.97 seconds
Started Jul 13 07:00:06 PM PDT 24
Finished Jul 13 07:00:22 PM PDT 24
Peak memory 224640 kb
Host smart-ccbcbc45-0992-409e-b352-9ee3929d4781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313012507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.3313012507
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.2425153046
Short name T660
Test name
Test status
Simulation time 42868759 ps
CPU time 0.75 seconds
Started Jul 13 07:00:07 PM PDT 24
Finished Jul 13 07:00:10 PM PDT 24
Peak memory 204944 kb
Host smart-6c24adb4-774e-46f4-a2b2-0cb2c7d48c10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425153046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
2425153046
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.3965546680
Short name T936
Test name
Test status
Simulation time 2421127999 ps
CPU time 7.19 seconds
Started Jul 13 07:00:06 PM PDT 24
Finished Jul 13 07:00:15 PM PDT 24
Peak memory 224648 kb
Host smart-9ddf4b11-9bc5-4cfc-8a67-24762283f347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965546680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.3965546680
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.2657725700
Short name T71
Test name
Test status
Simulation time 22041693 ps
CPU time 0.81 seconds
Started Jul 13 07:00:07 PM PDT 24
Finished Jul 13 07:00:10 PM PDT 24
Peak memory 206920 kb
Host smart-ba4ff256-521a-4661-bebf-2ff3f741d152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657725700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.2657725700
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.2375550927
Short name T236
Test name
Test status
Simulation time 27892596776 ps
CPU time 157.17 seconds
Started Jul 13 07:00:05 PM PDT 24
Finished Jul 13 07:02:43 PM PDT 24
Peak memory 241000 kb
Host smart-b368c141-d90e-4f5d-92a6-880b674e430a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375550927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.2375550927
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.1835131246
Short name T42
Test name
Test status
Simulation time 28710259084 ps
CPU time 95.15 seconds
Started Jul 13 07:00:08 PM PDT 24
Finished Jul 13 07:01:45 PM PDT 24
Peak memory 252780 kb
Host smart-347a7fd2-f87c-466d-95ed-5d9ecff7d249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835131246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.1835131246
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.2541874295
Short name T169
Test name
Test status
Simulation time 40335975986 ps
CPU time 255.03 seconds
Started Jul 13 07:00:05 PM PDT 24
Finished Jul 13 07:04:21 PM PDT 24
Peak memory 255100 kb
Host smart-f73934e3-7bbb-4f10-a69c-b82aee4eaf94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541874295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.2541874295
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.4146546269
Short name T730
Test name
Test status
Simulation time 6482838852 ps
CPU time 18.23 seconds
Started Jul 13 07:00:07 PM PDT 24
Finished Jul 13 07:00:28 PM PDT 24
Peak memory 236304 kb
Host smart-5ff6e2b6-4a22-46ce-95e8-da44e3156366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146546269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.4146546269
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_intercept.3835358417
Short name T764
Test name
Test status
Simulation time 1709202118 ps
CPU time 15.08 seconds
Started Jul 13 07:00:05 PM PDT 24
Finished Jul 13 07:00:21 PM PDT 24
Peak memory 224436 kb
Host smart-d97b83da-d571-485a-bc58-6781f4938563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835358417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.3835358417
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.3988473347
Short name T593
Test name
Test status
Simulation time 1124532963 ps
CPU time 13.58 seconds
Started Jul 13 07:00:06 PM PDT 24
Finished Jul 13 07:00:21 PM PDT 24
Peak memory 232720 kb
Host smart-f76132a1-85a1-4ee8-a069-57e972d38ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988473347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.3988473347
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.2428666758
Short name T567
Test name
Test status
Simulation time 1023844667 ps
CPU time 5.42 seconds
Started Jul 13 07:00:19 PM PDT 24
Finished Jul 13 07:00:25 PM PDT 24
Peak memory 232600 kb
Host smart-f9b0f57c-5c56-435e-b256-eed37eee4287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428666758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.2428666758
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.187087675
Short name T747
Test name
Test status
Simulation time 2544693458 ps
CPU time 12.32 seconds
Started Jul 13 07:00:07 PM PDT 24
Finished Jul 13 07:00:21 PM PDT 24
Peak memory 224620 kb
Host smart-0fc37578-d954-4d18-8e36-63458f87b6d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187087675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.187087675
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.3399342113
Short name T849
Test name
Test status
Simulation time 1202280239 ps
CPU time 12.44 seconds
Started Jul 13 07:00:06 PM PDT 24
Finished Jul 13 07:00:20 PM PDT 24
Peak memory 219716 kb
Host smart-d430f2d1-d794-4e93-8601-e5e506557da1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3399342113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.3399342113
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.3957314334
Short name T579
Test name
Test status
Simulation time 686895566 ps
CPU time 4.16 seconds
Started Jul 13 07:00:16 PM PDT 24
Finished Jul 13 07:00:21 PM PDT 24
Peak memory 216124 kb
Host smart-d2657488-ed62-4245-9ad6-91b4e082bca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957314334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.3957314334
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.1205814817
Short name T391
Test name
Test status
Simulation time 591834617 ps
CPU time 4.38 seconds
Started Jul 13 07:00:05 PM PDT 24
Finished Jul 13 07:00:11 PM PDT 24
Peak memory 216044 kb
Host smart-1733ddcd-83a5-4d71-a116-35c505579ba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205814817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.1205814817
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.734561680
Short name T435
Test name
Test status
Simulation time 141413736 ps
CPU time 2.14 seconds
Started Jul 13 07:00:07 PM PDT 24
Finished Jul 13 07:00:11 PM PDT 24
Peak memory 216196 kb
Host smart-eb804fa2-ffea-4cc2-ba61-841e6071c334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734561680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.734561680
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.16844689
Short name T993
Test name
Test status
Simulation time 22419490 ps
CPU time 0.77 seconds
Started Jul 13 07:00:06 PM PDT 24
Finished Jul 13 07:00:08 PM PDT 24
Peak memory 205996 kb
Host smart-2e31d565-8e31-4a95-b0ba-ca02f9b956bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16844689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.16844689
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.2377299814
Short name T670
Test name
Test status
Simulation time 1372202582 ps
CPU time 12.71 seconds
Started Jul 13 07:00:16 PM PDT 24
Finished Jul 13 07:00:30 PM PDT 24
Peak memory 248996 kb
Host smart-c5500caa-6fd3-4884-9bf7-5ae1e8795f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377299814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.2377299814
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.3608939566
Short name T967
Test name
Test status
Simulation time 15615605 ps
CPU time 0.73 seconds
Started Jul 13 07:00:15 PM PDT 24
Finished Jul 13 07:00:17 PM PDT 24
Peak memory 205544 kb
Host smart-887cf8b9-6646-4a4b-8514-6437a01fbcdb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608939566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
3608939566
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.4144593887
Short name T29
Test name
Test status
Simulation time 1055741335 ps
CPU time 4.47 seconds
Started Jul 13 07:00:21 PM PDT 24
Finished Jul 13 07:00:26 PM PDT 24
Peak memory 224448 kb
Host smart-1e2a46c8-194a-4190-8fc4-ddb03b0b86aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144593887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.4144593887
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.398808982
Short name T408
Test name
Test status
Simulation time 17357905 ps
CPU time 0.77 seconds
Started Jul 13 07:00:09 PM PDT 24
Finished Jul 13 07:00:11 PM PDT 24
Peak memory 206920 kb
Host smart-c21f0675-110b-4ebd-bd2b-4cb96b3169a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398808982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.398808982
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.995101437
Short name T826
Test name
Test status
Simulation time 102500245875 ps
CPU time 183.45 seconds
Started Jul 13 07:00:24 PM PDT 24
Finished Jul 13 07:03:29 PM PDT 24
Peak memory 249192 kb
Host smart-cbcc6619-0717-4e4d-89e5-0426a45c96c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995101437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.995101437
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.17200623
Short name T292
Test name
Test status
Simulation time 33911757204 ps
CPU time 96.5 seconds
Started Jul 13 07:00:16 PM PDT 24
Finished Jul 13 07:01:53 PM PDT 24
Peak memory 265012 kb
Host smart-59cdf59f-bb31-4a14-84ae-cd7fcfd89cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17200623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idle.17200623
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.3465595449
Short name T635
Test name
Test status
Simulation time 391326358 ps
CPU time 6.9 seconds
Started Jul 13 07:00:26 PM PDT 24
Finished Jul 13 07:00:34 PM PDT 24
Peak memory 224436 kb
Host smart-8f701c0c-19bb-438d-af84-34b105ca7b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465595449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.3465595449
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.2301216786
Short name T575
Test name
Test status
Simulation time 5654511647 ps
CPU time 45.68 seconds
Started Jul 13 07:00:14 PM PDT 24
Finished Jul 13 07:01:01 PM PDT 24
Peak memory 240512 kb
Host smart-c8318172-4210-48fe-bc20-8bb55cf5b28c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301216786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmd
s.2301216786
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.403737129
Short name T852
Test name
Test status
Simulation time 5832436035 ps
CPU time 15.33 seconds
Started Jul 13 07:00:15 PM PDT 24
Finished Jul 13 07:00:32 PM PDT 24
Peak memory 223860 kb
Host smart-6af8c7c0-8d37-44c9-ad1e-d41e9fa53e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403737129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.403737129
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.4080348829
Short name T45
Test name
Test status
Simulation time 19593390094 ps
CPU time 42.52 seconds
Started Jul 13 07:00:12 PM PDT 24
Finished Jul 13 07:00:56 PM PDT 24
Peak memory 232776 kb
Host smart-d541d973-95eb-4ba1-881f-d3acf7188cfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080348829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.4080348829
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.1117055647
Short name T844
Test name
Test status
Simulation time 191052637 ps
CPU time 3.83 seconds
Started Jul 13 07:00:25 PM PDT 24
Finished Jul 13 07:00:30 PM PDT 24
Peak memory 232644 kb
Host smart-f0829664-5761-4b80-8292-a6b94f406323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117055647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.1117055647
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.2947197337
Short name T515
Test name
Test status
Simulation time 13394884913 ps
CPU time 12.56 seconds
Started Jul 13 07:00:20 PM PDT 24
Finished Jul 13 07:00:33 PM PDT 24
Peak memory 224600 kb
Host smart-a0446a16-09c1-418b-ae6f-480213a5f604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947197337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.2947197337
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.610556925
Short name T776
Test name
Test status
Simulation time 195789167 ps
CPU time 4.05 seconds
Started Jul 13 07:00:19 PM PDT 24
Finished Jul 13 07:00:23 PM PDT 24
Peak memory 223124 kb
Host smart-48000a60-2bd2-48b4-83cf-9c237f73c442
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=610556925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dire
ct.610556925
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.383939858
Short name T91
Test name
Test status
Simulation time 12068297368 ps
CPU time 126.89 seconds
Started Jul 13 07:00:21 PM PDT 24
Finished Jul 13 07:02:29 PM PDT 24
Peak memory 252608 kb
Host smart-6906f0cf-0f1f-4f25-9a41-07c89f476f78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383939858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stres
s_all.383939858
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.3807972458
Short name T848
Test name
Test status
Simulation time 585617229 ps
CPU time 4.29 seconds
Started Jul 13 07:00:07 PM PDT 24
Finished Jul 13 07:00:13 PM PDT 24
Peak memory 216348 kb
Host smart-5a527e75-87ff-43f9-8d7e-3ee45cdc45e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807972458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.3807972458
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.3988122938
Short name T541
Test name
Test status
Simulation time 145442477 ps
CPU time 1.39 seconds
Started Jul 13 07:00:04 PM PDT 24
Finished Jul 13 07:00:07 PM PDT 24
Peak memory 207912 kb
Host smart-f1c48015-4da8-41ec-b524-5dad1374329c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988122938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.3988122938
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.463481530
Short name T368
Test name
Test status
Simulation time 60789691 ps
CPU time 2.48 seconds
Started Jul 13 07:00:14 PM PDT 24
Finished Jul 13 07:00:18 PM PDT 24
Peak memory 216292 kb
Host smart-e33d88c2-c8ab-4e54-9bd5-61b59aee2808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463481530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.463481530
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.3074052544
Short name T749
Test name
Test status
Simulation time 109663747 ps
CPU time 0.87 seconds
Started Jul 13 07:00:07 PM PDT 24
Finished Jul 13 07:00:10 PM PDT 24
Peak memory 205996 kb
Host smart-065bb3e0-64f9-4acf-8f81-919429941f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074052544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.3074052544
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.2238869444
Short name T205
Test name
Test status
Simulation time 16155133184 ps
CPU time 12.41 seconds
Started Jul 13 07:00:17 PM PDT 24
Finished Jul 13 07:00:30 PM PDT 24
Peak memory 232808 kb
Host smart-246f41f9-0149-42ac-9e4e-a736f3c7db94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238869444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.2238869444
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.1073485995
Short name T405
Test name
Test status
Simulation time 39501948 ps
CPU time 0.7 seconds
Started Jul 13 07:00:14 PM PDT 24
Finished Jul 13 07:00:15 PM PDT 24
Peak memory 204908 kb
Host smart-c7b0196f-7bcd-41a2-96c4-4219e568192c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073485995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
1073485995
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.1499945990
Short name T655
Test name
Test status
Simulation time 169767232 ps
CPU time 2.33 seconds
Started Jul 13 07:00:29 PM PDT 24
Finished Jul 13 07:00:33 PM PDT 24
Peak memory 224496 kb
Host smart-ffc93d56-19ca-488e-ae0e-9acb411675a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499945990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.1499945990
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.3755596955
Short name T1002
Test name
Test status
Simulation time 50864300 ps
CPU time 0.8 seconds
Started Jul 13 07:00:22 PM PDT 24
Finished Jul 13 07:00:24 PM PDT 24
Peak memory 205908 kb
Host smart-ba632e2a-466f-4ff8-bee4-635ec9527c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755596955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.3755596955
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.3759191989
Short name T937
Test name
Test status
Simulation time 10798614883 ps
CPU time 145.67 seconds
Started Jul 13 07:00:14 PM PDT 24
Finished Jul 13 07:02:42 PM PDT 24
Peak memory 261992 kb
Host smart-b8fdb354-b2ab-440f-bad9-778a3eab93c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759191989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.3759191989
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.1756621795
Short name T270
Test name
Test status
Simulation time 12005569577 ps
CPU time 102.46 seconds
Started Jul 13 07:00:14 PM PDT 24
Finished Jul 13 07:01:57 PM PDT 24
Peak memory 241088 kb
Host smart-c52116fa-c7a3-4ee5-8d2e-4d84485654d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756621795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.1756621795
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.729326650
Short name T185
Test name
Test status
Simulation time 7826718771 ps
CPU time 57.32 seconds
Started Jul 13 07:00:15 PM PDT 24
Finished Jul 13 07:01:13 PM PDT 24
Peak memory 256496 kb
Host smart-550c2601-4a44-4ec0-88f7-a2fc5d2aca58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729326650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idle
.729326650
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.525873711
Short name T721
Test name
Test status
Simulation time 3771187553 ps
CPU time 42.94 seconds
Started Jul 13 07:00:23 PM PDT 24
Finished Jul 13 07:01:06 PM PDT 24
Peak memory 233840 kb
Host smart-9ad2217e-a3a2-439a-992f-798cd58122c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525873711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.525873711
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.4287433214
Short name T430
Test name
Test status
Simulation time 4309829862 ps
CPU time 44.87 seconds
Started Jul 13 07:00:13 PM PDT 24
Finished Jul 13 07:00:59 PM PDT 24
Peak memory 251616 kb
Host smart-213d9446-ef33-4107-bc2c-fbdee3b0c3a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287433214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmd
s.4287433214
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.828594622
Short name T977
Test name
Test status
Simulation time 1032622809 ps
CPU time 6.21 seconds
Started Jul 13 07:00:14 PM PDT 24
Finished Jul 13 07:00:21 PM PDT 24
Peak memory 224484 kb
Host smart-8d9ff9bf-8c55-44a4-94eb-3cb37415b7ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828594622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.828594622
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.4269843816
Short name T663
Test name
Test status
Simulation time 2368427947 ps
CPU time 13.59 seconds
Started Jul 13 07:00:29 PM PDT 24
Finished Jul 13 07:00:44 PM PDT 24
Peak memory 233776 kb
Host smart-8c289df4-fa3d-4eb1-bd5c-d00d94012bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269843816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.4269843816
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.61929955
Short name T910
Test name
Test status
Simulation time 15776062910 ps
CPU time 22.37 seconds
Started Jul 13 07:00:12 PM PDT 24
Finished Jul 13 07:00:35 PM PDT 24
Peak memory 240740 kb
Host smart-4458ef54-cdba-4923-a1f0-510ff80141e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61929955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swap.61929955
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.601916422
Short name T761
Test name
Test status
Simulation time 424496351 ps
CPU time 3.78 seconds
Started Jul 13 07:00:11 PM PDT 24
Finished Jul 13 07:00:16 PM PDT 24
Peak memory 224412 kb
Host smart-b7179a2b-26b0-413b-b9ec-48cc046d6c2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601916422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.601916422
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.4214823050
Short name T369
Test name
Test status
Simulation time 826755126 ps
CPU time 7.78 seconds
Started Jul 13 07:00:19 PM PDT 24
Finished Jul 13 07:00:27 PM PDT 24
Peak memory 223660 kb
Host smart-54e86e41-e9d2-48a1-9286-02cfd5a07d70
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4214823050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.4214823050
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.3214396509
Short name T724
Test name
Test status
Simulation time 56972414 ps
CPU time 1.13 seconds
Started Jul 13 07:00:20 PM PDT 24
Finished Jul 13 07:00:21 PM PDT 24
Peak memory 207064 kb
Host smart-666027be-dfc1-4d13-84fe-e57b4f185756
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214396509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.3214396509
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.2116347612
Short name T744
Test name
Test status
Simulation time 5702313921 ps
CPU time 16.28 seconds
Started Jul 13 07:00:25 PM PDT 24
Finished Jul 13 07:00:42 PM PDT 24
Peak memory 216324 kb
Host smart-298165e0-cd84-488f-a509-3f9b5f004517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116347612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.2116347612
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.4114839054
Short name T846
Test name
Test status
Simulation time 6670913796 ps
CPU time 20 seconds
Started Jul 13 07:00:13 PM PDT 24
Finished Jul 13 07:00:34 PM PDT 24
Peak memory 216372 kb
Host smart-765bb215-069f-4770-8c10-5c7e6d61a486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114839054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.4114839054
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.3372802720
Short name T572
Test name
Test status
Simulation time 380973888 ps
CPU time 2.12 seconds
Started Jul 13 07:00:17 PM PDT 24
Finished Jul 13 07:00:19 PM PDT 24
Peak memory 216272 kb
Host smart-5bc68b0c-3894-4d66-bc98-b50325359f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372802720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.3372802720
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.3537540936
Short name T840
Test name
Test status
Simulation time 89213575 ps
CPU time 0.81 seconds
Started Jul 13 07:00:12 PM PDT 24
Finished Jul 13 07:00:14 PM PDT 24
Peak memory 206000 kb
Host smart-e6e8240c-8f20-400d-8059-a8759c577c75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537540936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.3537540936
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.521520398
Short name T948
Test name
Test status
Simulation time 570788648 ps
CPU time 3.96 seconds
Started Jul 13 07:00:21 PM PDT 24
Finished Jul 13 07:00:26 PM PDT 24
Peak memory 224504 kb
Host smart-194be961-cb08-4fb0-be59-3fa5e1e2d2d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521520398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.521520398
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.393239073
Short name T581
Test name
Test status
Simulation time 27826900 ps
CPU time 0.74 seconds
Started Jul 13 07:00:21 PM PDT 24
Finished Jul 13 07:00:23 PM PDT 24
Peak memory 205556 kb
Host smart-93bfcb3e-dc75-4c2a-ada2-b5c64d3eec94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393239073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.393239073
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.2250909726
Short name T55
Test name
Test status
Simulation time 6168938847 ps
CPU time 6.98 seconds
Started Jul 13 07:00:21 PM PDT 24
Finished Jul 13 07:00:29 PM PDT 24
Peak memory 232792 kb
Host smart-a00fc7d4-fe4a-4169-bf3e-55bce620908b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250909726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.2250909726
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.2730351955
Short name T615
Test name
Test status
Simulation time 132277234 ps
CPU time 0.78 seconds
Started Jul 13 07:00:17 PM PDT 24
Finished Jul 13 07:00:18 PM PDT 24
Peak memory 206604 kb
Host smart-01821496-99da-4f65-a036-83b469a75bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730351955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.2730351955
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.2464179335
Short name T963
Test name
Test status
Simulation time 2492688456 ps
CPU time 52 seconds
Started Jul 13 07:00:22 PM PDT 24
Finished Jul 13 07:01:15 PM PDT 24
Peak memory 251292 kb
Host smart-a3722e37-f007-4439-8d18-84321b70a9ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464179335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.2464179335
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.3909410443
Short name T552
Test name
Test status
Simulation time 303042247183 ps
CPU time 303.23 seconds
Started Jul 13 07:00:28 PM PDT 24
Finished Jul 13 07:05:32 PM PDT 24
Peak memory 257444 kb
Host smart-2a3bea56-a3b0-4314-b417-ee468b524d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909410443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.3909410443
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.2469107577
Short name T644
Test name
Test status
Simulation time 2747607295 ps
CPU time 21.78 seconds
Started Jul 13 07:00:28 PM PDT 24
Finished Jul 13 07:00:50 PM PDT 24
Peak memory 217696 kb
Host smart-c7c3cde8-2988-4c34-977f-473eaf155947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469107577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.2469107577
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.3980501328
Short name T1007
Test name
Test status
Simulation time 2731791088 ps
CPU time 21.12 seconds
Started Jul 13 07:00:25 PM PDT 24
Finished Jul 13 07:00:47 PM PDT 24
Peak memory 233176 kb
Host smart-2c809592-464c-4d3a-8e95-f23c1bd486b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980501328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.3980501328
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.3840855535
Short name T400
Test name
Test status
Simulation time 32901091794 ps
CPU time 61.54 seconds
Started Jul 13 07:00:28 PM PDT 24
Finished Jul 13 07:01:30 PM PDT 24
Peak memory 249216 kb
Host smart-0f9e4810-0e67-4d6f-9aba-8a161570fa14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840855535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmd
s.3840855535
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.1627727480
Short name T599
Test name
Test status
Simulation time 3513875805 ps
CPU time 8.73 seconds
Started Jul 13 07:00:22 PM PDT 24
Finished Jul 13 07:00:32 PM PDT 24
Peak memory 224572 kb
Host smart-31134096-282d-42eb-ac25-6b911d296fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627727480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.1627727480
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.2330849218
Short name T135
Test name
Test status
Simulation time 18249130602 ps
CPU time 69.77 seconds
Started Jul 13 07:00:21 PM PDT 24
Finished Jul 13 07:01:33 PM PDT 24
Peak memory 232836 kb
Host smart-c692ffb1-8988-428b-9d3d-22ec172a5261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330849218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.2330849218
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.4054071432
Short name T278
Test name
Test status
Simulation time 5485430811 ps
CPU time 9.79 seconds
Started Jul 13 07:00:20 PM PDT 24
Finished Jul 13 07:00:30 PM PDT 24
Peak memory 240704 kb
Host smart-97e7d036-ea68-49a0-a4e0-d5d5676f2b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054071432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.4054071432
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.4292292314
Short name T650
Test name
Test status
Simulation time 7377857184 ps
CPU time 16.99 seconds
Started Jul 13 07:00:25 PM PDT 24
Finished Jul 13 07:00:43 PM PDT 24
Peak memory 232816 kb
Host smart-7faa1dc4-b8b0-4d1f-898f-96867b0c358f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292292314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.4292292314
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.581760540
Short name T488
Test name
Test status
Simulation time 3695553189 ps
CPU time 4.37 seconds
Started Jul 13 07:00:25 PM PDT 24
Finished Jul 13 07:00:30 PM PDT 24
Peak memory 219144 kb
Host smart-6961740c-69ea-440b-b9ed-f68ef8f28e53
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=581760540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dire
ct.581760540
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.202030803
Short name T824
Test name
Test status
Simulation time 12013878311 ps
CPU time 61.52 seconds
Started Jul 13 07:00:21 PM PDT 24
Finished Jul 13 07:01:23 PM PDT 24
Peak memory 252028 kb
Host smart-75cc71b1-11cd-4333-b7df-38a049085386
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202030803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stres
s_all.202030803
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.291941622
Short name T802
Test name
Test status
Simulation time 1183294661 ps
CPU time 6.16 seconds
Started Jul 13 07:00:13 PM PDT 24
Finished Jul 13 07:00:20 PM PDT 24
Peak memory 216264 kb
Host smart-3afd19dd-1c82-4aa7-a07d-205e3f11a33a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291941622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.291941622
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.2129374602
Short name T526
Test name
Test status
Simulation time 13070944 ps
CPU time 0.72 seconds
Started Jul 13 07:00:20 PM PDT 24
Finished Jul 13 07:00:22 PM PDT 24
Peak memory 205720 kb
Host smart-77a31d27-5519-458a-bec9-ddf1e57fcd37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129374602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.2129374602
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.2974243780
Short name T350
Test name
Test status
Simulation time 56975726 ps
CPU time 1.42 seconds
Started Jul 13 07:00:23 PM PDT 24
Finished Jul 13 07:00:25 PM PDT 24
Peak memory 216220 kb
Host smart-5eb3081c-60c7-4e80-a6ce-551c722dfefb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974243780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.2974243780
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.867648198
Short name T534
Test name
Test status
Simulation time 115588188 ps
CPU time 0.81 seconds
Started Jul 13 07:00:22 PM PDT 24
Finished Jul 13 07:00:24 PM PDT 24
Peak memory 205992 kb
Host smart-d37452b7-5589-4e71-b4d9-4597f79d38c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867648198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.867648198
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.1094721685
Short name T628
Test name
Test status
Simulation time 1003852440 ps
CPU time 5.3 seconds
Started Jul 13 07:00:21 PM PDT 24
Finished Jul 13 07:00:28 PM PDT 24
Peak memory 224436 kb
Host smart-985ac552-50b0-48c6-89c0-d1f674861cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094721685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.1094721685
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.791528583
Short name T421
Test name
Test status
Simulation time 23149824 ps
CPU time 0.78 seconds
Started Jul 13 07:00:32 PM PDT 24
Finished Jul 13 07:00:34 PM PDT 24
Peak memory 204988 kb
Host smart-b1c2f734-8daa-4372-9ab4-2d121dd0d477
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791528583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.791528583
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.912415342
Short name T934
Test name
Test status
Simulation time 1060135338 ps
CPU time 5.53 seconds
Started Jul 13 07:00:21 PM PDT 24
Finished Jul 13 07:00:28 PM PDT 24
Peak memory 224512 kb
Host smart-eac0c86e-f0f0-4d5c-bd60-aee75f109bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912415342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.912415342
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.2062808515
Short name T677
Test name
Test status
Simulation time 98907460 ps
CPU time 0.73 seconds
Started Jul 13 07:00:24 PM PDT 24
Finished Jul 13 07:00:26 PM PDT 24
Peak memory 205580 kb
Host smart-c4713397-e69f-4807-a50c-03b5489c1354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062808515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.2062808515
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.3235779091
Short name T864
Test name
Test status
Simulation time 40728864395 ps
CPU time 136.29 seconds
Started Jul 13 07:00:28 PM PDT 24
Finished Jul 13 07:02:45 PM PDT 24
Peak memory 250676 kb
Host smart-4fb93ee8-fc80-402a-a38f-4c3e42d68bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235779091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.3235779091
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.2313782103
Short name T525
Test name
Test status
Simulation time 34997842072 ps
CPU time 83.8 seconds
Started Jul 13 07:00:26 PM PDT 24
Finished Jul 13 07:01:51 PM PDT 24
Peak memory 239232 kb
Host smart-eb5522f0-80b8-4a91-bfc0-314660e521cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313782103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.2313782103
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.2735010526
Short name T53
Test name
Test status
Simulation time 46953093903 ps
CPU time 374.06 seconds
Started Jul 13 07:00:33 PM PDT 24
Finished Jul 13 07:06:49 PM PDT 24
Peak memory 249596 kb
Host smart-c8f5b54f-7728-4ef0-aa7b-49647dd65e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735010526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.2735010526
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.3077165162
Short name T303
Test name
Test status
Simulation time 3946827512 ps
CPU time 12.91 seconds
Started Jul 13 07:00:22 PM PDT 24
Finished Jul 13 07:00:36 PM PDT 24
Peak memory 224620 kb
Host smart-9cef7fb4-166e-4b7e-a0bd-039d4e3bc81e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077165162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.3077165162
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.4186516176
Short name T591
Test name
Test status
Simulation time 1964125908 ps
CPU time 29.91 seconds
Started Jul 13 07:00:23 PM PDT 24
Finished Jul 13 07:00:53 PM PDT 24
Peak memory 249104 kb
Host smart-47310610-eaf4-4465-b588-42c9385cae26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186516176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmd
s.4186516176
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.3760660317
Short name T674
Test name
Test status
Simulation time 219022296 ps
CPU time 3.07 seconds
Started Jul 13 07:00:20 PM PDT 24
Finished Jul 13 07:00:24 PM PDT 24
Peak memory 224420 kb
Host smart-c6dbec0b-15c9-469e-bd96-da86b8aba5db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760660317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.3760660317
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.3323707725
Short name T833
Test name
Test status
Simulation time 363705456 ps
CPU time 6.95 seconds
Started Jul 13 07:00:29 PM PDT 24
Finished Jul 13 07:00:37 PM PDT 24
Peak memory 232620 kb
Host smart-8f39647c-e32b-4d4d-b8ea-df8627766cfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323707725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.3323707725
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.3569466482
Short name T800
Test name
Test status
Simulation time 146230275 ps
CPU time 2.42 seconds
Started Jul 13 07:00:21 PM PDT 24
Finished Jul 13 07:00:25 PM PDT 24
Peak memory 224476 kb
Host smart-005f5eda-bd9f-48c0-8e8c-8a31c6f54c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569466482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.3569466482
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.3952116273
Short name T197
Test name
Test status
Simulation time 7608389024 ps
CPU time 18.96 seconds
Started Jul 13 07:00:26 PM PDT 24
Finished Jul 13 07:00:46 PM PDT 24
Peak memory 224636 kb
Host smart-7024833f-e7d3-4589-8358-8ab48c68e2f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952116273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.3952116273
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.1857801996
Short name T489
Test name
Test status
Simulation time 207366880 ps
CPU time 3.33 seconds
Started Jul 13 07:00:24 PM PDT 24
Finished Jul 13 07:00:28 PM PDT 24
Peak memory 218864 kb
Host smart-09c659b3-94b6-4073-98fd-1f997b87fbb6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1857801996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.1857801996
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.1557735963
Short name T698
Test name
Test status
Simulation time 20653744444 ps
CPU time 118.6 seconds
Started Jul 13 07:00:32 PM PDT 24
Finished Jul 13 07:02:31 PM PDT 24
Peak memory 266512 kb
Host smart-c8ca5262-2179-4c0f-8133-90ca385aeed8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557735963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.1557735963
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.3255237624
Short name T732
Test name
Test status
Simulation time 19931421101 ps
CPU time 46.54 seconds
Started Jul 13 07:00:27 PM PDT 24
Finished Jul 13 07:01:14 PM PDT 24
Peak memory 216368 kb
Host smart-187afa30-1c65-4be0-a69d-6f3b8429f5e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255237624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.3255237624
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.364972519
Short name T903
Test name
Test status
Simulation time 2574169679 ps
CPU time 2.42 seconds
Started Jul 13 07:00:29 PM PDT 24
Finished Jul 13 07:00:33 PM PDT 24
Peak memory 208032 kb
Host smart-88378fbc-eea5-47d3-ab54-d10f119cec0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364972519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.364972519
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.1452903473
Short name T359
Test name
Test status
Simulation time 365536638 ps
CPU time 2.52 seconds
Started Jul 13 07:00:23 PM PDT 24
Finished Jul 13 07:00:26 PM PDT 24
Peak memory 216308 kb
Host smart-e5d67d48-1250-4500-8ca3-4371fde8b7d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452903473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.1452903473
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.1091616368
Short name T518
Test name
Test status
Simulation time 80577878 ps
CPU time 0.96 seconds
Started Jul 13 07:00:22 PM PDT 24
Finished Jul 13 07:00:24 PM PDT 24
Peak memory 207004 kb
Host smart-d006159d-b99a-4ed1-88d2-2c6d5369484f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091616368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.1091616368
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.4140317000
Short name T748
Test name
Test status
Simulation time 457175008 ps
CPU time 2.31 seconds
Started Jul 13 07:00:28 PM PDT 24
Finished Jul 13 07:00:31 PM PDT 24
Peak memory 232328 kb
Host smart-41cf79dc-eff1-45a1-b15d-feff6d2ffe5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140317000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.4140317000
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.505619799
Short name T1004
Test name
Test status
Simulation time 37420181 ps
CPU time 0.73 seconds
Started Jul 13 07:00:41 PM PDT 24
Finished Jul 13 07:00:43 PM PDT 24
Peak memory 205544 kb
Host smart-8d59dfc8-2856-4f19-b22f-920ea18ea141
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505619799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.505619799
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.3650371535
Short name T354
Test name
Test status
Simulation time 3559154121 ps
CPU time 6.46 seconds
Started Jul 13 07:00:35 PM PDT 24
Finished Jul 13 07:00:41 PM PDT 24
Peak memory 224604 kb
Host smart-ca2f2695-63fe-42d7-b241-96fb8ad5caa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650371535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.3650371535
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.4169769078
Short name T783
Test name
Test status
Simulation time 19767074 ps
CPU time 0.8 seconds
Started Jul 13 07:00:30 PM PDT 24
Finished Jul 13 07:00:32 PM PDT 24
Peak memory 206896 kb
Host smart-1d62ef43-20fa-4e3f-85ff-566e72072873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169769078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.4169769078
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.612999362
Short name T468
Test name
Test status
Simulation time 33641885006 ps
CPU time 141.39 seconds
Started Jul 13 07:00:35 PM PDT 24
Finished Jul 13 07:02:57 PM PDT 24
Peak memory 249212 kb
Host smart-e7b4aa5d-ae7f-44cc-8e39-bb0d586cda4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612999362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.612999362
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.3082307413
Short name T271
Test name
Test status
Simulation time 47981699323 ps
CPU time 220.22 seconds
Started Jul 13 07:00:33 PM PDT 24
Finished Jul 13 07:04:15 PM PDT 24
Peak memory 271412 kb
Host smart-a59ccd5e-1820-4036-87c9-da9c46e7dfdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082307413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.3082307413
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.2170831446
Short name T573
Test name
Test status
Simulation time 6916083714 ps
CPU time 100.04 seconds
Started Jul 13 07:00:37 PM PDT 24
Finished Jul 13 07:02:18 PM PDT 24
Peak memory 249708 kb
Host smart-fc05e85c-cfb0-412a-9e36-6d8c3fb0f978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170831446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.2170831446
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.3937931935
Short name T689
Test name
Test status
Simulation time 449815830 ps
CPU time 10.29 seconds
Started Jul 13 07:00:33 PM PDT 24
Finished Jul 13 07:00:44 PM PDT 24
Peak memory 240828 kb
Host smart-3dbf733c-4602-4bc9-9bcb-90b44851fbbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937931935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.3937931935
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.3045862599
Short name T209
Test name
Test status
Simulation time 367032327 ps
CPU time 8.04 seconds
Started Jul 13 07:00:41 PM PDT 24
Finished Jul 13 07:00:50 PM PDT 24
Peak memory 236032 kb
Host smart-94c7ddba-ee52-4e7b-8182-2d555462b79d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045862599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmd
s.3045862599
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.797174183
Short name T366
Test name
Test status
Simulation time 750539774 ps
CPU time 2.94 seconds
Started Jul 13 07:00:38 PM PDT 24
Finished Jul 13 07:00:42 PM PDT 24
Peak memory 224500 kb
Host smart-66469658-3518-4daa-9022-d1b66963ac98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797174183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.797174183
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.4129026586
Short name T550
Test name
Test status
Simulation time 17815773214 ps
CPU time 71.34 seconds
Started Jul 13 07:00:30 PM PDT 24
Finished Jul 13 07:01:42 PM PDT 24
Peak memory 232716 kb
Host smart-e501c4c1-15b1-42fd-aca9-89af3c066c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129026586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.4129026586
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.280603803
Short name T66
Test name
Test status
Simulation time 17415895879 ps
CPU time 16.81 seconds
Started Jul 13 07:00:28 PM PDT 24
Finished Jul 13 07:00:45 PM PDT 24
Peak memory 232724 kb
Host smart-aa5481a1-08c1-4e08-b1b4-da7e82e8a203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280603803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swap
.280603803
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.4258245626
Short name T90
Test name
Test status
Simulation time 10728249991 ps
CPU time 9.42 seconds
Started Jul 13 07:00:36 PM PDT 24
Finished Jul 13 07:00:46 PM PDT 24
Peak memory 224636 kb
Host smart-ca25c70c-61cd-4284-9e7d-035cbf93b70a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258245626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.4258245626
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.1348134235
Short name T620
Test name
Test status
Simulation time 191167321 ps
CPU time 4.41 seconds
Started Jul 13 07:00:33 PM PDT 24
Finished Jul 13 07:00:38 PM PDT 24
Peak memory 220452 kb
Host smart-1cf92567-0a58-4aad-9896-787ba6849e5c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1348134235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.1348134235
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.2389663940
Short name T881
Test name
Test status
Simulation time 2804604786 ps
CPU time 58.25 seconds
Started Jul 13 07:00:31 PM PDT 24
Finished Jul 13 07:01:30 PM PDT 24
Peak memory 249444 kb
Host smart-0543a244-2b70-4374-aeb5-05c4f8dc998e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389663940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.2389663940
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.4051684640
Short name T988
Test name
Test status
Simulation time 42310131 ps
CPU time 0.74 seconds
Started Jul 13 07:00:29 PM PDT 24
Finished Jul 13 07:00:30 PM PDT 24
Peak memory 205716 kb
Host smart-a75576ab-9887-4c65-901a-83004e9c6018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051684640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.4051684640
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.3471999821
Short name T308
Test name
Test status
Simulation time 10319197730 ps
CPU time 15.95 seconds
Started Jul 13 07:00:33 PM PDT 24
Finished Jul 13 07:00:50 PM PDT 24
Peak memory 216344 kb
Host smart-74f40c9d-c6eb-4d11-9c8d-55decf144797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471999821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.3471999821
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.4241982504
Short name T752
Test name
Test status
Simulation time 199158471 ps
CPU time 1.67 seconds
Started Jul 13 07:00:31 PM PDT 24
Finished Jul 13 07:00:33 PM PDT 24
Peak memory 216196 kb
Host smart-999b1072-7723-4ed1-9988-470dba358cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241982504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.4241982504
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.3353798996
Short name T332
Test name
Test status
Simulation time 65161037 ps
CPU time 0.76 seconds
Started Jul 13 07:00:32 PM PDT 24
Finished Jul 13 07:00:34 PM PDT 24
Peak memory 206004 kb
Host smart-38de191e-13c2-4d6d-ada9-917770cbc096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353798996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.3353798996
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.547247154
Short name T781
Test name
Test status
Simulation time 166671910 ps
CPU time 3.22 seconds
Started Jul 13 07:00:30 PM PDT 24
Finished Jul 13 07:00:34 PM PDT 24
Peak memory 224472 kb
Host smart-9dbeb25d-76a2-4768-9c9f-c240ed9251b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547247154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.547247154
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.3313366832
Short name T935
Test name
Test status
Simulation time 12950031 ps
CPU time 0.79 seconds
Started Jul 13 07:00:32 PM PDT 24
Finished Jul 13 07:00:34 PM PDT 24
Peak memory 205528 kb
Host smart-1f9d47ad-3e1d-4676-8044-7dd744bf3a9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313366832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
3313366832
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.1481928209
Short name T725
Test name
Test status
Simulation time 3234840107 ps
CPU time 4.58 seconds
Started Jul 13 07:00:35 PM PDT 24
Finished Jul 13 07:00:40 PM PDT 24
Peak memory 232792 kb
Host smart-ae6d19e9-759b-404e-8923-c843fd9cc26d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481928209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.1481928209
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.864385010
Short name T855
Test name
Test status
Simulation time 74156790 ps
CPU time 0.83 seconds
Started Jul 13 07:00:30 PM PDT 24
Finished Jul 13 07:00:32 PM PDT 24
Peak memory 206964 kb
Host smart-73a9ede7-20de-40c7-bbc0-4de26320843b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864385010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.864385010
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.733012546
Short name T1005
Test name
Test status
Simulation time 14405552 ps
CPU time 0.77 seconds
Started Jul 13 07:00:36 PM PDT 24
Finished Jul 13 07:00:37 PM PDT 24
Peak memory 215804 kb
Host smart-7e013d0b-497d-4b29-9632-01799c0d6214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733012546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.733012546
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.3217807392
Short name T931
Test name
Test status
Simulation time 23177883241 ps
CPU time 64.11 seconds
Started Jul 13 07:00:37 PM PDT 24
Finished Jul 13 07:01:41 PM PDT 24
Peak memory 252640 kb
Host smart-805cb963-e5fe-4fc7-a85d-07d98776d6f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217807392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.3217807392
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.4132496372
Short name T659
Test name
Test status
Simulation time 169368204450 ps
CPU time 354.19 seconds
Started Jul 13 07:00:39 PM PDT 24
Finished Jul 13 07:06:35 PM PDT 24
Peak memory 249440 kb
Host smart-e53c9946-0c2d-48ae-a90b-474617da2524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132496372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.4132496372
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.1386907272
Short name T731
Test name
Test status
Simulation time 1122989315 ps
CPU time 15.7 seconds
Started Jul 13 07:00:33 PM PDT 24
Finished Jul 13 07:00:50 PM PDT 24
Peak memory 224484 kb
Host smart-35061a5c-5593-47e0-bc93-622c87f5e1cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386907272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.1386907272
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.1507224383
Short name T999
Test name
Test status
Simulation time 479797715442 ps
CPU time 213.96 seconds
Started Jul 13 07:00:32 PM PDT 24
Finished Jul 13 07:04:07 PM PDT 24
Peak memory 249196 kb
Host smart-1bffbcb9-a619-44c3-bc01-a45d60954cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507224383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmd
s.1507224383
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.2565861039
Short name T204
Test name
Test status
Simulation time 68000768 ps
CPU time 3.39 seconds
Started Jul 13 07:00:31 PM PDT 24
Finished Jul 13 07:00:36 PM PDT 24
Peak memory 232716 kb
Host smart-c08523e6-cc51-4a60-980a-004d578222fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565861039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.2565861039
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.564001712
Short name T249
Test name
Test status
Simulation time 19304795939 ps
CPU time 76.21 seconds
Started Jul 13 07:00:38 PM PDT 24
Finished Jul 13 07:01:54 PM PDT 24
Peak memory 253044 kb
Host smart-506008f3-a027-4548-99fb-2ccc13230891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564001712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.564001712
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.2743615478
Short name T27
Test name
Test status
Simulation time 1749056372 ps
CPU time 9.69 seconds
Started Jul 13 07:00:30 PM PDT 24
Finished Jul 13 07:00:40 PM PDT 24
Peak memory 237080 kb
Host smart-7381dc22-a46a-4ea1-801d-29901163a7e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743615478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.2743615478
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.3194161324
Short name T370
Test name
Test status
Simulation time 286888382 ps
CPU time 2.27 seconds
Started Jul 13 07:00:30 PM PDT 24
Finished Jul 13 07:00:33 PM PDT 24
Peak memory 223768 kb
Host smart-95bc1bb2-fc21-4f1b-95b5-06aa8c5ee501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194161324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.3194161324
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.3199106268
Short name T580
Test name
Test status
Simulation time 7526221686 ps
CPU time 16.26 seconds
Started Jul 13 07:00:29 PM PDT 24
Finished Jul 13 07:00:46 PM PDT 24
Peak memory 219900 kb
Host smart-04d66d7e-b914-4869-a403-6593cbd6c23a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3199106268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.3199106268
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.3402558650
Short name T16
Test name
Test status
Simulation time 24991633456 ps
CPU time 196.23 seconds
Started Jul 13 07:00:30 PM PDT 24
Finished Jul 13 07:03:47 PM PDT 24
Peak memory 241272 kb
Host smart-d6504621-e7ba-4f71-acad-e696b77e939d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402558650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.3402558650
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.85618503
Short name T309
Test name
Test status
Simulation time 6215070806 ps
CPU time 22.73 seconds
Started Jul 13 07:00:39 PM PDT 24
Finished Jul 13 07:01:03 PM PDT 24
Peak memory 216584 kb
Host smart-2f4f694e-5486-4445-b199-8275e12732b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85618503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.85618503
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.2336227050
Short name T325
Test name
Test status
Simulation time 16288305 ps
CPU time 0.75 seconds
Started Jul 13 07:00:39 PM PDT 24
Finished Jul 13 07:00:41 PM PDT 24
Peak memory 205708 kb
Host smart-aeab2080-7d9c-4a62-b4e1-d80e22c7d04c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336227050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.2336227050
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.3458365930
Short name T743
Test name
Test status
Simulation time 133455688 ps
CPU time 1.33 seconds
Started Jul 13 07:00:34 PM PDT 24
Finished Jul 13 07:00:36 PM PDT 24
Peak memory 216224 kb
Host smart-a75929d3-b6f1-4c16-abf4-4a2398195117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458365930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.3458365930
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.3434740931
Short name T86
Test name
Test status
Simulation time 63845144 ps
CPU time 0.74 seconds
Started Jul 13 07:00:32 PM PDT 24
Finished Jul 13 07:00:34 PM PDT 24
Peak memory 206000 kb
Host smart-b135b13a-4134-481f-8f38-60fde53d31eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434740931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.3434740931
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.4157671510
Short name T830
Test name
Test status
Simulation time 3100122966 ps
CPU time 3.59 seconds
Started Jul 13 07:00:33 PM PDT 24
Finished Jul 13 07:00:37 PM PDT 24
Peak memory 224616 kb
Host smart-1e847b15-c953-4168-b07a-54d1470b3a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157671510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.4157671510
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.3673358296
Short name T450
Test name
Test status
Simulation time 12201232 ps
CPU time 0.73 seconds
Started Jul 13 07:02:46 PM PDT 24
Finished Jul 13 07:02:48 PM PDT 24
Peak memory 205676 kb
Host smart-88c4ccec-250b-42dc-b11e-88f1f26766fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673358296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.3
673358296
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.1319579557
Short name T979
Test name
Test status
Simulation time 424876581 ps
CPU time 5.67 seconds
Started Jul 13 06:59:12 PM PDT 24
Finished Jul 13 06:59:20 PM PDT 24
Peak memory 224448 kb
Host smart-a1dac8b5-9d5a-46ff-ac05-a3c38f6eb063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319579557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.1319579557
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.3943842794
Short name T703
Test name
Test status
Simulation time 13576112 ps
CPU time 0.79 seconds
Started Jul 13 06:59:12 PM PDT 24
Finished Jul 13 06:59:15 PM PDT 24
Peak memory 205596 kb
Host smart-d3333207-521c-4802-a7b2-ed7211fb5619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943842794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.3943842794
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.695055459
Short name T458
Test name
Test status
Simulation time 12664300088 ps
CPU time 36.08 seconds
Started Jul 13 06:59:11 PM PDT 24
Finished Jul 13 06:59:49 PM PDT 24
Peak memory 232872 kb
Host smart-d4152ff0-0b0a-432c-a0a4-c81a943e582f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695055459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle.
695055459
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.38473617
Short name T616
Test name
Test status
Simulation time 3874944000 ps
CPU time 19.62 seconds
Started Jul 13 06:59:13 PM PDT 24
Finished Jul 13 06:59:35 PM PDT 24
Peak memory 232760 kb
Host smart-742d17bf-daa2-449f-a9ff-8a5c26f50dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38473617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.38473617
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.2022160851
Short name T933
Test name
Test status
Simulation time 52471886112 ps
CPU time 101.27 seconds
Started Jul 13 06:59:12 PM PDT 24
Finished Jul 13 07:00:56 PM PDT 24
Peak memory 241032 kb
Host smart-2c3a9494-17bc-4a76-9545-809f7001d8ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022160851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds
.2022160851
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.2701083159
Short name T432
Test name
Test status
Simulation time 363645475 ps
CPU time 2.92 seconds
Started Jul 13 06:59:09 PM PDT 24
Finished Jul 13 06:59:13 PM PDT 24
Peak memory 224448 kb
Host smart-bed961f1-e196-423f-a50e-ec6ba093bc0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701083159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.2701083159
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.3825157160
Short name T365
Test name
Test status
Simulation time 31741870 ps
CPU time 2.52 seconds
Started Jul 13 06:59:10 PM PDT 24
Finished Jul 13 06:59:14 PM PDT 24
Peak memory 232340 kb
Host smart-861f4d31-aad6-44b1-ba8c-6adb70652a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825157160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.3825157160
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.779038101
Short name T665
Test name
Test status
Simulation time 24415553063 ps
CPU time 18.54 seconds
Started Jul 13 06:59:12 PM PDT 24
Finished Jul 13 06:59:33 PM PDT 24
Peak memory 224616 kb
Host smart-d0874fc5-36d0-43f6-95e4-4c79d8b186a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779038101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap.
779038101
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.777266890
Short name T221
Test name
Test status
Simulation time 246910435 ps
CPU time 2.69 seconds
Started Jul 13 06:59:10 PM PDT 24
Finished Jul 13 06:59:14 PM PDT 24
Peak memory 224388 kb
Host smart-80313d5d-f162-46c8-92f0-795a00590f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777266890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.777266890
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.4268607372
Short name T374
Test name
Test status
Simulation time 241253913 ps
CPU time 3.58 seconds
Started Jul 13 06:59:16 PM PDT 24
Finished Jul 13 06:59:20 PM PDT 24
Peak memory 220148 kb
Host smart-32600e93-d83e-4a77-a517-b487a8d60903
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4268607372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.4268607372
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.605721015
Short name T82
Test name
Test status
Simulation time 36615436 ps
CPU time 0.95 seconds
Started Jul 13 06:59:13 PM PDT 24
Finished Jul 13 06:59:16 PM PDT 24
Peak memory 236444 kb
Host smart-1ec07462-e113-4f6c-bd4a-2a1489dd2a1b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605721015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.605721015
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.167732931
Short name T722
Test name
Test status
Simulation time 1012805474 ps
CPU time 8.07 seconds
Started Jul 13 06:59:12 PM PDT 24
Finished Jul 13 06:59:23 PM PDT 24
Peak memory 219384 kb
Host smart-acaffd8f-f8b4-41f3-b6bd-c94f8ef5566b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167732931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.167732931
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.971076819
Short name T352
Test name
Test status
Simulation time 12586014676 ps
CPU time 22.77 seconds
Started Jul 13 06:59:08 PM PDT 24
Finished Jul 13 06:59:31 PM PDT 24
Peak memory 216332 kb
Host smart-a62893f0-6bc8-4b30-aac8-0241b44bdf58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971076819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.971076819
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.3003605055
Short name T657
Test name
Test status
Simulation time 80413700 ps
CPU time 1.52 seconds
Started Jul 13 06:59:19 PM PDT 24
Finished Jul 13 06:59:21 PM PDT 24
Peak memory 216284 kb
Host smart-8c80069c-b9ea-4be4-9b81-160d985de9cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003605055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.3003605055
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.406363944
Short name T324
Test name
Test status
Simulation time 13429001 ps
CPU time 0.7 seconds
Started Jul 13 06:59:10 PM PDT 24
Finished Jul 13 06:59:12 PM PDT 24
Peak memory 205668 kb
Host smart-9fc18d0c-9357-4554-9224-6988a1553434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406363944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.406363944
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.2025975200
Short name T448
Test name
Test status
Simulation time 954599752 ps
CPU time 3.29 seconds
Started Jul 13 06:59:13 PM PDT 24
Finished Jul 13 06:59:18 PM PDT 24
Peak memory 232712 kb
Host smart-dacef661-adc3-4b72-97c6-a668adb30468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025975200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.2025975200
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.1901551727
Short name T478
Test name
Test status
Simulation time 37537228 ps
CPU time 0.72 seconds
Started Jul 13 07:00:43 PM PDT 24
Finished Jul 13 07:00:45 PM PDT 24
Peak memory 204996 kb
Host smart-ee04cc12-e67f-4ef2-b453-8f3d8f207af4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901551727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
1901551727
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.3303565999
Short name T529
Test name
Test status
Simulation time 576897759 ps
CPU time 4.74 seconds
Started Jul 13 07:00:35 PM PDT 24
Finished Jul 13 07:00:40 PM PDT 24
Peak memory 232632 kb
Host smart-e383253b-62cf-4a46-b981-4909f11439c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303565999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.3303565999
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.2679659653
Short name T858
Test name
Test status
Simulation time 46014431 ps
CPU time 0.76 seconds
Started Jul 13 07:00:30 PM PDT 24
Finished Jul 13 07:00:32 PM PDT 24
Peak memory 206612 kb
Host smart-4248ffe0-4d48-4dd4-8824-e2232e62eb16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679659653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.2679659653
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.3666139760
Short name T642
Test name
Test status
Simulation time 12826105131 ps
CPU time 97.53 seconds
Started Jul 13 07:00:38 PM PDT 24
Finished Jul 13 07:02:16 PM PDT 24
Peak memory 249220 kb
Host smart-77f989a3-51bd-4e2b-9dc5-93b1cb1693b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666139760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.3666139760
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.211616922
Short name T417
Test name
Test status
Simulation time 39512044693 ps
CPU time 147.12 seconds
Started Jul 13 07:00:43 PM PDT 24
Finished Jul 13 07:03:12 PM PDT 24
Peak memory 252504 kb
Host smart-9e508c5b-a194-454d-addb-7e1fc478b563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211616922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.211616922
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.3935876495
Short name T426
Test name
Test status
Simulation time 12937062083 ps
CPU time 136.77 seconds
Started Jul 13 07:00:39 PM PDT 24
Finished Jul 13 07:02:56 PM PDT 24
Peak memory 250596 kb
Host smart-6ec71688-ccb6-49ac-8e2d-dfb8ccbe92ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935876495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.3935876495
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.1158541903
Short name T386
Test name
Test status
Simulation time 2944717725 ps
CPU time 20.8 seconds
Started Jul 13 07:00:33 PM PDT 24
Finished Jul 13 07:00:55 PM PDT 24
Peak memory 241016 kb
Host smart-30acf00f-57be-4cc2-b467-11e82482adf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158541903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmd
s.1158541903
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.4270353464
Short name T646
Test name
Test status
Simulation time 452353834 ps
CPU time 6.6 seconds
Started Jul 13 07:00:39 PM PDT 24
Finished Jul 13 07:00:47 PM PDT 24
Peak memory 232628 kb
Host smart-22ccd0d0-e1ea-43bf-893b-56723df56914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270353464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.4270353464
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.392091546
Short name T885
Test name
Test status
Simulation time 4534552220 ps
CPU time 27.27 seconds
Started Jul 13 07:00:32 PM PDT 24
Finished Jul 13 07:01:01 PM PDT 24
Peak memory 240800 kb
Host smart-319f8200-d69f-4d2f-a72c-856c2895b6de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392091546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.392091546
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.2677365174
Short name T215
Test name
Test status
Simulation time 27383831979 ps
CPU time 36.04 seconds
Started Jul 13 07:00:31 PM PDT 24
Finished Jul 13 07:01:09 PM PDT 24
Peak memory 232784 kb
Host smart-db8629c4-19ed-4048-b18b-1f2ac1f3cc63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677365174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.2677365174
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.2214792828
Short name T786
Test name
Test status
Simulation time 741555647 ps
CPU time 5.34 seconds
Started Jul 13 07:00:35 PM PDT 24
Finished Jul 13 07:00:41 PM PDT 24
Peak memory 232684 kb
Host smart-4c4f7124-de5e-4b5f-af50-5a9872716263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214792828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.2214792828
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.1774358715
Short name T333
Test name
Test status
Simulation time 728844450 ps
CPU time 5.24 seconds
Started Jul 13 07:00:29 PM PDT 24
Finished Jul 13 07:00:36 PM PDT 24
Peak memory 220432 kb
Host smart-ef2831ca-a757-4f33-8bdf-d52c42c570d6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1774358715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.1774358715
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.1831756846
Short name T63
Test name
Test status
Simulation time 83284579001 ps
CPU time 752.07 seconds
Started Jul 13 07:00:40 PM PDT 24
Finished Jul 13 07:13:15 PM PDT 24
Peak memory 269480 kb
Host smart-96c79f6d-9139-4621-a9bb-56a6226468a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831756846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.1831756846
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.1827967460
Short name T316
Test name
Test status
Simulation time 6237497465 ps
CPU time 18.4 seconds
Started Jul 13 07:00:33 PM PDT 24
Finished Jul 13 07:00:53 PM PDT 24
Peak memory 216460 kb
Host smart-ae253411-e22a-4fe0-97aa-d4d0865674c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827967460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.1827967460
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.3613792626
Short name T841
Test name
Test status
Simulation time 1414805474 ps
CPU time 2.27 seconds
Started Jul 13 07:00:31 PM PDT 24
Finished Jul 13 07:00:35 PM PDT 24
Peak memory 207068 kb
Host smart-17feac83-5812-4354-93dc-9471a480c1cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613792626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.3613792626
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.3447128183
Short name T853
Test name
Test status
Simulation time 30143349 ps
CPU time 0.99 seconds
Started Jul 13 07:00:30 PM PDT 24
Finished Jul 13 07:00:32 PM PDT 24
Peak memory 207136 kb
Host smart-55966cd5-5043-4cba-bee4-e4a044310024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447128183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.3447128183
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.3739732157
Short name T363
Test name
Test status
Simulation time 109323463 ps
CPU time 0.97 seconds
Started Jul 13 07:00:32 PM PDT 24
Finished Jul 13 07:00:34 PM PDT 24
Peak memory 206412 kb
Host smart-7d918fce-d727-4b70-a877-d36d6c0d81fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739732157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.3739732157
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.2404570841
Short name T211
Test name
Test status
Simulation time 1905008081 ps
CPU time 6.25 seconds
Started Jul 13 07:00:32 PM PDT 24
Finished Jul 13 07:00:40 PM PDT 24
Peak memory 232700 kb
Host smart-ff62d863-9fc8-4d94-8cc1-88ec91bbe80b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404570841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.2404570841
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.711066683
Short name T559
Test name
Test status
Simulation time 32108904 ps
CPU time 0.72 seconds
Started Jul 13 07:00:41 PM PDT 24
Finished Jul 13 07:00:43 PM PDT 24
Peak memory 205540 kb
Host smart-90d246eb-fc7d-4ec9-9aef-71aa7175e890
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711066683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.711066683
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.2342448563
Short name T373
Test name
Test status
Simulation time 107646047 ps
CPU time 2.08 seconds
Started Jul 13 07:00:42 PM PDT 24
Finished Jul 13 07:00:46 PM PDT 24
Peak memory 224116 kb
Host smart-2295034f-18fd-4df3-a767-963a2314ba9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342448563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.2342448563
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.1689919473
Short name T507
Test name
Test status
Simulation time 54956045 ps
CPU time 0.8 seconds
Started Jul 13 07:00:51 PM PDT 24
Finished Jul 13 07:00:56 PM PDT 24
Peak memory 205984 kb
Host smart-26f7ed66-d433-4789-9e53-85e269040776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689919473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.1689919473
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.685639117
Short name T274
Test name
Test status
Simulation time 148337805030 ps
CPU time 189.43 seconds
Started Jul 13 07:00:39 PM PDT 24
Finished Jul 13 07:03:50 PM PDT 24
Peak memory 257088 kb
Host smart-025e0593-d89c-4632-90e9-e89630c3cc76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685639117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.685639117
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.366294097
Short name T898
Test name
Test status
Simulation time 4686238419 ps
CPU time 77.67 seconds
Started Jul 13 07:00:40 PM PDT 24
Finished Jul 13 07:02:00 PM PDT 24
Peak memory 249360 kb
Host smart-f8e5e5b6-bfa5-4cb9-96be-9af9de89cb3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366294097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.366294097
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.2558793085
Short name T242
Test name
Test status
Simulation time 3847939281 ps
CPU time 69.01 seconds
Started Jul 13 07:00:39 PM PDT 24
Finished Jul 13 07:01:49 PM PDT 24
Peak memory 257432 kb
Host smart-bb19cb2f-8605-43d6-8ab7-439c35d239b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558793085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.2558793085
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.1011659364
Short name T306
Test name
Test status
Simulation time 257539896 ps
CPU time 4 seconds
Started Jul 13 07:00:39 PM PDT 24
Finished Jul 13 07:00:45 PM PDT 24
Peak memory 232648 kb
Host smart-05f15ec2-4c21-4ad7-b609-ff13705e112c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011659364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.1011659364
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.1363853323
Short name T277
Test name
Test status
Simulation time 3695787366 ps
CPU time 66.73 seconds
Started Jul 13 07:00:40 PM PDT 24
Finished Jul 13 07:01:49 PM PDT 24
Peak memory 251000 kb
Host smart-d59c84e6-b513-46fa-8dd5-55a9583ed856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363853323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmd
s.1363853323
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.1245710442
Short name T818
Test name
Test status
Simulation time 1336213775 ps
CPU time 12.46 seconds
Started Jul 13 07:00:43 PM PDT 24
Finished Jul 13 07:00:56 PM PDT 24
Peak memory 232676 kb
Host smart-2c9a650c-bfce-43a9-88a6-1eacd4c4cb54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245710442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.1245710442
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.2821921100
Short name T237
Test name
Test status
Simulation time 1986174123 ps
CPU time 28.21 seconds
Started Jul 13 07:00:40 PM PDT 24
Finished Jul 13 07:01:11 PM PDT 24
Peak memory 232644 kb
Host smart-c75adafc-6d6d-45dc-acb5-3106b4d04ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821921100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.2821921100
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.1386963401
Short name T261
Test name
Test status
Simulation time 3746378653 ps
CPU time 16.15 seconds
Started Jul 13 07:00:43 PM PDT 24
Finished Jul 13 07:01:01 PM PDT 24
Peak memory 232720 kb
Host smart-48de3bfe-8cbe-4a48-8d9b-77695da5dd74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386963401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.1386963401
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.1273123587
Short name T223
Test name
Test status
Simulation time 38298440434 ps
CPU time 27.6 seconds
Started Jul 13 07:00:40 PM PDT 24
Finished Jul 13 07:01:10 PM PDT 24
Peak memory 232840 kb
Host smart-713132b4-c645-4b25-b106-abd3ce62c465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273123587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.1273123587
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.3895128028
Short name T149
Test name
Test status
Simulation time 1409311187 ps
CPU time 6.62 seconds
Started Jul 13 07:00:41 PM PDT 24
Finished Jul 13 07:00:49 PM PDT 24
Peak memory 223028 kb
Host smart-8e381335-298d-4eb0-aea7-c7332fed29f1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3895128028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.3895128028
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.4241861480
Short name T165
Test name
Test status
Simulation time 125242429764 ps
CPU time 327.8 seconds
Started Jul 13 07:00:40 PM PDT 24
Finished Jul 13 07:06:10 PM PDT 24
Peak memory 249492 kb
Host smart-f62f6c48-5dee-4687-8abe-4bbb5a53fd5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241861480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.4241861480
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.2717174576
Short name T900
Test name
Test status
Simulation time 178481277 ps
CPU time 0.71 seconds
Started Jul 13 07:00:43 PM PDT 24
Finished Jul 13 07:00:45 PM PDT 24
Peak memory 205720 kb
Host smart-c6622512-5926-472c-bd1f-06eda45361f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717174576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.2717174576
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.2527887203
Short name T140
Test name
Test status
Simulation time 11080563234 ps
CPU time 11.84 seconds
Started Jul 13 07:00:42 PM PDT 24
Finished Jul 13 07:00:56 PM PDT 24
Peak memory 216312 kb
Host smart-41355065-3447-41d2-a26c-88bc9bdb271c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527887203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.2527887203
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.803649611
Short name T790
Test name
Test status
Simulation time 53282737 ps
CPU time 1.68 seconds
Started Jul 13 07:00:43 PM PDT 24
Finished Jul 13 07:00:46 PM PDT 24
Peak memory 216196 kb
Host smart-ec7900b9-f031-4e89-84c0-72fc10b6dd34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803649611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.803649611
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.466912754
Short name T980
Test name
Test status
Simulation time 23564791 ps
CPU time 0.74 seconds
Started Jul 13 07:00:39 PM PDT 24
Finished Jul 13 07:00:41 PM PDT 24
Peak memory 205996 kb
Host smart-83edf3d3-24fc-4ccf-8e54-04ce3c7e0020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466912754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.466912754
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.3275208937
Short name T694
Test name
Test status
Simulation time 7130799876 ps
CPU time 8.21 seconds
Started Jul 13 07:00:43 PM PDT 24
Finished Jul 13 07:00:52 PM PDT 24
Peak memory 241040 kb
Host smart-ad74d434-6b39-4742-87d6-9b4acde20f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275208937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.3275208937
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.2711296763
Short name T715
Test name
Test status
Simulation time 33842718 ps
CPU time 0.74 seconds
Started Jul 13 07:00:41 PM PDT 24
Finished Jul 13 07:00:43 PM PDT 24
Peak memory 205560 kb
Host smart-0441207c-9c72-4614-9a11-6d4e14df9768
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711296763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
2711296763
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.1750714460
Short name T101
Test name
Test status
Simulation time 7097892323 ps
CPU time 13.71 seconds
Started Jul 13 07:00:39 PM PDT 24
Finished Jul 13 07:00:55 PM PDT 24
Peak memory 232724 kb
Host smart-330355c1-b652-4abf-9570-b781d354ceda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750714460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.1750714460
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.3776600274
Short name T447
Test name
Test status
Simulation time 35446962 ps
CPU time 0.83 seconds
Started Jul 13 07:00:40 PM PDT 24
Finished Jul 13 07:00:43 PM PDT 24
Peak memory 206616 kb
Host smart-04cf2474-8830-40be-b25a-366c28d6cf7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776600274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.3776600274
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.1272944719
Short name T939
Test name
Test status
Simulation time 11691671518 ps
CPU time 78.39 seconds
Started Jul 13 07:00:39 PM PDT 24
Finished Jul 13 07:01:58 PM PDT 24
Peak memory 239152 kb
Host smart-2f80426b-55b0-467d-b727-7a5ba8b70798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272944719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.1272944719
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.472910931
Short name T422
Test name
Test status
Simulation time 39562768129 ps
CPU time 111.8 seconds
Started Jul 13 07:00:52 PM PDT 24
Finished Jul 13 07:02:49 PM PDT 24
Peak memory 256656 kb
Host smart-24bcb192-4cfe-42c0-ad56-b03b8863be28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472910931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.472910931
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.4157381592
Short name T510
Test name
Test status
Simulation time 16718624136 ps
CPU time 15.98 seconds
Started Jul 13 07:00:39 PM PDT 24
Finished Jul 13 07:00:57 PM PDT 24
Peak memory 217792 kb
Host smart-e26ec83d-3a20-44aa-85a3-6f0388c63f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157381592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.4157381592
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.8372298
Short name T65
Test name
Test status
Simulation time 3243294957 ps
CPU time 4.73 seconds
Started Jul 13 07:00:40 PM PDT 24
Finished Jul 13 07:00:47 PM PDT 24
Peak memory 235008 kb
Host smart-0ec8d26c-d994-475b-a977-4272bd3f2d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8372298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.8372298
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.2328909419
Short name T873
Test name
Test status
Simulation time 6295543609 ps
CPU time 44.37 seconds
Started Jul 13 07:00:40 PM PDT 24
Finished Jul 13 07:01:26 PM PDT 24
Peak memory 257012 kb
Host smart-9aee451d-d1c0-4fea-84f4-ef49228aac52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328909419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmd
s.2328909419
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.1125314857
Short name T227
Test name
Test status
Simulation time 2514185734 ps
CPU time 12.73 seconds
Started Jul 13 07:00:40 PM PDT 24
Finished Jul 13 07:00:55 PM PDT 24
Peak memory 224556 kb
Host smart-b576b263-f6be-4405-b44d-254fb07ba222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125314857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.1125314857
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.2417886650
Short name T791
Test name
Test status
Simulation time 1318580394 ps
CPU time 10.13 seconds
Started Jul 13 07:00:40 PM PDT 24
Finished Jul 13 07:00:53 PM PDT 24
Peak memory 232804 kb
Host smart-632d10bf-63b8-48ac-ade4-5c42e170623a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417886650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.2417886650
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.548739610
Short name T266
Test name
Test status
Simulation time 573708990 ps
CPU time 3.97 seconds
Started Jul 13 07:00:40 PM PDT 24
Finished Jul 13 07:00:46 PM PDT 24
Peak memory 224500 kb
Host smart-92ddd7f5-62f7-41ec-8d77-c7073630db39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548739610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swap
.548739610
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.152885968
Short name T12
Test name
Test status
Simulation time 984740514 ps
CPU time 4.33 seconds
Started Jul 13 07:00:51 PM PDT 24
Finished Jul 13 07:00:59 PM PDT 24
Peak memory 232624 kb
Host smart-054e39f5-5387-4f3b-9a26-b3ff61948155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152885968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.152885968
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.385547735
Short name T1008
Test name
Test status
Simulation time 665087242 ps
CPU time 7.23 seconds
Started Jul 13 07:00:40 PM PDT 24
Finished Jul 13 07:00:49 PM PDT 24
Peak memory 223128 kb
Host smart-ea20cbec-99a3-42d6-b098-7ea60547edfe
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=385547735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dire
ct.385547735
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.1416206878
Short name T423
Test name
Test status
Simulation time 412329321 ps
CPU time 0.9 seconds
Started Jul 13 07:00:39 PM PDT 24
Finished Jul 13 07:00:42 PM PDT 24
Peak memory 206796 kb
Host smart-7b5c9583-c35b-46b4-871f-e206e37156be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416206878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.1416206878
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.2361603294
Short name T975
Test name
Test status
Simulation time 5915692148 ps
CPU time 34.73 seconds
Started Jul 13 07:00:40 PM PDT 24
Finished Jul 13 07:01:17 PM PDT 24
Peak memory 216332 kb
Host smart-5cc095b3-32a1-42cd-91cd-bb52d973f069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361603294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.2361603294
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.3885156650
Short name T338
Test name
Test status
Simulation time 1052385366 ps
CPU time 3.07 seconds
Started Jul 13 07:00:43 PM PDT 24
Finished Jul 13 07:00:47 PM PDT 24
Peak memory 216248 kb
Host smart-0eb43e37-6d34-4d30-9166-f8f119efa8b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885156650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.3885156650
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.680408203
Short name T970
Test name
Test status
Simulation time 317009626 ps
CPU time 2.77 seconds
Started Jul 13 07:00:43 PM PDT 24
Finished Jul 13 07:00:47 PM PDT 24
Peak memory 216220 kb
Host smart-8ef86775-e3bd-496a-b664-a2cd156d3f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680408203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.680408203
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.3485921565
Short name T344
Test name
Test status
Simulation time 276748744 ps
CPU time 0.83 seconds
Started Jul 13 07:00:51 PM PDT 24
Finished Jul 13 07:00:55 PM PDT 24
Peak memory 205980 kb
Host smart-a4ddfd02-42ee-4ecb-882d-3742e75af8d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485921565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.3485921565
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.1986703898
Short name T203
Test name
Test status
Simulation time 1456471224 ps
CPU time 7.13 seconds
Started Jul 13 07:00:46 PM PDT 24
Finished Jul 13 07:00:53 PM PDT 24
Peak memory 232664 kb
Host smart-c27a6b26-1e15-47b0-bda0-eb1264b6afbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986703898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.1986703898
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.971336631
Short name T322
Test name
Test status
Simulation time 18620888 ps
CPU time 0.75 seconds
Started Jul 13 07:00:52 PM PDT 24
Finished Jul 13 07:00:58 PM PDT 24
Peak memory 204976 kb
Host smart-05fe71b5-e622-4541-93d1-43e519582bb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971336631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.971336631
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.1691012700
Short name T897
Test name
Test status
Simulation time 1526716952 ps
CPU time 9.38 seconds
Started Jul 13 07:00:51 PM PDT 24
Finished Jul 13 07:01:04 PM PDT 24
Peak memory 224448 kb
Host smart-984b57e1-e5b5-47a6-a02e-1848cae77a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691012700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.1691012700
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.2760878838
Short name T788
Test name
Test status
Simulation time 67260817 ps
CPU time 0.8 seconds
Started Jul 13 07:00:41 PM PDT 24
Finished Jul 13 07:00:43 PM PDT 24
Peak memory 205632 kb
Host smart-cfeb5824-af00-4bc4-bc78-2877fc338127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760878838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.2760878838
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.1696094090
Short name T425
Test name
Test status
Simulation time 3853413340 ps
CPU time 24.74 seconds
Started Jul 13 07:00:51 PM PDT 24
Finished Jul 13 07:01:21 PM PDT 24
Peak memory 240992 kb
Host smart-3e5e196a-085d-43ae-83e6-e1783593ed03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696094090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.1696094090
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.3956743121
Short name T586
Test name
Test status
Simulation time 15277227898 ps
CPU time 96.12 seconds
Started Jul 13 07:00:51 PM PDT 24
Finished Jul 13 07:02:31 PM PDT 24
Peak memory 253356 kb
Host smart-1e575ae7-719d-4029-8bdd-6d20a9af9a29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956743121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.3956743121
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.2611885707
Short name T966
Test name
Test status
Simulation time 6035214815 ps
CPU time 112.74 seconds
Started Jul 13 07:00:43 PM PDT 24
Finished Jul 13 07:02:37 PM PDT 24
Peak memory 250900 kb
Host smart-6810bf65-bb08-4ef9-94e8-3e49b6ba6aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611885707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.2611885707
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.2652629033
Short name T299
Test name
Test status
Simulation time 2084058921 ps
CPU time 13.57 seconds
Started Jul 13 07:00:41 PM PDT 24
Finished Jul 13 07:00:56 PM PDT 24
Peak memory 240896 kb
Host smart-e4ddd4f3-adf0-4c08-84ab-f63a3d658fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652629033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.2652629033
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.1925771349
Short name T47
Test name
Test status
Simulation time 778746383 ps
CPU time 12.39 seconds
Started Jul 13 07:00:46 PM PDT 24
Finished Jul 13 07:00:59 PM PDT 24
Peak memory 232656 kb
Host smart-f06fa628-0992-47b8-874a-80f4c88c31ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925771349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmd
s.1925771349
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.3627038097
Short name T688
Test name
Test status
Simulation time 1200159387 ps
CPU time 5.06 seconds
Started Jul 13 07:00:38 PM PDT 24
Finished Jul 13 07:00:43 PM PDT 24
Peak memory 224456 kb
Host smart-e2cd0154-327c-4d39-bebb-0cf8d3379fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627038097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.3627038097
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.3668074076
Short name T557
Test name
Test status
Simulation time 10161285531 ps
CPU time 35.83 seconds
Started Jul 13 07:00:51 PM PDT 24
Finished Jul 13 07:01:31 PM PDT 24
Peak memory 249056 kb
Host smart-128f419f-5a63-4671-b879-177e431e15f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668074076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.3668074076
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.3326024012
Short name T202
Test name
Test status
Simulation time 18831354008 ps
CPU time 28.59 seconds
Started Jul 13 07:00:51 PM PDT 24
Finished Jul 13 07:01:23 PM PDT 24
Peak memory 250944 kb
Host smart-26fb7240-6da8-4eb8-81d3-14f75688c122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326024012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.3326024012
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.3973073106
Short name T410
Test name
Test status
Simulation time 1388287915 ps
CPU time 11.12 seconds
Started Jul 13 07:00:51 PM PDT 24
Finished Jul 13 07:01:06 PM PDT 24
Peak memory 247912 kb
Host smart-b91b5434-0285-4e5c-82f9-0477f2bf3e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973073106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.3973073106
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.1057888903
Short name T662
Test name
Test status
Simulation time 408711283 ps
CPU time 4.17 seconds
Started Jul 13 07:00:51 PM PDT 24
Finished Jul 13 07:01:00 PM PDT 24
Peak memory 223124 kb
Host smart-47f2eacc-1ee3-4413-af91-7bc43a742276
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1057888903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.1057888903
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.1199846549
Short name T164
Test name
Test status
Simulation time 37685843025 ps
CPU time 179.85 seconds
Started Jul 13 07:00:51 PM PDT 24
Finished Jul 13 07:03:56 PM PDT 24
Peak memory 249292 kb
Host smart-54850b36-e02c-4ca6-8028-8685c36aca96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199846549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.1199846549
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.2024083626
Short name T938
Test name
Test status
Simulation time 8569428665 ps
CPU time 44.81 seconds
Started Jul 13 07:00:54 PM PDT 24
Finished Jul 13 07:01:44 PM PDT 24
Peak memory 216368 kb
Host smart-fa2c982e-7aa1-47e4-adff-3b71961a6887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024083626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.2024083626
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.467544902
Short name T613
Test name
Test status
Simulation time 5107448828 ps
CPU time 13.46 seconds
Started Jul 13 07:00:50 PM PDT 24
Finished Jul 13 07:01:07 PM PDT 24
Peak memory 216364 kb
Host smart-87436c20-a143-440e-b8a8-67ccec23f974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467544902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.467544902
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.105196534
Short name T672
Test name
Test status
Simulation time 264718897 ps
CPU time 11.17 seconds
Started Jul 13 07:00:50 PM PDT 24
Finished Jul 13 07:01:04 PM PDT 24
Peak memory 216204 kb
Host smart-54829e2f-63ad-4c4a-89e8-e2f5378b43f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105196534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.105196534
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.273075831
Short name T719
Test name
Test status
Simulation time 21981880 ps
CPU time 0.73 seconds
Started Jul 13 07:00:42 PM PDT 24
Finished Jul 13 07:00:44 PM PDT 24
Peak memory 206000 kb
Host smart-e88ae370-eedd-4d78-be28-ba0ee2e75fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273075831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.273075831
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.3211435357
Short name T439
Test name
Test status
Simulation time 156508367 ps
CPU time 2.35 seconds
Started Jul 13 07:00:51 PM PDT 24
Finished Jul 13 07:00:57 PM PDT 24
Peak memory 232316 kb
Host smart-96f21c2b-09ac-4e9e-a059-6e4f48e0d9ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211435357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.3211435357
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.3809729428
Short name T633
Test name
Test status
Simulation time 11487215 ps
CPU time 0.73 seconds
Started Jul 13 07:00:49 PM PDT 24
Finished Jul 13 07:00:51 PM PDT 24
Peak memory 205560 kb
Host smart-cff51edc-1028-403a-b9ff-b01146c5263c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809729428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
3809729428
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.1486944835
Short name T653
Test name
Test status
Simulation time 1414436097 ps
CPU time 13 seconds
Started Jul 13 07:00:48 PM PDT 24
Finished Jul 13 07:01:01 PM PDT 24
Peak memory 232668 kb
Host smart-8d3c14d0-308f-42aa-823a-99a89ce5c646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486944835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.1486944835
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.4053230194
Short name T996
Test name
Test status
Simulation time 25443822 ps
CPU time 0.79 seconds
Started Jul 13 07:00:50 PM PDT 24
Finished Jul 13 07:00:54 PM PDT 24
Peak memory 206632 kb
Host smart-d708e48e-1ee1-4783-9d38-6e8301cda288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053230194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.4053230194
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.1283022667
Short name T774
Test name
Test status
Simulation time 7762890681 ps
CPU time 73.24 seconds
Started Jul 13 07:00:50 PM PDT 24
Finished Jul 13 07:02:04 PM PDT 24
Peak memory 254928 kb
Host smart-6738983d-6bc2-4bf8-814c-b9f9974f524d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283022667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.1283022667
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.4125774712
Short name T199
Test name
Test status
Simulation time 47809217182 ps
CPU time 321.14 seconds
Started Jul 13 07:00:52 PM PDT 24
Finished Jul 13 07:06:18 PM PDT 24
Peak memory 249152 kb
Host smart-71c13123-c255-4367-b890-e4674521cb28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125774712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.4125774712
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.4209561573
Short name T805
Test name
Test status
Simulation time 3408474668 ps
CPU time 68.97 seconds
Started Jul 13 07:00:51 PM PDT 24
Finished Jul 13 07:02:03 PM PDT 24
Peak memory 249544 kb
Host smart-4dcb008b-e1b3-4279-8786-4800f488226b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209561573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.4209561573
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.2045203334
Short name T64
Test name
Test status
Simulation time 310082306 ps
CPU time 6.78 seconds
Started Jul 13 07:00:51 PM PDT 24
Finished Jul 13 07:01:03 PM PDT 24
Peak memory 224520 kb
Host smart-20f9d114-bf61-442d-b22f-6ef264e48560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045203334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.2045203334
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.1979817462
Short name T102
Test name
Test status
Simulation time 1354557331 ps
CPU time 13.33 seconds
Started Jul 13 07:00:52 PM PDT 24
Finished Jul 13 07:01:11 PM PDT 24
Peak memory 249088 kb
Host smart-f9e47096-c261-4365-97cf-ecdb2b8662da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979817462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmd
s.1979817462
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.3721113644
Short name T991
Test name
Test status
Simulation time 958280442 ps
CPU time 3.93 seconds
Started Jul 13 07:00:51 PM PDT 24
Finished Jul 13 07:01:00 PM PDT 24
Peak memory 224460 kb
Host smart-4337fcba-8b7b-4425-b469-0c9f070a314c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721113644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.3721113644
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.3541127995
Short name T100
Test name
Test status
Simulation time 10137287871 ps
CPU time 33.11 seconds
Started Jul 13 07:00:53 PM PDT 24
Finished Jul 13 07:01:31 PM PDT 24
Peak memory 249028 kb
Host smart-e716cf8f-ef59-4ff5-9712-95c958996ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541127995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.3541127995
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.1560008906
Short name T392
Test name
Test status
Simulation time 1212905621 ps
CPU time 5.82 seconds
Started Jul 13 07:00:51 PM PDT 24
Finished Jul 13 07:01:02 PM PDT 24
Peak memory 224584 kb
Host smart-09962c7d-9a0b-46f1-8139-7e44f59d3105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560008906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.1560008906
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.26592887
Short name T568
Test name
Test status
Simulation time 2676107963 ps
CPU time 4.46 seconds
Started Jul 13 07:00:50 PM PDT 24
Finished Jul 13 07:00:58 PM PDT 24
Peak memory 232712 kb
Host smart-474d1e0f-f983-4de6-a456-437471713766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26592887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.26592887
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.2661014975
Short name T153
Test name
Test status
Simulation time 1182479048 ps
CPU time 5.9 seconds
Started Jul 13 07:00:53 PM PDT 24
Finished Jul 13 07:01:04 PM PDT 24
Peak memory 218664 kb
Host smart-a553931c-cc78-496a-b119-9e5366f26991
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2661014975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.2661014975
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.1006814943
Short name T429
Test name
Test status
Simulation time 36130956 ps
CPU time 0.74 seconds
Started Jul 13 07:00:51 PM PDT 24
Finished Jul 13 07:00:56 PM PDT 24
Peak memory 205320 kb
Host smart-17bab04d-77dc-4830-8c6e-6555a9df6342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006814943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.1006814943
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.2771157046
Short name T343
Test name
Test status
Simulation time 11462522765 ps
CPU time 8.55 seconds
Started Jul 13 07:00:52 PM PDT 24
Finished Jul 13 07:01:05 PM PDT 24
Peak memory 216304 kb
Host smart-2ec2cce5-e643-46c2-ab5b-415743621504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771157046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.2771157046
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.349415094
Short name T444
Test name
Test status
Simulation time 23101583 ps
CPU time 1.01 seconds
Started Jul 13 07:00:50 PM PDT 24
Finished Jul 13 07:00:54 PM PDT 24
Peak memory 207748 kb
Host smart-ee4e17b7-8b3c-42fd-bd10-ab682cc282b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349415094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.349415094
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.3668571772
Short name T452
Test name
Test status
Simulation time 91921189 ps
CPU time 0.76 seconds
Started Jul 13 07:00:52 PM PDT 24
Finished Jul 13 07:00:58 PM PDT 24
Peak memory 205996 kb
Host smart-643099da-dc91-4ed8-a28a-bc64c567ff55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668571772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.3668571772
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.1366184859
Short name T984
Test name
Test status
Simulation time 369125770 ps
CPU time 7.39 seconds
Started Jul 13 07:00:52 PM PDT 24
Finished Jul 13 07:01:05 PM PDT 24
Peak memory 232688 kb
Host smart-625d33c9-201e-46ef-b04e-849c3a677611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366184859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.1366184859
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.3495096422
Short name T909
Test name
Test status
Simulation time 15810287 ps
CPU time 0.77 seconds
Started Jul 13 07:00:50 PM PDT 24
Finished Jul 13 07:00:54 PM PDT 24
Peak memory 204952 kb
Host smart-666c87a8-fc30-4e78-8680-4986f71f167e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495096422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
3495096422
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.3203240235
Short name T88
Test name
Test status
Simulation time 532999081 ps
CPU time 4.55 seconds
Started Jul 13 07:00:54 PM PDT 24
Finished Jul 13 07:01:03 PM PDT 24
Peak memory 224504 kb
Host smart-cf10c292-59f7-40ac-9846-d18a69cf2c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203240235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.3203240235
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.2087438521
Short name T342
Test name
Test status
Simulation time 14259979 ps
CPU time 0.83 seconds
Started Jul 13 07:00:53 PM PDT 24
Finished Jul 13 07:00:59 PM PDT 24
Peak memory 206812 kb
Host smart-148e1618-ae60-43d2-8cbf-034e87991c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087438521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.2087438521
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.1641599636
Short name T290
Test name
Test status
Simulation time 161288358491 ps
CPU time 105.29 seconds
Started Jul 13 07:00:51 PM PDT 24
Finished Jul 13 07:02:41 PM PDT 24
Peak memory 249204 kb
Host smart-39e5d33f-492e-472b-8d9e-0fb12575c451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641599636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.1641599636
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.2229369682
Short name T214
Test name
Test status
Simulation time 3648792216 ps
CPU time 33.9 seconds
Started Jul 13 07:00:49 PM PDT 24
Finished Jul 13 07:01:24 PM PDT 24
Peak memory 256640 kb
Host smart-e9d373b4-b993-4c01-acf7-99c628dc98af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229369682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.2229369682
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.369745496
Short name T281
Test name
Test status
Simulation time 119109120796 ps
CPU time 124.98 seconds
Started Jul 13 07:00:50 PM PDT 24
Finished Jul 13 07:02:58 PM PDT 24
Peak memory 264968 kb
Host smart-b72c4e59-1d2c-46c0-ba6c-23ccd322e954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369745496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idle
.369745496
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.2512658686
Short name T601
Test name
Test status
Simulation time 6538449016 ps
CPU time 25.04 seconds
Started Jul 13 07:00:49 PM PDT 24
Finished Jul 13 07:01:16 PM PDT 24
Peak memory 249000 kb
Host smart-4b3fe0d0-15ee-4b36-862a-8c33fb968a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512658686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.2512658686
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.3244323075
Short name T293
Test name
Test status
Simulation time 4522269065 ps
CPU time 76.73 seconds
Started Jul 13 07:00:51 PM PDT 24
Finished Jul 13 07:02:11 PM PDT 24
Peak memory 267024 kb
Host smart-10c0706e-2378-43ed-942e-1c56ed5d5273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244323075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmd
s.3244323075
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.1974096590
Short name T795
Test name
Test status
Simulation time 1632558515 ps
CPU time 3.33 seconds
Started Jul 13 07:00:48 PM PDT 24
Finished Jul 13 07:00:52 PM PDT 24
Peak memory 232600 kb
Host smart-dd9dfd97-e797-4d28-aed7-9b421daa111b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974096590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.1974096590
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.62476885
Short name T894
Test name
Test status
Simulation time 4121258444 ps
CPU time 20.11 seconds
Started Jul 13 07:00:52 PM PDT 24
Finished Jul 13 07:01:17 PM PDT 24
Peak memory 232824 kb
Host smart-03c137f8-9105-4146-99be-bb15ddd92228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62476885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.62476885
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.1246814251
Short name T736
Test name
Test status
Simulation time 983569109 ps
CPU time 6.78 seconds
Started Jul 13 07:00:51 PM PDT 24
Finished Jul 13 07:01:01 PM PDT 24
Peak memory 224492 kb
Host smart-4155e419-446d-4c94-a239-df862701f0a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246814251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.1246814251
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.3198923170
Short name T260
Test name
Test status
Simulation time 13503833827 ps
CPU time 16.84 seconds
Started Jul 13 07:00:51 PM PDT 24
Finished Jul 13 07:01:10 PM PDT 24
Peak memory 249168 kb
Host smart-93210e01-6812-49e9-b70c-da228f852f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198923170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.3198923170
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.1008694195
Short name T814
Test name
Test status
Simulation time 805811245 ps
CPU time 5.25 seconds
Started Jul 13 07:00:52 PM PDT 24
Finished Jul 13 07:01:03 PM PDT 24
Peak memory 218908 kb
Host smart-23f9a873-a722-4434-ac5a-5396c5ca0029
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1008694195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.1008694195
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.2465587980
Short name T868
Test name
Test status
Simulation time 29088091943 ps
CPU time 46.84 seconds
Started Jul 13 07:00:52 PM PDT 24
Finished Jul 13 07:01:44 PM PDT 24
Peak memory 216316 kb
Host smart-50af6a94-b0da-4f82-aa88-c44d4c33bf2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465587980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.2465587980
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.3546527278
Short name T566
Test name
Test status
Simulation time 14621592 ps
CPU time 0.71 seconds
Started Jul 13 07:00:50 PM PDT 24
Finished Jul 13 07:00:52 PM PDT 24
Peak memory 205648 kb
Host smart-23b84acb-71f3-46e9-bbd0-cfe281a9ee18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546527278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.3546527278
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.1247434844
Short name T483
Test name
Test status
Simulation time 284553125 ps
CPU time 4.65 seconds
Started Jul 13 07:00:49 PM PDT 24
Finished Jul 13 07:00:54 PM PDT 24
Peak memory 216196 kb
Host smart-cfe168b8-7370-4277-bd9d-0379987bcb2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247434844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.1247434844
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.156688990
Short name T678
Test name
Test status
Simulation time 238636217 ps
CPU time 0.78 seconds
Started Jul 13 07:00:52 PM PDT 24
Finished Jul 13 07:00:58 PM PDT 24
Peak memory 205992 kb
Host smart-4777d49b-cd5e-45a4-ac18-99645e56b822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156688990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.156688990
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.3647001319
Short name T453
Test name
Test status
Simulation time 445554726 ps
CPU time 2.57 seconds
Started Jul 13 07:00:50 PM PDT 24
Finished Jul 13 07:00:55 PM PDT 24
Peak memory 240808 kb
Host smart-2cd7033e-6019-41bf-bec2-16eb02e82d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647001319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.3647001319
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.1496326366
Short name T443
Test name
Test status
Simulation time 75993535 ps
CPU time 0.73 seconds
Started Jul 13 07:00:50 PM PDT 24
Finished Jul 13 07:00:54 PM PDT 24
Peak memory 204980 kb
Host smart-f8336c74-8335-4ecd-a644-757c562f8d0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496326366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
1496326366
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.2644286887
Short name T384
Test name
Test status
Simulation time 331006000 ps
CPU time 2.27 seconds
Started Jul 13 07:00:51 PM PDT 24
Finished Jul 13 07:00:57 PM PDT 24
Peak memory 224464 kb
Host smart-25b27d70-d195-41ce-bd34-8476de1ddb2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644286887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.2644286887
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.321808046
Short name T337
Test name
Test status
Simulation time 19663152 ps
CPU time 0.78 seconds
Started Jul 13 07:00:52 PM PDT 24
Finished Jul 13 07:00:57 PM PDT 24
Peak memory 206632 kb
Host smart-f21ddede-ab1b-4f4a-a365-59917bfaae49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321808046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.321808046
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.1693696896
Short name T184
Test name
Test status
Simulation time 2022921462 ps
CPU time 41.4 seconds
Started Jul 13 07:00:51 PM PDT 24
Finished Jul 13 07:01:36 PM PDT 24
Peak memory 237252 kb
Host smart-481d7257-9166-4217-a1a0-bcc3ca0dea2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693696896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.1693696896
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.1108670604
Short name T68
Test name
Test status
Simulation time 11621678238 ps
CPU time 28.2 seconds
Started Jul 13 07:00:53 PM PDT 24
Finished Jul 13 07:01:26 PM PDT 24
Peak memory 224648 kb
Host smart-83f99f10-38a0-4325-9d90-2b82a8d2dc90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108670604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.1108670604
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.3628724562
Short name T484
Test name
Test status
Simulation time 65414952786 ps
CPU time 169.16 seconds
Started Jul 13 07:00:51 PM PDT 24
Finished Jul 13 07:03:45 PM PDT 24
Peak memory 250832 kb
Host smart-3f7880c6-4bdc-4511-813f-26130017b319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628724562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.3628724562
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.4266363352
Short name T810
Test name
Test status
Simulation time 574914810 ps
CPU time 14.39 seconds
Started Jul 13 07:00:50 PM PDT 24
Finished Jul 13 07:01:08 PM PDT 24
Peak memory 249096 kb
Host smart-b2c26092-5fbe-4c5a-ab05-7601d8c3d695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266363352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.4266363352
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.431119204
Short name T799
Test name
Test status
Simulation time 199548157 ps
CPU time 0.92 seconds
Started Jul 13 07:00:51 PM PDT 24
Finished Jul 13 07:00:57 PM PDT 24
Peak memory 215936 kb
Host smart-816ff1a2-42e3-467e-82d8-da00e0e6ae5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431119204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmds
.431119204
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.3381058960
Short name T603
Test name
Test status
Simulation time 1636120144 ps
CPU time 9.26 seconds
Started Jul 13 07:00:53 PM PDT 24
Finished Jul 13 07:01:08 PM PDT 24
Peak memory 232488 kb
Host smart-584187fc-b16f-4eab-9d43-3758eb447517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381058960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.3381058960
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.2184557861
Short name T631
Test name
Test status
Simulation time 1609497543 ps
CPU time 10.5 seconds
Started Jul 13 07:00:51 PM PDT 24
Finished Jul 13 07:01:05 PM PDT 24
Peak memory 224456 kb
Host smart-491ac45d-1642-431a-bbc6-cd726a23329e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184557861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.2184557861
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.3698616110
Short name T691
Test name
Test status
Simulation time 4731285382 ps
CPU time 6.25 seconds
Started Jul 13 07:00:52 PM PDT 24
Finished Jul 13 07:01:04 PM PDT 24
Peak memory 232760 kb
Host smart-17a45327-d020-4234-a8e3-97184e3fc58b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698616110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.3698616110
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.1336115922
Short name T87
Test name
Test status
Simulation time 5461239619 ps
CPU time 19.28 seconds
Started Jul 13 07:00:50 PM PDT 24
Finished Jul 13 07:01:13 PM PDT 24
Peak memory 249232 kb
Host smart-1618f44a-ac02-4efd-b07f-d7aab0bf5d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336115922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.1336115922
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.1026855569
Short name T56
Test name
Test status
Simulation time 3760109547 ps
CPU time 29.68 seconds
Started Jul 13 07:00:48 PM PDT 24
Finished Jul 13 07:01:18 PM PDT 24
Peak memory 216496 kb
Host smart-a974dc1c-c72d-4e26-aebc-e9223e5c39d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026855569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.1026855569
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.1951824362
Short name T819
Test name
Test status
Simulation time 3414216161 ps
CPU time 13.24 seconds
Started Jul 13 07:00:50 PM PDT 24
Finished Jul 13 07:01:06 PM PDT 24
Peak memory 216348 kb
Host smart-73b45084-a9e4-4eab-951e-8cf395431eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951824362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.1951824362
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.3759804153
Short name T879
Test name
Test status
Simulation time 57540353 ps
CPU time 1.96 seconds
Started Jul 13 07:00:52 PM PDT 24
Finished Jul 13 07:00:58 PM PDT 24
Peak memory 216268 kb
Host smart-8dd005e5-f2c8-4f62-a746-d92fd1ea4572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759804153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.3759804153
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.405371048
Short name T727
Test name
Test status
Simulation time 59394063 ps
CPU time 0.79 seconds
Started Jul 13 07:00:51 PM PDT 24
Finished Jul 13 07:00:55 PM PDT 24
Peak memory 206000 kb
Host smart-ddbbdef1-626f-412d-b152-4e5b3316ba05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405371048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.405371048
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.12651727
Short name T741
Test name
Test status
Simulation time 6811141481 ps
CPU time 9.13 seconds
Started Jul 13 07:00:48 PM PDT 24
Finished Jul 13 07:00:57 PM PDT 24
Peak memory 232836 kb
Host smart-741e3dd6-e1b7-47d4-b889-b7e75ad312f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12651727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.12651727
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.2278774262
Short name T406
Test name
Test status
Simulation time 14333354 ps
CPU time 0.71 seconds
Started Jul 13 07:00:57 PM PDT 24
Finished Jul 13 07:01:01 PM PDT 24
Peak memory 205848 kb
Host smart-05065e9b-c524-416c-a59f-ee758f2db3e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278774262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
2278774262
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.3213175183
Short name T589
Test name
Test status
Simulation time 137108561 ps
CPU time 3.25 seconds
Started Jul 13 07:00:52 PM PDT 24
Finished Jul 13 07:01:00 PM PDT 24
Peak memory 232496 kb
Host smart-0db833d7-9b90-4023-8304-69a448213335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213175183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.3213175183
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.845816317
Short name T463
Test name
Test status
Simulation time 18125549 ps
CPU time 0.81 seconds
Started Jul 13 07:00:53 PM PDT 24
Finished Jul 13 07:00:59 PM PDT 24
Peak memory 206636 kb
Host smart-3c128821-793f-4b10-8c80-682cdbc6a13c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845816317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.845816317
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.1980470546
Short name T822
Test name
Test status
Simulation time 67918216203 ps
CPU time 270.31 seconds
Started Jul 13 07:00:59 PM PDT 24
Finished Jul 13 07:05:33 PM PDT 24
Peak memory 261124 kb
Host smart-48e54a05-8375-4804-b1db-c8224550a81c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980470546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.1980470546
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.2744060907
Short name T252
Test name
Test status
Simulation time 8904568599 ps
CPU time 119.76 seconds
Started Jul 13 07:00:58 PM PDT 24
Finished Jul 13 07:03:01 PM PDT 24
Peak memory 272748 kb
Host smart-b6e88bd9-2537-43cc-9633-4b8399ecf819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744060907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.2744060907
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.2542885222
Short name T310
Test name
Test status
Simulation time 38834467054 ps
CPU time 33.14 seconds
Started Jul 13 07:00:58 PM PDT 24
Finished Jul 13 07:01:34 PM PDT 24
Peak memory 217608 kb
Host smart-456f5aa6-19ae-46b7-8ad0-9b198577d402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542885222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.2542885222
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.2567891410
Short name T345
Test name
Test status
Simulation time 2710273991 ps
CPU time 28.45 seconds
Started Jul 13 07:00:52 PM PDT 24
Finished Jul 13 07:01:25 PM PDT 24
Peak memory 241008 kb
Host smart-124e52bd-9b29-4552-90b1-a9549a1b8201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567891410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.2567891410
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.2455178995
Short name T467
Test name
Test status
Simulation time 1085629073 ps
CPU time 5.86 seconds
Started Jul 13 07:01:07 PM PDT 24
Finished Jul 13 07:01:13 PM PDT 24
Peak memory 234552 kb
Host smart-1c5d1206-6f13-477d-afe4-72d6061eaa57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455178995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmd
s.2455178995
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.2085617262
Short name T461
Test name
Test status
Simulation time 10382089266 ps
CPU time 19.2 seconds
Started Jul 13 07:00:53 PM PDT 24
Finished Jul 13 07:01:17 PM PDT 24
Peak memory 224640 kb
Host smart-d38bc036-7446-4760-9da1-4f8eee231a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085617262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.2085617262
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.3241878174
Short name T812
Test name
Test status
Simulation time 1286325033 ps
CPU time 21.85 seconds
Started Jul 13 07:00:53 PM PDT 24
Finished Jul 13 07:01:20 PM PDT 24
Peak memory 240688 kb
Host smart-60e30031-30b0-4254-a0e3-84c2aac4d40d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241878174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.3241878174
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.3123287667
Short name T294
Test name
Test status
Simulation time 2151935414 ps
CPU time 7.12 seconds
Started Jul 13 07:00:51 PM PDT 24
Finished Jul 13 07:01:03 PM PDT 24
Peak memory 232772 kb
Host smart-13e4610d-1a66-474f-825e-10c1b44d026a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123287667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.3123287667
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.116137563
Short name T582
Test name
Test status
Simulation time 52925051 ps
CPU time 2.55 seconds
Started Jul 13 07:00:51 PM PDT 24
Finished Jul 13 07:00:57 PM PDT 24
Peak memory 232628 kb
Host smart-358822bd-b0d9-4526-8d75-7328de141d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116137563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.116137563
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.1781811784
Short name T327
Test name
Test status
Simulation time 8289886879 ps
CPU time 11.31 seconds
Started Jul 13 07:00:58 PM PDT 24
Finished Jul 13 07:01:12 PM PDT 24
Peak memory 219228 kb
Host smart-a69c6a11-b0ab-44de-8a30-deb44c52158d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1781811784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.1781811784
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.4169793259
Short name T273
Test name
Test status
Simulation time 23791596031 ps
CPU time 51.74 seconds
Started Jul 13 07:01:01 PM PDT 24
Finished Jul 13 07:01:56 PM PDT 24
Peak memory 235144 kb
Host smart-dbb94296-1ffc-4c6e-bc62-084dce80b8aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169793259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.4169793259
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.762177370
Short name T411
Test name
Test status
Simulation time 6050497954 ps
CPU time 43 seconds
Started Jul 13 07:00:53 PM PDT 24
Finished Jul 13 07:01:41 PM PDT 24
Peak memory 216076 kb
Host smart-bc0f53f1-0517-4760-bede-df4eea30bd86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762177370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.762177370
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.3915565401
Short name T441
Test name
Test status
Simulation time 32501914924 ps
CPU time 9.93 seconds
Started Jul 13 07:00:53 PM PDT 24
Finished Jul 13 07:01:08 PM PDT 24
Peak memory 216388 kb
Host smart-b84c7c63-1cec-4382-af52-f14f7b233fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915565401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.3915565401
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.1137850452
Short name T973
Test name
Test status
Simulation time 323385375 ps
CPU time 15.92 seconds
Started Jul 13 07:00:51 PM PDT 24
Finished Jul 13 07:01:12 PM PDT 24
Peak memory 216136 kb
Host smart-660f5bbf-5107-488e-a987-8e344298473f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137850452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.1137850452
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.3523175707
Short name T857
Test name
Test status
Simulation time 101213671 ps
CPU time 0.95 seconds
Started Jul 13 07:00:51 PM PDT 24
Finished Jul 13 07:00:56 PM PDT 24
Peak memory 205988 kb
Host smart-6a5724fa-b771-42c3-91a0-465e38dd6ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523175707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.3523175707
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.135218093
Short name T806
Test name
Test status
Simulation time 2126686196 ps
CPU time 16.22 seconds
Started Jul 13 07:00:53 PM PDT 24
Finished Jul 13 07:01:15 PM PDT 24
Peak memory 232684 kb
Host smart-19ad1d3c-ec12-456d-8b27-0d421182e2cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135218093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.135218093
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.3396338445
Short name T38
Test name
Test status
Simulation time 26747113 ps
CPU time 0.69 seconds
Started Jul 13 07:01:00 PM PDT 24
Finished Jul 13 07:01:05 PM PDT 24
Peak memory 205500 kb
Host smart-668a755f-08f3-4257-be4b-61c203d794c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396338445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
3396338445
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.1223248490
Short name T263
Test name
Test status
Simulation time 4368390646 ps
CPU time 9.15 seconds
Started Jul 13 07:01:02 PM PDT 24
Finished Jul 13 07:01:14 PM PDT 24
Peak memory 232820 kb
Host smart-baed0a7e-7fd1-479f-9eff-e8f0ca525c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223248490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.1223248490
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.3032587913
Short name T956
Test name
Test status
Simulation time 60216757 ps
CPU time 0.78 seconds
Started Jul 13 07:00:59 PM PDT 24
Finished Jul 13 07:01:03 PM PDT 24
Peak memory 205604 kb
Host smart-284704e2-ea5c-4323-b7e4-988fa1daedc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032587913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.3032587913
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.114515981
Short name T563
Test name
Test status
Simulation time 9457698205 ps
CPU time 81.1 seconds
Started Jul 13 07:01:00 PM PDT 24
Finished Jul 13 07:02:24 PM PDT 24
Peak memory 252276 kb
Host smart-f211da24-94a7-4157-abde-2539e633dbeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114515981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.114515981
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.3143218353
Short name T212
Test name
Test status
Simulation time 74916540334 ps
CPU time 208.07 seconds
Started Jul 13 07:01:00 PM PDT 24
Finished Jul 13 07:04:31 PM PDT 24
Peak memory 255316 kb
Host smart-b05a682e-1d0a-4dec-bcda-b6cf6048d980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143218353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.3143218353
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.3662470212
Short name T574
Test name
Test status
Simulation time 10205362357 ps
CPU time 52.93 seconds
Started Jul 13 07:00:57 PM PDT 24
Finished Jul 13 07:01:53 PM PDT 24
Peak memory 232860 kb
Host smart-7d47a7a2-2e96-462e-930a-cb1b107cf67a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662470212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.3662470212
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.78053013
Short name T300
Test name
Test status
Simulation time 19101039783 ps
CPU time 12.37 seconds
Started Jul 13 07:00:59 PM PDT 24
Finished Jul 13 07:01:15 PM PDT 24
Peak memory 224636 kb
Host smart-c313d3cc-0ebc-4eb7-a567-098e67c7b50f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78053013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.78053013
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.2515081290
Short name T253
Test name
Test status
Simulation time 84781704123 ps
CPU time 258.79 seconds
Started Jul 13 07:01:01 PM PDT 24
Finished Jul 13 07:05:23 PM PDT 24
Peak memory 249204 kb
Host smart-6599c43a-cf8c-475a-b52d-b45f4a75fa95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515081290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmd
s.2515081290
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.2450863478
Short name T330
Test name
Test status
Simulation time 33874001 ps
CPU time 2.31 seconds
Started Jul 13 07:00:58 PM PDT 24
Finished Jul 13 07:01:03 PM PDT 24
Peak memory 232384 kb
Host smart-3c857537-5f9d-40b0-99db-418834d10597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450863478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.2450863478
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.434733313
Short name T605
Test name
Test status
Simulation time 571522001 ps
CPU time 7.27 seconds
Started Jul 13 07:00:58 PM PDT 24
Finished Jul 13 07:01:09 PM PDT 24
Peak memory 232800 kb
Host smart-09333bec-27df-4f25-97bb-ed094d6d9178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434733313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.434733313
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.1607988850
Short name T614
Test name
Test status
Simulation time 139489499 ps
CPU time 2.05 seconds
Started Jul 13 07:00:58 PM PDT 24
Finished Jul 13 07:01:03 PM PDT 24
Peak memory 224096 kb
Host smart-cfd792dc-6c31-4b4a-825d-92b80e397492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607988850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.1607988850
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.1610454587
Short name T103
Test name
Test status
Simulation time 144118457 ps
CPU time 3.38 seconds
Started Jul 13 07:00:59 PM PDT 24
Finished Jul 13 07:01:06 PM PDT 24
Peak memory 224448 kb
Host smart-13ce4638-b473-4223-ad3a-3df6fbcc9784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610454587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.1610454587
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.1443098054
Short name T598
Test name
Test status
Simulation time 75275841 ps
CPU time 3.17 seconds
Started Jul 13 07:01:00 PM PDT 24
Finished Jul 13 07:01:06 PM PDT 24
Peak memory 218836 kb
Host smart-fa8f1531-2fa3-4ee8-8f01-af7f21eb17cc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1443098054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.1443098054
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.1196518443
Short name T587
Test name
Test status
Simulation time 30756507786 ps
CPU time 39.39 seconds
Started Jul 13 07:01:01 PM PDT 24
Finished Jul 13 07:01:44 PM PDT 24
Peak memory 216520 kb
Host smart-37d42827-10a9-48d1-b7a3-a590e2df559e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196518443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.1196518443
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.145502967
Short name T351
Test name
Test status
Simulation time 675591872 ps
CPU time 4.35 seconds
Started Jul 13 07:01:02 PM PDT 24
Finished Jul 13 07:01:10 PM PDT 24
Peak memory 216176 kb
Host smart-2df15eb0-1108-4928-979d-95aefc89554a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145502967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.145502967
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.366877120
Short name T457
Test name
Test status
Simulation time 122814793 ps
CPU time 1.7 seconds
Started Jul 13 07:00:59 PM PDT 24
Finished Jul 13 07:01:03 PM PDT 24
Peak memory 216284 kb
Host smart-88bd4513-6d6d-4941-ace0-813271cc7050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366877120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.366877120
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.1506768483
Short name T496
Test name
Test status
Simulation time 10361078 ps
CPU time 0.67 seconds
Started Jul 13 07:01:06 PM PDT 24
Finished Jul 13 07:01:07 PM PDT 24
Peak memory 205672 kb
Host smart-4ad72ec0-748b-41b3-9861-901c68642631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506768483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.1506768483
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.3328876397
Short name T104
Test name
Test status
Simulation time 1136067582 ps
CPU time 2.65 seconds
Started Jul 13 07:01:02 PM PDT 24
Finished Jul 13 07:01:11 PM PDT 24
Peak memory 224376 kb
Host smart-9e954c7a-47ff-41dc-8729-ddc92664e2ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328876397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.3328876397
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.1320736021
Short name T658
Test name
Test status
Simulation time 12884719 ps
CPU time 0.72 seconds
Started Jul 13 07:00:59 PM PDT 24
Finished Jul 13 07:01:03 PM PDT 24
Peak memory 204944 kb
Host smart-00924266-2160-410d-96a6-a1ccb8bb4763
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320736021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
1320736021
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.415680032
Short name T230
Test name
Test status
Simulation time 8800450854 ps
CPU time 7.24 seconds
Started Jul 13 07:01:00 PM PDT 24
Finished Jul 13 07:01:11 PM PDT 24
Peak memory 224580 kb
Host smart-30839261-04b5-454e-86eb-ce1c61c4afde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415680032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.415680032
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.4014111477
Short name T985
Test name
Test status
Simulation time 18620952 ps
CPU time 0.78 seconds
Started Jul 13 07:00:58 PM PDT 24
Finished Jul 13 07:01:01 PM PDT 24
Peak memory 205604 kb
Host smart-ebca7c81-14ed-4df3-941d-910cbf2344f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014111477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.4014111477
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.3378185254
Short name T487
Test name
Test status
Simulation time 15853462375 ps
CPU time 37.9 seconds
Started Jul 13 07:00:58 PM PDT 24
Finished Jul 13 07:01:39 PM PDT 24
Peak memory 241012 kb
Host smart-9c21341d-b402-4bfe-beb8-b5855f25a81e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378185254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.3378185254
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.2507274088
Short name T275
Test name
Test status
Simulation time 46321220254 ps
CPU time 491.29 seconds
Started Jul 13 07:01:01 PM PDT 24
Finished Jul 13 07:09:16 PM PDT 24
Peak memory 273100 kb
Host smart-8c7a2447-314c-42e8-9ea4-802669eabbb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507274088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.2507274088
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.1010357948
Short name T571
Test name
Test status
Simulation time 1932766332 ps
CPU time 11.64 seconds
Started Jul 13 07:01:00 PM PDT 24
Finished Jul 13 07:01:16 PM PDT 24
Peak memory 232764 kb
Host smart-3e065e73-68f7-46eb-871c-cd4c64395815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010357948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.1010357948
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.3598521145
Short name T438
Test name
Test status
Simulation time 71817744 ps
CPU time 4.19 seconds
Started Jul 13 07:00:59 PM PDT 24
Finished Jul 13 07:01:07 PM PDT 24
Peak memory 232680 kb
Host smart-8b4c6125-6a8a-4b79-b440-58c046902fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598521145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.3598521145
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.1573447802
Short name T701
Test name
Test status
Simulation time 6241730202 ps
CPU time 25.82 seconds
Started Jul 13 07:01:04 PM PDT 24
Finished Jul 13 07:01:31 PM PDT 24
Peak memory 224464 kb
Host smart-6993ed91-54d6-4014-9ec2-8264d9a22891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573447802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmd
s.1573447802
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.3688751830
Short name T666
Test name
Test status
Simulation time 3175486952 ps
CPU time 15.01 seconds
Started Jul 13 07:00:58 PM PDT 24
Finished Jul 13 07:01:16 PM PDT 24
Peak memory 232768 kb
Host smart-4842b7ea-ba5f-417c-8312-2a5fdf093894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688751830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.3688751830
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.725804363
Short name T671
Test name
Test status
Simulation time 544334608 ps
CPU time 12.45 seconds
Started Jul 13 07:00:59 PM PDT 24
Finished Jul 13 07:01:15 PM PDT 24
Peak memory 232716 kb
Host smart-d7a7e2a6-78ff-43c3-adf7-e2590292ddb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725804363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.725804363
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.1015587139
Short name T932
Test name
Test status
Simulation time 1509077642 ps
CPU time 11.27 seconds
Started Jul 13 07:00:58 PM PDT 24
Finished Jul 13 07:01:13 PM PDT 24
Peak memory 240544 kb
Host smart-e0cfed7e-3472-47a8-93cd-e4e6ae992d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015587139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.1015587139
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.480879107
Short name T536
Test name
Test status
Simulation time 59293144 ps
CPU time 1.94 seconds
Started Jul 13 07:00:59 PM PDT 24
Finished Jul 13 07:01:04 PM PDT 24
Peak memory 223664 kb
Host smart-43b9da7f-683b-4993-8500-c902cd2e3b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480879107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.480879107
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.682438753
Short name T884
Test name
Test status
Simulation time 115099020 ps
CPU time 4 seconds
Started Jul 13 07:00:57 PM PDT 24
Finished Jul 13 07:01:04 PM PDT 24
Peak memory 222984 kb
Host smart-41b2fb66-2681-4054-850c-a7afa67e4d52
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=682438753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dire
ct.682438753
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.2386046932
Short name T540
Test name
Test status
Simulation time 2147898418 ps
CPU time 31.16 seconds
Started Jul 13 07:00:59 PM PDT 24
Finished Jul 13 07:01:34 PM PDT 24
Peak memory 216388 kb
Host smart-a5d35a74-0eb6-4ebf-8ad5-558334225fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386046932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.2386046932
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.2935698417
Short name T380
Test name
Test status
Simulation time 1770914761 ps
CPU time 7.33 seconds
Started Jul 13 07:01:02 PM PDT 24
Finished Jul 13 07:01:12 PM PDT 24
Peak memory 216160 kb
Host smart-8324ef35-7ff2-4666-89ef-ca9e0ab5b14e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935698417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.2935698417
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.1375413374
Short name T521
Test name
Test status
Simulation time 100926762 ps
CPU time 1.18 seconds
Started Jul 13 07:01:02 PM PDT 24
Finished Jul 13 07:01:06 PM PDT 24
Peak memory 216128 kb
Host smart-e817cc23-dfd2-46be-be49-62691e5b2e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375413374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.1375413374
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.1770695186
Short name T759
Test name
Test status
Simulation time 487662330 ps
CPU time 0.98 seconds
Started Jul 13 07:01:00 PM PDT 24
Finished Jul 13 07:01:05 PM PDT 24
Peak memory 205984 kb
Host smart-13fb9bdc-2a50-4861-b47b-e587d3eced49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770695186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.1770695186
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.2168703388
Short name T697
Test name
Test status
Simulation time 382080237 ps
CPU time 3.31 seconds
Started Jul 13 07:00:59 PM PDT 24
Finished Jul 13 07:01:05 PM PDT 24
Peak memory 224384 kb
Host smart-0c6b42fa-22a4-4a88-b569-91b836fddf98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168703388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.2168703388
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.2074186085
Short name T328
Test name
Test status
Simulation time 99770025 ps
CPU time 0.7 seconds
Started Jul 13 06:59:13 PM PDT 24
Finished Jul 13 06:59:16 PM PDT 24
Peak memory 205540 kb
Host smart-e1ae3c3c-bf85-483b-ad25-bd6e1c2c1973
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074186085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.2
074186085
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.3746445319
Short name T811
Test name
Test status
Simulation time 225066539 ps
CPU time 4.76 seconds
Started Jul 13 06:59:10 PM PDT 24
Finished Jul 13 06:59:16 PM PDT 24
Peak memory 232684 kb
Host smart-a68a8dc1-4f22-400c-a0f5-d40ae1c8f97f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746445319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.3746445319
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.3803993465
Short name T746
Test name
Test status
Simulation time 24920850 ps
CPU time 0.78 seconds
Started Jul 13 06:59:12 PM PDT 24
Finished Jul 13 06:59:16 PM PDT 24
Peak memory 206956 kb
Host smart-44210cdd-793b-45fb-a548-e46af9242025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803993465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.3803993465
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.420491584
Short name T357
Test name
Test status
Simulation time 49676403383 ps
CPU time 99.99 seconds
Started Jul 13 06:59:11 PM PDT 24
Finished Jul 13 07:00:54 PM PDT 24
Peak memory 240960 kb
Host smart-9bdbe926-184a-428d-8b8d-ec8186e277af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420491584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.420491584
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.286931227
Short name T454
Test name
Test status
Simulation time 30859153809 ps
CPU time 116.36 seconds
Started Jul 13 06:59:19 PM PDT 24
Finished Jul 13 07:01:16 PM PDT 24
Peak memory 256080 kb
Host smart-bbbcd9ca-bd0b-4c4f-b875-8c0a51022543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286931227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.286931227
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.1514369799
Short name T190
Test name
Test status
Simulation time 190353083460 ps
CPU time 440.83 seconds
Started Jul 13 06:59:15 PM PDT 24
Finished Jul 13 07:06:37 PM PDT 24
Peak memory 255004 kb
Host smart-b3eb9e86-97d6-424b-9ed2-9bb6f105b906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514369799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.1514369799
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.930725912
Short name T498
Test name
Test status
Simulation time 88210917056 ps
CPU time 165.41 seconds
Started Jul 13 06:59:11 PM PDT 24
Finished Jul 13 07:02:00 PM PDT 24
Peak memory 256648 kb
Host smart-7888885a-ad69-46ba-9deb-92973db68231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930725912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds.
930725912
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.902773483
Short name T2
Test name
Test status
Simulation time 862127050 ps
CPU time 4.1 seconds
Started Jul 13 06:59:13 PM PDT 24
Finished Jul 13 06:59:19 PM PDT 24
Peak memory 232700 kb
Host smart-20b4e845-8c35-4e6a-b01d-415a9e8b2476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902773483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.902773483
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.2125664854
Short name T523
Test name
Test status
Simulation time 7157139687 ps
CPU time 37.55 seconds
Started Jul 13 06:59:12 PM PDT 24
Finished Jul 13 06:59:52 PM PDT 24
Peak memory 232784 kb
Host smart-750601ea-93dc-4476-b821-c640632c38cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125664854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.2125664854
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.1422027881
Short name T638
Test name
Test status
Simulation time 3587280331 ps
CPU time 15.05 seconds
Started Jul 13 06:59:10 PM PDT 24
Finished Jul 13 06:59:26 PM PDT 24
Peak memory 240616 kb
Host smart-06ab41d4-6f64-4c0c-81a6-a3de49eb22a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422027881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.1422027881
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.3245861664
Short name T940
Test name
Test status
Simulation time 987679050 ps
CPU time 8.52 seconds
Started Jul 13 06:59:13 PM PDT 24
Finished Jul 13 06:59:24 PM PDT 24
Peak memory 248064 kb
Host smart-fdae994b-713b-4a22-8d60-e947da7a04d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245861664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.3245861664
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.1922031486
Short name T361
Test name
Test status
Simulation time 1311781074 ps
CPU time 8.29 seconds
Started Jul 13 06:59:12 PM PDT 24
Finished Jul 13 06:59:23 PM PDT 24
Peak memory 220228 kb
Host smart-d231498d-454a-4381-89d0-2c4c7cc41f79
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1922031486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.1922031486
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.1976921383
Short name T81
Test name
Test status
Simulation time 1212455040 ps
CPU time 1.15 seconds
Started Jul 13 06:59:13 PM PDT 24
Finished Jul 13 06:59:16 PM PDT 24
Peak memory 237104 kb
Host smart-c98db31d-6cf9-4934-a904-ebd8654aa201
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976921383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.1976921383
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.3449431054
Short name T61
Test name
Test status
Simulation time 293147294495 ps
CPU time 697.01 seconds
Started Jul 13 06:59:10 PM PDT 24
Finished Jul 13 07:10:49 PM PDT 24
Peak memory 265068 kb
Host smart-6c33c810-1bb3-43f5-bc0d-f2cda12e31a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449431054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.3449431054
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.2213945788
Short name T312
Test name
Test status
Simulation time 4715657869 ps
CPU time 14.02 seconds
Started Jul 13 06:59:08 PM PDT 24
Finished Jul 13 06:59:23 PM PDT 24
Peak memory 219808 kb
Host smart-fd7c1c1a-a110-40a7-ae46-20d96b386171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213945788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.2213945788
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.2933750025
Short name T462
Test name
Test status
Simulation time 1085258560 ps
CPU time 7.65 seconds
Started Jul 13 06:59:08 PM PDT 24
Finished Jul 13 06:59:16 PM PDT 24
Peak memory 216124 kb
Host smart-48782d91-290a-49df-b4f9-f7a5777d584d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933750025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.2933750025
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.2264661437
Short name T336
Test name
Test status
Simulation time 415523998 ps
CPU time 2.22 seconds
Started Jul 13 06:59:10 PM PDT 24
Finished Jul 13 06:59:15 PM PDT 24
Peak memory 216056 kb
Host smart-cf90ab96-ebad-4762-900d-0a1c322472d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264661437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.2264661437
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.2279256928
Short name T654
Test name
Test status
Simulation time 213824963 ps
CPU time 0.94 seconds
Started Jul 13 06:59:14 PM PDT 24
Finished Jul 13 06:59:17 PM PDT 24
Peak memory 206964 kb
Host smart-56d93296-0393-4056-9752-267acb051273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279256928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.2279256928
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.3466154952
Short name T624
Test name
Test status
Simulation time 3266474258 ps
CPU time 10.61 seconds
Started Jul 13 06:59:14 PM PDT 24
Finished Jul 13 06:59:26 PM PDT 24
Peak memory 240808 kb
Host smart-44c1850d-0833-45a9-aa2c-247d87465d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466154952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.3466154952
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.2951505622
Short name T433
Test name
Test status
Simulation time 20611851 ps
CPU time 0.74 seconds
Started Jul 13 07:01:18 PM PDT 24
Finished Jul 13 07:01:20 PM PDT 24
Peak memory 204932 kb
Host smart-4b97765c-3439-4e9d-8f1d-beb759678740
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951505622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
2951505622
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.1793556548
Short name T778
Test name
Test status
Simulation time 29448284 ps
CPU time 2.07 seconds
Started Jul 13 07:01:00 PM PDT 24
Finished Jul 13 07:01:06 PM PDT 24
Peak memory 223036 kb
Host smart-9b2d7826-41ac-4ada-89f3-55b996ea87b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793556548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.1793556548
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.10068988
Short name T464
Test name
Test status
Simulation time 55439828 ps
CPU time 0.81 seconds
Started Jul 13 07:00:58 PM PDT 24
Finished Jul 13 07:01:01 PM PDT 24
Peak memory 206596 kb
Host smart-60f88915-1256-4f6f-929b-9a202cdb7dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10068988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.10068988
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.913810722
Short name T695
Test name
Test status
Simulation time 3790522262 ps
CPU time 30.42 seconds
Started Jul 13 07:01:04 PM PDT 24
Finished Jul 13 07:01:36 PM PDT 24
Peak memory 240996 kb
Host smart-0b53bf9a-ca54-4311-90a0-c7158b55915e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913810722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.913810722
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.3472956502
Short name T254
Test name
Test status
Simulation time 21704613944 ps
CPU time 102.27 seconds
Started Jul 13 07:01:00 PM PDT 24
Finished Jul 13 07:02:46 PM PDT 24
Peak memory 265672 kb
Host smart-25f04ce3-e469-496d-82a1-521cd8891d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472956502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.3472956502
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.2501012424
Short name T968
Test name
Test status
Simulation time 803382331 ps
CPU time 13.88 seconds
Started Jul 13 07:01:07 PM PDT 24
Finished Jul 13 07:01:21 PM PDT 24
Peak memory 240920 kb
Host smart-0ef5f6dc-a93c-4014-b2ce-da471863a1f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501012424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.2501012424
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.1779984297
Short name T554
Test name
Test status
Simulation time 43786930364 ps
CPU time 74.62 seconds
Started Jul 13 07:01:12 PM PDT 24
Finished Jul 13 07:02:26 PM PDT 24
Peak memory 241032 kb
Host smart-d6960811-0732-42a3-97fb-a23ca4d24f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779984297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmd
s.1779984297
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.2725389152
Short name T891
Test name
Test status
Simulation time 6801927947 ps
CPU time 8.21 seconds
Started Jul 13 07:01:00 PM PDT 24
Finished Jul 13 07:01:12 PM PDT 24
Peak memory 232776 kb
Host smart-ad64093a-ecc4-4c36-b31c-a0bdfdcaae00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725389152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.2725389152
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.1619599557
Short name T228
Test name
Test status
Simulation time 17687445978 ps
CPU time 43.34 seconds
Started Jul 13 07:01:04 PM PDT 24
Finished Jul 13 07:01:49 PM PDT 24
Peak memory 232580 kb
Host smart-017fc696-61dd-4d4f-8ad7-24cdfc1138fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619599557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.1619599557
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.2792573450
Short name T866
Test name
Test status
Simulation time 31299851 ps
CPU time 2.1 seconds
Started Jul 13 07:00:59 PM PDT 24
Finished Jul 13 07:01:05 PM PDT 24
Peak memory 223708 kb
Host smart-74dbf73e-a96e-4a92-ad31-d36c2dbe47b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792573450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.2792573450
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.463004444
Short name T232
Test name
Test status
Simulation time 578137182 ps
CPU time 4.84 seconds
Started Jul 13 07:01:01 PM PDT 24
Finished Jul 13 07:01:09 PM PDT 24
Peak memory 224468 kb
Host smart-55919d65-969a-47c8-8e13-a1ecb445bff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463004444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.463004444
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.1685868960
Short name T952
Test name
Test status
Simulation time 7804545761 ps
CPU time 21.44 seconds
Started Jul 13 07:01:02 PM PDT 24
Finished Jul 13 07:01:27 PM PDT 24
Peak memory 219388 kb
Host smart-40b2ff17-86d2-4374-a64b-ab9a571ffb62
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1685868960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.1685868960
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.3928805113
Short name T798
Test name
Test status
Simulation time 248616823 ps
CPU time 0.93 seconds
Started Jul 13 07:01:19 PM PDT 24
Finished Jul 13 07:01:21 PM PDT 24
Peak memory 207588 kb
Host smart-192e5400-d070-4f63-a862-b3a163614125
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928805113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.3928805113
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.3079141193
Short name T871
Test name
Test status
Simulation time 6318017821 ps
CPU time 19.94 seconds
Started Jul 13 07:01:00 PM PDT 24
Finished Jul 13 07:01:24 PM PDT 24
Peak memory 216372 kb
Host smart-2dac4a30-2158-42d7-afab-cfd57fb0cd72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079141193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.3079141193
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.1560859234
Short name T382
Test name
Test status
Simulation time 10786092 ps
CPU time 0.69 seconds
Started Jul 13 07:01:01 PM PDT 24
Finished Jul 13 07:01:05 PM PDT 24
Peak memory 205700 kb
Host smart-2846b2f2-31fd-4522-a7f0-456d5aea84e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560859234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.1560859234
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.3013308571
Short name T492
Test name
Test status
Simulation time 266903449 ps
CPU time 1.47 seconds
Started Jul 13 07:00:57 PM PDT 24
Finished Jul 13 07:01:01 PM PDT 24
Peak memory 216216 kb
Host smart-e51941af-806f-4e11-ba9b-01e825f01db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013308571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.3013308571
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.3188119558
Short name T92
Test name
Test status
Simulation time 19642441 ps
CPU time 0.69 seconds
Started Jul 13 07:01:07 PM PDT 24
Finished Jul 13 07:01:08 PM PDT 24
Peak memory 205672 kb
Host smart-795c9147-4f59-4602-8d32-3d782e7d00f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188119558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.3188119558
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.3933297909
Short name T825
Test name
Test status
Simulation time 1917718102 ps
CPU time 6.18 seconds
Started Jul 13 07:01:02 PM PDT 24
Finished Jul 13 07:01:11 PM PDT 24
Peak memory 224356 kb
Host smart-4ab3113c-34b7-417e-bb47-eb3d4eae13c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933297909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.3933297909
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.2114467247
Short name T755
Test name
Test status
Simulation time 159736099 ps
CPU time 0.74 seconds
Started Jul 13 07:01:06 PM PDT 24
Finished Jul 13 07:01:08 PM PDT 24
Peak memory 205860 kb
Host smart-84e704d2-8bbf-422f-a947-b9eb8c059b25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114467247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
2114467247
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.1601830988
Short name T832
Test name
Test status
Simulation time 1906566365 ps
CPU time 4.48 seconds
Started Jul 13 07:01:09 PM PDT 24
Finished Jul 13 07:01:14 PM PDT 24
Peak memory 232652 kb
Host smart-9f539bd1-30b2-4b1e-89c0-84880ff12106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601830988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.1601830988
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.1263021601
Short name T340
Test name
Test status
Simulation time 41160379 ps
CPU time 0.8 seconds
Started Jul 13 07:01:11 PM PDT 24
Finished Jul 13 07:01:12 PM PDT 24
Peak memory 206616 kb
Host smart-62ee2ed3-be8a-49c1-bedf-ae36163201cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263021601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.1263021601
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.3498418480
Short name T500
Test name
Test status
Simulation time 1603688190 ps
CPU time 38.47 seconds
Started Jul 13 07:01:12 PM PDT 24
Finished Jul 13 07:01:51 PM PDT 24
Peak memory 253660 kb
Host smart-4fef8541-4d1b-4852-a90e-1eb7a98f4cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498418480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.3498418480
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.2581920007
Short name T41
Test name
Test status
Simulation time 7614590331 ps
CPU time 42.51 seconds
Started Jul 13 07:01:07 PM PDT 24
Finished Jul 13 07:01:51 PM PDT 24
Peak memory 244108 kb
Host smart-3b30679a-0b6f-4f0d-a253-832dcc3180db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581920007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.2581920007
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.3593165516
Short name T60
Test name
Test status
Simulation time 119005435829 ps
CPU time 312.37 seconds
Started Jul 13 07:01:13 PM PDT 24
Finished Jul 13 07:06:26 PM PDT 24
Peak memory 249252 kb
Host smart-de7443be-57f1-4954-be3b-63326260716a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593165516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.3593165516
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.1541736844
Short name T304
Test name
Test status
Simulation time 1259851264 ps
CPU time 8.52 seconds
Started Jul 13 07:01:08 PM PDT 24
Finished Jul 13 07:01:17 PM PDT 24
Peak memory 235816 kb
Host smart-c46de5be-bb7d-4f64-a70c-b1bf5d5ab0e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541736844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.1541736844
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.2357673094
Short name T1009
Test name
Test status
Simulation time 96933521725 ps
CPU time 198.29 seconds
Started Jul 13 07:01:23 PM PDT 24
Finished Jul 13 07:04:42 PM PDT 24
Peak memory 249200 kb
Host smart-254f2e2f-7ee1-4413-b514-e4562194f09f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357673094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmd
s.2357673094
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.1136987361
Short name T240
Test name
Test status
Simulation time 2717485927 ps
CPU time 18.56 seconds
Started Jul 13 07:01:09 PM PDT 24
Finished Jul 13 07:01:27 PM PDT 24
Peak memory 224564 kb
Host smart-c24cdba9-9d4e-40f2-a5ba-dcf1dc5d4836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136987361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.1136987361
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.3531671793
Short name T318
Test name
Test status
Simulation time 654728229 ps
CPU time 9.64 seconds
Started Jul 13 07:01:17 PM PDT 24
Finished Jul 13 07:01:28 PM PDT 24
Peak memory 240680 kb
Host smart-c498b335-4cfa-498e-bd73-4f5642d5b73c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531671793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.3531671793
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.718568924
Short name T908
Test name
Test status
Simulation time 26344033854 ps
CPU time 36.36 seconds
Started Jul 13 07:01:20 PM PDT 24
Finished Jul 13 07:01:57 PM PDT 24
Peak memory 240948 kb
Host smart-d4cc2508-9521-46c0-9c08-51668250e71c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718568924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swap
.718568924
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.1449523242
Short name T360
Test name
Test status
Simulation time 421387379 ps
CPU time 2.7 seconds
Started Jul 13 07:01:09 PM PDT 24
Finished Jul 13 07:01:13 PM PDT 24
Peak memory 224480 kb
Host smart-c2be8661-5ca3-4ef6-a751-d47ddeeb23d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449523242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.1449523242
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.2791079086
Short name T1
Test name
Test status
Simulation time 337934137 ps
CPU time 6.06 seconds
Started Jul 13 07:01:17 PM PDT 24
Finished Jul 13 07:01:24 PM PDT 24
Peak memory 221944 kb
Host smart-599585b4-1779-4779-b293-f049ee500090
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2791079086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.2791079086
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.66663501
Short name T442
Test name
Test status
Simulation time 9951501635 ps
CPU time 55 seconds
Started Jul 13 07:01:11 PM PDT 24
Finished Jul 13 07:02:06 PM PDT 24
Peak memory 249288 kb
Host smart-91227001-a510-4e3d-a6d6-a368d6002a92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66663501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stress
_all.66663501
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.437701177
Short name T376
Test name
Test status
Simulation time 23840307767 ps
CPU time 22.13 seconds
Started Jul 13 07:01:08 PM PDT 24
Finished Jul 13 07:01:30 PM PDT 24
Peak memory 216372 kb
Host smart-a1ac8b15-ee03-4afc-8ab3-0320d3244c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437701177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.437701177
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.3405661301
Short name T889
Test name
Test status
Simulation time 40674423 ps
CPU time 0.71 seconds
Started Jul 13 07:01:17 PM PDT 24
Finished Jul 13 07:01:18 PM PDT 24
Peak memory 205696 kb
Host smart-16c1323a-2dfd-4817-87ea-e1106e9ad884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405661301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.3405661301
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.2633713154
Short name T753
Test name
Test status
Simulation time 489844740 ps
CPU time 6.18 seconds
Started Jul 13 07:01:21 PM PDT 24
Finished Jul 13 07:01:28 PM PDT 24
Peak memory 216268 kb
Host smart-da90fe40-4de6-4d58-a8a9-a12da7f64f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633713154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.2633713154
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.3519766973
Short name T807
Test name
Test status
Simulation time 22864649 ps
CPU time 0.78 seconds
Started Jul 13 07:01:11 PM PDT 24
Finished Jul 13 07:01:12 PM PDT 24
Peak memory 205984 kb
Host smart-18b4ac93-5b8b-4856-ba75-f09c08830f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519766973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.3519766973
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.2532608720
Short name T6
Test name
Test status
Simulation time 1058105448 ps
CPU time 8 seconds
Started Jul 13 07:01:13 PM PDT 24
Finished Jul 13 07:01:22 PM PDT 24
Peak memory 232540 kb
Host smart-7d0bf4f3-eee9-4d0d-9304-ca57a65342c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532608720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.2532608720
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.1232796057
Short name T643
Test name
Test status
Simulation time 42531111 ps
CPU time 0.76 seconds
Started Jul 13 07:01:13 PM PDT 24
Finished Jul 13 07:01:14 PM PDT 24
Peak memory 204804 kb
Host smart-5790a930-9834-493b-bda8-c9867bb41b40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232796057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
1232796057
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.1648538778
Short name T479
Test name
Test status
Simulation time 283382218 ps
CPU time 4.31 seconds
Started Jul 13 07:01:11 PM PDT 24
Finished Jul 13 07:01:16 PM PDT 24
Peak memory 224512 kb
Host smart-e92c9b39-b866-40fe-9d35-fffb15d8eb86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648538778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.1648538778
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.337510656
Short name T942
Test name
Test status
Simulation time 15476620 ps
CPU time 0.8 seconds
Started Jul 13 07:01:17 PM PDT 24
Finished Jul 13 07:01:19 PM PDT 24
Peak memory 206920 kb
Host smart-71a7dd81-3219-447d-9bc6-374dff67d858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337510656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.337510656
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.504840912
Short name T816
Test name
Test status
Simulation time 69896532614 ps
CPU time 123.47 seconds
Started Jul 13 07:01:14 PM PDT 24
Finished Jul 13 07:03:18 PM PDT 24
Peak memory 256008 kb
Host smart-3dce2a35-3a76-4507-95ea-8b8ba7497177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504840912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.504840912
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.1562197923
Short name T726
Test name
Test status
Simulation time 3067347787 ps
CPU time 69.77 seconds
Started Jul 13 07:01:10 PM PDT 24
Finished Jul 13 07:02:21 PM PDT 24
Peak memory 239316 kb
Host smart-309879ea-a5cf-44e0-a75d-7983911accd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562197923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.1562197923
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.1888373926
Short name T692
Test name
Test status
Simulation time 31616180607 ps
CPU time 173.85 seconds
Started Jul 13 07:01:15 PM PDT 24
Finished Jul 13 07:04:10 PM PDT 24
Peak memory 267184 kb
Host smart-e8da482a-05f0-4868-b6a2-d655894f687b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888373926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.1888373926
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.2434912256
Short name T549
Test name
Test status
Simulation time 380208850 ps
CPU time 4.31 seconds
Started Jul 13 07:01:14 PM PDT 24
Finished Jul 13 07:01:18 PM PDT 24
Peak memory 233736 kb
Host smart-72a97b51-38c7-46b7-a896-84d28bda111c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434912256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.2434912256
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.3627866422
Short name T262
Test name
Test status
Simulation time 57526210232 ps
CPU time 393.73 seconds
Started Jul 13 07:01:18 PM PDT 24
Finished Jul 13 07:07:53 PM PDT 24
Peak memory 267168 kb
Host smart-37fe5cc7-0033-423b-8580-5d1ba0c3e444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627866422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmd
s.3627866422
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.2629322842
Short name T917
Test name
Test status
Simulation time 485681968 ps
CPU time 5.29 seconds
Started Jul 13 07:01:10 PM PDT 24
Finished Jul 13 07:01:16 PM PDT 24
Peak memory 232636 kb
Host smart-3de2ffac-c200-4e95-8786-b901329e9450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629322842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.2629322842
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.2621002047
Short name T728
Test name
Test status
Simulation time 27128201025 ps
CPU time 27.16 seconds
Started Jul 13 07:01:10 PM PDT 24
Finished Jul 13 07:01:38 PM PDT 24
Peak memory 240880 kb
Host smart-6489420c-3323-4633-abee-182746c88360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621002047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.2621002047
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.1211910675
Short name T531
Test name
Test status
Simulation time 9383721768 ps
CPU time 14.02 seconds
Started Jul 13 07:01:20 PM PDT 24
Finished Jul 13 07:01:34 PM PDT 24
Peak memory 232752 kb
Host smart-7d36af8b-c474-4856-a4d9-8eaf37d6197f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211910675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.1211910675
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.1259646928
Short name T705
Test name
Test status
Simulation time 4205486492 ps
CPU time 8.81 seconds
Started Jul 13 07:01:07 PM PDT 24
Finished Jul 13 07:01:17 PM PDT 24
Peak memory 251864 kb
Host smart-73914741-b8b7-4626-8bd2-6deaeb05f5b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259646928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.1259646928
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.1181161191
Short name T745
Test name
Test status
Simulation time 1275435554 ps
CPU time 10.69 seconds
Started Jul 13 07:01:10 PM PDT 24
Finished Jul 13 07:01:21 PM PDT 24
Peak memory 222636 kb
Host smart-a6569150-8d02-4639-9676-cc892075f8e9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1181161191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.1181161191
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.2782614314
Short name T163
Test name
Test status
Simulation time 94987337 ps
CPU time 0.93 seconds
Started Jul 13 07:01:09 PM PDT 24
Finished Jul 13 07:01:11 PM PDT 24
Peak memory 207596 kb
Host smart-d31301dc-ebc8-4ff9-91f8-a8aa968044b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782614314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.2782614314
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.808701386
Short name T667
Test name
Test status
Simulation time 99717483212 ps
CPU time 44.73 seconds
Started Jul 13 07:01:09 PM PDT 24
Finished Jul 13 07:01:55 PM PDT 24
Peak memory 216388 kb
Host smart-8d42545e-5a92-42e8-af47-120d37d8bde8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808701386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.808701386
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.3572639925
Short name T11
Test name
Test status
Simulation time 11395756959 ps
CPU time 7.9 seconds
Started Jul 13 07:01:14 PM PDT 24
Finished Jul 13 07:01:23 PM PDT 24
Peak memory 216492 kb
Host smart-c8152f81-b466-4122-b545-1ff68c332979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572639925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.3572639925
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.3961123486
Short name T676
Test name
Test status
Simulation time 35537765 ps
CPU time 1.29 seconds
Started Jul 13 07:01:25 PM PDT 24
Finished Jul 13 07:01:27 PM PDT 24
Peak memory 216192 kb
Host smart-f5aa9871-f8f7-4f38-93c2-77beac804f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961123486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.3961123486
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.2539386942
Short name T597
Test name
Test status
Simulation time 46341443 ps
CPU time 0.68 seconds
Started Jul 13 07:01:09 PM PDT 24
Finished Jul 13 07:01:10 PM PDT 24
Peak memory 205664 kb
Host smart-1b69308e-47af-44e4-aedb-4e8683141343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539386942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.2539386942
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.530735421
Short name T415
Test name
Test status
Simulation time 115180207 ps
CPU time 3.15 seconds
Started Jul 13 07:01:21 PM PDT 24
Finished Jul 13 07:01:24 PM PDT 24
Peak memory 224512 kb
Host smart-bf9be56c-0065-487a-aadc-0ed42ce0f8a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530735421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.530735421
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.2658920304
Short name T958
Test name
Test status
Simulation time 34087718 ps
CPU time 0.72 seconds
Started Jul 13 07:01:25 PM PDT 24
Finished Jul 13 07:01:27 PM PDT 24
Peak memory 205528 kb
Host smart-edef5042-250e-4f87-9a60-e45889103196
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658920304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
2658920304
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.4029486922
Short name T809
Test name
Test status
Simulation time 583497921 ps
CPU time 4.84 seconds
Started Jul 13 07:01:18 PM PDT 24
Finished Jul 13 07:01:24 PM PDT 24
Peak memory 224444 kb
Host smart-a1b829d9-abde-4b90-b0b6-589b7149cdb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029486922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.4029486922
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.181202081
Short name T428
Test name
Test status
Simulation time 13149118 ps
CPU time 0.75 seconds
Started Jul 13 07:01:10 PM PDT 24
Finished Jul 13 07:01:11 PM PDT 24
Peak memory 205892 kb
Host smart-b6da6998-da18-471c-abb0-f95df3917de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181202081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.181202081
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.2039449268
Short name T372
Test name
Test status
Simulation time 2424798212 ps
CPU time 50.77 seconds
Started Jul 13 07:01:20 PM PDT 24
Finished Jul 13 07:02:11 PM PDT 24
Peak memory 257372 kb
Host smart-262e631a-8d9c-4705-81bc-997fefd7e60e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039449268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.2039449268
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.4110010201
Short name T637
Test name
Test status
Simulation time 3462619691 ps
CPU time 47.09 seconds
Started Jul 13 07:01:19 PM PDT 24
Finished Jul 13 07:02:07 PM PDT 24
Peak memory 239220 kb
Host smart-377f0be6-2790-4310-9719-13812bb209e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110010201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.4110010201
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.308576458
Short name T682
Test name
Test status
Simulation time 7517704144 ps
CPU time 26.65 seconds
Started Jul 13 07:01:20 PM PDT 24
Finished Jul 13 07:01:47 PM PDT 24
Peak memory 240972 kb
Host smart-1df63f5b-bcbc-4c80-bb58-a9b8fe82d936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308576458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.308576458
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.528124458
Short name T872
Test name
Test status
Simulation time 17702778229 ps
CPU time 39.32 seconds
Started Jul 13 07:01:30 PM PDT 24
Finished Jul 13 07:02:10 PM PDT 24
Peak memory 249220 kb
Host smart-ef29a8bb-3882-456a-91a3-ecc402d29869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528124458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmds
.528124458
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.743836128
Short name T472
Test name
Test status
Simulation time 7914187303 ps
CPU time 14.68 seconds
Started Jul 13 07:01:22 PM PDT 24
Finished Jul 13 07:01:37 PM PDT 24
Peak memory 232788 kb
Host smart-5dc480c4-ed64-4505-b0ca-73bb855d34be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743836128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.743836128
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.4260165032
Short name T785
Test name
Test status
Simulation time 568982737 ps
CPU time 7.1 seconds
Started Jul 13 07:01:30 PM PDT 24
Finished Jul 13 07:01:38 PM PDT 24
Peak memory 224432 kb
Host smart-87ca6b9b-8c28-4a6e-bd38-7f7040780ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260165032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.4260165032
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.2059259896
Short name T636
Test name
Test status
Simulation time 148843165 ps
CPU time 2.52 seconds
Started Jul 13 07:01:26 PM PDT 24
Finished Jul 13 07:01:29 PM PDT 24
Peak memory 232616 kb
Host smart-e8b3ad0a-f167-4f5c-8890-76d9f7fa3f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059259896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.2059259896
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.3035296705
Short name T641
Test name
Test status
Simulation time 6372306832 ps
CPU time 22.9 seconds
Started Jul 13 07:01:18 PM PDT 24
Finished Jul 13 07:01:42 PM PDT 24
Peak memory 224648 kb
Host smart-d658eaeb-ac61-4488-8f23-4d2bfc3d9f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035296705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.3035296705
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.484413527
Short name T28
Test name
Test status
Simulation time 689632002 ps
CPU time 3.88 seconds
Started Jul 13 07:01:17 PM PDT 24
Finished Jul 13 07:01:21 PM PDT 24
Peak memory 222604 kb
Host smart-be691615-3a9d-4f30-8dc5-8c46821a6b3b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=484413527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dire
ct.484413527
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.3229819628
Short name T59
Test name
Test status
Simulation time 156358794573 ps
CPU time 745.04 seconds
Started Jul 13 07:01:21 PM PDT 24
Finished Jul 13 07:13:47 PM PDT 24
Peak memory 268100 kb
Host smart-87ccb2a2-ac6e-4361-91cd-56ed4898a312
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229819628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.3229819628
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.1523212229
Short name T696
Test name
Test status
Simulation time 655080403 ps
CPU time 7.06 seconds
Started Jul 13 07:01:22 PM PDT 24
Finished Jul 13 07:01:30 PM PDT 24
Peak memory 216376 kb
Host smart-23e6fc47-549b-4a37-a276-041d56ae32fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523212229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.1523212229
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.2322925523
Short name T847
Test name
Test status
Simulation time 127869009034 ps
CPU time 19.48 seconds
Started Jul 13 07:01:15 PM PDT 24
Finished Jul 13 07:01:35 PM PDT 24
Peak memory 216268 kb
Host smart-63200a40-5ee8-476d-bd36-4bd9d55eb19d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322925523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.2322925523
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.420168016
Short name T434
Test name
Test status
Simulation time 21149082 ps
CPU time 0.9 seconds
Started Jul 13 07:01:23 PM PDT 24
Finished Jul 13 07:01:24 PM PDT 24
Peak memory 206608 kb
Host smart-7881c5d7-be48-47d5-a368-adb9ea8b80d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420168016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.420168016
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.4041465497
Short name T446
Test name
Test status
Simulation time 85961569 ps
CPU time 0.93 seconds
Started Jul 13 07:01:17 PM PDT 24
Finished Jul 13 07:01:19 PM PDT 24
Peak memory 206048 kb
Host smart-7c031ea6-3366-485b-810d-6414579a16d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041465497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.4041465497
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.2473505901
Short name T544
Test name
Test status
Simulation time 730488194 ps
CPU time 5.6 seconds
Started Jul 13 07:01:27 PM PDT 24
Finished Jul 13 07:01:33 PM PDT 24
Peak memory 224588 kb
Host smart-603e7e2f-a26a-4939-ad10-3fd8288d30be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473505901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.2473505901
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.2736498720
Short name T612
Test name
Test status
Simulation time 23866075 ps
CPU time 0.72 seconds
Started Jul 13 07:01:25 PM PDT 24
Finished Jul 13 07:01:27 PM PDT 24
Peak memory 204928 kb
Host smart-b0360442-2ac5-40a3-8584-3724ccd1b5b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736498720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
2736498720
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.401466148
Short name T921
Test name
Test status
Simulation time 144455018 ps
CPU time 2.52 seconds
Started Jul 13 07:01:25 PM PDT 24
Finished Jul 13 07:01:29 PM PDT 24
Peak memory 232628 kb
Host smart-a4daf971-3f55-4e5b-9b85-34fc6d96648a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401466148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.401466148
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.997676170
Short name T720
Test name
Test status
Simulation time 31226478 ps
CPU time 0.79 seconds
Started Jul 13 07:01:18 PM PDT 24
Finished Jul 13 07:01:19 PM PDT 24
Peak memory 205916 kb
Host smart-d3010a67-8a3b-40fd-9531-2aa217378884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997676170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.997676170
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.137893774
Short name T780
Test name
Test status
Simulation time 2712686280 ps
CPU time 59.2 seconds
Started Jul 13 07:01:25 PM PDT 24
Finished Jul 13 07:02:26 PM PDT 24
Peak memory 251444 kb
Host smart-9d61e880-32ea-43cf-b09a-e450a2deeff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137893774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.137893774
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.700649675
Short name T206
Test name
Test status
Simulation time 67014215070 ps
CPU time 156.42 seconds
Started Jul 13 07:01:22 PM PDT 24
Finished Jul 13 07:03:59 PM PDT 24
Peak memory 257440 kb
Host smart-605cfeaf-a2f1-4b7b-9db1-dd617a386d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700649675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.700649675
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.4123833999
Short name T196
Test name
Test status
Simulation time 32708389159 ps
CPU time 241.04 seconds
Started Jul 13 07:01:20 PM PDT 24
Finished Jul 13 07:05:22 PM PDT 24
Peak memory 256640 kb
Host smart-989764a6-e7d2-4d6c-82be-4278b0582cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123833999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.4123833999
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.188045561
Short name T914
Test name
Test status
Simulation time 9464255489 ps
CPU time 35.01 seconds
Started Jul 13 07:01:19 PM PDT 24
Finished Jul 13 07:01:55 PM PDT 24
Peak memory 238168 kb
Host smart-8d334e28-0328-41be-8dfb-ce5e66c2bb53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188045561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.188045561
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.1855763712
Short name T608
Test name
Test status
Simulation time 17071335396 ps
CPU time 45.08 seconds
Started Jul 13 07:01:18 PM PDT 24
Finished Jul 13 07:02:04 PM PDT 24
Peak memory 253708 kb
Host smart-e27c3c0d-f091-462e-bae4-4a7aad8b0a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855763712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmd
s.1855763712
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.2092222781
Short name T960
Test name
Test status
Simulation time 4670518943 ps
CPU time 9.47 seconds
Started Jul 13 07:01:25 PM PDT 24
Finished Jul 13 07:01:35 PM PDT 24
Peak memory 224580 kb
Host smart-95c10b58-3573-44ec-8a0d-85c1966f6afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092222781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.2092222781
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.1354210344
Short name T965
Test name
Test status
Simulation time 379289195 ps
CPU time 9.71 seconds
Started Jul 13 07:01:19 PM PDT 24
Finished Jul 13 07:01:29 PM PDT 24
Peak memory 232504 kb
Host smart-5679e3cd-f267-45c2-8e8f-989aee7b399c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354210344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.1354210344
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.3134496900
Short name T683
Test name
Test status
Simulation time 33126339 ps
CPU time 2.49 seconds
Started Jul 13 07:01:25 PM PDT 24
Finished Jul 13 07:01:28 PM PDT 24
Peak memory 232340 kb
Host smart-9ddb137c-107c-4754-be31-4be7b48e3edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134496900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.3134496900
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.1504252970
Short name T226
Test name
Test status
Simulation time 28480140123 ps
CPU time 41.94 seconds
Started Jul 13 07:01:25 PM PDT 24
Finished Jul 13 07:02:08 PM PDT 24
Peak memory 253736 kb
Host smart-1fc8af1b-14c9-4dcc-9533-25a39b00130e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504252970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.1504252970
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.2839089165
Short name T326
Test name
Test status
Simulation time 299604055 ps
CPU time 5.29 seconds
Started Jul 13 07:01:25 PM PDT 24
Finished Jul 13 07:01:32 PM PDT 24
Peak memory 218660 kb
Host smart-09ea37d2-c9da-4fd4-ab55-a19c8ac183b5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2839089165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.2839089165
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.1900126656
Short name T279
Test name
Test status
Simulation time 21339781412 ps
CPU time 151.84 seconds
Started Jul 13 07:01:19 PM PDT 24
Finished Jul 13 07:03:52 PM PDT 24
Peak memory 256820 kb
Host smart-f1443e45-1513-4f4d-82dc-9555b87872c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900126656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.1900126656
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.3133798227
Short name T916
Test name
Test status
Simulation time 213345127 ps
CPU time 3.92 seconds
Started Jul 13 07:01:19 PM PDT 24
Finished Jul 13 07:01:24 PM PDT 24
Peak memory 216200 kb
Host smart-d4a131f1-c92b-400b-ac27-cd8f5a1d412c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133798227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.3133798227
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.3373144168
Short name T767
Test name
Test status
Simulation time 3593254639 ps
CPU time 13.46 seconds
Started Jul 13 07:01:22 PM PDT 24
Finished Jul 13 07:01:36 PM PDT 24
Peak memory 216292 kb
Host smart-83e13496-b052-4460-8020-d95df0ac7a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373144168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.3373144168
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.2448429272
Short name T992
Test name
Test status
Simulation time 73630136 ps
CPU time 0.95 seconds
Started Jul 13 07:01:22 PM PDT 24
Finished Jul 13 07:01:23 PM PDT 24
Peak memory 207160 kb
Host smart-0681bf3b-93cd-42d6-b0d6-5580c2aafcb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448429272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.2448429272
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.1256245821
Short name T346
Test name
Test status
Simulation time 84772597 ps
CPU time 0.78 seconds
Started Jul 13 07:01:16 PM PDT 24
Finished Jul 13 07:01:18 PM PDT 24
Peak memory 206024 kb
Host smart-93da74c4-3ae2-43a2-83e6-2f2c397f7d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256245821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.1256245821
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.906791616
Short name T469
Test name
Test status
Simulation time 388957726 ps
CPU time 3.66 seconds
Started Jul 13 07:01:20 PM PDT 24
Finished Jul 13 07:01:25 PM PDT 24
Peak memory 232712 kb
Host smart-b8bf28eb-9e1a-4a5e-8a00-b9cb92701f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906791616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.906791616
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.70533566
Short name T335
Test name
Test status
Simulation time 12460557 ps
CPU time 0.78 seconds
Started Jul 13 07:01:37 PM PDT 24
Finished Jul 13 07:01:39 PM PDT 24
Peak memory 204976 kb
Host smart-c13a68e8-ba93-4623-a1f4-8e98f9607a08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70533566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.70533566
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.1526932099
Short name T716
Test name
Test status
Simulation time 33358899 ps
CPU time 2.5 seconds
Started Jul 13 07:01:24 PM PDT 24
Finished Jul 13 07:01:28 PM PDT 24
Peak memory 232364 kb
Host smart-67c31a00-bb1c-4656-a4b6-bf1667f817ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526932099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.1526932099
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.1917689947
Short name T911
Test name
Test status
Simulation time 53479399 ps
CPU time 0.73 seconds
Started Jul 13 07:01:18 PM PDT 24
Finished Jul 13 07:01:19 PM PDT 24
Peak memory 205920 kb
Host smart-d87a92ad-aa12-49b3-aea0-ca9e61718b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917689947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.1917689947
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.3063548213
Short name T590
Test name
Test status
Simulation time 2130598153 ps
CPU time 8.35 seconds
Started Jul 13 07:01:25 PM PDT 24
Finished Jul 13 07:01:35 PM PDT 24
Peak memory 224504 kb
Host smart-2a2804a5-33e8-47b7-ac81-d76e17a269b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063548213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.3063548213
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.1614812695
Short name T714
Test name
Test status
Simulation time 11553513518 ps
CPU time 104.16 seconds
Started Jul 13 07:01:31 PM PDT 24
Finished Jul 13 07:03:16 PM PDT 24
Peak memory 249616 kb
Host smart-50f81064-f5a4-4aba-9f9b-b7b8a9dd0056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614812695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.1614812695
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.3643679554
Short name T817
Test name
Test status
Simulation time 101550635074 ps
CPU time 213.36 seconds
Started Jul 13 07:01:29 PM PDT 24
Finished Jul 13 07:05:03 PM PDT 24
Peak memory 253868 kb
Host smart-f084bd43-3f57-49e6-b09c-ea44a9249058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643679554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.3643679554
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.3277326884
Short name T592
Test name
Test status
Simulation time 7886040272 ps
CPU time 24.22 seconds
Started Jul 13 07:01:25 PM PDT 24
Finished Jul 13 07:01:50 PM PDT 24
Peak memory 249220 kb
Host smart-e61e3bde-47b8-42d5-9689-7973d71a7119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277326884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.3277326884
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.1305550663
Short name T180
Test name
Test status
Simulation time 96845284687 ps
CPU time 73.72 seconds
Started Jul 13 07:01:25 PM PDT 24
Finished Jul 13 07:02:40 PM PDT 24
Peak memory 255280 kb
Host smart-c897b636-f993-4f13-870c-cf3a40f3fe5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305550663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmd
s.1305550663
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.1743008830
Short name T24
Test name
Test status
Simulation time 1790810846 ps
CPU time 6.37 seconds
Started Jul 13 07:01:19 PM PDT 24
Finished Jul 13 07:01:26 PM PDT 24
Peak memory 224464 kb
Host smart-d159c66e-c46d-4852-bcd6-de7bc549b67a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743008830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.1743008830
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.2926546480
Short name T618
Test name
Test status
Simulation time 59559504 ps
CPU time 2.6 seconds
Started Jul 13 07:01:27 PM PDT 24
Finished Jul 13 07:01:30 PM PDT 24
Peak memory 232292 kb
Host smart-345b638d-fd5c-46fc-9f1f-23159a1e08de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926546480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.2926546480
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.1764761901
Short name T527
Test name
Test status
Simulation time 3114314696 ps
CPU time 12.36 seconds
Started Jul 13 07:01:20 PM PDT 24
Finished Jul 13 07:01:33 PM PDT 24
Peak memory 232704 kb
Host smart-af341ede-6b89-4422-8316-04547611a99f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764761901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.1764761901
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.1985233127
Short name T987
Test name
Test status
Simulation time 8514758850 ps
CPU time 13.73 seconds
Started Jul 13 07:01:18 PM PDT 24
Finished Jul 13 07:01:32 PM PDT 24
Peak memory 224584 kb
Host smart-61f287ee-a13d-4be7-a132-000a715bd298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985233127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.1985233127
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.3729699405
Short name T986
Test name
Test status
Simulation time 2669484000 ps
CPU time 8.57 seconds
Started Jul 13 07:01:25 PM PDT 24
Finished Jul 13 07:01:35 PM PDT 24
Peak memory 221916 kb
Host smart-232f6496-0397-4c52-af9d-9ab02080ec1b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3729699405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.3729699405
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.1615827634
Short name T588
Test name
Test status
Simulation time 57513658 ps
CPU time 1.09 seconds
Started Jul 13 07:01:29 PM PDT 24
Finished Jul 13 07:01:31 PM PDT 24
Peak memory 206720 kb
Host smart-62895147-6de7-4366-a729-2e74850f1738
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615827634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.1615827634
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.2725493586
Short name T317
Test name
Test status
Simulation time 8947016197 ps
CPU time 15.55 seconds
Started Jul 13 07:01:23 PM PDT 24
Finished Jul 13 07:01:39 PM PDT 24
Peak memory 216416 kb
Host smart-eb73cfba-b554-4bf0-920b-187c37a3e112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725493586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.2725493586
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.2814844964
Short name T440
Test name
Test status
Simulation time 4519613331 ps
CPU time 5.34 seconds
Started Jul 13 07:01:26 PM PDT 24
Finished Jul 13 07:01:32 PM PDT 24
Peak memory 216380 kb
Host smart-4aad9deb-c6df-4e12-99bf-c4796da88f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814844964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.2814844964
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.2322994933
Short name T943
Test name
Test status
Simulation time 196986051 ps
CPU time 5.02 seconds
Started Jul 13 07:01:27 PM PDT 24
Finished Jul 13 07:01:33 PM PDT 24
Peak memory 216196 kb
Host smart-5b27ada7-e8a0-4b7f-a937-c48581b08e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322994933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.2322994933
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.3871171793
Short name T735
Test name
Test status
Simulation time 50800797 ps
CPU time 0.93 seconds
Started Jul 13 07:01:28 PM PDT 24
Finished Jul 13 07:01:29 PM PDT 24
Peak memory 207020 kb
Host smart-df425e0a-d584-4f0e-8f91-6943f4443ba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871171793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.3871171793
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.2596652973
Short name T789
Test name
Test status
Simulation time 2093835733 ps
CPU time 9.09 seconds
Started Jul 13 07:01:25 PM PDT 24
Finished Jul 13 07:01:36 PM PDT 24
Peak memory 224448 kb
Host smart-624eed7f-aba2-4c7a-84ce-4b0c5bf860db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596652973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.2596652973
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.1108558099
Short name T364
Test name
Test status
Simulation time 37315220 ps
CPU time 0.71 seconds
Started Jul 13 07:01:30 PM PDT 24
Finished Jul 13 07:01:32 PM PDT 24
Peak memory 205360 kb
Host smart-88bb7f31-3e75-4565-a368-ab377b82c048
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108558099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
1108558099
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.2026712662
Short name T754
Test name
Test status
Simulation time 4248664021 ps
CPU time 4.45 seconds
Started Jul 13 07:01:35 PM PDT 24
Finished Jul 13 07:01:40 PM PDT 24
Peak memory 232836 kb
Host smart-1ac9f880-4953-4d9d-b004-b6226780ff31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026712662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.2026712662
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.1178356078
Short name T686
Test name
Test status
Simulation time 64538412 ps
CPU time 0.77 seconds
Started Jul 13 07:01:30 PM PDT 24
Finished Jul 13 07:01:31 PM PDT 24
Peak memory 206596 kb
Host smart-24bb03f8-9ef5-47ee-a8c5-53bf1fda56b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178356078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.1178356078
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.1891288911
Short name T656
Test name
Test status
Simulation time 61544903864 ps
CPU time 85.04 seconds
Started Jul 13 07:01:31 PM PDT 24
Finished Jul 13 07:02:57 PM PDT 24
Peak memory 251288 kb
Host smart-e969a671-c048-491b-916f-3d912d722cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891288911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.1891288911
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.566859520
Short name T964
Test name
Test status
Simulation time 13495670759 ps
CPU time 103.45 seconds
Started Jul 13 07:01:29 PM PDT 24
Finished Jul 13 07:03:13 PM PDT 24
Peak memory 257052 kb
Host smart-bd1bcb82-8547-4ad0-b1bc-34b56c594b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566859520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.566859520
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.1539770469
Short name T664
Test name
Test status
Simulation time 11035228994 ps
CPU time 37.74 seconds
Started Jul 13 07:01:40 PM PDT 24
Finished Jul 13 07:02:21 PM PDT 24
Peak memory 249108 kb
Host smart-eb6b5e8b-d078-4750-916e-0a433de4a776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539770469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.1539770469
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.3071026668
Short name T296
Test name
Test status
Simulation time 5480386171 ps
CPU time 23.36 seconds
Started Jul 13 07:01:37 PM PDT 24
Finished Jul 13 07:02:01 PM PDT 24
Peak memory 238884 kb
Host smart-d85f3910-6bdb-4c77-ab14-abaa185f216d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071026668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.3071026668
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.3804165339
Short name T777
Test name
Test status
Simulation time 3706037608 ps
CPU time 46.57 seconds
Started Jul 13 07:01:30 PM PDT 24
Finished Jul 13 07:02:17 PM PDT 24
Peak memory 249392 kb
Host smart-856c8f7d-411c-45e2-a59c-cb0a72c0fcde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804165339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmd
s.3804165339
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.2860534760
Short name T460
Test name
Test status
Simulation time 1037148661 ps
CPU time 6.51 seconds
Started Jul 13 07:01:27 PM PDT 24
Finished Jul 13 07:01:34 PM PDT 24
Peak memory 224472 kb
Host smart-c40e4dd8-7c40-4572-ad54-537cf1ae0894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860534760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.2860534760
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.433777154
Short name T860
Test name
Test status
Simulation time 6947247026 ps
CPU time 45.27 seconds
Started Jul 13 07:01:36 PM PDT 24
Finished Jul 13 07:02:22 PM PDT 24
Peak memory 231440 kb
Host smart-ec085d48-7743-419e-96d9-8d699c9709a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433777154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.433777154
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.1252491653
Short name T583
Test name
Test status
Simulation time 100515894 ps
CPU time 2.83 seconds
Started Jul 13 07:01:33 PM PDT 24
Finished Jul 13 07:01:36 PM PDT 24
Peak memory 224420 kb
Host smart-9e5e4771-553e-49d2-8dcd-60ebba417906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252491653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.1252491653
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.2735447713
Short name T403
Test name
Test status
Simulation time 13785224519 ps
CPU time 14.65 seconds
Started Jul 13 07:01:29 PM PDT 24
Finished Jul 13 07:01:44 PM PDT 24
Peak memory 235564 kb
Host smart-b1e54a3b-05f5-4d38-9470-8b47a7738125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735447713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.2735447713
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.2547420337
Short name T353
Test name
Test status
Simulation time 271366586 ps
CPU time 3.81 seconds
Started Jul 13 07:01:30 PM PDT 24
Finished Jul 13 07:01:34 PM PDT 24
Peak memory 223064 kb
Host smart-5fe14556-aaf4-4f0e-b30e-428be39f7945
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2547420337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.2547420337
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.445585655
Short name T850
Test name
Test status
Simulation time 32743212125 ps
CPU time 290.32 seconds
Started Jul 13 07:01:34 PM PDT 24
Finished Jul 13 07:06:25 PM PDT 24
Peak memory 250276 kb
Host smart-47236dbe-2ed2-4aaf-8606-861a40010005
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445585655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stres
s_all.445585655
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.2102121553
Short name T576
Test name
Test status
Simulation time 19162062182 ps
CPU time 34.81 seconds
Started Jul 13 07:01:34 PM PDT 24
Finished Jul 13 07:02:10 PM PDT 24
Peak memory 216384 kb
Host smart-ff62e0cb-126f-4cea-8296-38b22a114b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102121553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.2102121553
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.2952466141
Short name T420
Test name
Test status
Simulation time 2325357814 ps
CPU time 4.06 seconds
Started Jul 13 07:01:31 PM PDT 24
Finished Jul 13 07:01:36 PM PDT 24
Peak memory 216304 kb
Host smart-49243279-5850-4636-9998-0880a6b1730b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952466141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.2952466141
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.3918579858
Short name T8
Test name
Test status
Simulation time 155606278 ps
CPU time 2.56 seconds
Started Jul 13 07:01:36 PM PDT 24
Finished Jul 13 07:01:39 PM PDT 24
Peak memory 215076 kb
Host smart-ccf14b52-4124-4a69-867e-17f4386d5ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918579858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.3918579858
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.738746536
Short name T606
Test name
Test status
Simulation time 114837944 ps
CPU time 0.89 seconds
Started Jul 13 07:01:29 PM PDT 24
Finished Jul 13 07:01:31 PM PDT 24
Peak memory 206000 kb
Host smart-a8c797d4-9998-4535-b977-a893d669a181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738746536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.738746536
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.2895511342
Short name T882
Test name
Test status
Simulation time 79671493 ps
CPU time 2.94 seconds
Started Jul 13 07:01:32 PM PDT 24
Finished Jul 13 07:01:35 PM PDT 24
Peak memory 228188 kb
Host smart-83bc8388-f010-4284-bf1e-8622ba85a7dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895511342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.2895511342
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.799852350
Short name T501
Test name
Test status
Simulation time 35933271 ps
CPU time 0.72 seconds
Started Jul 13 07:01:29 PM PDT 24
Finished Jul 13 07:01:31 PM PDT 24
Peak memory 204980 kb
Host smart-1b4f5fbe-ab28-43ed-9aae-3b186b94b108
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799852350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.799852350
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.1424011927
Short name T700
Test name
Test status
Simulation time 139771825 ps
CPU time 3.78 seconds
Started Jul 13 07:01:33 PM PDT 24
Finished Jul 13 07:01:38 PM PDT 24
Peak memory 224448 kb
Host smart-98086894-3c6e-46d0-8bc5-4aa6a3f1643b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424011927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.1424011927
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.513955167
Short name T685
Test name
Test status
Simulation time 17300208 ps
CPU time 0.79 seconds
Started Jul 13 07:01:34 PM PDT 24
Finished Jul 13 07:01:36 PM PDT 24
Peak memory 205600 kb
Host smart-9f6e2b6e-5a33-4c63-b908-225a7594caf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513955167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.513955167
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.215737827
Short name T519
Test name
Test status
Simulation time 36695159125 ps
CPU time 267.25 seconds
Started Jul 13 07:01:27 PM PDT 24
Finished Jul 13 07:05:54 PM PDT 24
Peak memory 265624 kb
Host smart-a91f6400-c940-4658-872b-d3f8d85f34d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215737827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.215737827
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.874646892
Short name T493
Test name
Test status
Simulation time 3268077101 ps
CPU time 28.96 seconds
Started Jul 13 07:01:27 PM PDT 24
Finished Jul 13 07:01:57 PM PDT 24
Peak memory 238764 kb
Host smart-5d263e40-3727-4720-8c2a-56670f74a044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874646892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.874646892
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.4117667834
Short name T971
Test name
Test status
Simulation time 2449255168 ps
CPU time 24.1 seconds
Started Jul 13 07:01:34 PM PDT 24
Finished Jul 13 07:01:59 PM PDT 24
Peak memory 241068 kb
Host smart-81d930e2-2cc9-477b-bc6a-dfc3fe23d82a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117667834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.4117667834
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.1501740322
Short name T298
Test name
Test status
Simulation time 11305472030 ps
CPU time 36.16 seconds
Started Jul 13 07:01:36 PM PDT 24
Finished Jul 13 07:02:12 PM PDT 24
Peak memory 239692 kb
Host smart-0f5b6cc8-aa1d-4b55-8cad-824b7e07166c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501740322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.1501740322
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.662790808
Short name T217
Test name
Test status
Simulation time 3113495020 ps
CPU time 39.35 seconds
Started Jul 13 07:01:30 PM PDT 24
Finished Jul 13 07:02:11 PM PDT 24
Peak memory 249676 kb
Host smart-acd835e4-6a9f-4785-bd46-930d7bd12657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662790808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmds
.662790808
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.418531620
Short name T668
Test name
Test status
Simulation time 246295387 ps
CPU time 5.26 seconds
Started Jul 13 07:01:28 PM PDT 24
Finished Jul 13 07:01:34 PM PDT 24
Peak memory 232700 kb
Host smart-b13dfcff-131c-4454-90ba-f6585e67c679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418531620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.418531620
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.1702250729
Short name T530
Test name
Test status
Simulation time 42871392099 ps
CPU time 84.13 seconds
Started Jul 13 07:01:29 PM PDT 24
Finished Jul 13 07:02:54 PM PDT 24
Peak memory 230580 kb
Host smart-a83be1bb-10f7-4588-a4e8-c054c38301a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702250729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.1702250729
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.986740518
Short name T699
Test name
Test status
Simulation time 12846980725 ps
CPU time 11.49 seconds
Started Jul 13 07:01:27 PM PDT 24
Finished Jul 13 07:01:40 PM PDT 24
Peak memory 224588 kb
Host smart-316947a5-1a69-4b9c-8b07-8771e672e873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986740518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swap
.986740518
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.2066371342
Short name T547
Test name
Test status
Simulation time 7827626197 ps
CPU time 7.38 seconds
Started Jul 13 07:01:34 PM PDT 24
Finished Jul 13 07:01:42 PM PDT 24
Peak memory 232792 kb
Host smart-3208e2a3-f868-4a1d-b946-2f82db0121c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066371342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.2066371342
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.2069962022
Short name T154
Test name
Test status
Simulation time 841563493 ps
CPU time 4.49 seconds
Started Jul 13 07:01:28 PM PDT 24
Finished Jul 13 07:01:33 PM PDT 24
Peak memory 223120 kb
Host smart-031abf50-2ea9-4529-b9ac-bbe84b8b4673
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2069962022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.2069962022
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.1328171661
Short name T514
Test name
Test status
Simulation time 674976311 ps
CPU time 3.93 seconds
Started Jul 13 07:01:27 PM PDT 24
Finished Jul 13 07:01:32 PM PDT 24
Peak memory 216252 kb
Host smart-3be75f4c-6135-48f2-baaf-db371706337b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328171661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.1328171661
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.3045244372
Short name T388
Test name
Test status
Simulation time 695493365 ps
CPU time 4.04 seconds
Started Jul 13 07:01:34 PM PDT 24
Finished Jul 13 07:01:39 PM PDT 24
Peak memory 216220 kb
Host smart-7c97c888-004e-408c-b6c2-24e8e8061ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045244372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.3045244372
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.4147814134
Short name T669
Test name
Test status
Simulation time 35098327 ps
CPU time 2.07 seconds
Started Jul 13 07:01:41 PM PDT 24
Finished Jul 13 07:01:45 PM PDT 24
Peak memory 216196 kb
Host smart-c7cc03c2-60cf-4df5-824a-ceb47a49bcc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147814134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.4147814134
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.3083209618
Short name T645
Test name
Test status
Simulation time 76583262 ps
CPU time 0.78 seconds
Started Jul 13 07:01:31 PM PDT 24
Finished Jul 13 07:01:33 PM PDT 24
Peak memory 205984 kb
Host smart-1ae0abaa-8382-4eb5-b2ee-ef87dc7b4182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083209618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.3083209618
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.2864833782
Short name T564
Test name
Test status
Simulation time 1194818104 ps
CPU time 5.19 seconds
Started Jul 13 07:01:34 PM PDT 24
Finished Jul 13 07:01:39 PM PDT 24
Peak memory 224468 kb
Host smart-2b98fd1d-6b4c-460e-b9fc-0fe7edd13664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864833782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.2864833782
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.2694262983
Short name T961
Test name
Test status
Simulation time 45956676 ps
CPU time 0.72 seconds
Started Jul 13 07:01:42 PM PDT 24
Finished Jul 13 07:01:45 PM PDT 24
Peak memory 204960 kb
Host smart-dbddd75b-175b-4078-9349-857685eda041
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694262983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
2694262983
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.3349259344
Short name T5
Test name
Test status
Simulation time 142180163 ps
CPU time 2.12 seconds
Started Jul 13 07:01:38 PM PDT 24
Finished Jul 13 07:01:41 PM PDT 24
Peak memory 224512 kb
Host smart-5720fa24-ab2e-409d-89ba-4c0f6203eae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349259344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.3349259344
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.2450541246
Short name T702
Test name
Test status
Simulation time 163495535 ps
CPU time 0.74 seconds
Started Jul 13 07:01:35 PM PDT 24
Finished Jul 13 07:01:37 PM PDT 24
Peak memory 206620 kb
Host smart-ab069caf-7391-484f-9da4-dc5e81777a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450541246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.2450541246
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.844191355
Short name T218
Test name
Test status
Simulation time 232881962203 ps
CPU time 389.49 seconds
Started Jul 13 07:01:42 PM PDT 24
Finished Jul 13 07:08:15 PM PDT 24
Peak memory 255652 kb
Host smart-dce20ba0-070c-4ea0-a130-e172bfdd3fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844191355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.844191355
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.2551784093
Short name T989
Test name
Test status
Simulation time 4316130647 ps
CPU time 64.9 seconds
Started Jul 13 07:01:44 PM PDT 24
Finished Jul 13 07:02:51 PM PDT 24
Peak memory 249916 kb
Host smart-88698f25-6cf9-43c3-82c0-d028932ef38b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551784093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.2551784093
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.3955318102
Short name T875
Test name
Test status
Simulation time 53044045136 ps
CPU time 486.26 seconds
Started Jul 13 07:01:40 PM PDT 24
Finished Jul 13 07:09:49 PM PDT 24
Peak memory 252792 kb
Host smart-d6e2c765-c6d9-4050-aa85-6e56dd672057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955318102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.3955318102
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.17940323
Short name T804
Test name
Test status
Simulation time 234641435 ps
CPU time 4.91 seconds
Started Jul 13 07:01:39 PM PDT 24
Finished Jul 13 07:01:45 PM PDT 24
Peak memory 235168 kb
Host smart-a869953c-922d-4884-9ff8-f32ab6902a29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17940323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.17940323
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.2443718937
Short name T675
Test name
Test status
Simulation time 25872873041 ps
CPU time 57.63 seconds
Started Jul 13 07:01:41 PM PDT 24
Finished Jul 13 07:02:41 PM PDT 24
Peak memory 262644 kb
Host smart-cba13a32-0d86-4292-9b8f-73201769ecde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443718937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmd
s.2443718937
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.3242869430
Short name T823
Test name
Test status
Simulation time 145482913 ps
CPU time 3.1 seconds
Started Jul 13 07:01:38 PM PDT 24
Finished Jul 13 07:01:42 PM PDT 24
Peak memory 218776 kb
Host smart-5fb7f47e-c66a-4670-9f61-aeefecb9e094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242869430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.3242869430
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.2217727550
Short name T712
Test name
Test status
Simulation time 5085258973 ps
CPU time 25.72 seconds
Started Jul 13 07:01:42 PM PDT 24
Finished Jul 13 07:02:11 PM PDT 24
Peak memory 238160 kb
Host smart-b029f499-f5ae-41e1-9513-a25ef3948174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217727550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.2217727550
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.401033934
Short name T356
Test name
Test status
Simulation time 19533447544 ps
CPU time 13.89 seconds
Started Jul 13 07:01:41 PM PDT 24
Finished Jul 13 07:01:58 PM PDT 24
Peak memory 239996 kb
Host smart-ecc4cab0-0470-49d4-8d49-c266383950b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401033934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swap
.401033934
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.212866973
Short name T713
Test name
Test status
Simulation time 462345227 ps
CPU time 3.84 seconds
Started Jul 13 07:01:41 PM PDT 24
Finished Jul 13 07:01:48 PM PDT 24
Peak memory 224480 kb
Host smart-33d70f19-a168-4ee0-9a4c-27f54f74e3de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212866973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.212866973
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.1803121366
Short name T994
Test name
Test status
Simulation time 4048287666 ps
CPU time 4.08 seconds
Started Jul 13 07:01:41 PM PDT 24
Finished Jul 13 07:01:47 PM PDT 24
Peak memory 220228 kb
Host smart-c93de02c-d23b-45f1-bfd9-883b590d0f68
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1803121366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.1803121366
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.3956244249
Short name T390
Test name
Test status
Simulation time 61779687 ps
CPU time 0.74 seconds
Started Jul 13 07:01:40 PM PDT 24
Finished Jul 13 07:01:41 PM PDT 24
Peak memory 205716 kb
Host smart-0b125da8-45a3-44dc-9be0-f263a1ecb3ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956244249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.3956244249
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.3529239315
Short name T473
Test name
Test status
Simulation time 5261983808 ps
CPU time 9.67 seconds
Started Jul 13 07:01:45 PM PDT 24
Finished Jul 13 07:01:56 PM PDT 24
Peak memory 216336 kb
Host smart-87b08e5f-2322-41d6-8d1b-17136d7eb539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529239315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.3529239315
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.459588017
Short name T393
Test name
Test status
Simulation time 11136846 ps
CPU time 0.7 seconds
Started Jul 13 07:01:42 PM PDT 24
Finished Jul 13 07:01:46 PM PDT 24
Peak memory 205648 kb
Host smart-c1f47c0c-d6c4-4931-8995-e84316a8c650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459588017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.459588017
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.2230944341
Short name T949
Test name
Test status
Simulation time 28828187 ps
CPU time 0.77 seconds
Started Jul 13 07:01:40 PM PDT 24
Finished Jul 13 07:01:41 PM PDT 24
Peak memory 205988 kb
Host smart-42c1acac-ccf6-4f99-8361-77fb44219a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230944341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.2230944341
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.2256272033
Short name T648
Test name
Test status
Simulation time 2347182357 ps
CPU time 9.21 seconds
Started Jul 13 07:01:42 PM PDT 24
Finished Jul 13 07:01:54 PM PDT 24
Peak memory 238800 kb
Host smart-111ced51-06ff-4e8b-99c0-584284a9754f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256272033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.2256272033
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.457321777
Short name T918
Test name
Test status
Simulation time 14571153 ps
CPU time 0.72 seconds
Started Jul 13 07:01:40 PM PDT 24
Finished Jul 13 07:01:42 PM PDT 24
Peak memory 205536 kb
Host smart-be8b3ff7-8b82-423b-ae4d-10f3ce05895f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457321777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.457321777
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.245134537
Short name T50
Test name
Test status
Simulation time 1621739245 ps
CPU time 6.9 seconds
Started Jul 13 07:01:40 PM PDT 24
Finished Jul 13 07:01:49 PM PDT 24
Peak memory 232632 kb
Host smart-deeffe6c-1536-4307-854b-719bab93df38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245134537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.245134537
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.2755032140
Short name T331
Test name
Test status
Simulation time 47295402 ps
CPU time 0.75 seconds
Started Jul 13 07:01:41 PM PDT 24
Finished Jul 13 07:01:44 PM PDT 24
Peak memory 205916 kb
Host smart-25ad5e46-fce5-4abb-8cd3-4635582c42ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755032140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.2755032140
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.2035560922
Short name T577
Test name
Test status
Simulation time 557846125 ps
CPU time 11.26 seconds
Started Jul 13 07:01:42 PM PDT 24
Finished Jul 13 07:01:57 PM PDT 24
Peak memory 239848 kb
Host smart-f9a1f203-4d1f-4c08-81f3-36b11b8bd0f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035560922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.2035560922
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.1434940080
Short name T1001
Test name
Test status
Simulation time 21702773434 ps
CPU time 38.82 seconds
Started Jul 13 07:01:41 PM PDT 24
Finished Jul 13 07:02:23 PM PDT 24
Peak memory 224584 kb
Host smart-1afb09e1-97bf-4034-8b51-9a59e8438bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434940080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.1434940080
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.4070895390
Short name T398
Test name
Test status
Simulation time 4110151024 ps
CPU time 50.69 seconds
Started Jul 13 07:01:42 PM PDT 24
Finished Jul 13 07:02:36 PM PDT 24
Peak memory 238376 kb
Host smart-afacddda-e1a8-4efa-b1c8-43364b9c96d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070895390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.4070895390
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.3955776309
Short name T704
Test name
Test status
Simulation time 1407235381 ps
CPU time 3.68 seconds
Started Jul 13 07:01:40 PM PDT 24
Finished Jul 13 07:01:47 PM PDT 24
Peak memory 224468 kb
Host smart-c5f7dfd2-0ca6-4ea4-8b79-68babd43e2c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955776309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.3955776309
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.2127184762
Short name T729
Test name
Test status
Simulation time 77205036 ps
CPU time 2.3 seconds
Started Jul 13 07:01:40 PM PDT 24
Finished Jul 13 07:01:45 PM PDT 24
Peak memory 218800 kb
Host smart-7e9dbd99-ec11-4a96-80e8-4dd0388bb0cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127184762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.2127184762
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.2169770360
Short name T734
Test name
Test status
Simulation time 48686172273 ps
CPU time 65.86 seconds
Started Jul 13 07:01:40 PM PDT 24
Finished Jul 13 07:02:48 PM PDT 24
Peak memory 232212 kb
Host smart-550fc096-9c96-425a-bbb7-eeb22056a52c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169770360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.2169770360
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.3210984076
Short name T258
Test name
Test status
Simulation time 2121559528 ps
CPU time 4.4 seconds
Started Jul 13 07:01:40 PM PDT 24
Finished Jul 13 07:01:45 PM PDT 24
Peak memory 232632 kb
Host smart-45661551-be59-4f3d-a93e-afe45a156171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210984076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.3210984076
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.2286121118
Short name T480
Test name
Test status
Simulation time 307264042 ps
CPU time 4.21 seconds
Started Jul 13 07:01:38 PM PDT 24
Finished Jul 13 07:01:43 PM PDT 24
Peak memory 232648 kb
Host smart-1f9d04a5-f0ae-431d-8b9e-0c5a7f30e768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286121118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.2286121118
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.3306619121
Short name T46
Test name
Test status
Simulation time 210854823 ps
CPU time 3.4 seconds
Started Jul 13 07:01:42 PM PDT 24
Finished Jul 13 07:01:48 PM PDT 24
Peak memory 219700 kb
Host smart-da666001-1999-4b8c-aec8-aebe5b54c439
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3306619121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.3306619121
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.387796443
Short name T276
Test name
Test status
Simulation time 183734300790 ps
CPU time 493.83 seconds
Started Jul 13 07:01:40 PM PDT 24
Finished Jul 13 07:09:56 PM PDT 24
Peak memory 283616 kb
Host smart-59b5a569-cb52-4aa4-be1b-918bf2d20602
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387796443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stres
s_all.387796443
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.1534057335
Short name T634
Test name
Test status
Simulation time 692771425 ps
CPU time 10.78 seconds
Started Jul 13 07:01:41 PM PDT 24
Finished Jul 13 07:01:55 PM PDT 24
Peak memory 216260 kb
Host smart-683f4481-d548-419e-a887-f45f10a6ea4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534057335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.1534057335
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.2753214679
Short name T524
Test name
Test status
Simulation time 2918647143 ps
CPU time 11.52 seconds
Started Jul 13 07:01:40 PM PDT 24
Finished Jul 13 07:01:54 PM PDT 24
Peak memory 216312 kb
Host smart-dea59d80-fc98-4f3a-a427-f88436cc960f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753214679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.2753214679
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.3312124124
Short name T808
Test name
Test status
Simulation time 67124043 ps
CPU time 1.31 seconds
Started Jul 13 07:01:41 PM PDT 24
Finished Jul 13 07:01:46 PM PDT 24
Peak memory 216220 kb
Host smart-8edfc543-8929-4991-a6b5-5fdc62f50571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312124124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.3312124124
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.3486750789
Short name T945
Test name
Test status
Simulation time 93595390 ps
CPU time 0.72 seconds
Started Jul 13 07:01:38 PM PDT 24
Finished Jul 13 07:01:39 PM PDT 24
Peak memory 205992 kb
Host smart-b5fef7b9-05f8-444d-acab-c4ce1b123180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486750789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.3486750789
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.3745398326
Short name T649
Test name
Test status
Simulation time 3038646675 ps
CPU time 11.78 seconds
Started Jul 13 07:01:42 PM PDT 24
Finished Jul 13 07:01:56 PM PDT 24
Peak memory 232780 kb
Host smart-2ee3bcea-d032-4b1f-b2be-c38eda4e9189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745398326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.3745398326
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.504342906
Short name T843
Test name
Test status
Simulation time 13218283 ps
CPU time 0.7 seconds
Started Jul 13 06:59:21 PM PDT 24
Finished Jul 13 06:59:22 PM PDT 24
Peak memory 204996 kb
Host smart-042cacec-84d6-4782-81d4-3f157d68636a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504342906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.504342906
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.4093572542
Short name T578
Test name
Test status
Simulation time 75813757 ps
CPU time 2.37 seconds
Started Jul 13 06:59:21 PM PDT 24
Finished Jul 13 06:59:24 PM PDT 24
Peak memory 224524 kb
Host smart-cda08b8a-c7cb-4a1c-89b6-0bd2aa215f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093572542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.4093572542
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.1979237192
Short name T793
Test name
Test status
Simulation time 86874668 ps
CPU time 0.82 seconds
Started Jul 13 06:59:13 PM PDT 24
Finished Jul 13 06:59:16 PM PDT 24
Peak memory 206036 kb
Host smart-4eb492c6-0677-49aa-8043-11413ba646d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979237192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.1979237192
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.985589368
Short name T269
Test name
Test status
Simulation time 4371673709 ps
CPU time 27.92 seconds
Started Jul 13 06:59:23 PM PDT 24
Finished Jul 13 06:59:53 PM PDT 24
Peak memory 240996 kb
Host smart-e8462489-14cd-40ff-b8c4-454f847086f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985589368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.985589368
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.698486381
Short name T23
Test name
Test status
Simulation time 66341920327 ps
CPU time 510.26 seconds
Started Jul 13 06:59:47 PM PDT 24
Finished Jul 13 07:08:20 PM PDT 24
Peak memory 257456 kb
Host smart-1c471f3c-59b4-4335-a6a4-f25b51e86639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698486381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.698486381
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.85781270
Short name T142
Test name
Test status
Simulation time 49602347624 ps
CPU time 265.64 seconds
Started Jul 13 06:59:19 PM PDT 24
Finished Jul 13 07:03:45 PM PDT 24
Peak memory 267120 kb
Host smart-c44e2a8d-5b1d-4b0f-8bd5-6ce891f20d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85781270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle.85781270
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.995793263
Short name T297
Test name
Test status
Simulation time 18455131193 ps
CPU time 46.15 seconds
Started Jul 13 06:59:20 PM PDT 24
Finished Jul 13 07:00:07 PM PDT 24
Peak memory 233936 kb
Host smart-474ff92e-e38a-496f-af3f-29f25ea7d5a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995793263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.995793263
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.3894462369
Short name T737
Test name
Test status
Simulation time 664477360 ps
CPU time 3.44 seconds
Started Jul 13 06:59:22 PM PDT 24
Finished Jul 13 06:59:26 PM PDT 24
Peak memory 232636 kb
Host smart-f5ed8f5a-93e4-4ab3-a6e3-4558e052103c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894462369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.3894462369
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.460076895
Short name T762
Test name
Test status
Simulation time 14778647022 ps
CPU time 18.91 seconds
Started Jul 13 06:59:21 PM PDT 24
Finished Jul 13 06:59:41 PM PDT 24
Peak memory 232792 kb
Host smart-c6a993b4-e813-4900-b4f4-f2a6e4c3f46d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460076895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.460076895
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.2962624291
Short name T640
Test name
Test status
Simulation time 912023466 ps
CPU time 4.23 seconds
Started Jul 13 06:59:27 PM PDT 24
Finished Jul 13 06:59:32 PM PDT 24
Peak memory 232696 kb
Host smart-0671182e-e151-44bf-9c9d-be3cc5b09b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962624291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.2962624291
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.4082760668
Short name T976
Test name
Test status
Simulation time 210293930 ps
CPU time 4.58 seconds
Started Jul 13 06:59:16 PM PDT 24
Finished Jul 13 06:59:22 PM PDT 24
Peak memory 224452 kb
Host smart-13eb49a7-83e9-411a-a1cf-04cdadfc75b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082760668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.4082760668
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.4072823155
Short name T962
Test name
Test status
Simulation time 11696467227 ps
CPU time 8.51 seconds
Started Jul 13 06:59:25 PM PDT 24
Finished Jul 13 06:59:34 PM PDT 24
Peak memory 219080 kb
Host smart-c44e29bd-2801-4b56-8318-044a3a37c784
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4072823155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.4072823155
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.4182933874
Short name T787
Test name
Test status
Simulation time 131460403561 ps
CPU time 1360.89 seconds
Started Jul 13 06:59:24 PM PDT 24
Finished Jul 13 07:22:07 PM PDT 24
Peak memory 322784 kb
Host smart-0f63ddcc-cf92-422b-b99f-1a2991b7da08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182933874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.4182933874
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.1661128731
Short name T67
Test name
Test status
Simulation time 28446815044 ps
CPU time 36.08 seconds
Started Jul 13 06:59:13 PM PDT 24
Finished Jul 13 06:59:52 PM PDT 24
Peak memory 216320 kb
Host smart-dd55b828-9241-41f7-bad0-dc910f8ae64d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661128731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.1661128731
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.1151281966
Short name T381
Test name
Test status
Simulation time 5406587701 ps
CPU time 14.81 seconds
Started Jul 13 06:59:13 PM PDT 24
Finished Jul 13 06:59:30 PM PDT 24
Peak memory 216376 kb
Host smart-8b4f94de-e835-46d4-90a8-3c341f0bbe28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151281966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.1151281966
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.2595374391
Short name T708
Test name
Test status
Simulation time 384134018 ps
CPU time 5.69 seconds
Started Jul 13 06:59:11 PM PDT 24
Finished Jul 13 06:59:19 PM PDT 24
Peak memory 216324 kb
Host smart-1aff430f-1188-4442-965f-e91337a8abac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595374391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.2595374391
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.1252532319
Short name T506
Test name
Test status
Simulation time 386029921 ps
CPU time 0.99 seconds
Started Jul 13 06:59:13 PM PDT 24
Finished Jul 13 06:59:16 PM PDT 24
Peak memory 206236 kb
Host smart-856f2f5b-0bd3-4941-8cd8-b240d5ad8982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252532319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.1252532319
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.1631073111
Short name T246
Test name
Test status
Simulation time 16593201941 ps
CPU time 13.6 seconds
Started Jul 13 06:59:35 PM PDT 24
Finished Jul 13 06:59:50 PM PDT 24
Peak memory 224628 kb
Host smart-0d2c807b-da76-4e8f-b2fb-b6e1ce925b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631073111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.1631073111
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.179690378
Short name T73
Test name
Test status
Simulation time 32864544 ps
CPU time 0.82 seconds
Started Jul 13 06:59:44 PM PDT 24
Finished Jul 13 06:59:46 PM PDT 24
Peak memory 205736 kb
Host smart-46d7826f-6d82-48c4-92aa-eae342434583
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179690378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.179690378
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.3044895941
Short name T602
Test name
Test status
Simulation time 54433024 ps
CPU time 2.59 seconds
Started Jul 13 06:59:21 PM PDT 24
Finished Jul 13 06:59:24 PM PDT 24
Peak memory 224512 kb
Host smart-0b7d8454-6ec0-4000-881f-1ee83fd183e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044895941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.3044895941
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.2288699551
Short name T813
Test name
Test status
Simulation time 24419660 ps
CPU time 0.79 seconds
Started Jul 13 06:59:23 PM PDT 24
Finished Jul 13 06:59:26 PM PDT 24
Peak memory 206648 kb
Host smart-cfe006cd-c85f-4ce4-a1a2-ee9115f5b626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288699551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.2288699551
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.3699723834
Short name T134
Test name
Test status
Simulation time 58562508196 ps
CPU time 187.82 seconds
Started Jul 13 06:59:22 PM PDT 24
Finished Jul 13 07:02:31 PM PDT 24
Peak memory 250148 kb
Host smart-92ed941c-7b82-4bb3-8c8c-8996ecf68fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699723834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.3699723834
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.1493017344
Short name T200
Test name
Test status
Simulation time 150742433742 ps
CPU time 580.85 seconds
Started Jul 13 06:59:23 PM PDT 24
Finished Jul 13 07:09:09 PM PDT 24
Peak memory 261416 kb
Host smart-4eac6d16-c6de-43e3-b0af-0bf794a3afeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493017344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.1493017344
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.3568476834
Short name T301
Test name
Test status
Simulation time 403471542 ps
CPU time 6.49 seconds
Started Jul 13 06:59:34 PM PDT 24
Finished Jul 13 06:59:41 PM PDT 24
Peak memory 224488 kb
Host smart-479a44e0-dc20-48ca-87ac-02f40e76e899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568476834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.3568476834
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.2392324021
Short name T191
Test name
Test status
Simulation time 1423696905 ps
CPU time 22.27 seconds
Started Jul 13 06:59:22 PM PDT 24
Finished Jul 13 06:59:45 PM PDT 24
Peak memory 224440 kb
Host smart-7946262a-48b6-4153-9fd2-cefc5895a0f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392324021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds
.2392324021
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.2507911694
Short name T693
Test name
Test status
Simulation time 1129568762 ps
CPU time 5.97 seconds
Started Jul 13 06:59:20 PM PDT 24
Finished Jul 13 06:59:26 PM PDT 24
Peak memory 224492 kb
Host smart-0f4b91cc-50fa-46cc-a892-aca237d42995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507911694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.2507911694
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.3174167542
Short name T865
Test name
Test status
Simulation time 1188537413 ps
CPU time 11.62 seconds
Started Jul 13 06:59:20 PM PDT 24
Finished Jul 13 06:59:33 PM PDT 24
Peak memory 249752 kb
Host smart-f31d22ed-e106-47df-a44c-f914de580457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174167542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.3174167542
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.3757484422
Short name T983
Test name
Test status
Simulation time 3439475933 ps
CPU time 9.35 seconds
Started Jul 13 06:59:28 PM PDT 24
Finished Jul 13 06:59:38 PM PDT 24
Peak memory 224532 kb
Host smart-f47edf63-541e-4230-b147-6b378aff3a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757484422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.3757484422
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.1197040716
Short name T711
Test name
Test status
Simulation time 20354606914 ps
CPU time 31.7 seconds
Started Jul 13 06:59:22 PM PDT 24
Finished Jul 13 06:59:56 PM PDT 24
Peak memory 240984 kb
Host smart-03b1ee74-00ba-4359-a589-4c832f4d33ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197040716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.1197040716
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.260705917
Short name T854
Test name
Test status
Simulation time 239421218 ps
CPU time 4.53 seconds
Started Jul 13 06:59:22 PM PDT 24
Finished Jul 13 06:59:29 PM PDT 24
Peak memory 222620 kb
Host smart-b7b0021d-d7c9-4e9a-88df-6e22bae2acbd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=260705917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_direc
t.260705917
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.647438904
Short name T680
Test name
Test status
Simulation time 298075720 ps
CPU time 0.98 seconds
Started Jul 13 06:59:22 PM PDT 24
Finished Jul 13 06:59:24 PM PDT 24
Peak memory 206736 kb
Host smart-cc4eca71-01a9-49ac-9d6e-8987d29f2ff7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647438904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stress
_all.647438904
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.676436260
Short name T313
Test name
Test status
Simulation time 4331713126 ps
CPU time 18.01 seconds
Started Jul 13 06:59:20 PM PDT 24
Finished Jul 13 06:59:39 PM PDT 24
Peak memory 216572 kb
Host smart-a1a3bb73-31de-4118-9637-12b130901692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676436260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.676436260
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.3359378459
Short name T886
Test name
Test status
Simulation time 2682985010 ps
CPU time 5.65 seconds
Started Jul 13 06:59:21 PM PDT 24
Finished Jul 13 06:59:28 PM PDT 24
Peak memory 216364 kb
Host smart-605942a2-d7b5-4951-914b-3d0b716949f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359378459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.3359378459
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.444809482
Short name T923
Test name
Test status
Simulation time 27278515 ps
CPU time 1.07 seconds
Started Jul 13 06:59:23 PM PDT 24
Finished Jul 13 06:59:26 PM PDT 24
Peak memory 207892 kb
Host smart-4877f5f3-fa51-452e-8099-608a9a3a4edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444809482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.444809482
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.3286019213
Short name T459
Test name
Test status
Simulation time 18193843 ps
CPU time 0.75 seconds
Started Jul 13 06:59:37 PM PDT 24
Finished Jul 13 06:59:39 PM PDT 24
Peak memory 205976 kb
Host smart-bf8d10fe-1ec7-4f4d-92a9-fd6c6f66c3be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286019213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.3286019213
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.1720196617
Short name T231
Test name
Test status
Simulation time 1457006187 ps
CPU time 7.21 seconds
Started Jul 13 06:59:45 PM PDT 24
Finished Jul 13 06:59:54 PM PDT 24
Peak memory 232680 kb
Host smart-89fe43f1-6efe-455c-beee-390f539737de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720196617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.1720196617
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.2393213182
Short name T707
Test name
Test status
Simulation time 13114435 ps
CPU time 0.74 seconds
Started Jul 13 06:59:23 PM PDT 24
Finished Jul 13 06:59:26 PM PDT 24
Peak memory 205888 kb
Host smart-6a88d153-28f0-46af-9778-c5d4e0ba4257
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393213182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.2
393213182
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.471258682
Short name T229
Test name
Test status
Simulation time 161094078 ps
CPU time 4.26 seconds
Started Jul 13 06:59:26 PM PDT 24
Finished Jul 13 06:59:31 PM PDT 24
Peak memory 232652 kb
Host smart-f989268f-121b-49a0-af67-63fe40c97814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471258682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.471258682
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.1086324634
Short name T920
Test name
Test status
Simulation time 57310511 ps
CPU time 0.75 seconds
Started Jul 13 06:59:20 PM PDT 24
Finished Jul 13 06:59:22 PM PDT 24
Peak memory 205576 kb
Host smart-1542f69a-3ce3-411f-86ab-dd6c8e97d69c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086324634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.1086324634
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.2248920879
Short name T836
Test name
Test status
Simulation time 5174372699 ps
CPU time 48.94 seconds
Started Jul 13 06:59:30 PM PDT 24
Finished Jul 13 07:00:19 PM PDT 24
Peak memory 254140 kb
Host smart-1482eeff-e0c4-4d31-9029-90cd45d6b942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248920879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.2248920879
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.1431678374
Short name T57
Test name
Test status
Simulation time 7456814615 ps
CPU time 114.22 seconds
Started Jul 13 06:59:25 PM PDT 24
Finished Jul 13 07:01:20 PM PDT 24
Peak memory 261160 kb
Host smart-6611fe33-fcf7-4161-95ad-1a243097f702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431678374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.1431678374
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.2082916748
Short name T186
Test name
Test status
Simulation time 225462890689 ps
CPU time 519.07 seconds
Started Jul 13 06:59:22 PM PDT 24
Finished Jul 13 07:08:02 PM PDT 24
Peak memory 265656 kb
Host smart-af88ed9b-3373-4ed2-ab38-5d15d4dc2cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082916748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.2082916748
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.3628938676
Short name T867
Test name
Test status
Simulation time 613748663 ps
CPU time 4.43 seconds
Started Jul 13 06:59:45 PM PDT 24
Finished Jul 13 06:59:51 PM PDT 24
Peak memory 232696 kb
Host smart-d68a3866-d92d-4101-89e0-613557f2531d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628938676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.3628938676
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.4083203738
Short name T54
Test name
Test status
Simulation time 10491128138 ps
CPU time 24.7 seconds
Started Jul 13 06:59:23 PM PDT 24
Finished Jul 13 06:59:50 PM PDT 24
Peak memory 253744 kb
Host smart-385f73e6-8204-4c95-b5a2-d07dea73ab3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083203738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds
.4083203738
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.1694419674
Short name T784
Test name
Test status
Simulation time 186102264 ps
CPU time 4.13 seconds
Started Jul 13 06:59:22 PM PDT 24
Finished Jul 13 06:59:29 PM PDT 24
Peak memory 224484 kb
Host smart-c20e8f93-1122-4ced-9da4-addb54eb09f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694419674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.1694419674
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.3638178223
Short name T907
Test name
Test status
Simulation time 4410761481 ps
CPU time 53.67 seconds
Started Jul 13 06:59:22 PM PDT 24
Finished Jul 13 07:00:17 PM PDT 24
Peak memory 232764 kb
Host smart-f0571921-d045-4fbd-a724-0ba2f25f0631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638178223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.3638178223
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.750355055
Short name T863
Test name
Test status
Simulation time 1656408488 ps
CPU time 5.69 seconds
Started Jul 13 06:59:20 PM PDT 24
Finished Jul 13 06:59:26 PM PDT 24
Peak memory 224480 kb
Host smart-14ed9700-7d7f-4f4d-8c93-547ef95a1e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750355055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap.
750355055
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.682424644
Short name T1006
Test name
Test status
Simulation time 825563383 ps
CPU time 4.66 seconds
Started Jul 13 06:59:23 PM PDT 24
Finished Jul 13 06:59:29 PM PDT 24
Peak memory 232616 kb
Host smart-a62f13bd-451f-46f1-8064-d3f06c016e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682424644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.682424644
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.1251953000
Short name T561
Test name
Test status
Simulation time 333545561 ps
CPU time 3.69 seconds
Started Jul 13 06:59:21 PM PDT 24
Finished Jul 13 06:59:26 PM PDT 24
Peak memory 218776 kb
Host smart-5a9c408a-a309-44d8-aaac-aade3a9f7017
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1251953000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.1251953000
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.2738203789
Short name T481
Test name
Test status
Simulation time 2244344698 ps
CPU time 5.17 seconds
Started Jul 13 06:59:24 PM PDT 24
Finished Jul 13 06:59:31 PM PDT 24
Peak memory 218956 kb
Host smart-e4380ec8-13fa-4071-b29b-77eb3f49eb0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738203789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.2738203789
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.4204936691
Short name T733
Test name
Test status
Simulation time 5061513710 ps
CPU time 7.85 seconds
Started Jul 13 06:59:20 PM PDT 24
Finished Jul 13 06:59:29 PM PDT 24
Peak memory 216308 kb
Host smart-9491b172-8ab1-44be-b4ac-94c141e0707e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204936691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.4204936691
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.3013118329
Short name T35
Test name
Test status
Simulation time 43093541 ps
CPU time 0.79 seconds
Started Jul 13 06:59:21 PM PDT 24
Finished Jul 13 06:59:23 PM PDT 24
Peak memory 206004 kb
Host smart-32cabbf7-4f1b-4e17-b825-71f3109f1b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013118329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.3013118329
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.4051243570
Short name T679
Test name
Test status
Simulation time 86827411 ps
CPU time 0.8 seconds
Started Jul 13 06:59:21 PM PDT 24
Finished Jul 13 06:59:23 PM PDT 24
Peak memory 206000 kb
Host smart-bd8f2008-32f8-41ea-be95-c0cb2c2ab42a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051243570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.4051243570
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.1553835533
Short name T990
Test name
Test status
Simulation time 11514020094 ps
CPU time 22.82 seconds
Started Jul 13 06:59:22 PM PDT 24
Finished Jul 13 06:59:46 PM PDT 24
Peak memory 232800 kb
Host smart-8677c764-9bc3-4e36-bf12-5161ce6a412f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553835533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.1553835533
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.3320154267
Short name T632
Test name
Test status
Simulation time 51641361 ps
CPU time 0.72 seconds
Started Jul 13 06:59:45 PM PDT 24
Finished Jul 13 06:59:48 PM PDT 24
Peak memory 205552 kb
Host smart-af6d78e0-661b-402f-a077-faf91dcdc290
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320154267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.3
320154267
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.2911535525
Short name T969
Test name
Test status
Simulation time 442435538 ps
CPU time 2.37 seconds
Started Jul 13 06:59:41 PM PDT 24
Finished Jul 13 06:59:45 PM PDT 24
Peak memory 224476 kb
Host smart-0a240603-949f-4ceb-8794-63af441d920c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911535525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.2911535525
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.3874991722
Short name T768
Test name
Test status
Simulation time 44243378 ps
CPU time 0.76 seconds
Started Jul 13 06:59:23 PM PDT 24
Finished Jul 13 06:59:26 PM PDT 24
Peak memory 205580 kb
Host smart-1c881f3c-39c6-44b1-905c-c49e6b34b0a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874991722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.3874991722
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.1860221020
Short name T490
Test name
Test status
Simulation time 2265110390 ps
CPU time 7.56 seconds
Started Jul 13 06:59:20 PM PDT 24
Finished Jul 13 06:59:29 PM PDT 24
Peak memory 218836 kb
Host smart-8d5b7276-2083-4c26-8ab0-f7edb1c06fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860221020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.1860221020
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.654058747
Short name T944
Test name
Test status
Simulation time 20233542866 ps
CPU time 59.06 seconds
Started Jul 13 06:59:23 PM PDT 24
Finished Jul 13 07:00:23 PM PDT 24
Peak memory 249288 kb
Host smart-cad58fc0-1a14-4935-82d4-e37e07a8e243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654058747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.654058747
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.1019523251
Short name T62
Test name
Test status
Simulation time 142310741408 ps
CPU time 346.61 seconds
Started Jul 13 06:59:41 PM PDT 24
Finished Jul 13 07:05:28 PM PDT 24
Peak memory 268248 kb
Host smart-dfa04cce-4b17-4166-a398-668b88a8a544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019523251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.1019523251
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.1219265930
Short name T892
Test name
Test status
Simulation time 167496822 ps
CPU time 5.88 seconds
Started Jul 13 06:59:23 PM PDT 24
Finished Jul 13 06:59:31 PM PDT 24
Peak memory 240884 kb
Host smart-864a6795-2636-47bd-8ae0-8399aba8df0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219265930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.1219265930
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.2953129593
Short name T285
Test name
Test status
Simulation time 19783374042 ps
CPU time 17.03 seconds
Started Jul 13 06:59:21 PM PDT 24
Finished Jul 13 06:59:39 PM PDT 24
Peak memory 235256 kb
Host smart-8cfd6a78-0352-4a8d-bb69-a4d39516ba3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953129593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds
.2953129593
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.4125570682
Short name T739
Test name
Test status
Simulation time 4772666908 ps
CPU time 11.78 seconds
Started Jul 13 06:59:39 PM PDT 24
Finished Jul 13 06:59:51 PM PDT 24
Peak memory 232848 kb
Host smart-47e095d9-e5bd-44b9-955d-1f747b6eaab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125570682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.4125570682
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.3101647702
Short name T367
Test name
Test status
Simulation time 1044203136 ps
CPU time 10.8 seconds
Started Jul 13 06:59:42 PM PDT 24
Finished Jul 13 06:59:54 PM PDT 24
Peak memory 232684 kb
Host smart-2152e1a5-52ee-4953-b487-2df284570f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101647702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.3101647702
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.1616260735
Short name T451
Test name
Test status
Simulation time 346980613 ps
CPU time 2.13 seconds
Started Jul 13 06:59:22 PM PDT 24
Finished Jul 13 06:59:26 PM PDT 24
Peak memory 223116 kb
Host smart-5b9a2d7d-07b3-4f62-b146-5b444476cd0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616260735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.1616260735
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.523594175
Short name T470
Test name
Test status
Simulation time 16526010829 ps
CPU time 11.78 seconds
Started Jul 13 06:59:28 PM PDT 24
Finished Jul 13 06:59:40 PM PDT 24
Peak memory 232816 kb
Host smart-cd01fc5c-9f8d-45e9-bcaf-cf11619b5639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523594175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.523594175
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.1938521601
Short name T522
Test name
Test status
Simulation time 1858903580 ps
CPU time 5.09 seconds
Started Jul 13 06:59:23 PM PDT 24
Finished Jul 13 06:59:29 PM PDT 24
Peak memory 223108 kb
Host smart-d2e18f19-3a76-4db7-b1ce-b90963c941c0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1938521601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.1938521601
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.1361890972
Short name T925
Test name
Test status
Simulation time 101549210 ps
CPU time 1 seconds
Started Jul 13 06:59:25 PM PDT 24
Finished Jul 13 06:59:27 PM PDT 24
Peak memory 205724 kb
Host smart-cc958b30-050f-4760-b0c8-531d58c32308
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361890972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.1361890972
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.1670682669
Short name T639
Test name
Test status
Simulation time 22499592451 ps
CPU time 32.08 seconds
Started Jul 13 06:59:23 PM PDT 24
Finished Jul 13 06:59:57 PM PDT 24
Peak memory 216488 kb
Host smart-d14d6791-9171-4419-8cc6-29af8a085e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670682669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.1670682669
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.2777040238
Short name T431
Test name
Test status
Simulation time 2770031350 ps
CPU time 8.32 seconds
Started Jul 13 06:59:23 PM PDT 24
Finished Jul 13 06:59:33 PM PDT 24
Peak memory 216340 kb
Host smart-dee9dc5e-fa75-47d5-ad10-1e715fb684b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777040238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.2777040238
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.1923420268
Short name T718
Test name
Test status
Simulation time 825720078 ps
CPU time 7.97 seconds
Started Jul 13 06:59:41 PM PDT 24
Finished Jul 13 06:59:49 PM PDT 24
Peak memory 216172 kb
Host smart-9cfff4ea-c3f5-4be9-9d9d-5c16aada44ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923420268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.1923420268
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.932914296
Short name T34
Test name
Test status
Simulation time 221668748 ps
CPU time 0.86 seconds
Started Jul 13 06:59:22 PM PDT 24
Finished Jul 13 06:59:24 PM PDT 24
Peak memory 205980 kb
Host smart-cf9e6fc4-c693-4e51-abd3-d2e99fa63463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932914296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.932914296
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.871411955
Short name T385
Test name
Test status
Simulation time 103112020719 ps
CPU time 34.5 seconds
Started Jul 13 06:59:41 PM PDT 24
Finished Jul 13 07:00:17 PM PDT 24
Peak memory 224604 kb
Host smart-994eb9ba-4296-47ed-b99b-378d1c3bc02f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871411955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.871411955
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.3857255281
Short name T349
Test name
Test status
Simulation time 12969426 ps
CPU time 0.74 seconds
Started Jul 13 06:59:53 PM PDT 24
Finished Jul 13 06:59:58 PM PDT 24
Peak memory 205548 kb
Host smart-e9c772b0-2ac5-4fc4-b4d5-5001263d06b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857255281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.3
857255281
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.596634282
Short name T182
Test name
Test status
Simulation time 954928200 ps
CPU time 5.14 seconds
Started Jul 13 06:59:47 PM PDT 24
Finished Jul 13 06:59:54 PM PDT 24
Peak memory 232736 kb
Host smart-5d8be217-8aeb-41a2-a963-44a68a16455a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596634282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.596634282
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.910792290
Short name T895
Test name
Test status
Simulation time 18392648 ps
CPU time 0.77 seconds
Started Jul 13 06:59:24 PM PDT 24
Finished Jul 13 06:59:26 PM PDT 24
Peak memory 206788 kb
Host smart-3a0101e6-c791-43ce-bb21-8fc484705202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910792290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.910792290
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.4078472823
Short name T546
Test name
Test status
Simulation time 51451371733 ps
CPU time 93.76 seconds
Started Jul 13 06:59:48 PM PDT 24
Finished Jul 13 07:01:25 PM PDT 24
Peak memory 240988 kb
Host smart-4a9b3d43-05ff-44cb-b9da-a6dc3910378b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078472823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.4078472823
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.982006845
Short name T792
Test name
Test status
Simulation time 18206421207 ps
CPU time 178.7 seconds
Started Jul 13 06:59:49 PM PDT 24
Finished Jul 13 07:02:51 PM PDT 24
Peak memory 249268 kb
Host smart-41225c4d-faf9-4d41-8d4b-e3545fd9138e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982006845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.982006845
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.2443239679
Short name T287
Test name
Test status
Simulation time 23394462256 ps
CPU time 75.17 seconds
Started Jul 13 06:59:31 PM PDT 24
Finished Jul 13 07:00:46 PM PDT 24
Peak memory 266476 kb
Host smart-23f97b57-6631-4192-a5f9-99dba1db3461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443239679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.2443239679
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.2961004158
Short name T765
Test name
Test status
Simulation time 8350085080 ps
CPU time 21.59 seconds
Started Jul 13 06:59:33 PM PDT 24
Finished Jul 13 06:59:55 PM PDT 24
Peak memory 239944 kb
Host smart-42cfbc82-156f-4f49-a9bf-8da2c2b49904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961004158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.2961004158
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.4145235282
Short name T94
Test name
Test status
Simulation time 128010857278 ps
CPU time 223.25 seconds
Started Jul 13 06:59:45 PM PDT 24
Finished Jul 13 07:03:31 PM PDT 24
Peak memory 257384 kb
Host smart-df315fb5-095e-4e20-a574-a57cd99651ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145235282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds
.4145235282
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.3260493857
Short name T477
Test name
Test status
Simulation time 155250714 ps
CPU time 3.2 seconds
Started Jul 13 06:59:44 PM PDT 24
Finished Jul 13 06:59:50 PM PDT 24
Peak memory 224444 kb
Host smart-57055c28-846c-4d5e-a7b9-9870e58a0552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260493857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.3260493857
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.3059099151
Short name T888
Test name
Test status
Simulation time 287455542 ps
CPU time 2.25 seconds
Started Jul 13 06:59:37 PM PDT 24
Finished Jul 13 06:59:40 PM PDT 24
Peak memory 223056 kb
Host smart-7892ab99-b934-4b97-bbf0-b2b04727b86e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059099151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.3059099151
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.1408429271
Short name T883
Test name
Test status
Simulation time 1230143584 ps
CPU time 10.06 seconds
Started Jul 13 06:59:31 PM PDT 24
Finished Jul 13 06:59:41 PM PDT 24
Peak memory 239088 kb
Host smart-a35a7ad0-9923-491b-80c5-8a164cc42a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408429271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.1408429271
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.1446361062
Short name T560
Test name
Test status
Simulation time 1145033857 ps
CPU time 6.1 seconds
Started Jul 13 06:59:30 PM PDT 24
Finished Jul 13 06:59:37 PM PDT 24
Peak memory 232704 kb
Host smart-60c23c44-ef04-47ef-8875-373625d3ce23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446361062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.1446361062
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.2441015750
Short name T684
Test name
Test status
Simulation time 196269518 ps
CPU time 5.39 seconds
Started Jul 13 06:59:40 PM PDT 24
Finished Jul 13 06:59:46 PM PDT 24
Peak memory 220448 kb
Host smart-06788176-70cc-48c1-9485-cd2deaefca8c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2441015750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.2441015750
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.2196062191
Short name T22
Test name
Test status
Simulation time 730432785 ps
CPU time 1.12 seconds
Started Jul 13 06:59:49 PM PDT 24
Finished Jul 13 06:59:53 PM PDT 24
Peak memory 207200 kb
Host smart-6f77e1fc-1757-4c8e-9a0a-2b663aa638a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196062191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.2196062191
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.445524697
Short name T896
Test name
Test status
Simulation time 11652722860 ps
CPU time 9.76 seconds
Started Jul 13 06:59:33 PM PDT 24
Finished Jul 13 06:59:44 PM PDT 24
Peak memory 220404 kb
Host smart-08d06a54-9eb6-4575-ab9f-76f6042e0dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445524697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.445524697
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.2648227727
Short name T706
Test name
Test status
Simulation time 594037919 ps
CPU time 1.43 seconds
Started Jul 13 06:59:48 PM PDT 24
Finished Jul 13 06:59:52 PM PDT 24
Peak memory 207904 kb
Host smart-8d86fd13-5aaa-4cc0-bfc8-50ecbd5bf366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648227727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.2648227727
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.1700288509
Short name T709
Test name
Test status
Simulation time 91495927 ps
CPU time 2.67 seconds
Started Jul 13 06:59:35 PM PDT 24
Finished Jul 13 06:59:38 PM PDT 24
Peak memory 216256 kb
Host smart-e0c1082a-0f4b-401a-ba12-5fe3471feea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700288509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.1700288509
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.787739692
Short name T972
Test name
Test status
Simulation time 71410067 ps
CPU time 0.93 seconds
Started Jul 13 06:59:32 PM PDT 24
Finished Jul 13 06:59:33 PM PDT 24
Peak memory 206500 kb
Host smart-e8a7e804-2ec8-4404-a9f8-be7ca102540b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787739692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.787739692
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.1452835273
Short name T402
Test name
Test status
Simulation time 1432009734 ps
CPU time 3.51 seconds
Started Jul 13 06:59:38 PM PDT 24
Finished Jul 13 06:59:42 PM PDT 24
Peak memory 224460 kb
Host smart-e2b3a7c8-49d7-4540-9b17-a115d9c3048c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452835273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.1452835273
Directory /workspace/9.spi_device_upload/latest
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