Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2835408	1			T2	17760		T3	5092		T4	1
all_values[1]	2835408	1			T2	17760		T3	5092		T4	1
all_values[2]	2835408	1			T2	17760		T3	5092		T4	1
all_values[3]	2835408	1			T2	17760		T3	5092		T4	1
all_values[4]	2835408	1			T2	17760		T3	5092		T4	1
all_values[5]	2835408	1			T2	17760		T3	5092		T4	1
all_values[6]	2835408	1			T2	17760		T3	5092		T4	1
all_values[7]	2835408	1			T2	17760		T3	5092		T4	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22262653

1

T2

142080

T3

40736

T4

8

auto[1]

420611

1

T52

23

T19

64

T20

29193

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22656365

1

T2

141761

T3

40736

T4

8

auto[1]

26899

1

T2

319

T15

35

T16

211

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2785545	1			T2	17596		T3	5092		T4	1
all_values[0]	auto[0]	auto[1]	12717	1			T2	164		T15	17		T16	170
all_values[0]	auto[1]	auto[0]	36782	1			T19	5		T20	7091		T21	2
all_values[0]	auto[1]	auto[1]	364	1			T52	1		T19	4		T20	199
all_values[1]	auto[0]	auto[0]	2756771	1			T2	17629		T3	5092		T4	1
all_values[1]	auto[0]	auto[1]	8391	1			T2	131		T15	14		T16	35
all_values[1]	auto[1]	auto[0]	69810	1			T52	4		T19	4		T20	7114
all_values[1]	auto[1]	auto[1]	436	1			T19	2		T20	172		T22	1
all_values[2]	auto[0]	auto[0]	2761250	1			T2	17736		T3	5092		T4	1
all_values[2]	auto[0]	auto[1]	2930	1			T2	24		T15	4		T16	6
all_values[2]	auto[1]	auto[0]	70961	1			T52	2		T19	5		T20	7
all_values[2]	auto[1]	auto[1]	267	1			T52	3		T19	2		T20	2
all_values[3]	auto[0]	auto[0]	2734616	1			T2	17760		T3	5092		T4	1
all_values[3]	auto[0]	auto[1]	173	1			T52	2		T19	2		T20	4
all_values[3]	auto[1]	auto[0]	100467	1			T52	2		T19	5		T20	5
all_values[3]	auto[1]	auto[1]	152	1			T52	2		T19	6		T20	5
all_values[4]	auto[0]	auto[0]	2794385	1			T2	17760		T3	5092		T4	1
all_values[4]	auto[0]	auto[1]	223	1			T52	4		T19	4		T20	5
all_values[4]	auto[1]	auto[0]	40608	1			T19	2		T20	7288		T21	1
all_values[4]	auto[1]	auto[1]	192	1			T19	2		T20	3		T21	4
all_values[5]	auto[0]	auto[0]	2805387	1			T2	17760		T3	5092		T4	1
all_values[5]	auto[0]	auto[1]	180	1			T19	3		T20	7		T21	2
all_values[5]	auto[1]	auto[0]	29687	1			T52	4		T19	7		T20	5
all_values[5]	auto[1]	auto[1]	154	1			T52	1		T19	3		T20	3
all_values[6]	auto[0]	auto[0]	2772232	1			T2	17760		T3	5092		T4	1
all_values[6]	auto[0]	auto[1]	193	1			T19	7		T20	2		T21	1
all_values[6]	auto[1]	auto[0]	62800	1			T52	2		T19	2		T20	7
all_values[6]	auto[1]	auto[1]	183	1			T19	3		T20	4		T22	5
all_values[7]	auto[0]	auto[0]	2827484	1			T2	17760		T3	5092		T4	1
all_values[7]	auto[0]	auto[1]	176	1			T19	2		T20	5		T21	1
all_values[7]	auto[1]	auto[0]	7580	1			T52	1		T19	9		T20	7287
all_values[7]	auto[1]	auto[1]	168	1			T52	1		T19	3		T20	1