Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	34094	1			T2	114		T5	7		T10	4
auto[SpiFlashAddrCfg]	7382	1			T2	52		T5	8		T9	2
auto[SpiFlashAddr3b]	9204	1			T2	39		T5	5		T7	6
auto[SpiFlashAddr4b]	7636	1			T2	42		T7	6		T15	18

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33812

1

T2

152

T5

13

T7

12

auto[1]

24504

1

T2

95

T5

7

T9

4

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31541

1

T2

121

T5

9

T10

6

auto[1]

26775

1

T2

126

T5

11

T7

12

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	38633	1			T2	143		T5	9		T7	6
values[1]	1153	1			T2	5		T5	1		T15	3
values[2]	1371	1			T2	3		T10	4		T15	6
values[3]	1475	1			T2	5		T15	3		T16	15
values[4]	1487	1			T2	9		T5	1		T15	3
values[5]	1431	1			T2	7		T5	2		T12	2
values[6]	1451	1			T2	10		T7	4		T10	2
values[7]	1509	1			T2	12		T15	5		T16	5
values[8]	9806	1			T2	53		T5	7		T7	2

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27346

1

T7

12

T9

4

T10

10

auto[1]

30970

1

T2

247

T5

20

T44

530

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

55107

1

T2

219

T5

19

T7

12

write

3209

1

T2

28

T5

1

T15

7

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

19037

1

T2

113

T5

12

T7

4

valids[0x1]

39279

1

T2

134

T5

8

T7

8

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1530	1			T2	9		T5	1		T15	6
internal_process_ops[0x5a]	1634	1			T2	5		T15	6		T16	9
internal_process_ops[0x05]	20239	1			T2	35		T5	2		T10	4
internal_process_ops[0x35]	1570	1			T2	5		T15	7		T16	13
internal_process_ops[0x15]	1546	1			T2	6		T15	5		T16	8
internal_process_ops[0x03]	1017	1			T2	3		T7	6		T15	5
internal_process_ops[0x0b]	1007	1			T2	5		T7	2		T15	2
internal_process_ops[0x3b]	976	1			T2	2		T10	2		T15	4
internal_process_ops[0x6b]	991	1			T5	2		T7	4		T10	2
internal_process_ops[0xbb]	1000	1			T2	2		T12	2		T15	1
internal_process_ops[0xeb]	1009	1			T2	4		T10	2		T15	5

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

56713

1

T2

227

T5

19

T7

12

auto[1]

1603

1

T2

20

T5

1

T15

4

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

55968

1

T2

236

T5

15

T7

12

auto[1]

2348

1

T2

11

T5

5

T12

2

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9191

1

T10

4

T12

10

T15

26

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

5073

1

T15

13

T16

51

T29

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1953

1

T10

6

T12

2

T15

9

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1617

1

T9

2

T15

15

T16

24

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2360

1

T7

6

T12

4

T15

23

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2005

1

T9

2

T15

12

T16

19

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1969

1

T7

6

T15

6

T16

30

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1717

1

T15

12

T16

33

T29

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

110

1

T16

1

T46

3

T26

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

68

1

T15

1

T45

1

T46

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

82

1

T15

1

T45

1

T46

4

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

104

1

T46

2

T26

1

T47

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

125

1

T15

1

T46

2

T56

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

79

1

T15

2

T16

1

T45

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

89

1

T16

1

T46

1

T47

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

125

1

T15

1

T16

2

T26

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

101

1

T16

1

T45

1

T46

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

103

1

T16

1

T46

1

T26

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

101

1

T15

1

T16

1

T46

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

73

1

T46

1

T20

1

T47

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

85

1

T45

1

T46

1

T26

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

70

1

T46

1

T26

3

T20

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

68

1

T16

1

T46

2

T26

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

78

1

T26

1

T167

1

T87

1

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

11592

1

T2

81

T5

5

T44

183

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7450

1

T2

26

T5

2

T44

169

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1512

1

T2

25

T5

6

T44

22

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1432

1

T2

20

T5

1

T44

17

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1946

1

T2

18

T5

1

T44

20

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2085

1

T2

17

T5

4

T44

41

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1640

1

T2

14

T44

29

T52

18

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1565

1

T2

18

T44

27

T52

10

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

100

1

T2

1

T36

3

T168

4

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

117

1

T2

4

T52

1

T19

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

112

1

T2

2

T52

2

T19

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

95

1

T52

1

T42

1

T36

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

123

1

T2

2

T44

1

T42

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

119

1

T2

3

T5

1

T52

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

114

1

T2

1

T44

3

T52

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

94

1

T2

1

T44

3

T169

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

111

1

T2

1

T44

2

T52

4

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

125

1

T2

2

T170

1

T171

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

92

1

T170

3

T21

1

T172

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

102

1

T2

1

T44

3

T52

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

93

1

T2

1

T44

3

T52

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

120

1

T44

1

T19

4

T168

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

100

1

T44

3

T42

1

T19

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

131

1

T2

9

T44

3

T52

4

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3703	1			T12	2		T15	14		T16	58
auto[0]	values[0]	valids[0x1]	13185	1			T7	6		T9	2		T10	4
auto[0]	values[1]	valids[0x1]	555	1			T15	3		T16	7		T45	2
auto[0]	values[2]	valids[0x0]	474	1			T10	4		T15	4		T16	3
auto[0]	values[2]	valids[0x1]	281	1			T15	2		T57	2		T45	2
auto[0]	values[3]	valids[0x0]	460	1			T15	3		T16	9		T45	1
auto[0]	values[3]	valids[0x1]	312	1			T16	6		T152	2		T46	7
auto[0]	values[4]	valids[0x0]	533	1			T15	2		T16	10		T45	3
auto[0]	values[4]	valids[0x1]	241	1			T15	1		T16	5		T29	1
auto[0]	values[5]	valids[0x0]	496	1			T12	2		T15	4		T16	2
auto[0]	values[5]	valids[0x1]	274	1			T16	3		T53	2		T29	3
auto[0]	values[6]	valids[0x0]	505	1			T7	4		T10	2		T15	2
auto[0]	values[6]	valids[0x1]	254	1			T15	2		T46	7		T26	1
auto[0]	values[7]	valids[0x0]	540	1			T15	5		T16	3		T18	2
auto[0]	values[7]	valids[0x1]	311	1			T16	2		T45	3		T152	2
auto[0]	values[8]	valids[0x0]	3201	1			T9	2		T12	2		T15	21
auto[0]	values[8]	valids[0x1]	2021	1			T7	2		T15	21		T16	33
auto[1]	values[0]	valids[0x0]	4050	1			T2	44		T5	5		T44	52
auto[1]	values[0]	valids[0x1]	17695	1			T2	99		T5	4		T44	341
auto[1]	values[1]	valids[0x1]	598	1			T2	5		T5	1		T44	11
auto[1]	values[2]	valids[0x0]	351	1			T44	8		T52	5		T42	4
auto[1]	values[2]	valids[0x1]	265	1			T2	3		T52	4		T42	3
auto[1]	values[3]	valids[0x0]	441	1			T2	3		T44	2		T52	2
auto[1]	values[3]	valids[0x1]	262	1			T2	2		T44	4		T52	5
auto[1]	values[4]	valids[0x0]	444	1			T2	7		T5	1		T44	3
auto[1]	values[4]	valids[0x1]	269	1			T2	2		T44	5		T52	5
auto[1]	values[5]	valids[0x0]	411	1			T2	5		T44	5		T52	6
auto[1]	values[5]	valids[0x1]	250	1			T2	2		T5	2		T52	1
auto[1]	values[6]	valids[0x0]	399	1			T2	4		T44	5		T52	4
auto[1]	values[6]	valids[0x1]	293	1			T2	6		T44	7		T52	2
auto[1]	values[7]	valids[0x0]	405	1			T2	10		T44	3		T52	2
auto[1]	values[7]	valids[0x1]	253	1			T2	2		T44	3		T52	1
auto[1]	values[8]	valids[0x0]	2624	1			T2	40		T5	6		T44	50
auto[1]	values[8]	valids[0x1]	1960	1			T2	13		T5	1		T44	31