Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3401664

1

T2

5310

T5

29

T7

7026

auto[1]

28653

1

T2

27

T5

31

T12

10

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1064552

1

T2

58

T5

51

T7

7026

auto[1]

2365765

1

T2

5279

T5

9

T12

10

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	650918	1			T2	996		T5	31		T7	1482
auto[524288:1048575]	418034	1			T2	2185		T5	15		T7	927
auto[1048576:1572863]	365580	1			T2	778		T5	6		T7	251
auto[1572864:2097151]	367023	1			T2	257		T7	1541		T10	248
auto[2097152:2621439]	416816	1			T2	1		T5	2		T7	472
auto[2621440:3145727]	455951	1			T2	1100		T7	978		T10	6
auto[3145728:3670015]	365696	1			T2	8		T7	678		T10	408
auto[3670016:4194303]	390299	1			T2	12		T5	6		T7	697

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2400673

1

T2

5336

T5

57

T7

791

auto[1]

1029644

1

T2

1

T5

3

T7

6235

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3016784

1

T2

4631

T5

60

T7

7026

auto[1]

413533

1

T2

706

T15

3656

T16

5635

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	218131	1			T2	15		T5	20		T7	1482
auto[0]	auto[0]	auto[0:524287]	auto[1]	364229	1			T2	264		T12	2		T15	3503
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	96527	1			T2	5		T5	3		T7	927
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	259520	1			T2	2178		T15	488		T16	3279
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	128765	1			T2	6		T5	3		T7	251
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	197117	1			T2	769		T15	1		T16	514
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	102467	1			T2	1		T7	1541		T10	248
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	209790	1			T2	256		T45	1		T46	258
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	131494	1			T2	1		T7	472		T10	2
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	223374	1			T15	384		T16	1281		T29	4
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	162737	1			T2	3		T7	978		T10	6
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	235076	1			T2	1095		T16	3054		T44	330
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	84667	1			T2	3		T7	678		T10	408
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	233399	1			T2	5		T16	512		T44	1
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	125727	1			T2	4		T5	3		T7	697
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	220058	1			T2	2		T16	1551		T44	1918
auto[0]	auto[1]	auto[0:524287]	auto[0]	2613	1			T2	4		T15	2		T16	2
auto[0]	auto[1]	auto[0:524287]	auto[1]	61697	1			T2	694		T15	1		T16	256
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	970	1			T16	3		T151	1		T52	2
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	56574	1			T16	249		T46	2854		T52	129
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	1910	1			T2	1		T16	4		T44	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	34463	1			T16	9		T46	770		T42	2
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	1467	1			T15	3		T44	4		T151	456
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	49371	1			T15	768		T44	2		T46	514
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	426	1			T16	4		T46	6		T52	5
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	58640	1			T16	1949		T46	2511		T52	5104
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	545	1			T2	2		T44	2		T45	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	53924	1			T16	3132		T44	5		T45	2941
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	674	1			T15	6		T16	6		T46	3
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	43882	1			T15	10		T16	5		T46	2
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	1629	1			T2	2		T16	2		T151	1
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	39801	1			T15	2865		T16	1		T52	1
auto[1]	auto[0]	auto[0:524287]	auto[0]	459	1			T2	5		T5	7		T12	2
auto[1]	auto[0]	auto[0:524287]	auto[1]	3150	1			T2	11		T5	4		T12	8
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	429	1			T2	1		T5	7		T16	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	3529	1			T2	1		T5	5		T16	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	350	1			T2	1		T5	3		T15	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2586	1			T2	1		T44	1		T42	5
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	361	1			T45	1		T46	2		T52	5
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	2925	1			T45	4		T52	1		T26	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	344	1			T5	2		T16	1		T44	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	1883	1			T16	16		T44	11		T46	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	416	1			T16	4		T44	2		T45	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2492	1			T16	10		T44	71		T45	12
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	431	1			T44	1		T46	1		T42	2
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2010	1			T44	28		T42	2		T19	2
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	330	1			T2	2		T5	3		T16	3
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2011	1			T2	2		T16	6		T44	35
auto[1]	auto[1]	auto[0:524287]	auto[0]	98	1			T2	2		T15	1		T44	3
auto[1]	auto[1]	auto[0:524287]	auto[1]	541	1			T2	1		T44	29		T170	2
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	86	1			T16	1		T52	1		T19	2
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	399	1			T16	2		T52	1		T19	2
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	62	1			T16	1		T46	2		T42	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	327	1			T16	1		T46	1		T42	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	105	1			T44	2		T46	2		T36	2
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	537	1			T44	6		T36	14		T56	18
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	71	1			T46	1		T20	2		T168	2
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	584	1			T20	4		T168	1		T56	31
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	98	1			T46	1		T42	3		T36	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	663	1			T46	1		T42	7		T36	13
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	88	1			T16	3		T46	2		T26	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	545	1			T16	3		T26	1		T20	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	75	1			T16	1		T26	1		T56	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	668	1			T16	1		T56	1		T201	12

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1969779	1			T2	4607		T5	29		T7	791
auto[0]	auto[0]	auto[1]	1023299	1			T7	6235		T10	1255		T16	2
auto[0]	auto[1]	auto[0]	402856	1			T2	703		T15	3655		T16	5622
auto[0]	auto[1]	auto[1]	5730	1			T151	929		T36	1		T37	243
auto[1]	auto[0]	auto[0]	23189	1			T2	24		T5	28		T12	10
auto[1]	auto[0]	auto[1]	517	1			T5	3		T16	4		T44	2
auto[1]	auto[1]	auto[0]	4849	1			T2	2		T15	1		T16	13
auto[1]	auto[1]	auto[1]	98	1			T2	1		T47	1		T56	7