Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2835408	1			T2	17760		T3	5092		T4	1
all_pins[1]	2835408	1			T2	17760		T3	5092		T4	1
all_pins[2]	2835408	1			T2	17760		T3	5092		T4	1
all_pins[3]	2835408	1			T2	17760		T3	5092		T4	1
all_pins[4]	2835408	1			T2	17760		T3	5092		T4	1
all_pins[5]	2835408	1			T2	17760		T3	5092		T4	1
all_pins[6]	2835408	1			T2	17760		T3	5092		T4	1
all_pins[7]	2835408	1			T2	17760		T3	5092		T4	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	22618572	1			T2	142080		T3	40736		T4	8
values[0x1]	64692	1			T52	8		T19	25		T20	416
transitions[0x0=>0x1]	63764	1			T52	6		T19	20		T20	231
transitions[0x1=>0x0]	63779	1			T52	6		T19	20		T20	231

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2835026	1			T2	17760		T3	5092		T4	1
all_pins[0]	values[0x1]	382	1			T52	1		T19	4		T20	215
all_pins[0]	transitions[0x0=>0x1]	163	1			T52	1		T19	2		T20	33
all_pins[0]	transitions[0x1=>0x0]	243	1			T20	1		T22	1		T32	2
all_pins[1]	values[0x0]	2834946	1			T2	17760		T3	5092		T4	1
all_pins[1]	values[0x1]	462	1			T19	2		T20	183		T22	1
all_pins[1]	transitions[0x0=>0x1]	343	1			T19	2		T20	183		T22	1
all_pins[1]	transitions[0x1=>0x0]	161	1			T52	3		T19	2		T20	2
all_pins[2]	values[0x0]	2835128	1			T2	17760		T3	5092		T4	1
all_pins[2]	values[0x1]	280	1			T52	3		T19	2		T20	2
all_pins[2]	transitions[0x0=>0x1]	242	1			T52	1		T20	1		T22	2
all_pins[2]	transitions[0x1=>0x0]	114	1			T19	4		T20	4		T22	4
all_pins[3]	values[0x0]	2835256	1			T2	17760		T3	5092		T4	1
all_pins[3]	values[0x1]	152	1			T52	2		T19	6		T20	5
all_pins[3]	transitions[0x0=>0x1]	112	1			T52	2		T19	5		T20	3
all_pins[3]	transitions[0x1=>0x0]	152	1			T19	1		T20	1		T21	3
all_pins[4]	values[0x0]	2835216	1			T2	17760		T3	5092		T4	1
all_pins[4]	values[0x1]	192	1			T19	2		T20	3		T21	4
all_pins[4]	transitions[0x0=>0x1]	163	1			T19	2		T20	3		T21	4
all_pins[4]	transitions[0x1=>0x0]	488	1			T52	1		T19	3		T20	3
all_pins[5]	values[0x0]	2834891	1			T2	17760		T3	5092		T4	1
all_pins[5]	values[0x1]	517	1			T52	1		T19	3		T20	3
all_pins[5]	transitions[0x0=>0x1]	130	1			T52	1		T19	3		T20	3
all_pins[5]	transitions[0x1=>0x0]	62152	1			T19	3		T20	4		T22	4
all_pins[6]	values[0x0]	2772869	1			T2	17760		T3	5092		T4	1
all_pins[6]	values[0x1]	62539	1			T19	3		T20	4		T22	5
all_pins[6]	transitions[0x0=>0x1]	62492	1			T19	3		T20	4		T22	1
all_pins[6]	transitions[0x1=>0x0]	121	1			T52	1		T19	3		T20	1
all_pins[7]	values[0x0]	2835240	1			T2	17760		T3	5092		T4	1
all_pins[7]	values[0x1]	168	1			T52	1		T19	3		T20	1
all_pins[7]	transitions[0x0=>0x1]	119	1			T52	1		T19	3		T20	1
all_pins[7]	transitions[0x1=>0x0]	348	1			T52	1		T19	4		T20	215